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Nicolai Haehnle [Wed, 26 Jun 2019 19:16:35 +0000 (19:16 +0000)]
llvm-objcopy: silence warning introduced in r364296
Change-Id: I306e866d497e55945fb3b471eb0727b63ad9e4b9
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364460
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Simon Pilgrim [Wed, 26 Jun 2019 18:53:24 +0000 (18:53 +0000)]
Fix Wdocumentation warnings. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364459
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Simon Pilgrim [Wed, 26 Jun 2019 18:21:26 +0000 (18:21 +0000)]
[X86][SSE] getFauxShuffleMask - handle OR(x,y) where x and y have no overlapping bits
Create a per-byte shuffle mask based on the computeKnownBits from each operand - if for each byte we have a known zero (or both) then it can be safely blended.
Fixes PR41545
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364458
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Sanjay Patel [Wed, 26 Jun 2019 18:06:51 +0000 (18:06 +0000)]
Revert [InstCombine] change 'tmp' variable names; NFC
This reverts r364452 (git commit
6083ae0b4a250c69f6d5b13b3742ee1fe5b878d5)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364455
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Simon Pilgrim [Wed, 26 Jun 2019 17:56:53 +0000 (17:56 +0000)]
[X86][AVX] Add reduced test case for PR41545
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364454
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Nico Weber [Wed, 26 Jun 2019 17:51:47 +0000 (17:51 +0000)]
Make AddLastArg() variadic and use it more. No behavior change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364453
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Sanjay Patel [Wed, 26 Jun 2019 17:43:30 +0000 (17:43 +0000)]
[InstCombine] change 'tmp' variable names; NFC
I don't think there was anything going wrong here,
but the auto-generating CHECK line script is known
to have problems with 'TMP' because it uses that
to match nameless values.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364452
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Ryan Taylor [Wed, 26 Jun 2019 17:34:57 +0000 (17:34 +0000)]
[AMDGPU] Fix for branch offset hardware workaround
Summary:
This fixes a hardware bug that makes a branch offset of 0x3f unsafe.
This replaces the 32 bit branch with offset 0x3f to a 64 bit
instruction that includes the same 32 bit branch and the encoding
for a s_nop 0 to follow. The relaxer than modifies the offsets
accordingly.
Change-Id: I10b7aed99d651f8159401b01bb421f105fa6288e
Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63494
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364451
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Ulrich Weigand [Wed, 26 Jun 2019 17:19:12 +0000 (17:19 +0000)]
Allow matching extend-from-memory with strict FP nodes
This implements a small enhancement to https://reviews.llvm.org/D55506
Specifically, while we were able to match strict FP nodes for
floating-point extend operations with a register as source, this
did not work for operations with memory as source.
That is because from regular operations, this is represented as
a combined "extload" node (which is a variant of a load SD node);
but there is no equivalent using a strict FP operation.
However, it turns out that even in the absence of an extload
node, we can still just match the operations explicitly, e.g.
(strict_fpextend (f32 (load node:$ptr))
This patch implements that method to match the LDEB/LXEB/LXDB
SystemZ instructions even when the extend uses a strict-FP node.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364450
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Philip Reames [Wed, 26 Jun 2019 17:19:09 +0000 (17:19 +0000)]
[IndVars] Kill a redundant bit of debug output
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364449
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Greg Clayton [Wed, 26 Jun 2019 16:22:58 +0000 (16:22 +0000)]
Fix builbots after r364427.
I was using an iterator that was equal to the end of a collection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364447
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Thomas Lively [Wed, 26 Jun 2019 16:19:59 +0000 (16:19 +0000)]
[WebAssembly] Omit wrap on i64x2.{shl,shr*} ISel when possible
Summary:
Since the WebAssembly SIMD shift instructions take i32 operands, we
truncate the i64 operand to <2 x i64> shifts during ISel. When the i64
operand is sign extended from i32, this CL makes it so the sign
extension is dropped instead of a wrap instruction added.
Reviewers: dschuff, aheejin
Subscribers: sbc100, jgravelle-google, hiraditya, sunfish, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63615
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364446
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Thomas Lively [Wed, 26 Jun 2019 16:17:15 +0000 (16:17 +0000)]
[WebAssembly] Implement tail calls and unify tablegen call classes
Summary:
Implements direct and indirect tail calls enabled by the 'tail-call'
feature in both DAG ISel and FastISel. Updates existing call tests and
adds new tests including a binary encoding test.
Reviewers: aheejin
Subscribers: dschuff, sbc100, jgravelle-google, hiraditya, sunfish, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62877
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364445
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Scott Linder [Wed, 26 Jun 2019 16:13:17 +0000 (16:13 +0000)]
Fix leaks in LLVMCreateDisasmCPUFeatures
Differential Revision: https://reviews.llvm.org/D63795
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364444
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Sanjay Patel [Wed, 26 Jun 2019 15:52:59 +0000 (15:52 +0000)]
[InstCombine] simplify code for inserts -> splat; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364441
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Michael Liao [Wed, 26 Jun 2019 15:46:48 +0000 (15:46 +0000)]
Fix build in shared lib mode.
- The newly added GSYM misses LLVMBuild.txt. Add a barely one to pass
the build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364440
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Alexandre Ganea [Wed, 26 Jun 2019 15:42:42 +0000 (15:42 +0000)]
[xray] Remove usage of procid_t
Differential Revision: https://reviews.llvm.org/D61946
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364439
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Sanjay Patel [Wed, 26 Jun 2019 15:24:08 +0000 (15:24 +0000)]
[InstCombine] regenerate test checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364437
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Evandro Menezes [Wed, 26 Jun 2019 15:11:31 +0000 (15:11 +0000)]
[CodeGen] Improve formatting of jump tables (NFC)
Split jump tables into individual lines and fix spacing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364436
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Simon Pilgrim [Wed, 26 Jun 2019 14:58:11 +0000 (14:58 +0000)]
[X86][SSE] X86TargetLowering::isCommutativeBinOp - add PMULDQ
Allows narrowInsertExtractVectorBinOp to reduce vector size instead of the more restricted SimplifyDemandedVectorEltsForTargetNode
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364434
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Roman Lebedev [Wed, 26 Jun 2019 14:42:39 +0000 (14:42 +0000)]
[NFC][InstCombine] Revisit one-use tests in shift-amount-reassociation-in-bittest.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364433
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Simon Pilgrim [Wed, 26 Jun 2019 14:40:49 +0000 (14:40 +0000)]
[X86][SSE] X86TargetLowering::isCommutativeBinOp - add PCMPEQ
Allows narrowInsertExtractVectorBinOp to reduce vector size
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364432
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Simon Pilgrim [Wed, 26 Jun 2019 14:34:41 +0000 (14:34 +0000)]
[X86][SSE] X86TargetLowering::isBinOp - add PCMPGT
Allows narrowInsertExtractVectorBinOp to reduce vector size
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364431
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Roman Lebedev [Wed, 26 Jun 2019 14:24:41 +0000 (14:24 +0000)]
[NFC][InstCombine] Add shift amount reassociation in bittest tests (PR42399)
https://bugs.llvm.org/show_bug.cgi?id=42399
https://rise4fun.com/Alive/kBb
https://rise4fun.com/Alive/1SB
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364430
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Simon Pilgrim [Wed, 26 Jun 2019 14:21:29 +0000 (14:21 +0000)]
[X86] shouldScalarizeBinop - never scalarize target opcodes.
We have (almost) no target opcodes that have scalar/vector equivalents - for now assume we can't scalarize them (we can add exceptions if we need to).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364429
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Greg Clayton [Wed, 26 Jun 2019 14:09:09 +0000 (14:09 +0000)]
Add GSYM utility files along with unit tests.
The full GSYM patch started with: https://reviews.llvm.org/D53379
In that patch we wanted to split up getting GSYM into the LLVM code base so we are not committing too much code at once.
This is a first in a series of patches where I only add the foundation classes along with complete unit tests. They provide the foundation for encoding and decoding a GSYM file.
File entries are defined in llvm::gsym::FileEntry. This class splits the file up into a directory and filename represented by uniqued string table offsets. This allows all files that are referred to in a GSYM file to be encoded as 1 based indexes into a global file table in the GSYM file.
Function information in stored in llvm::gsym::FunctionInfo. This object represents a contiguous address range that has a name and range with an optional line table and inline call stack information.
Line table entries are defined in llvm::gsym::LineEntry. They store only address, file and line information to keep the line tables simple and allows the information to be efficiently encoded in a subsequent patch.
Inline information is defined in llvm::gsym::InlineInfo. These structs store the name of the inline function, along with one or more address ranges, and the file and line that called this function. They also contain any child inline information.
There are also utility classes for address ranges in llvm::gsym::AddressRange, and string table support in llvm::gsym::StringTable which are simple classes.
The unit tests test all the APIs on these simple classes so they will be ready for the next patches where we will create GSYM files and parse GSYM files.
Differential Revision: https://reviews.llvm.org/D63104
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364427
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Matt Arsenault [Wed, 26 Jun 2019 13:48:04 +0000 (13:48 +0000)]
AMDGPU: Fix unused variable
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364426
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Matt Arsenault [Wed, 26 Jun 2019 13:39:29 +0000 (13:39 +0000)]
AMDGPU: Check MRI for callee saved regs instead of TRI
This should the same, but MRI does allow dynamically changing the CSR
set, although currently not used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364425
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Fedor Sergeev [Wed, 26 Jun 2019 13:24:24 +0000 (13:24 +0000)]
[InlineCost] cleanup calculations of Cost and Threshold
Summary:
Doing better separation of Cost and Threshold.
Cost counts the abstract complexity of live instructions, while Threshold is an upper bound of complexity that inlining is comfortable to pay.
There are two parts:
- huge 15K last-call-to-static bonus is no longer subtracted from Cost
but rather is now added to Threshold.
That makes much more sense, as the cost of inlining (Cost) is not changed by the fact
that internal function is called once. It only changes the likelyhood of this inlining
being profitable (Threshold).
- bonus for calls proved-to-be-inlinable into callee is no longer subtracted from Cost
but added to Threshold instead.
While calculations are somewhat different, overall InlineResult should stay the same since Cost >= Threshold compares the same.
Reviewers: eraman, greened, chandlerc, yrouban, apilipenko
Reviewed By: apilipenko
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D60740
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364422
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Roman Lebedev [Wed, 26 Jun 2019 12:19:52 +0000 (12:19 +0000)]
[X86][Codegen] X86DAGToDAGISel::matchBitExtract(): consistently capture lambdas by value
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364420
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Roman Lebedev [Wed, 26 Jun 2019 12:19:47 +0000 (12:19 +0000)]
[X86] X86DAGToDAGISel::matchBitExtract(): pattern c: truncation awareness
Summary:
The one thing of note here is that the 'bitwidth' constant (32/64) was previously pessimistic.
Given `x & (-1 >> (C - z))`, we were taking `C` to be `bitwidth(x)`, but in reality
we want `(-1 >> (C - z))` pattern to mean "low z bits must be all-ones".
And for that, `C` should be `bitwidth(-1 >> (C - z))`, i.e. of the shift operation itself.
Last pattern D does not seem to exhibit any of these truncation issues.
Although it has the opposite problem - if we extract low bits (no shift) from i64,
and then truncate to i32, then we fail to shrink this 64-bit extraction into 32-bit extraction.
Reviewers: RKSimon, craig.topper, spatel
Reviewed By: RKSimon
Subscribers: llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62806
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364419
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Roman Lebedev [Wed, 26 Jun 2019 12:19:39 +0000 (12:19 +0000)]
[X86] X86DAGToDAGISel::matchBitExtract(): pattern b: truncation awareness
Summary:
(Not so) boringly identical to pattern a (D62786)
Not yet sure how do deal with the last pattern c.
Reviewers: RKSimon, craig.topper, spatel
Reviewed By: RKSimon
Subscribers: llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62793
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364418
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Roman Lebedev [Wed, 26 Jun 2019 12:19:11 +0000 (12:19 +0000)]
[X86] X86DAGToDAGISel::matchBitExtract(): pattern a: truncation awareness
Summary:
Finally tying up loose ends here.
The problem is quite simple:
If we have pattern `(x >> start) & (1 << nbits) - 1`,
and then truncate the result, that truncation will be propagated upwards,
into the `and`. And that isn't currently handled.
I'm only fixing pattern `a` here,
the same fix will be needed for patterns `b`/`c` too.
I *think* this isn't missing any extra legality checks,
since we only look past truncations. Similary, i don't think
we can get any other truncation there other than i64->i32.
Reviewers: craig.topper, RKSimon, spatel
Reviewed By: craig.topper
Subscribers: llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62786
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364417
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Clement Courbet [Wed, 26 Jun 2019 12:13:13 +0000 (12:13 +0000)]
Revert "r364412 [ExpandMemCmp][MergeICmps] Move passes out of CodeGen into opt pipeline."
Breaks sanitizers:
libFuzzer :: cxxstring.test
libFuzzer :: memcmp.test
libFuzzer :: recommended-dictionary.test
libFuzzer :: strcmp.test
libFuzzer :: value-profile-mem.test
libFuzzer :: value-profile-strcmp.test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364416
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Chen Zheng [Wed, 26 Jun 2019 12:02:43 +0000 (12:02 +0000)]
[HardwareLoops] NFC - move loop with irreducible control flow checking logic to HarewareLoopInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364415
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Hans Wennborg [Wed, 26 Jun 2019 11:56:38 +0000 (11:56 +0000)]
Fix the build after r364401
It was failing with:
/b/s/w/ir/cache/builder/src/third_party/llvm/llvm/lib/Target/X86/X86ISelLowering.cpp:18772:66:
error: call of overloaded 'makeArrayRef(<brace-enclosed initializer list>)' is ambiguous
scaleShuffleMask<int>(Scale, makeArrayRef<int>({ 0, 2, 1, 3 }), Mask);
^
/b/s/w/ir/cache/builder/src/third_party/llvm/llvm/lib/Target/X86/X86ISelLowering.cpp:18772:66: note: candidates are:
In file included from /b/s/w/ir/cache/builder/src/third_party/llvm/llvm/include/llvm/CodeGen/MachineFunction.h:20:0,
from /b/s/w/ir/cache/builder/src/third_party/llvm/llvm/include/llvm/CodeGen/CallingConvLower.h:19,
from /b/s/w/ir/cache/builder/src/third_party/llvm/llvm/lib/Target/X86/X86ISelLowering.h:17,
from /b/s/w/ir/cache/builder/src/third_party/llvm/llvm/lib/Target/X86/X86ISelLowering.cpp:14:
/b/s/w/ir/cache/builder/src/third_party/llvm/llvm/include/llvm/ADT/ArrayRef.h:480:15:
note: llvm::ArrayRef<T> llvm::makeArrayRef(const std::vector<_RealType>&) [with T = int]
ArrayRef<T> makeArrayRef(const std::vector<T> &Vec) {
^
/b/s/w/ir/cache/builder/src/third_party/llvm/llvm/include/llvm/ADT/ArrayRef.h:485:37:
note: llvm::ArrayRef<T> llvm::makeArrayRef(const llvm::ArrayRef<T>&) [with T = int]
template <typename T> ArrayRef<T> makeArrayRef(const ArrayRef<T> &Vec) {
^
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364414
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Clement Courbet [Wed, 26 Jun 2019 11:50:18 +0000 (11:50 +0000)]
[ExpandMemCmp][MergeICmps] Move passes out of CodeGen into opt pipeline.
This allows later passes (in particular InstCombine) to optimize more
cases.
One that's important to us is `memcmp(p, q, constant) < 0` and memcmp(p, q, constant) > 0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364412
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Nico Weber [Wed, 26 Jun 2019 11:44:54 +0000 (11:44 +0000)]
gn build: Merge r364387
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364411
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James Henderson [Wed, 26 Jun 2019 11:42:03 +0000 (11:42 +0000)]
[docs][llvm-symbolizer] Improve llvm-symbolizer documentation
As detailed in https://bugs.llvm.org/show_bug.cgi?id=42253, there were a
number of issues in the llvm-symbolizer documentation. This patch fixes
them by:
1. Adding [addresses...] to the synopsis, and matching the formatting
of other tools.
2. Rewriting the description to fix grammar issues and mention other
usage options.
3. Rewriting the examples to be easier to read.
4. Re-ordering the options into alphabetical order.
5. Improving the text of some of the option descriptions, and adding
some examples to individual options.
6. Splitting the Mach-O options into a separate section of the
document.
7. Standardizing on double dashes for long options throughout the file.
8. Adding a reference to the llvm-addr2line document.
Reviewed by: mtrent, ikudrin
Differential Revision: https://reviews.llvm.org/D63651
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364410
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Nico Weber [Wed, 26 Jun 2019 11:35:28 +0000 (11:35 +0000)]
gn build: Merge r364386
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364409
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Nico Weber [Wed, 26 Jun 2019 11:33:56 +0000 (11:33 +0000)]
gn build: Merge r364389
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364408
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Simon Pilgrim [Wed, 26 Jun 2019 11:21:09 +0000 (11:21 +0000)]
[X86][AVX] combineExtractSubvector - 'little to big' extract_subvector(bitcast()) support
Ideally this needs to be a generic combine in DAGCombiner::visitEXTRACT_SUBVECTOR but there's some nasty regressions in aarch64 due to neon shuffles not handling bitcasts at all.....
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364407
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Djordje Todorovic [Wed, 26 Jun 2019 11:19:26 +0000 (11:19 +0000)]
[IR/DIVar] Add the flag for params that have unmodified value
Introduce the debug info flag that indicates that a parameter has unchanged
value throughout a function. This info will be used to emit the expressions
with DW_OP_entry_value.
([4/13] Introduce the debug entry values.)
Co-authored-by: Ananth Sowda <asowda@cisco.com>
Co-authored-by: Nikola Prica <nikola.prica@rt-rk.com>
Co-authored-by: Ivan Baev <ibaev@cisco.com>
Differential Revision: https://reviews.llvm.org/D58034
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364406
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Simon Pilgrim [Wed, 26 Jun 2019 11:17:38 +0000 (11:17 +0000)]
[DAGCombine] visitEXTRACT_SUBVECTOR - add TODO for extract_subvector(bitcast()) support
We support 'big to little' (e.g. extract_subvector(v16i8 bitcast(v2i64))) but not 'little to big' cases (e.g. extract_subvector(v2i64 bitcast(v16i8)))
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364405
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Mikhail Maltsev [Wed, 26 Jun 2019 10:48:40 +0000 (10:48 +0000)]
[ARM] Handle fixup_arm_pcrel_9 correctly on big-endian targets
Summary:
The getFixupKindContainerSizeBytes function returns the size of the
instruction containing a given fixup. Currently fixup_arm_pcrel_9 is
not handled in this function, this causes an assertion failure in
the debug build and incorrect codegen in the release build.
This patch fixes the problem.
Reviewers: ostannard, simon_tatham
Reviewed By: ostannard
Subscribers: javed.absar, kristof.beyls, hiraditya, pbarrio, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63778
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364404
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Lewis Revill [Wed, 26 Jun 2019 10:35:58 +0000 (10:35 +0000)]
[RISCV] Add pseudo instruction for calls with explicit register
This patch adds the PseudoCALLReg instruction which allows using an
explicit register operand as the destination for the return address.
GCC can successfully parse this form of the call instruction, which
would be used for calls to functions which do not use ra as the return
address register, such as the __riscv_save libcalls. This patch forms
the first part of an implementation of -msave-restore for RISC-V.
Differential Revision: https://reviews.llvm.org/D62685
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364403
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Wed, 26 Jun 2019 09:50:11 +0000 (09:50 +0000)]
[X86][AVX] truncateVectorWithPACK - avoid bitcasted shuffles
truncateVectorWithPACK is often used in conjunction with ComputeNumSignBits which struggles when peeking through bitcasts.
This fix tries to avoid bitcast(shuffle(bitcast())) patterns in the 256-bit 64-bit sublane shuffles so we can still see through at least until lowering when the shuffles will need to be bitcasted to widen the shuffle type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364401
91177308-0d34-0410-b5e6-
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Florian Hahn [Wed, 26 Jun 2019 09:16:57 +0000 (09:16 +0000)]
[LoopUnroll] Add support for loops with exiting headers and uncond latches.
This patch generalizes the UnrollLoop utility to support loops that exit
from the header instead of the latch. Usually, LoopRotate would take care
of must of those cases, but in some cases (e.g. -Oz), LoopRotate does
not kick in.
Codesize impact looks relatively neutral on ARM64 with -Oz + LTO.
Program master patch diff
External/S.../CFP2006/447.dealII/447.dealII 629060.00 627676.00 -0.2%
External/SPEC/CINT2000/176.gcc/176.gcc
1245916.00
1244932.00 -0.1%
MultiSourc...Prolangs-C/simulator/simulator 86100.00 86156.00 0.1%
MultiSourc...arks/Rodinia/backprop/backprop 66212.00 66252.00 0.1%
MultiSourc...chmarks/Prolangs-C++/life/life 67276.00 67312.00 0.1%
MultiSourc...s/Prolangs-C/compiler/compiler 69824.00 69788.00 -0.1%
MultiSourc...Prolangs-C/assembler/assembler 86672.00 86696.00 0.0%
Reviewers: efriedma, vsk, paquette
Reviewed By: paquette
Differential Revision: https://reviews.llvm.org/D61962
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364398
91177308-0d34-0410-b5e6-
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Chen Zheng [Wed, 26 Jun 2019 09:12:52 +0000 (09:12 +0000)]
[HardwareLoops] NFC - move loop with irreducible control flow checking logic to isHardwareLoopProfitable()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364397
91177308-0d34-0410-b5e6-
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Djordje Todorovic [Wed, 26 Jun 2019 08:35:43 +0000 (08:35 +0000)]
[TargetOption] Add option to ebanble the debug entry values
The option enables debug info about parameter's entry values.
([2/13] Introduce the debug entry values.)
Co-authored-by: Ananth Sowda <asowda@cisco.com>
Co-authored-by: Nikola Prica <nikola.prica@rt-rk.com>
Co-authored-by: Ivan Baev <ibaev@cisco.com>
Differential Revision: https://reviews.llvm.org/D60961
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364395
91177308-0d34-0410-b5e6-
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Roman Lebedev [Wed, 26 Jun 2019 08:17:05 +0000 (08:17 +0000)]
[NFC][InstCombine] Add shift amount reassociation tests (PR42391)
https://bugs.llvm.org/show_bug.cgi?id=42391
https://rise4fun.com/Alive/9E2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364393
91177308-0d34-0410-b5e6-
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Djordje Todorovic [Wed, 26 Jun 2019 07:31:09 +0000 (07:31 +0000)]
[Metadata] Add GNU extensions for call site DWARF symbols
As discussed on RFC
(http://lists.llvm.org/pipermail/llvm-dev/2019-February/130094.html), this
is set of patches that introduces debug information about call site and
call site parameters. Since the LLVM has portion of this support (dumping
DWARF 5 symbols for calls), we generate GNU extensions as well. All of that
will be restricted under an option.
([1/13] Introduce the debug entry values.)
Co-authored-by: Ananth Sowda <asowda@cisco.com>
Co-authored-by: Nikola Prica <nikola.prica@rt-rk.com>
Co-authored-by: Ivan Baev <ibaev@cisco.com>
Differential Revision: https://reviews.llvm.org/D60712
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364385
91177308-0d34-0410-b5e6-
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Clement Courbet [Wed, 26 Jun 2019 07:06:49 +0000 (07:06 +0000)]
[ExpandMemCmp] Honor prefer-vector-width.
Reviewers: gchatelet, echristo, spatel, atdt
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63769
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364384
91177308-0d34-0410-b5e6-
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Kai Luo [Wed, 26 Jun 2019 05:25:16 +0000 (05:25 +0000)]
[PowerPC] Fixed missing change flag of emitRLDICWhenLoweringJumpTables
PPCMIPeephole::emitRLDICWhenLoweringJumpTables should return a bool
value to indicate optimization is conducted or not.
Differential Revision: https://reviews.llvm.org/D63801
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364383
91177308-0d34-0410-b5e6-
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QingShan Zhang [Wed, 26 Jun 2019 05:12:53 +0000 (05:12 +0000)]
Teach the DAGCombine to fold this pattern(c1 and c2 is constant).
// fold (sext (select cond, c1, c2)) -> (select cond, sext c1, sext c2)
// fold (zext (select cond, c1, c2)) -> (select cond, zext c1, zext c2)
// fold (aext (select cond, c1, c2)) -> (select cond, sext c1, sext c2)
Sign extend the operands if it is any_extend, to keep the signess of the operands that, the other combine rule would apply. The any_extend is handled as zero extend for constants. i.e.
t1: i8 = select t0, Constant:i8<-1>, Constant:i8<0>
t2: i64 = any_extend t1
-->
t3: i64 = select t0, Constant:i64<-1>, Constant:i64<0>
-->
t4: i64 = sign_extend_inreg t3
Differential Revision: https://reviews.llvm.org/D63318
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364382
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Rumeet Dhindsa [Wed, 26 Jun 2019 03:00:57 +0000 (03:00 +0000)]
Revert [llvm-objcopy][NFC] Refactor output target parsing
This reverts r364254 (git commit
545f001d1b9a7b58a68d75e70bfc36c841de8999)
This change causes some llvm-obcopy tests to fail with valgrind.
Following is the output for basic-keep.test
Command Output (stderr):
--
==107406== Conditional jump or move depends on uninitialised value(s)
==107406== at 0x1A30DD: executeObjcopy(llvm::objcopy::CopyConfig const&) (llvm-objcopy.cpp:235)
==107406== by 0x1A3935: main (llvm-objcopy.cpp:294)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364379
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Rumeet Dhindsa [Wed, 26 Jun 2019 02:57:34 +0000 (02:57 +0000)]
Revert [llvm-objcopy][NFCI] Fix build failure with GCC
This reverts r364263 (git commit
81eb82840524818ec0ec14285c866c09b9634df0)
This commit is related to r364254 which is causing some llvm-objcopy tests
to fail with valgrind.
Error:
Conditional jump or move depends on uninitialised value(s)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364378
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Nemanja Ivanovic [Wed, 26 Jun 2019 02:46:03 +0000 (02:46 +0000)]
[NFC] Fix buildbot breaks due to r364375
For some reason, the update_llc_checks.py script produces checks for
empty lines which cause failures. Corrected that to check for actual
text produced by llc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364377
91177308-0d34-0410-b5e6-
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Fangrui Song [Wed, 26 Jun 2019 02:34:10 +0000 (02:34 +0000)]
[ARM] Fix -Wimplicit-fallthrough after D60709/r364331
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364376
91177308-0d34-0410-b5e6-
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Nemanja Ivanovic [Wed, 26 Jun 2019 02:01:11 +0000 (02:01 +0000)]
[PowerPC][NFC] Add a TOC save test case prior to posting a related patch
An upcoming patch will modify the behaviour with respect to saving the TOC
in functions with indirect calls.
Adding a test case so the patch will show the difference in codegen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364375
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Peter Collingbourne [Wed, 26 Jun 2019 01:52:22 +0000 (01:52 +0000)]
gn build: Merge r364288.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364374
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Nemanja Ivanovic [Wed, 26 Jun 2019 01:48:57 +0000 (01:48 +0000)]
[PowerPC] Mark FCOPYSIGN legal for FP vectors
This was just an omission in the back end. We have had the instructions for both
single and double precision for a few HW generations, but never got around to
legalizing these.
Differential revision: https://reviews.llvm.org/D63634
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364373
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Kai Luo [Wed, 26 Jun 2019 01:34:37 +0000 (01:34 +0000)]
[PowerPC][NFC] Move peephole optimization of RLDICR into a method.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364372
91177308-0d34-0410-b5e6-
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Saleem Abdulrasool [Wed, 26 Jun 2019 01:09:52 +0000 (01:09 +0000)]
MC: correct the emission of weak aliases in COFF
The weak alias should have the characteristics set to
`IMAGE_EXTERN_WEAK_SEARCH_ALIAS` to indicate that the weak external here
is a symbol alias and that the symbol is aliased to a locally defined
symbol. We were previously setting the characteristics to
`IMAGE_EXTERN_WEAK_SEARCH_LIBRARY` which indicates that the symbol
should be looked for in the libraries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364370
91177308-0d34-0410-b5e6-
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Keno Fischer [Wed, 26 Jun 2019 00:52:42 +0000 (00:52 +0000)]
[WebAssembly] Fix list of relocations with addends in lld
Summary:
The list of relocations with addend in lld was missing `R_WASM_MEMORY_ADDR_REL_SLEB`,
causing `wasm-ld` to generate corrupted output. This fixes that problem and while
we're at it pulls the list of such relocations into the Wasm.h header, to avoid
duplicating it in multiple places.
Reviewers: sbc100
Differential Revision: https://reviews.llvm.org/D63696
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364367
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Erich Keane [Wed, 26 Jun 2019 00:08:22 +0000 (00:08 +0000)]
Teach TableGen Intrin Emitter to handle LLVMPointerType<llvm_any_ty>
r363233 rewrote a bunch of the Intrin Emitter code, however the new
function to update the arg codes did not properly consider a pointer to
an any. This patch adds that logic.
Differential Revision: https://reviews.llvm.org/D63507
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364364
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Heejin Ahn [Tue, 25 Jun 2019 23:04:12 +0000 (23:04 +0000)]
[WebAssembly] Remove catch_all from AsmParser
Summary:
`catch_all` is from the first version of EH proposal and now has been
removed. There were no tests covering this, and thus no tests to remove
or fix.
Reviewers: aardappel
Subscribers: dschuff, sbc100, jgravelle-google, sunfish, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63737
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364360
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Reid Kleckner [Tue, 25 Jun 2019 22:33:32 +0000 (22:33 +0000)]
Dump what value failed byval attribute verification
This verifier check is failing for us while doing ThinLTO on Chrome for
x86, see https://crbug.com/978218, and this helps to debug the problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364357
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Jinsong Ji [Tue, 25 Jun 2019 21:50:56 +0000 (21:50 +0000)]
[MachinePipeliner] Fix risky iterator usage R++, --R
When we calculate MII, we use two loops, one with iterator R++ to
check whether we can reserve the resource, then --R to move back
the iterator to do reservation.
This is risky, as R++, --R may not point to the same element at all.
The can cause wrong MII.
Differential Revision: https://reviews.llvm.org/D63536
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364353
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Jinsong Ji [Tue, 25 Jun 2019 20:56:17 +0000 (20:56 +0000)]
[PowerPC][NFC]Add a test for MachinePipeliner bug
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364350
91177308-0d34-0410-b5e6-
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Matt Arsenault [Tue, 25 Jun 2019 20:53:35 +0000 (20:53 +0000)]
Don't look for the TargetFrameLowering in the implementation
The same oddity was apparently copy-pasted between multiple targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364349
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Huihui Zhang [Tue, 25 Jun 2019 20:44:52 +0000 (20:44 +0000)]
[InstCombine] Simplify icmp ult/uge (shl %x, C2), C1 iff C1 is power of two -> icmp eq/ne (and %x, (lshr -C1, C2)), 0.
Simplify 'shl' inequality test into 'and' equality test.
This pattern happens in the middle-end while simplifying bitfield access,
Exposed in https://reviews.llvm.org/D63505
https://rise4fun.com/Alive/6uz
Reviewers: lebedev.ri, efriedma
Reviewed By: lebedev.ri
Subscribers: spatel, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63675
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364348
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Philip Reames [Tue, 25 Jun 2019 20:14:08 +0000 (20:14 +0000)]
[LFTR] Adjust debug output to include extensions (if any)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364346
91177308-0d34-0410-b5e6-
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Pirama Arumuga Nainar [Tue, 25 Jun 2019 19:34:52 +0000 (19:34 +0000)]
[llvm-shlib] Do not use version script when building with MinGW
Summary:
The MinGW driver for lld does not support the --version-script option.
For GNU ld, it's a no-op since LLVM.dll exports all symbols.
Reviewers: srhines, mstorsjo
Subscribers: mgorny, fedor.sergeev, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63743
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364343
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Diego Novillo [Tue, 25 Jun 2019 18:55:16 +0000 (18:55 +0000)]
Update phis in AMDGPUUnifyDivergentExitNodes
Original patch https://reviews.llvm.org/D63659 from
Steven Perron <stevenperron@google.com>
The pass AMDGPUUnifyDivergentExitNodes does not update the phi nodes in
the successors of blocks that is splits. This is fixed by calling
BasicBlock::splitBasicBlock to split the block instead of doing it
manually. This does extra work because a new conditional branch is
created in BB which is immediately replaced, but I think the simplicity
is worth it. It also helps make the code more future proof in case other
things need to be updated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364342
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Sanjay Patel [Tue, 25 Jun 2019 18:51:44 +0000 (18:51 +0000)]
[InstCombine] reduce checks for power-of-2-or-zero using ctpop
This follows up the transform from rL363956 to use the ctpop intrinsic when checking for power-of-2-or-zero.
This is matching the isPowerOf2() patterns used in PR42314:
https://bugs.llvm.org/show_bug.cgi?id=42314
But there's at least 1 instcombine follow-up needed to match the alternate form:
(v & (v - 1)) == 0;
We should have all of the backend expansions handled with:
rL364319
(x86-specific changes still needed for optimal code based on subtarget)
And the larger patterns to exclude zero as a power-of-2 are joining with this change after:
rL364153 ( D63660 )
rL364246
Differential Revision: https://reviews.llvm.org/D63777
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364341
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Stanislav Mekhanoshin [Tue, 25 Jun 2019 18:33:53 +0000 (18:33 +0000)]
[AMDGPU] Removed dead SIMachineFunctionInfo::getWorkItemIDVGPR()
Differential Revision: https://reviews.llvm.org/D63780
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364339
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Craig Topper [Tue, 25 Jun 2019 17:31:52 +0000 (17:31 +0000)]
[X86] Remove isel patterns that look for (vzext_movl (scalar_to_vector (load)))
I believe these all get canonicalized to vzext_movl. The only case where that wasn't true was when the load was loadi32 and the load was an extload aligned to 32 bits. But that was fixed in r364207.
Differential Revision: https://reviews.llvm.org/D63701
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364337
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Philip Reames [Tue, 25 Jun 2019 17:29:18 +0000 (17:29 +0000)]
[Peephole] Allow folding loads into instructions w/multiple uses (such as test64rr)
Peephole opt has a one use limitation which appears to be accidental. The function being used was incorrectly documented as returning whether the def had one *user*, but instead returned true only when there was one *use*. Add a corresponding hasOneNonDbgUser helper, and adjust peephole-opt to use the appropriate one.
All of the actual folding code handles multiple uses within a single instruction. That codepath is well exercised through instruction selection.
Differential Revision: https://reviews.llvm.org/D63656
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364336
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Craig Topper [Tue, 25 Jun 2019 17:08:26 +0000 (17:08 +0000)]
[X86] Add a DAG combine to turn vzmovl+load into vzload if the load isn't volatile. Remove isel patterns for vzmovl+load
We currently have some isel patterns for treating vzmovl+load the same as vzload, but that shrinks the load which we shouldn't do if the load is volatile.
Rather than adding isel checks for volatile. This patch removes the patterns and teachs DAG combine to merge them into vzload when its legal to do so.
Differential Revision: https://reviews.llvm.org/D63665
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364333
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Simon Tatham [Tue, 25 Jun 2019 16:49:32 +0000 (16:49 +0000)]
[ARM] Support inline assembler constraints for MVE.
"To" selects an odd-numbered GPR, and "Te" an even one. There are some
8.1-M instructions that have one too few bits in their register fields
and require registers of particular parity, without necessarily using
a consecutive even/odd pair.
Also, the constraint letter "t" should select an MVE q-register, when
MVE is present. This didn't need any source changes, but some extra
tests have been added.
Reviewers: dmgreen, samparker, SjoerdMeijer
Subscribers: javed.absar, eraman, kristof.beyls, hiraditya, cfe-commits, llvm-commits
Tags: #clang, #llvm
Differential Revision: https://reviews.llvm.org/D60709
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364331
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Ayke van Laethem [Tue, 25 Jun 2019 16:49:22 +0000 (16:49 +0000)]
[AVR] Adjust to Register class change
A refactor in r364191 changed register types from an unsigned int to the
llvm:Register class. Adjust the AVR backend to this change.
This fixes build errors when building with the experimental AVR backend
enabled.
Differential Revision: https://reviews.llvm.org/D63776
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364330
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Simon Tatham [Tue, 25 Jun 2019 16:48:46 +0000 (16:48 +0000)]
[ARM] Code-generation infrastructure for MVE.
This provides the low-level support to start using MVE vector types in
LLVM IR, loading and storing them, passing them to __asm__ statements
containing hand-written MVE vector instructions, and *if* you have the
hard-float ABI turned on, using them as function parameters.
(In the soft-float ABI, vector types are passed in integer registers,
and combining all those 32-bit integers into a q-reg requires support
for selection DAG nodes like insert_vector_elt and build_vector which
aren't implemented yet for MVE. In fact I've also had to add
`arm_aapcs_vfpcc` to a couple of existing tests to avoid that
problem.)
Specifically, this commit adds support for:
* spills, reloads and register moves for MVE vector registers
* ditto for the VPT predication mask that lives in VPR.P0
* make all the MVE vector types legal in ISel, and provide selection
DAG patterns for BITCAST, LOAD and STORE
* make loads and stores of scalar FP types conditional on
`hasFPRegs()` rather than `hasVFP2Base()`. As a result a few
existing tests needed their llc command lines updating to use
`-mattr=-fpregs` as their method of turning off all hardware FP
support.
Reviewers: dmgreen, samparker, SjoerdMeijer
Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D60708
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364329
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Kevin P. Neal [Tue, 25 Jun 2019 16:09:39 +0000 (16:09 +0000)]
[FPEnv] A missing crucial step was undocumented.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364328
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Tue, 25 Jun 2019 16:00:16 +0000 (16:00 +0000)]
[DAGCombine] combineRepeatedFPDivisors - recognize -1.0 / X as a reciprocal
Fixes issue identified by @nemanjai (Nemanja Ivanovic) in D62963 / rL363040 - infinite loop due to GetNegatedExpression fighting combineRepeatedFPDivisors resulting in fneg(fdiv(x,splat)) -> fneg(fmul(x,1.0/splat)) -> fmul(x,-1.0/splat) -> fmul(x,(-1.0 * 1.0)/splat) ......
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364326
91177308-0d34-0410-b5e6-
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Fangrui Song [Tue, 25 Jun 2019 15:56:32 +0000 (15:56 +0000)]
[PPC32] Support PLT calls for -msecure-plt -fpic
Summary:
In Secure PLT ABI, -fpic is similar to -fPIC. The differences are that:
* -fpic stores the address of _GLOBAL_OFFSET_TABLE_ in r30, while -fPIC stores .got2+0x8000.
* -fpic uses an addend of 0 for R_PPC_PLTREL24, while -fPIC uses 0x8000.
Reviewers: hfinkel, jhibbits, joerg, nemanjai, spetrovic
Reviewed By: jhibbits
Subscribers: adalava, kbarton, jsji, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63563
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364324
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Sam Parker [Tue, 25 Jun 2019 15:11:17 +0000 (15:11 +0000)]
[ARM] Fix for DLS/LE CodeGen
The expensive buildbots highlighted the mir tests were broken, which
I've now updated and added --verify-machineinstrs to them. This also
uncovered a couple of bugs in the backend pass, so these have also
been fixed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364323
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Xing Xue [Tue, 25 Jun 2019 15:08:28 +0000 (15:08 +0000)]
Improve zero-size allocation with safe_malloc, etc.
Summary:
The current implementations of the memory allocation functions mistake a nullptr returned from std::malloc, std::calloc, or std::realloc as a failure. The behaviour for each of std::malloc, std::calloc, and std::realloc when the size is 0 is implementation defined (ISO/IEC 9899:2018 7.22.3), and may return a nullptr.
This patch checks if space requested is zero when a nullptr is returned, retry requesting non-zero if it is.
Authored By: andusy
Reviewers: hubert.reinterpretcast, xingxue, jasonliu
Reviewed By: hubert.reinterpretcast, xingxue, abrachet
Subscribers: abrachet, jsji, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63668
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364322
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Simon Pilgrim [Tue, 25 Jun 2019 14:58:20 +0000 (14:58 +0000)]
[SLPVectorizer] Precommit of supernode.ll test for D63661
This is a pre-commit of the tests introduced by the SuperNode SLP patch D63661.
Committed on behalf of @vporpo (Vasileios Porpodas)
Differential Revision: https://reviews.llvm.org/D63664
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364320
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Sanjay Patel [Tue, 25 Jun 2019 14:46:52 +0000 (14:46 +0000)]
[SDAG] expand ctpop != 1
Change the generic ctpop expansion to more efficiently handle a
check for not-a-power-of-two value:
(ctpop x) != 1 --> (x == 0) || ((x & x-1) != 0)
This is the inverted predicate sibling pattern that was added with:
D63004
This should have been done before I changed IR canonicalization to
favor this form with:
rL364246
...so if this requires revert/changing, the earlier commit may also
need to modified.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364319
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Michael Liao [Tue, 25 Jun 2019 14:06:34 +0000 (14:06 +0000)]
[AMDGPU] Null checking on TS to avoid crashing in clang tests.
- `test/Misc/backend-resource-limit-diagnostics.cl` crashes as null
streamer is used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364318
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Matt Arsenault [Tue, 25 Jun 2019 13:57:53 +0000 (13:57 +0000)]
AMDGPU/GlobalISel: Fix broken test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364316
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Sanjay Patel [Tue, 25 Jun 2019 13:37:16 +0000 (13:37 +0000)]
[AArch64][x86] add tests for ctpop != 1; NFC
This is the inverted predicate pattern for D63004.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364314
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Simon Pilgrim [Tue, 25 Jun 2019 13:36:53 +0000 (13:36 +0000)]
[X86] lowerShuffleAsSpecificZeroOrAnyExtend - add ANY_EXTEND TODO.
lowerShuffleAsSpecificZeroOrAnyExtend should be able to lower to ANY_EXTEND_VECTOR_INREG as well as ZER_EXTEND_VECTOR_INREG.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364313
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Fangrui Song [Tue, 25 Jun 2019 13:28:44 +0000 (13:28 +0000)]
[ARM] Fix -Wunused-variable in -DLLVM_ENABLE_ASSERTIONS=off builds after D60692
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364312
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Simon Pilgrim [Tue, 25 Jun 2019 13:25:57 +0000 (13:25 +0000)]
[TargetLowering] SimplifyDemandedBits - add ANY_EXTEND_VECTOR_INREG support
Add 'lowest' demanded elt -> bitcast fold to all *_EXTEND_VECTOR_INREG cases.
Reapplies rL363856.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364311
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Whitney Tsang [Tue, 25 Jun 2019 13:23:13 +0000 (13:23 +0000)]
Expand cloneLoopWithPreheader() to support cloning loop nest
Summary: cloneLoopWithPreheader() currently only support innermost loop,
and assert otherwise.
Reviewers: Meinersbur, fhahn, kbarton
Reviewed By: Meinersbur
Subscribers: hiraditya, jsji, llvm-commits
Tag: LLVM
Differential Revision: https://reviews.llvm.org/D63446
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364310
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Matt Arsenault [Tue, 25 Jun 2019 13:23:08 +0000 (13:23 +0000)]
AMDGPU/GlobalISel: Fix duplicated test
Somehow ended up with copies of the same tests in AMDGPU and
AMDGPU/GlobalISel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364309
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Matt Arsenault [Tue, 25 Jun 2019 13:18:11 +0000 (13:18 +0000)]
AMDGPU: Select G_SEXT/G_ZEXT/G_ANYEXT
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364308
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James Henderson [Tue, 25 Jun 2019 13:14:18 +0000 (13:14 +0000)]
[llvm-objcopy][llvm-strip] Fix help text typo for --allow-broken-links
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364307
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