OSDN Git Service
Sanjoy Das [Thu, 10 Nov 2016 07:56:12 +0000 (07:56 +0000)]
[SCEVExpander] Hoist unsigned divisons when safe
That is, when the divisor is a constant non-zero.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286438
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Sanjoy Das [Thu, 10 Nov 2016 07:56:09 +0000 (07:56 +0000)]
[SCEVExpander] Don't hoist divisions
Fixes PR30942.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286437
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Sanjoy Das [Thu, 10 Nov 2016 07:56:05 +0000 (07:56 +0000)]
Lift out a helper lambda; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286436
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Craig Topper [Thu, 10 Nov 2016 07:47:17 +0000 (07:47 +0000)]
[AVX-512] Allow legacy cvtpd2dq intrinsics to select EVEX encoded instruction when available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286435
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Craig Topper [Thu, 10 Nov 2016 07:24:52 +0000 (07:24 +0000)]
[AVX-512][X86] Convert avx_cvtt_ps2dq_256 and sse2_cvttps2dq intrinsics to ISD::FP_TO_SINT in the intrinsics table and delete patterns. While nearby also move CVTDQ2PS patterns into their instructions.
This allows these intrinsics to also use EVEX instructons.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286434
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Craig Topper [Thu, 10 Nov 2016 06:45:39 +0000 (06:45 +0000)]
[X86] Convert int_x86_avx_cvtt_pd2dq_256 to fp_to_sint using the intrinsics table. Removes extra patterns and allows legacy intrinsic to select EVEX encoded instructions when available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286433
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Craig Topper [Thu, 10 Nov 2016 06:45:37 +0000 (06:45 +0000)]
[X86] Move some custom patterns into the currently empty pattern of their corresponding instructions. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286432
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Craig Topper [Thu, 10 Nov 2016 06:45:34 +0000 (06:45 +0000)]
[X86] Remove some patterns still referencing int_x86_sse2_cvttpd2dq that should have been removed in r286344. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286431
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Sanjoy Das [Thu, 10 Nov 2016 06:33:54 +0000 (06:33 +0000)]
[SCEV] Eta reduce some lambdas; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286429
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Sanjoy Das [Thu, 10 Nov 2016 06:21:10 +0000 (06:21 +0000)]
[LangRef] Drop "experimental" caveat from operand bundles
I think we're past that point now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286428
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Craig Topper [Thu, 10 Nov 2016 03:39:19 +0000 (03:39 +0000)]
[AVX-512] Add test cases to show missed opportunities for using VALIGND/Q to handle shuffles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286425
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Sanjay Patel [Thu, 10 Nov 2016 00:15:14 +0000 (00:15 +0000)]
[InstCombine] avoid infinite loop from shuffle-extract-insert sequence (PR30923)
Removing the limitation in visitInsertElementInst() causes several regressions
because we're not prepared to fold sequences of shuffles or inserts and extracts
separated by shuffles. Fixing that appears to be a difficult mission because we
are purposely trying to avoid creating shuffles with arbitrary shuffle masks
because some targets may choke on those.
https://llvm.org/bugs/show_bug.cgi?id=30923
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286423
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Peter Collingbourne [Wed, 9 Nov 2016 23:53:43 +0000 (23:53 +0000)]
Re-apply r286384, "X86: Introduce the "relocImm" ComplexPattern, which represents a relocatable immediate.", with a fix for 32-bit x86.
Teach X86InstrInfo::analyzeCompare() not to crash on CMP and SUB instructions
that take a global address operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286420
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Dylan McKay [Wed, 9 Nov 2016 23:46:52 +0000 (23:46 +0000)]
[AVR] Add a selection of CodeGen tests
Summary: This adds all of the CodeGen tests which currently pass.
Reviewers: arsenm, kparzysz
Subscribers: japaric, wdng
Differential Revision: https://reviews.llvm.org/D26388
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286418
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Dylan McKay [Wed, 9 Nov 2016 23:46:25 +0000 (23:46 +0000)]
[AVR] Add all of the machine code test suite
Summary: This adds all of the AVR machine code tests.
Reviewers: arsenm, kparzysz
Subscribers: wdng, japaric
Differential Revision: https://reviews.llvm.org/D26387
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286417
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Dehao Chen [Wed, 9 Nov 2016 23:36:02 +0000 (23:36 +0000)]
Add isHotBB helper function to ProfileSummaryInfo
Summary: This will unify all BB hotness checks.
Reviewers: eraman, davidxl
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D26353
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286415
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Eli Friedman [Wed, 9 Nov 2016 23:05:01 +0000 (23:05 +0000)]
Preserve assumption cache in loop-rotate.
No testcase included because I can't figure out how to reduce it.
(It's easy to write a testcase where rotation clones an assume,
but that doesn't actually seem to trigger the crash in opt on
its own; maybe an issue with the laziness?)
Differential Revision: https://reviews.llvm.org/D26434
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286410
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Tim Northover [Wed, 9 Nov 2016 22:40:02 +0000 (22:40 +0000)]
GlobalISel: fix typo. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286408
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Tim Northover [Wed, 9 Nov 2016 22:39:54 +0000 (22:39 +0000)]
GlobalISel: translate invoke and landingpad instructions
Pretty bare-bones support for exception handling (no weird MSVC stuff, no SjLj
etc), but it should get things going.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286407
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Dehao Chen [Wed, 9 Nov 2016 22:25:19 +0000 (22:25 +0000)]
Update vectorization debug info unittest.
Summary:
The change will test the change in r286159.
The idea behind the change: Make the dbg location different between loop header and preheader/exit. Originally, dbg location 21 exists in 3 BBs: preheader, header, critical edge (exit). Update the debug location of inside the loop header from !21 to !22 so that it will reflect the correct location.
Reviewers: probinson
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D26428
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286403
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Sanjay Patel [Wed, 9 Nov 2016 22:21:58 +0000 (22:21 +0000)]
[InstCombine] regenerate checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286402
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Sanjay Patel [Wed, 9 Nov 2016 21:41:34 +0000 (21:41 +0000)]
[InstCombine] regenerate checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286399
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Davide Italiano [Wed, 9 Nov 2016 21:30:33 +0000 (21:30 +0000)]
[tools] Unbreak the GCC build (workaround a GCC bug).
../tools/llvm-extract/llvm-extract.cpp: In function ‘int main(int, char**)’:
warning: ISO C++ forbids zero-size array ‘argv’ [-Wpedantic]
GCC reference bug https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61259
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286396
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Mehdi Amini [Wed, 9 Nov 2016 21:26:49 +0000 (21:26 +0000)]
Make BitcodeReader::parseIdentificationBlock() robust to EOF
This method is particular: it iterates at the top-level and does
not have an enclosing block.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286394
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Evgeny Stupachenko [Wed, 9 Nov 2016 19:56:39 +0000 (19:56 +0000)]
Minor unroll pass refacoring.
Summary:
Unrolled Loop Size calculations moved to a function.
Constant representing number of optimized instructions
when "back edge" becomes "fall through" replaced with
variable.
Some comments added.
Reviewers: mzolotukhin
Differential Revision: http://reviews.llvm.org/D21719
From: Evgeny Stupachenko <evstupac@gmail.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286389
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Sanjoy Das [Wed, 9 Nov 2016 19:36:39 +0000 (19:36 +0000)]
[Verifier] clang-format a section; NFC
Suggested in D26438 since I'm touching related code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286388
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Sanjoy Das [Wed, 9 Nov 2016 18:22:43 +0000 (18:22 +0000)]
[SCEV] Refactor out a useful pattern; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286386
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Peter Collingbourne [Wed, 9 Nov 2016 18:17:50 +0000 (18:17 +0000)]
Revert r286384, "X86: Introduce the "relocImm" ComplexPattern, which represents a relocatable immediate."
Suspected to be the cause of a sanitizer-windows bot failure:
Assertion failed: isImm() && "Wrong MachineOperand accessor", file C:\b\slave\sanitizer-windows\llvm\include\llvm/CodeGen/MachineOperand.h, line 420
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286385
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Peter Collingbourne [Wed, 9 Nov 2016 17:51:58 +0000 (17:51 +0000)]
X86: Introduce the "relocImm" ComplexPattern, which represents a relocatable immediate.
A relocatable immediate is either an immediate operand or an operand that
can be relocated by the linker to an immediate, such as a regular symbol
in non-PIC code.
Start using relocImm for 32-bit and 64-bit MOV instructions, and for operands
of type "imm32_su". Remove a number of now-redundant patterns.
Differential Revision: https://reviews.llvm.org/D25812
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286384
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Krzysztof Parzyszek [Wed, 9 Nov 2016 17:50:46 +0000 (17:50 +0000)]
[Hexagon] Silence "sometimes uninitialized" warning in HexagonCopyToCombine
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286383
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Peter Collingbourne [Wed, 9 Nov 2016 17:49:19 +0000 (17:49 +0000)]
Bitcode: Change the materializer interface to return llvm::Error.
Differential Revision: https://reviews.llvm.org/D26439
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286382
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Krzysztof Parzyszek [Wed, 9 Nov 2016 16:19:08 +0000 (16:19 +0000)]
[Hexagon] Separate Hexagon subreg indices for different register classes
For pairs of 32-bit registers: isub_lo, isub_hi.
For pairs of vector registers: vsub_lo, vsub_hi.
Add generic subreg indices: ps_sub_lo, ps_sub_hi, and a function
HexagonRegisterInfo::getHexagonSubRegIndex(RegClass, GenericSubreg)
that returns the appropriate subreg index for RegClass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286377
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Krzysztof Parzyszek [Wed, 9 Nov 2016 14:16:29 +0000 (14:16 +0000)]
[Hexagon] Eliminate Insert4 pseudo-instruction, use combines instead
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286368
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Jonas Paulsson [Wed, 9 Nov 2016 12:47:57 +0000 (12:47 +0000)]
[SystemZ] A few fixes in scheduler files.
Review: U Weigand
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286362
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Pavel Labath [Wed, 9 Nov 2016 12:07:12 +0000 (12:07 +0000)]
Remove TimeValue usage from Scalar/SROA.cpp. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286361
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Pavel Labath [Wed, 9 Nov 2016 11:43:57 +0000 (11:43 +0000)]
Zero-initialize chrono duration objects
The default duration constructor does not zero-initialize the object, we need to
do that manually.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286359
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Pavel Labath [Wed, 9 Nov 2016 11:43:52 +0000 (11:43 +0000)]
[dsymutil] Replace TimeValue with TimePoint
Summary:
All changes are pretty straight-forward. I chose to use TimePoints with
second precision, as that is all that seems to be required here.
Reviewers: friss, zturner
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D25908
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286358
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Simon Atanasyan [Wed, 9 Nov 2016 10:14:55 +0000 (10:14 +0000)]
[mips] Add non-const getter for the Elf_Mips_Options class. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286351
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Jonas Paulsson [Wed, 9 Nov 2016 09:59:27 +0000 (09:59 +0000)]
[MachineScheduler] Comments fixing.
The name/comment of the third argument to the ScheduleDAGMI constructor
is RemoveKillFlags and not IsPostRA. Only the comments are changed.
Review: A Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286350
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Alexandros Lamprineas [Wed, 9 Nov 2016 08:53:07 +0000 (08:53 +0000)]
[ARM] Loop Strength Reduction crashes when targeting ARM or Thumb.
Scalar Evolution asserts when not all the operands of an Add Recurrence
Expression are loop invariants. Loop Strength Reduction should only
create affine Add Recurrences, so that both the start and the step of
the expression are loop invariants.
Differential Revision: https://reviews.llvm.org/D26185
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286347
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Craig Topper [Wed, 9 Nov 2016 07:48:51 +0000 (07:48 +0000)]
[AVX-512] Add lowering to cvttpd2udq/cvttps2udq for fptoui v2f64/2f32 to 2i32
This patch adds support for fptoui to 2i32 from both 2f64 and 2f32, building on Simon's change for the signed version in r284459 and using AVX-512 instructions.
If we don't have VLX support we need to use a 512-bit operation for v2f64->v2i32 and extract the result.
It also recognises that cvttpd2udq zeroes the upper 64-bits of the xmm result.
Differential Revision: https://reviews.llvm.org/D26331
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286345
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Craig Topper [Wed, 9 Nov 2016 07:31:32 +0000 (07:31 +0000)]
[X86] Lower AVX512 and SSE intrinsics for CVTTPD2DQ to X86ISD::CVTTPD2DQ.
Summary: This allows the SSE intrinsic to use the EVEX instruction when available. It also fixes EVEX to not use a weird (v4i32 (fp_to_sint v2f64)) node and it merges some isel patterns. This also fixes some cases that weren't combining vzmovl with cvttpd2dq to remove extra moves.
Reviewers: delena, zvi, RKSimon
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D26330
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286344
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Craig Topper [Wed, 9 Nov 2016 05:38:47 +0000 (05:38 +0000)]
[AVX-512] Add more varied alignments to tests for storing the lower 128-bits of a 256 or 512-bit subvector extract.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286343
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Craig Topper [Wed, 9 Nov 2016 05:31:57 +0000 (05:31 +0000)]
[AVX-512] Use alignedstore256 in patterns that look for stores of the lower 256-bits of a 512-bit vector to use a 256-bit aligned store.
Previously we were only checking for 16 byte alignment instead of 32 byte alignment. Fixes PR30947.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286342
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Craig Topper [Wed, 9 Nov 2016 05:31:53 +0000 (05:31 +0000)]
[AVX-512] Add test cases to demonstrate PR30947. We accidentally use 32 byte aligned store instructions when the original store was only 16 byte aligned if the store is from the lower bits of a subvector extract.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286341
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Craig Topper [Wed, 9 Nov 2016 04:50:48 +0000 (04:50 +0000)]
[AVX-512] Make VBMI instruction set enabling imply that the BWI instruction set is also enabled.
Summary:
This is needed to make the v64i8 and v32i16 types legal for the 512-bit VBMI instructions. Fixes PR30912.
Reviewers: delena, zvi
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D26322
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286339
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Dean Michael Berris [Wed, 9 Nov 2016 02:12:13 +0000 (02:12 +0000)]
[XRay][docs] Fix llvm snippets to be well-formed
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286330
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Mehdi Amini [Wed, 9 Nov 2016 01:45:13 +0000 (01:45 +0000)]
Revert "[ThinLTO] Prevent exporting of locals used/defined in module level asm"
This reverts commit r286297.
Introduces a dependency from libAnalysis to libObject, which I missed
during the review.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286329
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Mehdi Amini [Wed, 9 Nov 2016 01:44:42 +0000 (01:44 +0000)]
[doc] Remove explicit CMake version requirement for MSVC
The global minimum one is way past this version.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286328
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Peter Collingbourne [Wed, 9 Nov 2016 01:09:11 +0000 (01:09 +0000)]
Bitcode: Remove the remnants of the BitcodeDiagnosticInfo class.
The BitcodeReader no longer produces BitcodeDiagnosticInfo diagnostics.
The only remaining reference was in the gold plugin; the code there has been
dead since we stopped producing InvalidBitcodeSignature error codes in r225562.
While at it remove the InvalidBitcodeSignature error code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286326
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Dehao Chen [Wed, 9 Nov 2016 00:58:19 +0000 (00:58 +0000)]
Enable Loop Sink pass for functions that has profile.
Summary: For functions with profile data, we are confident that loop sink will be optimal in sinking code.
Reviewers: davidxl, hfinkel
Subscribers: mehdi_amini, mzolotukhin, llvm-commits
Differential Revision: https://reviews.llvm.org/D26155
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286325
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Peter Collingbourne [Wed, 9 Nov 2016 00:51:04 +0000 (00:51 +0000)]
Bitcode: Change the BitcodeReader to use llvm::Error internally.
Differential Revision: https://reviews.llvm.org/D26430
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286323
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Dean Michael Berris [Wed, 9 Nov 2016 00:24:58 +0000 (00:24 +0000)]
[XRay][Docs] Add documentation for XRay in LLVM
Summary:
This is the initial version of the documentation for how to use XRay as
it stands in LLVM, Clang, and compiler-rt. We leave some room for later
expansion mentioining what is work in progress and what could be
expected moving forward.
We also give a high level overview of future work that's both ongoing
and planned.
Reviewers: echristo, dblaikie, chandlerc
Subscribers: mehdi_amini, llvm-commits
Differential Revision: https://reviews.llvm.org/D26386
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286319
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Sanjay Patel [Wed, 9 Nov 2016 00:24:44 +0000 (00:24 +0000)]
[ValueTracking] recognize obfuscated variants of umin/umax
The smallest tests that expose this are codegen tests (because SelectionDAGBuilder::visitSelect() uses matchSelectPattern
to create UMAX/UMIN nodes), but it's also possible to see the effects in IR alone with folds of min/max pairs.
If these were written as unsigned compares in IR, InstCombine canonicalizes the unsigned compares to signed compares.
Ie, running the optimizer pessimizes the codegen for this case without this patch:
define <4 x i32> @umax_vec(<4 x i32> %x) {
%cmp = icmp ugt <4 x i32> %x, <i32
2147483647, i32
2147483647, i32
2147483647, i32
2147483647>
%sel = select <4 x i1> %cmp, <4 x i32> %x, <4 x i32> <i32
2147483647, i32
2147483647, i32
2147483647, i32
2147483647>
ret <4 x i32> %sel
}
$ ./opt umax.ll -S | ./llc -o - -mattr=avx
vpmaxud LCPI0_0(%rip), %xmm0, %xmm0
$ ./opt -instcombine umax.ll -S | ./llc -o - -mattr=avx
vpxor %xmm1, %xmm1, %xmm1
vpcmpgtd %xmm0, %xmm1, %xmm1
vmovaps LCPI0_0(%rip), %xmm2 ## xmm2 = [
2147483647,
2147483647,
2147483647,
2147483647]
vblendvps %xmm1, %xmm0, %xmm2, %xmm0
Differential Revision: https://reviews.llvm.org/D26096
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286318
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Mehdi Amini [Wed, 9 Nov 2016 00:23:20 +0000 (00:23 +0000)]
[cmake] Fix handling compiler-rt in LLVM_ENABLE_PROJECTS by turning any "-" into "_"
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286317
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Greg Clayton [Wed, 9 Nov 2016 00:15:54 +0000 (00:15 +0000)]
Added the ability to dump hex bytes easily into a raw_ostream.
Unit tests were added to verify this functionality keeps working correctly.
Example output for raw hex bytes:
llvm::ArrayRef<uint8_t> Bytes = ...;
llvm::outs() << format_hex_bytes(Bytes);
554889e5 4881ec70 04000048 8d051002
00004c8d 05fd0100 004c8b0d d0020000
Example output for raw hex bytes with offsets:
llvm::outs() << format_hex_bytes(Bytes, 0x100000d10);
0x0000000100000d10:
554889e5 4881ec70 04000048 8d051002
0x0000000100000d20:
00004c8d 05fd0100 004c8b0d d0020000
Example output for raw hex bytes with ASCII with offsets:
llvm::outs() << format_hex_bytes_with_ascii(Bytes, 0x100000d10);
0x0000000100000d10:
554889e5 4881ec70 04000048 8d051002 |UH.?H.?p...H....|
0x0000000100000d20:
00004c8d 05fd0100 004c8b0d d0020000 |..L..?...L..?...|
The default groups bytes into 4 byte groups, but this can be changed to 1 byte:
llvm::outs() << format_hex_bytes(Bytes, 0x100000d10, 16 /*NumPerLine*/, 1 /*ByteGroupSize*/);
0x0000000100000d10: 55 48 89 e5 48 81 ec 70 04 00 00 48 8d 05 10 02
0x0000000100000d20: 00 00 4c 8d 05 fd 01 00 00 4c 8b 0d d0 02 00 00
llvm::outs() << format_hex_bytes(Bytes, 0x100000d10, 16 /*NumPerLine*/, 2 /*ByteGroupSize*/);
0x0000000100000d10: 5548 89e5 4881 ec70 0400 0048 8d05 1002
0x0000000100000d20: 0000 4c8d 05fd 0100 004c 8b0d d002 0000
llvm::outs() << format_hex_bytes(Bytes, 0x100000d10, 8 /*NumPerLine*/, 1 /*ByteGroupSize*/);
0x0000000100000d10: 55 48 89 e5 48 81 ec 70
0x0000000100000d18: 04 00 00 48 8d 05 10 02
0x0000000100000d20: 00 00 4c 8d 05 fd 01 00
0x0000000100000d28: 00 4c 8b 0d d0 02 00 00
https://reviews.llvm.org/D26405
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286316
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Sanjay Patel [Wed, 9 Nov 2016 00:13:11 +0000 (00:13 +0000)]
[InstCombine] fix profitability equation for max-of-nots transform
As the test change shows, we can increase the critical path by adding
a 'not' instruction, so make sure that we're actually removing an
instruction if we do this transform.
This transform could also cause us to miss folds of min/max pairs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286315
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Sanjay Patel [Tue, 8 Nov 2016 23:49:15 +0000 (23:49 +0000)]
[InstCombine] reduce indentation; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286314
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Zachary Turner [Tue, 8 Nov 2016 22:30:11 +0000 (22:30 +0000)]
Fix some size_t / uint32_t ambiguity errors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286305
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Zachary Turner [Tue, 8 Nov 2016 22:24:53 +0000 (22:24 +0000)]
[CodeView] Hook up CodeViewRecordIO to type serialization path.
Previously support had been added for using CodeViewRecordIO
to read (deserialize) CodeView type records. This patch adds
support for writing those same records. With this patch,
reading and writing of CodeView type records finally uses a single
codepath.
Differential Revision: https://reviews.llvm.org/D26253
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286304
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Adrian Prantl [Tue, 8 Nov 2016 22:11:38 +0000 (22:11 +0000)]
Emit the DW_AT_type for a C++ static member definition
if it is more specific than the one in its DW_AT_specification.
If a static member is an array, the translation unit containing the
member definition may have a more specific type (including its length)
than TUs only seeing the class declaration. This patch adds a
DW_AT_type to the member's DW_TAG_variable in addition to the
DW_AT_specification in these cases. The member type in the
DW_AT_specification still shows the more generic type (without the
length) to avoid defeating type uniquing.
The DWARF standard discourages “duplicating” a DW_AT_type in a member
variable definition but doesn’t explicitly forbid it. Having the more
specific type (with the array length) available is what allows the
debugger to print the contents of a static array member variable.
https://reviews.llvm.org/D26368
rdar://problem/
28706946
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286302
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David L. Jones [Tue, 8 Nov 2016 22:03:23 +0000 (22:03 +0000)]
GlobalISel: make sure debugging variables are appropriately elided in release builds.
Summary:
There are two variables here that break. This change constrains both of them to
debug builds (via DEBUG() or #ifndef NDEBUG).
Reviewers: bkramer, t.p.northover
Subscribers: mehdi_amini, vkalintiris
Differential Revision: https://reviews.llvm.org/D26421
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286300
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Kostya Serebryany [Tue, 8 Nov 2016 21:57:37 +0000 (21:57 +0000)]
[libFuzzer] minor docs update
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286299
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Teresa Johnson [Tue, 8 Nov 2016 21:53:35 +0000 (21:53 +0000)]
[ThinLTO] Prevent exporting of locals used/defined in module level asm
Summary:
This patch uses the same approach added for inline asm in r285513 to
similarly prevent promotion/renaming of locals used or defined in module
level asm.
All static global values defined in normal IR and used in module level asm
should be included on either the llvm.used or llvm.compiler.used global.
The former were already being flagged as NoRename in the summary, and
I've simply added llvm.compiler.used values to this handling.
Module level asm may also contain defs of values. We need to prevent
export of any refs to local values defined in module level asm (e.g. a
ref in normal IR), since that also requires renaming/promotion of the
local. To do that, the summary index builder looks at all values in the
module level asm string that are not marked Weak or Global, which is
exactly the set of locals that are defined. A summary is created for
each of these local defs and flagged as NoRename.
This required adding handling to the BitcodeWriter to look at GV
declarations to see if they have a summary (rather than skipping them
all).
Finally, added an assert to IRObjectFile::CollectAsmUndefinedRefs to
ensure that an MCAsmParser is available, otherwise the module asm parse
would silently fail. Initialized the asm parser in the opt tool for use
in testing this fix.
Fixes PR30610.
Reviewers: mehdi_amini
Subscribers: johanengelen, krasin, llvm-commits
Differential Revision: https://reviews.llvm.org/D26146
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286297
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Kuba Brecka [Tue, 8 Nov 2016 21:30:41 +0000 (21:30 +0000)]
[asan] Speed up compilation of large C++ stringmaps (tons of allocas) with ASan
This addresses PR30746, <https://llvm.org/bugs/show_bug.cgi?id=30746>. The ASan pass iterates over entry-block instructions and checks each alloca whether it's in NonInstrumentedStaticAllocaVec, which is apparently slow. This patch gathers the instructions to move during visitAllocaInst.
Differential Revision: https://reviews.llvm.org/D26380
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286296
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Andrew Kaylor [Tue, 8 Nov 2016 21:07:42 +0000 (21:07 +0000)]
[BasicAA] Teach BasicAA to handle the inaccessiblememonly and inaccessiblemem_or_argmemonly attributes
Differential Revision: https://reviews.llvm.org/D26382
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286294
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Matthias Braun [Tue, 8 Nov 2016 20:59:03 +0000 (20:59 +0000)]
AArch64DeadRegisterDefinitionsPass: Fix Changed flag
Fix a bug in the calculation of the changed flag introduced in r285488.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286293
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Adrian Prantl [Tue, 8 Nov 2016 20:48:38 +0000 (20:48 +0000)]
Use a default constructor. (NFC)
Thanks to David Blaikie for suggesting this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286292
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Sanjoy Das [Tue, 8 Nov 2016 20:46:01 +0000 (20:46 +0000)]
[TBAA] Drop support for "old style" scalar TBAA tags
Summary:
We've had support for auto upgrading old style scalar TBAA access
metadata tags into the "new" struct path aware TBAA metadata for 3 years
now. The only way to actually generate old style TBAA was explicitly
through the IRBuilder API. I think this is a good time for dropping
support for old style scalar TBAA.
I'm not removing support for textual or bitcode upgrade -- if you have
IR with the old style scalar TBAA tags that go through the AsmParser orf
the bitcode parser before LLVM sees them, they will keep working as
usual.
Note:
%val = load i32, i32* %ptr, !tbaa !N
!N = < scalar tbaa node >
is equivalent to
%val = load i32, i32* %ptr, !tbaa !M
!N = < scalar tbaa node >
!M = !{!N, !N, 0}
Reviewers: manmanren, chandlerc, sunfish
Subscribers: mcrosier, llvm-commits, mgorny
Differential Revision: https://reviews.llvm.org/D26229
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286291
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Tim Northover [Tue, 8 Nov 2016 20:39:03 +0000 (20:39 +0000)]
GlobalISel: allow CodeGen to fallback on VReg type/class issues.
After instruction selection we perform some checks on each VReg just before
discarding the type information. These checks were assertions before, but that
breaks the fallback path so this patch moves the logic into the main flow and
reports a better error on failure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286289
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Ulrich Weigand [Tue, 8 Nov 2016 20:18:41 +0000 (20:18 +0000)]
[SystemZ] Add missing FP extension instructions
This completes assembler / disassembler support for all BFP
instructions provided by the floating-point extensions facility.
The instructions added here are not currently used for codegen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286285
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Ulrich Weigand [Tue, 8 Nov 2016 20:17:02 +0000 (20:17 +0000)]
[SystemZ] Add program mask and addressing mode instructions
Add several instructions that operate on the program mask
or the addressing mode. These are not really needed for
code generation under Linux, but are provided for completeness
for the assembler/disassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286284
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Ulrich Weigand [Tue, 8 Nov 2016 20:15:26 +0000 (20:15 +0000)]
[SystemZ] Model access registers as LLVM registers
Add the 16 access registers as LLVM registers. This allows removing
a lot of special cases in the assembler and disassembler where we
were handling access registers; this can all just use the generic
register code now.
Also add a bunch of instructions to operate on access registers,
for assembler/disassembler use only. No change in code generation
intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286283
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Davide Italiano [Tue, 8 Nov 2016 19:52:32 +0000 (19:52 +0000)]
[LoopDistribute] Preserve GlobalsAA also in the new Pass Manager.
Differential Revision: https://reviews.llvm.org/D26408
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286280
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Eli Friedman [Tue, 8 Nov 2016 19:43:56 +0000 (19:43 +0000)]
Don't store Twine in a local variable.
Fixes post-commit review comment from r286177.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286275
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Dan Gohman [Tue, 8 Nov 2016 19:40:38 +0000 (19:40 +0000)]
[WebAssembly] Convert stackified IMPLICIT_DEF into constant 0.
Since IMPLIFIT_DEF instructions are omitted in the output, when the output
of an IMPLICIT_DEF instruction is stackified, the resulting register lacks
an explicit push, leading to a push/pop mismatch. Fix this by converting
such IMPLICIT_DEFs into CONST_I32 0 instructions so that they have explicit
pushes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286274
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Ahmed Bougacha [Tue, 8 Nov 2016 19:27:13 +0000 (19:27 +0000)]
[GlobalISel] Dump all instructions inserted by selector.
This is helpful when multiple instructions are inserted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286273
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Ahmed Bougacha [Tue, 8 Nov 2016 19:27:10 +0000 (19:27 +0000)]
[GlobalISel] Permit select() to erase.
Erasing reverse_iterators is problematic; iterate manually.
While there, keep track of the range of inserted instructions.
It can miss instructions inserted elsewhere, but those are harder
to track.
Differential Revision: http://reviews.llvm.org/D22924
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286272
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Davide Italiano [Tue, 8 Nov 2016 19:18:20 +0000 (19:18 +0000)]
[LibcallsShrinkWrap] This pass doesn't preserve the CFG.
For example, it invalidates the domtree, causing assertions
in later passes which need dominator infos. Make it preserve
GlobalsAA, as suggested by Eli.
Differential Revision: https://reviews.llvm.org/D26381
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286271
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Chad Rosier [Tue, 8 Nov 2016 19:10:25 +0000 (19:10 +0000)]
Fix typo in comment. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286270
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Michael Kuperstein [Tue, 8 Nov 2016 18:44:40 +0000 (18:44 +0000)]
CODE_OWNERS: Take ownership of the loop vectorizer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286269
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Ulrich Weigand [Tue, 8 Nov 2016 18:37:48 +0000 (18:37 +0000)]
[SystemZ] Always use semantic instruction classes
Define a couple of additional semantic classes and use them
throughout the .td files to make them more consistent and
more easily readable.
No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286268
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Ulrich Weigand [Tue, 8 Nov 2016 18:36:31 +0000 (18:36 +0000)]
[SystemZ] Refactor InstRR* instruction format patterns
This changes the InstRR (and related) patterns to no longer
automatically add an "r" at the end of the mnemonic. This
makes the .td files more obviously understandable, and also
allows using the patterns for those few instructions that
do not follow the *r scheme.
Also add some more sub-formats of the RRF format class, to
match operand names and sequence from the PoP better.
No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286267
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Ulrich Weigand [Tue, 8 Nov 2016 18:32:50 +0000 (18:32 +0000)]
[SystemZ] Rename some Inst* instruction format classes
Now that we've added instruction format subclasses like
InstRIb, it makes sense to rename the old InstRI to InstRIa.
Similar for InstRX, InstRXY, InstRS, InstRSY, and InstSS.
No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286266
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Nirav Dave [Tue, 8 Nov 2016 18:31:04 +0000 (18:31 +0000)]
[MC][AArch64] Cleanup end-of-line parsing in AArch64 AsmParser.
Reviewers: t.p.northover, rengolin
Subscribers: llvm-commits, aemerson
Differential Revision: https://reviews.llvm.org/D26309
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286265
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Ulrich Weigand [Tue, 8 Nov 2016 18:30:50 +0000 (18:30 +0000)]
[SystemZ] Refactor branch and conditional instruction patterns
Rework patterns for branches, call & return instructions,
compare-and-branch, compare-and-trap, and conditional move
instructions.
In particular, simplify creation of patterns for the extended
opcodes of instructions that take a CC mask.
Also, use semantical instruction classes for all the instructions
instead of open-coding them in SystemZInstrInfo.td.
Adds a couple of the basic branch instructions (that are unused
for codegen) for the assembler/disassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286263
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Piotr Padlewski [Tue, 8 Nov 2016 18:20:51 +0000 (18:20 +0000)]
NFC small changes in MemDep
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286260
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Wei Mi [Tue, 8 Nov 2016 18:19:36 +0000 (18:19 +0000)]
[RegAllocGreedy] Another fix about NewVRegs for last chance recoloring after r281783.
About when we should move a vreg from CurrentNewVRegs to NewVRegs,
if the vreg in CurrentNewVRegs was added into RecoloringCandidate and was
evicted, it shouldn't be added to NewVRegs because its physical register
will be restored at the end of tryLastChanceRecoloring after the recoloring
failed. If the vreg in CurrentNewVRegs was not in RecoloringCandidate, i.e.
it was evicted in selectOrSplitImpl inside tryRecoloringCandidates, its
physical register will not be restored even if the recoloring failed. In
that case, we need to add the vreg to NewVRegs.
Same as r281783, the problem was seen on out-of-tree target and we didn't
have a test case that reproduce the problem with in-tree targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286259
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Sanjay Patel [Tue, 8 Nov 2016 18:12:19 +0000 (18:12 +0000)]
[InstCombine] move min/max tests to min/max test file; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286256
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Sanjay Patel [Tue, 8 Nov 2016 18:06:14 +0000 (18:06 +0000)]
[InstCombine] update checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286255
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Tim Northover [Tue, 8 Nov 2016 17:44:07 +0000 (17:44 +0000)]
GlobalISel: support selecting fpext/fptrunc instructions on AArch64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286253
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Anton Korobeynikov [Tue, 8 Nov 2016 17:19:59 +0000 (17:19 +0000)]
Fix PR27500: on MSP430 the branch destination offset is measured in words, not bytes.
Summary: In addition, the branch instructions will have proper BB destinations, not offsets, like before.
Reviewers: asl
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D23718
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286252
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Chad Rosier [Tue, 8 Nov 2016 16:51:19 +0000 (16:51 +0000)]
Remove unused include. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286250
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Sanjay Patel [Tue, 8 Nov 2016 16:49:24 +0000 (16:49 +0000)]
[docs] fix link to AMD manuals (PR30946)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286249
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Dehao Chen [Tue, 8 Nov 2016 16:32:32 +0000 (16:32 +0000)]
Use the last 7 bits to represent the discriminator to fit it in 1 byte ULEB128 (NFC).
From experiments, discriminator is rarely greater than 127. Here we enforce it to be no greater than 127 so that it will always fit in 1 byte.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286245
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Simon Pilgrim [Tue, 8 Nov 2016 15:42:49 +0000 (15:42 +0000)]
[X86][SSE] Regenerate test (just adds missing header)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286241
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Simon Pilgrim [Tue, 8 Nov 2016 15:07:01 +0000 (15:07 +0000)]
[TargetLowering] Fix undef vector element issue with true/false result handling
Fixed an issue with vector usage of TargetLowering::isConstTrueVal / TargetLowering::isConstFalseVal boolean result matching.
The comment said we shouldn't handle constant splat vectors with undef elements. But the the actual code was returning false if the build vector contained no undef elements....
This patch now ignores the number of undefs (getConstantSplatNode will return null if the build vector is all undefs).
The change has also unearthed a couple of missed opportunities in AVX512 comparison code that will need to be addressed.
Differential Revision: https://reviews.llvm.org/D26031
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286238
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Pablo Barrio [Tue, 8 Nov 2016 14:53:30 +0000 (14:53 +0000)]
[JumpThreading] Unfold selects that depend on the same condition
Summary:
These are good candidates for jump threading. This enables later opts
(such as InstCombine) to combine instructions from the selects with
instructions out of the selects. SimplifyCFG will fold the select
again if unfolding wasn't worth it.
Patch by James Molloy and Pablo Barrio.
Reviewers: rengolin, haicheng, sebpop
Subscribers: jojo, jmolloy, llvm-commits
Differential Revision: https://reviews.llvm.org/D26391
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286236
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Simon Pilgrim [Tue, 8 Nov 2016 14:10:28 +0000 (14:10 +0000)]
[VectorLegalizer] Expansion of CTLZ using CTPOP when possible
This patch avoids scalarization of CTLZ by instead expanding to use CTPOP (ref: "Hacker's Delight") when the necessary operations are available.
This also adds the necessary cost models for X86 SSE2 targets (the main beneficiary) to ensure vectorization only happens when its useful.
Differential Revision: https://reviews.llvm.org/D25910
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286233
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Rafael Espindola [Tue, 8 Nov 2016 14:04:16 +0000 (14:04 +0000)]
cleanup hashSysV a bit.
Don't pass a reference to a StringRef and use a range loop.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286232
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