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Chris Lattner [Sat, 5 May 2012 22:04:11 +0000 (22:04 +0000)]
add missing header <shame>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156244
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Chris Lattner [Sat, 5 May 2012 21:39:51 +0000 (21:39 +0000)]
refactor some code to expose column numbers more and make diagnostic printing slightly more efficient.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156243
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Jim Grosbach [Sat, 5 May 2012 17:45:12 +0000 (17:45 +0000)]
Nuke a few dead remnants of the CBE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156241
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Daniel Dunbar [Sat, 5 May 2012 16:49:11 +0000 (16:49 +0000)]
[Support] Add missing include.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156240
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Daniel Dunbar [Sat, 5 May 2012 16:39:22 +0000 (16:39 +0000)]
[Support] Fix up comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156239
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Daniel Dunbar [Sat, 5 May 2012 16:36:24 +0000 (16:36 +0000)]
[Support] Rewrite sys::fs::unique_file to not be stupid with /dev/urandom.
- Just use sys::Process::GetRandomNumber instead of having two poor
implementations.
- This is ~70 times (!) faster on my OS X machine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156238
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Daniel Dunbar [Sat, 5 May 2012 16:36:20 +0000 (16:36 +0000)]
[Support] Add sys::Process::GetRandomNumber().
- Primitive API, but we rarely have need for random numbers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156237
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Daniel Dunbar [Sat, 5 May 2012 16:36:16 +0000 (16:36 +0000)]
[build] Add build check for ::arc4random().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156236
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Benjamin Kramer [Sat, 5 May 2012 15:02:39 +0000 (15:02 +0000)]
Update all outdated autoconf files in the sample project.
We might just use symlinks here, but I'm afraid of possible portability issues.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156235
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Benjamin Kramer [Sat, 5 May 2012 12:49:22 +0000 (12:49 +0000)]
CodeGenPrepare: Add a transform to turn selects into branches in some cases.
This came up when a change in block placement formed a cmov and slowed down a
hot loop by 50%:
ucomisd (%rdi), %xmm0
cmovbel %edx, %esi
cmov is a really bad choice in this context because it doesn't get branch
prediction. If we emit it as a branch, an out-of-order CPU can do a better job
(if the branch is predicted right) and avoid waiting for the slow load+compare
instruction to finish. Of course it won't help if the branch is unpredictable,
but those are really rare in practice.
This patch uses a dumb conservative heuristic, it turns all cmovs that have one
use and a direct memory operand into branches. cmovs usually save some code
size, so we disable the transform in -Os mode. In-Order architectures are
unlikely to benefit as well, those are included in the
"predictableSelectIsExpensive" flag.
It would be better to reuse branch probability info here, but BPI doesn't
support select instructions currently. It would make sense to use the same
heuristics as the if-converter pass, which does the opposite direction of this
transform.
Test suite shows a small improvement here and there on corei7-level machines,
but the actual results depend a lot on the used microarchitecture. The
transformation is currently disabled by default and available by passing the
-enable-cgp-select2branch flag to the code generator.
Thanks to Chandler for the initial test case to him and Evan Cheng for providing
me with comments and test-suite numbers that were more stable than mine :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156234
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Benjamin Kramer [Sat, 5 May 2012 12:49:14 +0000 (12:49 +0000)]
Add a new target hook "predictableSelectIsExpensive".
This will be used to determine whether it's profitable to turn a select into a
branch when the branch is likely to be predicted.
Currently enabled for everything but Atom on X86 and Cortex-A9 devices on ARM.
I'm not entirely happy with the name of this flag, suggestions welcome ;)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156233
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Benjamin Kramer [Sat, 5 May 2012 11:22:02 +0000 (11:22 +0000)]
NVPTX: Initialize the UseF32FTZ flag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156232
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Stepan Dyatkovskiy [Sat, 5 May 2012 07:09:40 +0000 (07:09 +0000)]
Small fix in InstCombineCasts.cpp. Restored "alloca + bitcast" reducing for case when alloca's size is calculated within the "add/sub/... nsw".
Also added fix to 2011-06-13-nsw-alloca.ll test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156231
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Eric Christopher [Sat, 5 May 2012 01:16:06 +0000 (01:16 +0000)]
Typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156226
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Jakob Stoklund Olesen [Fri, 4 May 2012 23:12:22 +0000 (23:12 +0000)]
Order register classes by spill size first, members last.
This is still a topological ordering such that every register class gets
a smaller enum value than its sub-classes.
Placing the smaller spill sizes first makes a difference for the
super-register class bit masks. When looking for a super-register class,
we usually want the smallest possible kind of super-register. That is
now available as the first bit set in the bit mask.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156222
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Jakob Stoklund Olesen [Fri, 4 May 2012 22:53:28 +0000 (22:53 +0000)]
Make sure findRepresentativeClass picks the widest super-register.
We want the representative register class to contain the largest
super-registers available. This makes the function less sensitive to the
register class numbering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156220
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Jakob Stoklund Olesen [Fri, 4 May 2012 22:53:26 +0000 (22:53 +0000)]
Remove extra comma in debug output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156219
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David Blaikie [Fri, 4 May 2012 22:34:16 +0000 (22:34 +0000)]
Fix warnings in release build.
This fixes a couple of Clang warnings in release builds of LLVM:
* Missing return in ISelLowering
* Unused variable in NVPTXutil.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156216
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Kevin Enderby [Fri, 4 May 2012 22:09:52 +0000 (22:09 +0000)]
Tweak to the fix in r156212, as with the change in removing the shift the
SignExtend32<22>(Val<<1) also needs to change to SignExtend32<21>(Val) .
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156213
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Kevin Enderby [Fri, 4 May 2012 22:02:27 +0000 (22:02 +0000)]
Fix a bug in the ARM disassembler for wide branch conditional instructions
where the symbolic operand's displacement was incorrectly shifted left by 1.
rdar://
11387046
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156212
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Chandler Carruth [Fri, 4 May 2012 21:35:49 +0000 (21:35 +0000)]
Fix a Clang warning in the new NVPTX backend:
In file included from ../lib/Target/NVPTX/VectorElementize.cpp:53:
../lib/Target/NVPTX/NVPTX.h:44:3: warning: default label in switch which covers all enumeration values [-Wcovered-switch-default]
default: assert(0 && "Unknown condition code");
^
1 warning generated.
The prevailing pattern in LLVM is to not use a default label, and instead to
use llvm_unreachable to denote that the switch in fact covers all return paths
from the function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156209
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Chandler Carruth [Fri, 4 May 2012 21:33:30 +0000 (21:33 +0000)]
Teach the code extractor how to extract a sequence of blocks from
RegionInfo's RegionNode. This mirrors the logic for automating the
extraction from a Loop.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156208
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Chandler Carruth [Fri, 4 May 2012 20:55:23 +0000 (20:55 +0000)]
Rename the Region::block_iterator to Region::block_node_iterator, and
add a new Region::block_iterator which actually iterates over the basic
blocks of the region.
The old iterator, now call 'block_node_iterator' iterates over
RegionNodes which contain a single basic block. This works well with the
GraphTraits-based iterator design, however most users actually want an
iterator over the BasicBlocks inside these RegionNodes. Now the
'block_iterator' is a wrapper which exposes exactly this interface.
Internally it uses the block_node_iterator to walk all nodes which are
single basic blocks, but transparently unwraps the basic block to make
user code simpler.
While this patch is a bit of a wash, most of the updates are to internal
users, not external users of the RegionInfo. I have an accompanying
patch to Polly that is a strict simplification of every user of this
interface, and I'm working on a pass that also wants the same simplified
interface.
This patch alone should have no functional impact.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156202
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Justin Holewinski [Fri, 4 May 2012 20:18:50 +0000 (20:18 +0000)]
This patch adds a new NVPTX back-end to LLVM which supports code generation for NVIDIA PTX 3.0. This back-end will (eventually) replace the current PTX back-end, while maintaining compatibility with it.
The new target machines are:
nvptx (old ptx32) => 32-bit PTX
nvptx64 (old ptx64) => 64-bit PTX
The sources are based on the internal NVIDIA NVPTX back-end, and
contain more functionality than the current PTX back-end currently
provides.
NV_CONTRIB
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156196
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Sebastian Pop [Fri, 4 May 2012 19:53:56 +0000 (19:53 +0000)]
Added missing CMN case in Thumb2SizeReduction pass so that LLVM emits 16-bits encoding of CMN instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156195
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Preston Gurd [Fri, 4 May 2012 19:26:37 +0000 (19:26 +0000)]
Adds Intel Atom scheduling latencies to X86InstrSystem.td.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156194
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Matt Beaumont-Gay [Fri, 4 May 2012 18:34:27 +0000 (18:34 +0000)]
Pacify GCC's -Wreturn-type
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156189
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Chandler Carruth [Fri, 4 May 2012 11:20:27 +0000 (11:20 +0000)]
Factor the computation of input and output sets into a public interface
of the CodeExtractor utility. This allows speculatively computing input
and output sets to measure the likely size impact of the code
extraction.
These sets cannot be reused sadly -- we mutate the function prior to
forming the final sets used by the actual extraction.
The interface has been revamped slightly to make it easier to use
correctly by making the interface const and sinking the computation of
the number of exit blocks into the full extraction function and away
from the rest of this logic which just computed two output parameters.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156168
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Chandler Carruth [Fri, 4 May 2012 11:17:06 +0000 (11:17 +0000)]
Rather than trying to gracefully handle input sequences with repeated
blocks, assert that this doesn't happen. We don't want to bother trying
to support this call pattern as it isn't necessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156167
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Chandler Carruth [Fri, 4 May 2012 11:14:19 +0000 (11:14 +0000)]
Fix a goof with my previous commit by completely returning when we
detect an in-eligible block rather than just breaking out of the loop.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156166
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Chandler Carruth [Fri, 4 May 2012 10:26:45 +0000 (10:26 +0000)]
Hoist a safety assert from the extraction method into the construction
of the extractor itself.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156164
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Chandler Carruth [Fri, 4 May 2012 10:18:49 +0000 (10:18 +0000)]
Move the CodeExtractor utility to a dedicated header file / source file,
and expose it as a utility class rather than as free function wrappers.
The simple free-function interface works well for the bugpoint-specific
pass's uses of code extraction, but in an upcoming patch for more
advanced code extraction, they simply don't expose a rich enough
interface. I need to expose various stages of the process of doing the
code extraction and query information to decide whether or not to
actually complete the extraction or give up.
Rather than build up a new predicate model and pass that into these
functions, just take the class that was actually implementing the
functions and lift it up into a proper interface that can be used to
perform code extraction. The interface is cleaned up and re-documented
to work better in a header. It also is now setup to accept the blocks to
be extracted in the constructor rather than in a method.
In passing this essentially reverts my previous commit here exposing
a block-level query for eligibility of extraction. That is no longer
necessary with the more rich interface as clients can query the
extraction object for eligibility directly. This will reduce the number
of walks of the input basic block sequence by quite a bit which is
useful if this enters the normal optimization pipeline.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156163
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Hans Wennborg [Fri, 4 May 2012 09:40:39 +0000 (09:40 +0000)]
Make ARM and Mips use TargetMachine::getTLSModel()
This moves the logic for selecting a TLS model to a single place,
instead of the previous three (ARM, Mips, and X86 which already
uses this function).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156162
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Craig Topper [Fri, 4 May 2012 06:39:13 +0000 (06:39 +0000)]
Fix some loops to match coding standards. No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156159
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Craig Topper [Fri, 4 May 2012 06:18:33 +0000 (06:18 +0000)]
Fix up some spacing. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156158
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Craig Topper [Fri, 4 May 2012 05:49:51 +0000 (05:49 +0000)]
Simplify broadcast lowering code. No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156157
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Craig Topper [Fri, 4 May 2012 04:44:49 +0000 (04:44 +0000)]
Allow v16i16 and v32i8 shuffles to be rewritten as narrower shuffles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156156
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Bill Wendling [Fri, 4 May 2012 04:22:32 +0000 (04:22 +0000)]
Add 'landingpad' instructions to the list of instructions to ignore.
Also combine the code in the 'assert' statement.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156155
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Craig Topper [Fri, 4 May 2012 04:08:44 +0000 (04:08 +0000)]
Simplify shuffle narrowing code a bit. No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156154
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Jakob Stoklund Olesen [Fri, 4 May 2012 03:30:34 +0000 (03:30 +0000)]
Remove the SubRegClasses field from RegisterClass descriptions.
This information in now computed by TableGen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156152
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Jakob Stoklund Olesen [Fri, 4 May 2012 03:30:28 +0000 (03:30 +0000)]
Remove TargetRegisterClass::SuperRegClasses.
This manually enumerated list of super-register classes has been
superceeded by the automatically computed super-register class masks
available through SuperRegClassIterator.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156151
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Rafael Espindola [Fri, 4 May 2012 03:23:36 +0000 (03:23 +0000)]
Pass -fcolor-diagnostics when it is supported. This makes a difference when
using cmake+ninja, since ninja buffers the compiler output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156150
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Jakob Stoklund Olesen [Fri, 4 May 2012 02:19:22 +0000 (02:19 +0000)]
Use SuperRegClassIterator for findRepresentativeClass().
The masks returned by SuperRegClassIterator are computed automatically
by TableGen. This is better than depending on the manually specified
SuperRegClasses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156147
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Jakob Stoklund Olesen [Fri, 4 May 2012 02:16:39 +0000 (02:16 +0000)]
Initialize SparcInstrInfo before SparcTargetLowering.
The TargetLowering construction needs to use a valid TargetRegisterInfo
instance.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156146
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Jakob Stoklund Olesen [Fri, 4 May 2012 01:48:29 +0000 (01:48 +0000)]
Add a SuperRegClassIterator class.
This iterator class provides a more abstract interface to the (Idx,
Mask) lists of super-registers for a register class. The layout of the
tables shouldn't be exposed to clients.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156144
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Chandler Carruth [Fri, 4 May 2012 00:58:03 +0000 (00:58 +0000)]
A pile of long over-due refactorings here. There are some very, *very*
minor behavior changes with this, but nothing I have seen evidence of in
the wild or expect to be meaningful. The real goal is unifying our logic
and simplifying the interfaces. A summary of the changes follows:
- Make 'callIsSmall' actually accept a callsite so it can handle
intrinsics, and simplify callers appropriately.
- Nuke a completely bogus declaration of 'callIsSmall' that was still
lurking in InlineCost.h... No idea how this got missed.
- Teach the 'isInstructionFree' about the various more intelligent
'free' heuristics that got added to the inline cost analysis during
review and testing. This mostly surrounds int->ptr and ptr->int casts.
- Switch most of the interesting parts of the inline cost analysis that
were essentially computing 'is this instruction free?' to use the code
metrics routine instead. This way we won't keep duplicating logic.
All of this is motivated by the desire to allow other passes to compute
a roughly equivalent 'cost' metric for a particular basic block as the
inline cost analysis. Sadly, re-using the same analysis for both is
really messy because only the actual inline cost analysis is ever going
to go to the contortions required for simplification, SROA analysis,
etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156140
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Chandler Carruth [Thu, 3 May 2012 23:38:34 +0000 (23:38 +0000)]
Add a FoldingSetVector datastructure which is analogous to a SetVector,
but using a FoldingSet underneath and with a largely compatible
interface to that of FoldingSet. This can be used anywhere a FoldingSet
would be natural, but iteration order is significant. The initial
intended use case is in Clang's template specialization lists to
preserve instantiation order iteration.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156131
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Pete Cooper [Thu, 3 May 2012 23:20:10 +0000 (23:20 +0000)]
PR12729: Change 'llvm-objdump' to display the available targets.
Patch by Meador Inge.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156128
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Jakob Stoklund Olesen [Thu, 3 May 2012 22:49:58 +0000 (22:49 +0000)]
Remove accidentally added file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156124
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Jakob Stoklund Olesen [Thu, 3 May 2012 22:49:04 +0000 (22:49 +0000)]
Use a shared implementation of getMatchingSuperRegClass().
TargetRegisterClass now gives access to the necessary tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156122
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Jakob Stoklund Olesen [Thu, 3 May 2012 22:49:00 +0000 (22:49 +0000)]
Add TargetRegisterClass::getSuperRegIndices().
This is a pointer into one of the tables used by
getMatchingSuperRegClass(). It makes it possible to use a shared
implementation of that function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156121
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Jakob Stoklund Olesen [Thu, 3 May 2012 22:48:56 +0000 (22:48 +0000)]
Emit SuperRegMasks as part of the existing SubClassMask arrays.
The RC->getSubClassMask() pointer now points to a sequence of register
class bit masks. The first bit mask is the normal sub-class mask. The
following masks are super-reg class masks used by
getMatchingSuperRegClass().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156120
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Kevin Enderby [Thu, 3 May 2012 22:41:56 +0000 (22:41 +0000)]
Fix issues with the ARM bl and blx thumb instructions and the J1 and J2 bits
for the assembler and disassembler. Which were not being set/read correctly
for offsets greater than 22 bits in some cases.
Changes to lib/Target/ARM/ARMAsmBackend.cpp from Gideon Myles!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156118
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Chandler Carruth [Thu, 3 May 2012 22:26:53 +0000 (22:26 +0000)]
Factor the logic for testing whether a basic block is viable for code
extraction into a public interface. Also clean it up and apply it more
consistently such that we check for landing pads *anywhere* in the
extracted code, not just in single-block extraction.
This will be used to guide decisions in passes that are planning to
eventually perform a round of code extraction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156114
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Nuno Lopes [Thu, 3 May 2012 22:08:19 +0000 (22:08 +0000)]
remove calls to calloc if the allocated memory is not used (it was already being done for malloc)
fix a few typos found by Chad in my previous commit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156110
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Sirish Pande [Thu, 3 May 2012 21:52:53 +0000 (21:52 +0000)]
Support for target dependent Hexagon VLIW packetizer.
This patch creates and optimizes packets as per Hexagon ISA rules.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156109
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Ted Kremenek [Thu, 3 May 2012 21:51:05 +0000 (21:51 +0000)]
Add rudimentary CMake logic for detecting Graphviz.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156108
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Nuno Lopes [Thu, 3 May 2012 21:19:58 +0000 (21:19 +0000)]
add support for calloc to objectsize lowering
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156102
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Jakob Stoklund Olesen [Thu, 3 May 2012 18:17:32 +0000 (18:17 +0000)]
Fix the type of SubClassMask.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156084
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Jakob Stoklund Olesen [Thu, 3 May 2012 18:14:20 +0000 (18:14 +0000)]
Compress tables for getMatchingSuperRegClass().
Many register classes only have a few super-registers, so it is not
necessary to keep individual bit masks for all possible sub-register
indices.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156083
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Owen Anderson [Thu, 3 May 2012 17:24:12 +0000 (17:24 +0000)]
Add the half type to the LLVM IR vim syntax highlighting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156080
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Silviu Baranga [Thu, 3 May 2012 16:38:40 +0000 (16:38 +0000)]
Fixed disassembler for vstm/vldm ARM VFP instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156077
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Jakob Stoklund Olesen [Thu, 3 May 2012 16:26:20 +0000 (16:26 +0000)]
Don't override subreg functions in targets without subregisters.
Some targets have no sub-registers at all. Use the TargetRegisterInfo
versions of composeSubRegIndices(), getSubClassWithSubReg(), and
getMatchingSuperRegClass() for those targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156075
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Sirish Pande [Thu, 3 May 2012 16:18:50 +0000 (16:18 +0000)]
Extensions of Hexagon V4 instructions.
This adds new instructions for Hexagon V4 architecture.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156071
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Nuno Lopes [Thu, 3 May 2012 16:06:07 +0000 (16:06 +0000)]
replace 'break's with 'return 0' in visitCallInst code for objectsize, since there is no need to fallback to visitCallSite.
This gives a 0.9% in a test case
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156069
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Duncan Sands [Thu, 3 May 2012 15:25:19 +0000 (15:25 +0000)]
Use correct variable in this example. Pointed out by waynix on IRC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156067
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Craig Topper [Thu, 3 May 2012 07:26:59 +0000 (07:26 +0000)]
Use 'unsigned' instead of 'int' in a few places dealing with counts of vector elements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156060
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Craig Topper [Thu, 3 May 2012 07:12:59 +0000 (07:12 +0000)]
Fix 256-bit vpshuflw and vpshufhw immediate encoding to handle undefs in the lower half correctly. Missed in r155982.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156059
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Evan Cheng [Thu, 3 May 2012 01:45:13 +0000 (01:45 +0000)]
Fix two-address pass's aggressive instruction commuting heuristics. It's meant
to catch cases like:
%reg1024<def> = MOV r1
%reg1025<def> = MOV r0
%reg1026<def> = ADD %reg1024, %reg1025
r0 = MOV %reg1026
By commuting ADD, it let coalescer eliminate all of the copies. However, there
was a bug in the heuristics where it ended up commuting the ADD in:
%reg1024<def> = MOV r0
%reg1025<def> = MOV 0
%reg1026<def> = ADD %reg1024, %reg1025
r0 = MOV %reg1026
That did no benefit but rather ensure the last MOV would not be coalesced.
rdar://
11355268
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156048
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Andrew Trick [Thu, 3 May 2012 01:14:37 +0000 (01:14 +0000)]
Added TargetRegisterInfo::getAllocatableClass.
The ensures that virtual registers always belong to an allocatable class.
If your target attempts to create a vreg for an operand that has no
allocatable register subclass, you will crash quickly.
This ensures that targets define register classes as intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156046
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Bill Wendling [Wed, 2 May 2012 23:43:23 +0000 (23:43 +0000)]
Whitespace cleanup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156034
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Daniel Dunbar [Wed, 2 May 2012 22:46:36 +0000 (22:46 +0000)]
[docs] Include the Kaleidescope tutorial in the Sphinx docs build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156032
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Owen Anderson [Wed, 2 May 2012 22:17:40 +0000 (22:17 +0000)]
Teach DAGCombine the same multiply-by-1.0 folding trick when doing FMAs, just like it now knows for FMULs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156029
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Preston Gurd [Wed, 2 May 2012 22:02:02 +0000 (22:02 +0000)]
For Intel Atom, use ILP scheduling always, instead of ILP for 64 bit
and Hybrid for 32 bit, since benchmarks show ILP scheduling is better
most of the time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156028
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Preston Gurd [Wed, 2 May 2012 21:38:46 +0000 (21:38 +0000)]
Change the Intel Atom detection code to recognize
Lincroft and Medfield.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156025
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Owen Anderson [Wed, 2 May 2012 21:32:35 +0000 (21:32 +0000)]
Teach DAG combine that multiplication by 1.0 can always be constant folded.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156023
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Michael J. Spencer [Wed, 2 May 2012 21:25:32 +0000 (21:25 +0000)]
Add tools/lld to .gitignore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156021
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Jim Grosbach [Wed, 2 May 2012 21:11:56 +0000 (21:11 +0000)]
ARM: Add missing two-operand VBIC aliases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156019
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Douglas Gregor [Wed, 2 May 2012 17:32:48 +0000 (17:32 +0000)]
Move llvm-tblgen's StringMatcher into the TableGen library so it can
be used by clang-tblgen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156000
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Anders Waldenborg [Wed, 2 May 2012 16:15:32 +0000 (16:15 +0000)]
[llvm-c] Make a few function declarations proper prototypes
This avoids warnings when included in a application that
uses -Wstrict-prototypes.
e.g: AsmPrinters.def:27:1: warning: function declaration isn't a prototype [-Wstrict-prototypes]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155997
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Preston Gurd [Wed, 2 May 2012 16:03:35 +0000 (16:03 +0000)]
This patch continues the work of adding instruction latencies for X86 Atom,
by providing the latencies for the instructions in X86InstrFPStack.td.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155996
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Manman Ren [Wed, 2 May 2012 15:24:32 +0000 (15:24 +0000)]
Revert r155853
The commit is intended to fix rdar://
10961709.
But it is the root cause of PR12720.
Revert it for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155992
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Kostya Serebryany [Wed, 2 May 2012 13:12:19 +0000 (13:12 +0000)]
[tsan] typo and style (thanks to Nick Lewycky)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155986
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Bill Wendling [Wed, 2 May 2012 09:59:45 +0000 (09:59 +0000)]
The value held in the vector may be RAUW'ed by some of the canonicalization
methods. Use a weak value handle to keep up with this.
PR12245
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155984
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Richard Barton [Wed, 2 May 2012 09:43:18 +0000 (09:43 +0000)]
Disallow YIELD and other allocated nop hints in pre-ARMv6 architectures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155983
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Craig Topper [Wed, 2 May 2012 08:03:44 +0000 (08:03 +0000)]
Add support for selecting AVX2 vpshuflw and vpshufhw. Add decoding support for AsmPrinter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155982
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John McCall [Wed, 2 May 2012 05:39:15 +0000 (05:39 +0000)]
Update SmallVector to support move semantics if the host does.
Note that support for rvalue references does not imply support
for the full set of move-related STL operations.
I've preserved support for an odd little thing in insert() where
we're trying to support inserting a new element from an existing
one. If we actually want to support that, there's a lot more we
need to do: insert can call either grow or push_back, neither of
which is safe against this particular use pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155979
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John McCall [Wed, 2 May 2012 05:39:10 +0000 (05:39 +0000)]
Fix unintentional use of operator bool.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155978
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Eli Friedman [Wed, 2 May 2012 02:31:28 +0000 (02:31 +0000)]
Fix the implementation of MachOObjectFile::isSectionZeroInit so it follows the MachO spec.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155976
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Jim Grosbach [Tue, 1 May 2012 23:21:41 +0000 (23:21 +0000)]
Tidy up. Naming conventions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155960
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Jakub Staszak [Tue, 1 May 2012 23:08:16 +0000 (23:08 +0000)]
Remove unneeded break.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155959
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Jakub Staszak [Tue, 1 May 2012 23:06:00 +0000 (23:06 +0000)]
Use dyn_cast instead of checking opcode and cast.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155957
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Jakub Staszak [Tue, 1 May 2012 23:04:38 +0000 (23:04 +0000)]
Remove trailing spaces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155956
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Bill Wendling [Tue, 1 May 2012 22:50:45 +0000 (22:50 +0000)]
Strip the pointer casts off of allocas so that the selection DAG can find them.
PR10799
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155954
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Sirish Pande [Tue, 1 May 2012 21:28:30 +0000 (21:28 +0000)]
Target independent Hexagon Packetizer fix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155947
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Jim Grosbach [Tue, 1 May 2012 21:17:34 +0000 (21:17 +0000)]
ARM: Add a few missing add->sub aliases w/ 'w' suffix.
Aliases for adding a negative immediate when using an explicit 'w'
suffix. E.g.,
adds.w r2, #-16
adds.w r2, r2, #-16
addw r2, #-16
addw r2, #-16
addw r2, r2, #-16
rdar://
11330769
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155946
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Jim Grosbach [Tue, 1 May 2012 20:43:21 +0000 (20:43 +0000)]
ARM: allow vanilla expressions for movw/movt.
Expressions for movw/movt don't always have an :upper16: or :lower16:
on them and that's ok. When they don't, it's just a plain [0-65536]
immediate result, effectively the same as a :lower16: variant kind.
rdar://
10550147
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155941
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Preston Gurd [Tue, 1 May 2012 19:50:22 +0000 (19:50 +0000)]
This patch marks the X86 floating point stack registers ST0-ST7 as reserved
in order to avoid assertion failures in the register scavenger. The assertion
failures were “Bad machine code: Using an undefined physical register” and
“Bad machine code: MBB exits via unconditional fall-through but its successor
differs from its CFG successor!”.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155930
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Jim Grosbach [Tue, 1 May 2012 18:38:27 +0000 (18:38 +0000)]
MC: Unknown assembler directives are now hard errors.
Previously, an unsupported/unknown assembler directive issued a warning.
That's generally unsafe, and inconsistent with the behaviour of pretty
much every system assembler. Now that the MC assemblers are mature
enough to be the default on multiple targets, it's reasonable to
issue errors for these.
For target or platform directives that need to stay warnings, we
should add explicit handlers for them in, e.g., ELFAsmParser.cpp,
DarwinAsmParser.cpp, et. al., and issue the warning there.
rdar://
9246275
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155926
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Jim Grosbach [Tue, 1 May 2012 18:38:24 +0000 (18:38 +0000)]
MC: Remove errant EatToEndOfStatement() in asm parser.
The caller is already responsible for eating any additional input on the
line. Putting an additional EatToEndOfStatement() in ParseStatement()
causes an entire extra statement to be consumed when treating warnings
as errors. For example, test/MC/macros.s will assert() because the
.endmacro directive is missed as a result.
rdar://
11355843
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155925
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