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Jason Ekstrand [Wed, 17 Feb 2016 21:23:45 +0000 (13:23 -0800)]
i965/nir: Do lower_io late for fragment shaders
The Vulkan driver wants to be able to delete fragment outputs that are
beyond key.nr_color_regions; this is a lot easier if we lower outputs at
specialization time rather than link time.
(Rationale added to commit message by Ken)
Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Jordan Justen [Mon, 1 Feb 2016 02:28:42 +0000 (18:28 -0800)]
i965: Set dest type to UW for several send messages
Without this, on SIMD 16 the send instruction destination will appear
to write more than one destination register, causing the simulator to
report an error.
Of course, the send instruction can actually write more than one
destination register regardless of the type set for the destination,
so this is a bit strange.
Suggested-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Samuel Pitoiset [Wed, 24 Feb 2016 17:44:56 +0000 (18:44 +0100)]
nvc0: rework nvc0_compute_validate_program()
Reduce the amount of duplicated code by re-using
nvc0_program_validate(). While we are at it, change the prototype
to return void and remove nvc0_compute.h which is now useless.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Pierre Moreau <pierre.morrow@free.fr>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
Samuel Pitoiset [Wed, 24 Feb 2016 17:44:55 +0000 (18:44 +0100)]
nvc0: make sure to validate compute global buffers on Fermi
No reason to not validate those global buffers and this might avoid
fails if someone try to use the global memory from compute programs.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Pierre Moreau <pierre.morrow@free.fr>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
Samuel Pitoiset [Wed, 24 Feb 2016 17:44:54 +0000 (18:44 +0100)]
nvc0: move nvc0_validate_global_residents() to nvc0_compute.c
While we are at it, rename it to nvc0_compute_validate_globals() and
update its prototype.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Pierre Moreau <pierre.morrow@free.fr>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
Derek Foreman [Tue, 16 Feb 2016 16:34:39 +0000 (10:34 -0600)]
egl/wayland: Try to use wl_surface.damage_buffer for SwapBuffersWithDamage
Since commit
d1314de293e9e4a63c35f094c3893aaaed8580b4 we ignore
damage passed to SwapBuffersWithDamage.
Wayland 1.10 now has functionality that allows us to properly
process those damage rectangles, and a way to query if it's
available.
Now we can use wl_surface.damage_buffer and interpret the incoming
damage as being in buffer co-ordinates.
Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Pekka Paalanen <pekka.paalanen@collabora.co.uk>
Signed-off-by: Derek Foreman <derekf@osg.samsung.com>
Dave Airlie [Fri, 26 Feb 2016 04:02:56 +0000 (04:02 +0000)]
virgl: add missing CAP turned off.
Miklós Máté [Tue, 15 Dec 2015 23:05:44 +0000 (00:05 +0100)]
program: Remove extra reference_program()
It was already done in get_mesa_program()
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Emil Velikov [Thu, 25 Feb 2016 15:12:49 +0000 (15:12 +0000)]
automake: add nine to make distcheck
Will allow us to catch/prevent issues, like the one in mesa 11.2.0-rc1.
Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Emil Velikov [Thu, 25 Feb 2016 16:07:45 +0000 (16:07 +0000)]
st/nine: don't forget to bundle the nine_limits.h file
Without this mesa 11.2.0-rc1 ended up busted :-(
Cc: "11.2" <mesa-stable@lists.freedesktop.org>
Repored-by: Ondřej Súkup <mimi.vx@gmail.com>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Matt Turner [Wed, 11 Feb 2015 01:45:28 +0000 (17:45 -0800)]
i965/fs: Allow saturate propagation to propagate negations into MADs.
Allows us to transform
mad res src0 src1 src2
mov.sat dst -res
into
mad.sat dst -src0 -src1 src2
instructions in affected programs: 3712 -> 3688 (-0.65%)
helped: 24
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Matt Turner [Thu, 29 Jan 2015 22:17:20 +0000 (14:17 -0800)]
i965/fs: Allow saturate propagation to propagate negations into ADDs.
Allows us to transform
add res src0 src1
mov.sat dst -res
into
add.sat dst -src0 -src1
No shader-db changes.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Matt Turner [Wed, 28 Jan 2015 06:46:22 +0000 (22:46 -0800)]
i965/fs: Allow saturate propagation to propagate negations into MULs.
Allows us to transform
mul res src0 src1
mov.sat dst -res
into
mul.sat dst src0 -src1
instructions in affected programs: 45246 -> 45054 (-0.42%)
helped: 162
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Matt Turner [Mon, 22 Feb 2016 18:25:38 +0000 (10:25 -0800)]
i965/fs: Don't CSE negated multiplies with saturation.
It's not correct to CSE these multiplies
mul.sat dst1, -a, b
mul.sat dst2, a, b
by emitting a negated MOV from dst1 to dst2:
mul.sat dst1, -a, b
mov dst2, -dst1
Take 2.0*2.0 for example. The first multiply would produce 0.0 and the
second would produce 1.0.
Fixes bad generated code in 18 to 22 shaders:
instructions in affected programs: 432 -> 464 (7.41%)
helped: 4
HURT: 18
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Matt Turner [Mon, 22 Feb 2016 17:36:48 +0000 (09:36 -0800)]
glsl: Consider ubo_load to be a horizontal operation.
Unclear to me whether it actually is a horizontal operation that cannot
be vectorized, but the fact that i965 generates the same code in either
case makes me less interested in finding out.
Cc: mesa-stable@lists.freedesktop.org
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94199
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Andres Gomez [Thu, 25 Feb 2016 10:49:24 +0000 (12:49 +0200)]
glsl/ast: Implicit conversion from double to float is not allowed
Also, renamed get_conversion_operation to avoid
future misunderstandings.
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Oded Gabbay [Wed, 24 Feb 2016 12:43:28 +0000 (14:43 +0200)]
gallium/radeon: return correct values for BE in r600_translate_colorswap
Because I changed the swizzle check, I also need to adapt the return
values for each check.
It's basically almost the same as before, we just cross between STD and
STD_REV, and cross between ALT and ALT_REV
This fixes the rgba test in gl-1.0-readpixsanity (piglit) and also
fixes tri-flat (mesa demos).
Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Oded Gabbay [Wed, 24 Feb 2016 09:49:53 +0000 (11:49 +0200)]
gallium: remove duplicate define from enum pipe_format
Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
Reviewed-by: Thomas Helland <thomashelland90@gmail.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Ian Romanick [Fri, 19 Feb 2016 02:08:58 +0000 (18:08 -0800)]
glsl: Detect do-while-false loops and unroll them
Previously loops like
do {
// ...
} while (false);
that did not have any other loop-branch instructions would not be
unrolled. This is commonly used to wrap multiline preprocessor macros.
This produces IR like
(loop (
...
break
))
Since limiting_terminator was NULL, the loop unroller would
throw up its hands and say, "I don't know how many iterations. How
can I unroll this?"
We can detect this another way. If there is no limiting_terminator
and the only loop-branch is a break as the last IR, there's only one
iteration.
On my very old checkout of shader-db, this removes a loop from Orbital
Explorer, but it does not otherwise affect the shader. The loop removed
is the one the compiler inserts surrounding the switch statement.
This change does prevent some seriously bad code generation in some
patches to meta shaders that I recently sent out for review.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Nanley Chery [Thu, 11 Feb 2016 00:53:57 +0000 (16:53 -0800)]
i965: Enable tiled mem_copy with sRGB-formatted resources
RGBA8 and BGRA8 unorm formats are compatible with the various
mem_copy functions. Their sRGB counterparts are also compatible
because they're also color-renderable (of importance when the
specified resource is a readbuffer) and they share the same
physical layout.
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Brian Paul [Tue, 23 Feb 2016 20:46:28 +0000 (13:46 -0700)]
mesa: replace for loop with bitshifting in supported_buffer_bitmask()
Reviewed-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Brian Paul [Tue, 23 Feb 2016 20:41:27 +0000 (13:41 -0700)]
mesa: updates some comments in buffers.c
Reviewed-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Brian Paul [Tue, 23 Feb 2016 20:35:32 +0000 (13:35 -0700)]
mesa: make _mesa_draw_buffers() static
Reviewed-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Brian Paul [Tue, 23 Feb 2016 20:34:46 +0000 (13:34 -0700)]
mesa: make _mesa_draw_buffer() static
Reviewed-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Brian Paul [Tue, 23 Feb 2016 20:32:21 +0000 (13:32 -0700)]
mesa: make _mesa_read_buffer() static
Not called from any other file. Remove _mesa_ prefix and update comments.
Reviewed-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Brian Paul [Tue, 23 Feb 2016 20:25:43 +0000 (13:25 -0700)]
mesa: move declaration of buffer var in handle_first_current()
Declare the var in the scopes where it's used.
Reviewed-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Brian Paul [Tue, 23 Feb 2016 20:24:11 +0000 (13:24 -0700)]
mesa: use gl_buffer_index in a few places
Reviewed-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Brian Paul [Tue, 23 Feb 2016 20:19:29 +0000 (13:19 -0700)]
st/mesa: remove useless break statement
Reviewed-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Brian Paul [Tue, 23 Feb 2016 20:12:56 +0000 (13:12 -0700)]
st/mesa: rename st_readpixels to st_ReadPixels
To match the convention of other device driver functions.
Reviewed-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Brian Paul [Tue, 23 Feb 2016 23:15:34 +0000 (16:15 -0700)]
st/mesa: fix frontbuffer glReadPixels regressions
The change "mesa/readpix: Don't clip in _mesa_readpixels()" caused a
few piglit regressions. The failing tests use glReadPixels to read
from the front color buffer. The problem is we were trying to read
from a non-existant front color buffer. The front color buffer is
created on demand in st/mesa. Since the missing buffer bounds were
effectively 0 x 0 the glReadPixels was totally clipped and returned
early.
The fix involves creating the real front color buffer when we're about
to try reading from it.
Tested with llvmpipe and VMware driver on Linux, Windows.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94253
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94254
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94257
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Oded Gabbay [Tue, 23 Feb 2016 14:33:45 +0000 (16:33 +0200)]
gallium/radeon: Correctly translate colorswaps for big endian
The current code in r600_translate_colorswap uses the swizzle information
to determine which colorswap to use.
This works for BE & LE when the nr_channels is <4, but when nr_channels==4
(e.g. PIPE_FORMAT_A8R8G8B8_UNORM), this method can not be used for both BE
and LE, because the swizzle info is the same for both of them.
As a result, r600g doesn't support 24bit color formats, only 16bit, which
forces the user to choose 16bit color in X server.
This patch fixes this bug by separating the checks for LE and BE and
adapting the swizzle conditions in the BE part of the checks.
Tested on an Evergreen GPU (Cedar GL FirePro 2270) running inside POWER7
Big-Endian Machine.
Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
CC: "11.2" "11.1" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Thomas Hindoe Paaboel Andersen [Mon, 22 Feb 2016 22:58:00 +0000 (15:58 -0700)]
mesa: use sizeof on the correct type
Before the luminance stride was based on the size of GL_FLOAT
which is just the type constant (0x1406). Change it to use the
size of GLfloat.
Reviewed-by: Brian Paul <brianp@vmware.com>
Marek Olšák [Mon, 22 Feb 2016 23:37:39 +0000 (00:37 +0100)]
tgsi/scan: handle holes between VS inputs, assert-fail in other cases
"st/mesa: overhaul vertex setup for clearing, glDrawPixels, glBitmap"
added a vertex shader declaring IN[0] and IN[2], but not IN[1].
Drivers relying on tgsi_shader_info can't handle holes in declarations,
because tgsi_shader_info doesn't track that.
This is just a quick workaround meant for stable that will work for vertex
shaders.
This fixes radeonsi DrawPixels and CopyPixels crashes.
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Brian Paul <brianp@vmware.com>
Francisco Jerez [Mon, 22 Feb 2016 23:48:17 +0000 (15:48 -0800)]
docs: Mark off GL_OES_shader_image_atomic as done.
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Francisco Jerez [Sun, 16 Aug 2015 22:52:19 +0000 (01:52 +0300)]
i965/fs: Return result of image atomic in a register of the expected type.
So the result is of float type if we're implementing the float
overload of imageAtomicExchange. This is the only back-end change
required to support OES_shader_image_atomic AFAICT.
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Francisco Jerez [Fri, 21 Aug 2015 11:12:22 +0000 (14:12 +0300)]
glsl: Implement the required built-in functions when OES_shader_image_atomic is enabled.
This is basically just the same atomic functions exposed by
ARB_shader_image_load_store, with one exception:
"highp float imageAtomicExchange(
coherent IMAGE_PARAMS,
float data);"
There's no float atomic exchange overload in the original
ARB_shader_image_load_store or GL 4.2, so this seems like new
functionality that requires specific back-end support and a separate
availability condition in the built-in function generator.
v2: Move image availability predicate logic into a separate static
function for clarity. Had to pull out the image_function_flags
enum from the builtin_builder class for that to be possible.
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Francisco Jerez [Mon, 22 Feb 2016 23:06:45 +0000 (15:06 -0800)]
glsl: Add usual extension boilerplate for OES_shader_image_atomic.
v2: No need for extension enable bits (Ilia).
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Francisco Jerez [Mon, 22 Feb 2016 23:04:37 +0000 (15:04 -0800)]
mesa: Add extension table entry for OES_shader_image_atomic.
v2: No need for extension enable bits (Ilia).
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Samuel Pitoiset [Sun, 21 Feb 2016 10:58:35 +0000 (11:58 +0100)]
nvc0: rename 3d binding points to NVC0_BIND_3D_XXX
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Samuel Pitoiset [Sun, 21 Feb 2016 10:49:25 +0000 (11:49 +0100)]
nvc0: rename 3d dirty flags to NVC0_NEW_3D_XXX
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Samuel Pitoiset [Sun, 21 Feb 2016 10:15:43 +0000 (11:15 +0100)]
nvc0: prefix compute macros with _CP_ instead of _COMPUTE_
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Samuel Pitoiset [Sun, 21 Feb 2016 10:13:01 +0000 (11:13 +0100)]
nvc0: rename NVXX_COMPUTE to NVXX_CP
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Samuel Pitoiset [Sun, 21 Feb 2016 10:06:27 +0000 (11:06 +0100)]
nvc0: rename nvc0_context::dirty to nvc0_context::dirty_3d
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Samuel Pitoiset [Mon, 22 Feb 2016 20:11:33 +0000 (21:11 +0100)]
nvc0/ir: add missing emission of locked load predicate
Like unlocked store on shared memory, locked store can fail and the
second dest which is a predicate must be emitted.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
Samuel Pitoiset [Sun, 21 Feb 2016 14:28:16 +0000 (15:28 +0100)]
nvc0/ir: add ld lock/st unlock emission on GK104
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Samuel Pitoiset [Sun, 21 Feb 2016 18:40:01 +0000 (19:40 +0100)]
nv50/ir: restore OP_SELP to be a regular instruction
Actually OP_SELP doesn't need to be a compare instruction. Instead we
just need to set the NOT modifier when building the instruction.
While we are at it, fix the dst register type and use a GPR.
Suggested by Ilia Mirkin.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Brian Paul [Mon, 22 Feb 2016 15:53:47 +0000 (08:53 -0700)]
svga: unbind index buffer when drawing non-indexed primitives
Silences a warning reported by the svga3d device.
v2: also null-out the index buffer pointer
Reviewed-by: Sinclair Yeh <syeh@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Ilia Mirkin [Wed, 17 Feb 2016 12:36:58 +0000 (07:36 -0500)]
mesa: add GL_EXT_texture_border_clamp support
This extension is identical to GL_OES_texture_border_clamp. But dEQP has
tests that want the EXT variant.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Ilia Mirkin [Tue, 16 Feb 2016 00:09:15 +0000 (19:09 -0500)]
mesa: add GL_OES_texture_border_clamp support
Only minor differences to the existing ARB_texture_border_clamp support.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Ilia Mirkin [Mon, 22 Feb 2016 14:06:59 +0000 (09:06 -0500)]
mesa: bump version
11.2 has been branched, we're on 11.3 now.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Emil Velikov [Mon, 22 Feb 2016 10:22:21 +0000 (10:22 +0000)]
nouveau: update the Makefile.sources list
Reflect the nv50->g80 change and the new gm107_texture header.
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Marek Olšák [Thu, 11 Feb 2016 14:49:34 +0000 (15:49 +0100)]
radeonsi: implement binary shaders & shader cache in memory (v2)
v2: handle _mesa_hash_table_insert failure
other cosmetic changes
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 11 Feb 2016 22:33:54 +0000 (23:33 +0100)]
gallium/radeon: remove unused radeon_shader_binary_free_* functions
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 11 Feb 2016 22:20:38 +0000 (23:20 +0100)]
radeonsi: make radeon_shader_reloc name string fixed-sized
This will simplify implementations of binary shaders.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 11 Feb 2016 20:09:38 +0000 (21:09 +0100)]
radeonsi: move some struct si_shader members to new struct si_shader_info
This will be part of shader binaries.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 11 Feb 2016 20:06:33 +0000 (21:06 +0100)]
radeonsi: use smaller types for some si_shader members
in order to decrease the shader size for a shader cache.
v2: add & use SI_MAX_VS_OUTPUTS
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 28 Jan 2016 00:29:59 +0000 (01:29 +0100)]
radeonsi: enable compiling one variant per shader
Shader stats from VERDE:
Default scheduler:
Totals:
SGPRS: 491272 -> 488672 (-0.53 %)
VGPRS: 289980 -> 311093 (7.28 %)
Code Size:
11091656 ->
11219948 (1.16 %) bytes
LDS: 97 -> 97 (0.00 %) blocks
Scratch:
1732608 ->
2246656 (29.67 %) bytes per wave
Max Waves: 78063 -> 77352 (-0.91 %)
Wait states: 0 -> 0 (0.00 %)
Looking at some of the worst regressions, I get:
- The VGPR increase seems to be caused by the fact that if PS has used less
than 16 VGPRs, now it will always use 16 VGPRs and sometimes even 20.
However, the wave count remains at 10 if VGPRs <= 24, so no harm there.
- The scratch increase seems to be caused by SGPR spilling.
The unnecessary SGPR spilling has been an ongoing issue with the compiler
and it's completely fixable by rematerializing s_loads or reordering
instructions.
SI scheduler:
Totals:
SGPRS: 374848 -> 374576 (-0.07 %)
VGPRS: 284456 -> 307515 (8.11 %)
Code Size:
11433068 ->
11535452 (0.90 %) bytes
LDS: 97 -> 97 (0.00 %) blocks
Scratch: 509952 -> 522240 (2.41 %) bytes per wave
Max Waves: 79456 -> 78217 (-1.56 %)
Wait states: 0 -> 0 (0.00 %)
VGPRs - same story as before. The SI scheduler doesn't spill SGPRs so much
and generally spills way less than the default scheduler.
(522240 spills vs
2246656 spills)
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Fri, 5 Feb 2016 22:30:01 +0000 (23:30 +0100)]
radeonsi: print full shader name before disassembly
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 28 Jan 2016 01:53:13 +0000 (02:53 +0100)]
radeonsi: compile non-GS middle parts of shaders immediately if enabled
Still disabled.
Only prologs & epilogs are compiled in draw calls, but each variant of those
is compiled only once per process.
VS is always compiled as hw VS.
TES is always compiled as hw VS.
LS and ES stages are always compiled on demand.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Wed, 27 Jan 2016 01:59:23 +0000 (02:59 +0100)]
radeonsi: rework polygon stippling for PS prolog
Don't use the pstipple module.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Mon, 15 Feb 2016 22:57:54 +0000 (23:57 +0100)]
radeonsi: add PS prolog
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 26 Jan 2016 23:50:29 +0000 (00:50 +0100)]
radeonsi: add PS epilog
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 26 Jan 2016 23:38:03 +0000 (00:38 +0100)]
radeonsi: add TCS epilog
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 26 Jan 2016 23:33:07 +0000 (00:33 +0100)]
radeonsi: add VS epilog
It only exports the primitive ID.
Also used by TES when it's compiled as VS.
The VS input location of the primitive ID input is v2.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 26 Jan 2016 23:29:53 +0000 (00:29 +0100)]
radeonsi: add VS prolog
This is disabled with use_monolithic_shaders = true.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Mon, 15 Feb 2016 22:16:32 +0000 (23:16 +0100)]
radeonsi: first bits for non-monolithic shaders
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 26 Jan 2016 21:15:27 +0000 (22:15 +0100)]
radeonsi: add code for dumping all shader parts together (v2)
v2: unify some code into si_get_shader_binary_size
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Marek Olšák [Tue, 26 Jan 2016 21:12:26 +0000 (22:12 +0100)]
radeonsi: add code for combining and uploading shaders from 3 shader parts
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 11 Feb 2016 21:04:35 +0000 (22:04 +0100)]
radeonsi: fail compilation if non-GS non-CS shaders have rodata
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 26 Jan 2016 21:05:16 +0000 (22:05 +0100)]
radeonsi: separate 2 pieces of code from create_function
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 26 Jan 2016 20:57:57 +0000 (21:57 +0100)]
radeonsi: add samplemask parameter to si_export_mrt_color
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 26 Jan 2016 20:55:28 +0000 (21:55 +0100)]
radeonsi: add start_instance parameter to get_instance_index_for_fetch
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 26 Jan 2016 17:46:31 +0000 (18:46 +0100)]
radeonsi: separate out shader key bits for prologs & epilogs
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sun, 3 Jan 2016 02:26:28 +0000 (03:26 +0100)]
radeonsi: compute how many input VGPRs fragment shaders have
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Fri, 1 Jan 2016 19:37:38 +0000 (20:37 +0100)]
radeonsi: compute how many input SGPRs and VGPRs shaders have
Prologs (shader binaries inserted before the API shader binary) need to
know this, so that they won't change the input registers unintentionally.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 22 Dec 2015 19:55:53 +0000 (20:55 +0100)]
gallium/radeon: add basic code for setting shader return values
LLVMBuildInsertValue will be used on return_value.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Samuel Pitoiset [Fri, 5 Feb 2016 12:32:59 +0000 (13:32 +0100)]
nvc0: enable compute shaders on Fermi
Kepler compute support is really different than Fermi and it's not
ready yet.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Samuel Pitoiset [Tue, 26 Jan 2016 00:32:23 +0000 (01:32 +0100)]
nv50/ir: add atomics support on shared memory for Fermi
Changes from v3:
- move the previous OP_SELP change to the previous commit
Changes from v2:
- make sure the op is OP_SELP when emitting the predicate and add one
assert
- use bld.getSSA() for mkOp2()
- add cross edge between tryLockAndSetBB and joinBB
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
Samuel Pitoiset [Fri, 5 Feb 2016 14:09:07 +0000 (15:09 +0100)]
nv50/ir: make OP_SELP a compare instruction
This OP_SELP insn will be used to handle compare and swap subops.
Changes from v2:
- fix logic for GK110+
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Samuel Pitoiset [Mon, 25 Jan 2016 20:43:13 +0000 (21:43 +0100)]
nv50/ir: add lock/unlock subops for load/store
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Samuel Pitoiset [Sat, 16 Jan 2016 14:34:34 +0000 (15:34 +0100)]
nv50/ir: use s[] addr space for shared buffers
Shared memory address space (FILE_MEMORY_SHARED) must be used instead
of global memory when a shared memory area is declared.
Changes from v2:
- oops, do not remove TGSI_FILE_BUFFER in a switch in
nv50_ir_from_tgsi.cpp
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Samuel Pitoiset [Thu, 11 Feb 2016 22:49:45 +0000 (23:49 +0100)]
nvc0: reduce likelihood of collision for real buffers on Fermi
Reduce likelihood of collision with real buffers by placing the
hole at the top of the 4G area. This fixes some indirect draw+compute
tests with large buffers.
Suggested by Ilia Mirkin.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Samuel Pitoiset [Wed, 17 Feb 2016 21:01:18 +0000 (22:01 +0100)]
nvc0: invalidate compute state when switching pipe contexts
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Samuel Pitoiset [Tue, 12 Jan 2016 22:51:00 +0000 (23:51 +0100)]
nvc0: add support for indirect compute on Fermi
When indirect compute is used, the size of the grid (in blocks) is
stored as three integers inside a buffer. This requires a macro to
set up GRIDDIM_YX and GRIDDIM_Z.
Changes from v2:
- do not launch the grid if the number of groups for a dimension is 0
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Samuel Pitoiset [Mon, 11 Jan 2016 22:21:45 +0000 (23:21 +0100)]
nvc0: bind textures/samplers for compute on Fermi
Textures and samplers don't seem to be aliased between COMPUTE and 3D.
Changes from v2:
- refactor the code to share (almost) the same logic between 3d and
compute
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Samuel Pitoiset [Wed, 6 Jan 2016 17:46:00 +0000 (18:46 +0100)]
nvc0: bind shader buffers for compute on Fermi
This is loosely based on 3D. Shader buffers are bound on c15 (the
driver constbuf) at offset 0x200.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Samuel Pitoiset [Mon, 11 Jan 2016 21:11:19 +0000 (22:11 +0100)]
nvc0: bind driver constbuf for compute on Fermi
Changes from v3:
- add new validation state for COMPUTE driver constbuf
Changes from v2:
- always bind the driver consts even if user params come in via clover
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Samuel Pitoiset [Wed, 17 Feb 2016 20:43:40 +0000 (21:43 +0100)]
nvc0: add a new validation state for 3D driver constbuf
This will be used to invalidate 3D driver constbuf when using COMPUTE
and vice-versa. This is needed because this CB contains a bunch of
useful information like the addrs of shader buffers.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Samuel Pitoiset [Mon, 11 Jan 2016 14:35:21 +0000 (15:35 +0100)]
nvc0: bind constant buffers for compute on Fermi
Loosely based on 3D.
Changs from v3:
- invalidate COMPUTE CBs after validating 3D CBs because they are
aliased
Changes from v2:
- get rid of the 's' param to nvc0_cb_bo_push() because it doesn't
matter to upload constbufs for compute using the 3d chan
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Samuel Pitoiset [Mon, 11 Jan 2016 13:59:08 +0000 (14:59 +0100)]
nvc0: allocate an area for compute user constbufs
For compute shaders, we might need to upload uniforms.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Samuel Pitoiset [Fri, 19 Feb 2016 19:25:10 +0000 (20:25 +0100)]
nv50: do not advertise about compute shaders
Compute shaders are totally unsupported. This avoids Clover to
report that OpenCL is supported on Tesla because it's a lie.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Pierre Moreau <pierre.morrow@free.fr>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Rhys Kidd [Sat, 20 Feb 2016 15:15:35 +0000 (16:15 +0100)]
docs: Correct typo in LLVMpipe envvar description
Signed-off-by: Rhys Kidd <rhyskidd@gmail.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Ilia Mirkin [Wed, 17 Feb 2016 13:17:35 +0000 (08:17 -0500)]
st/mesa: force depth mode to GL_RED for sized depth/stencil formats
See commit
9db2098d for the i965 version of this.
This fixes depth in a bunch of dEQP EXT_texture_border_clamp tests. And
probably other ones as well.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: mesa-stable@lists.freedesktop.org
Daniel Czarnowski [Mon, 15 Feb 2016 07:31:09 +0000 (09:31 +0200)]
egl_dri2: set correct error code if swapbuffers fails
A return value of '-1' means that there was error during swap with a
window drawable, in this case we set error as EGL_BAD_NATIVE_WINDOW.
v2: coding style cleanup, better commit message
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Dongwon Kim [Tue, 2 Feb 2016 23:06:28 +0000 (15:06 -0800)]
egl: move Null check to eglGetSyncAttribKHR to prevent Segfault
Null-check on "*value" is currently done in _eglGetSyncAttrib, which is
after eglGetSyncAttribKHR dereferences it.
Move the check a layer up (in the beginning of eglGetSyncAttribKHR) to
avoid segfaults.
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org
Signed-off-by: Dongwon Kim <dongwon.kim@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
[Emil Velikov: tweak commit message, add stable tag]
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Ilia Mirkin [Wed, 17 Feb 2016 17:28:04 +0000 (12:28 -0500)]
meta/copy_image: use precomputed dst_internal_format to avoid segfault
If the destination is a renderbuffer, dst_tex_image will be NULL. This
fixes the *to_renderbuffer dEQP copy image tests.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Cc: mesa-stable@lists.freedesktop.org
Ilia Mirkin [Tue, 16 Feb 2016 04:57:06 +0000 (23:57 -0500)]
mesa: add GL_OES_texture_stencil8 support
It's basically the same thing as GL_ARB_texture_stencil8 except that
glCopyTexImage isn't supported, so add STENCIL_INDEX to the list of
invalid GLES formats for glCopyTexImage.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>
Ilia Mirkin [Thu, 18 Feb 2016 06:04:13 +0000 (01:04 -0500)]
st/mesa: fix pbo uploads
- LOD must be provided in .w for TXF (even for buffer textures)
- User buffer must be valid at draw time
- Must have a sampler associated with the sampler view
This makes PBO uploads work again on nouveau.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Ilia Mirkin [Thu, 18 Feb 2016 01:31:38 +0000 (20:31 -0500)]
mesa: check fbo completeness based on internal format, not driver format
The base format is a function of the user-requested format, while the
driver format is not. So we should use the base format instead.
The driver format can be anything. Specifically in the stencil-only
case, it might be a depth/stencil format. However we still want to
refuse such an attachment when bound to GL_DEPTH.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Brian Paul <brianp@vmware.com>
Brian Paul [Fri, 19 Feb 2016 15:51:51 +0000 (08:51 -0700)]
mesa: small optimization of _mesa_expand_bitmap()
Avoid a per-pixel multiply.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>