OSDN Git Service
Alex Bradbury [Thu, 18 Jul 2019 07:52:41 +0000 (07:52 +0000)]
[RISCV] Reset NoPHIS MachineFunctionProperty in emitSelectPseudo
We insered PHIS were there were none before, so the property must be
reset. This error was found on an EXPENSIVE_CHECKS build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366412
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Serguei Katkov [Thu, 18 Jul 2019 07:36:20 +0000 (07:36 +0000)]
[LoopInfo] Use early return in branch weight update functions. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366411
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Alex Bradbury [Thu, 18 Jul 2019 07:25:56 +0000 (07:25 +0000)]
[RISCV][DebugInfo] Fix dwarf-riscv-relocs.ll test on Windows
Windows sees DW_AT_decl_file (".\dwarf-riscv-relocs.c") while Linux sees
DW_AT_decl_file ("./dwarf-riscv-relocs.c").
This fixes a failure introduced in rL366402.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366410
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Kang Zhang [Thu, 18 Jul 2019 06:56:49 +0000 (06:56 +0000)]
[NFC][PowerPC] Add the test to test the pass block-placement
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366407
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Craig Topper [Thu, 18 Jul 2019 06:18:06 +0000 (06:18 +0000)]
[X86] Disable combineConcatVectors for vXi1 vectors.
I'm not convinced the code this calls is properly vetted for
vXi1 vectors. Experimental vector widening legalization testing
for D55251 is now hitting an assertion failure inside
EltsFromConsecutiveLoads. This is occurring from a v2i1 load
having a store size different than its VT size. Hopefully
this commit will keep such issues from happening.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366405
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Nathan Lanza [Thu, 18 Jul 2019 05:24:22 +0000 (05:24 +0000)]
Fix typo in programmer's manual cantFile -> cantFail
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366403
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Alex Bradbury [Thu, 18 Jul 2019 05:22:55 +0000 (05:22 +0000)]
[DWARF][RISCV] Add support for RISC-V relocations needed for debug info
When code relaxation is enabled many RISC-V fixups are not resolved but
instead relocations are emitted. This happens even for DWARF debug
sections. Therefore, to properly support the parsing of DWARF debug info
we need to be able to resolve RISC-V relocations. This patch adds:
* Support for RISC-V relocations in RelocationResolver
* DWARF support for two relocations per object file offset
* DWARF changes to support relocations in more DIE fields
The two relocations per offset change is needed because some RISC-V
relocations (used for label differences) come in pairs.
Relocations can also be emitted for DWARF fields where relocations were
not yet evaluated. Adding relocation support for some of these fields is
essencial. On the other hand, LLVM currently emits RISC-V relocations
for fixups that could be safely evaluated, since they can never be
affected by code relaxations. This patch also adds relocation support
for the fields affected by those extraneous relocations (the DWARF unit
entry Length, and the DWARF debug line entry TotalLength and
PrologueLength), for testing purposes.
Differential Revision: https://reviews.llvm.org/D62062
Patch by Luís Marques.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366402
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Alex Bradbury [Thu, 18 Jul 2019 04:05:18 +0000 (04:05 +0000)]
[RISCV] Re-land r366331 d RISCV to LLVM_ALL_TARGETS
*San flagged issues should be now be addressed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366399
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Alex Bradbury [Thu, 18 Jul 2019 04:02:58 +0000 (04:02 +0000)]
[RISCV] Avoid signed integer overflow UB in RISCVMatInt::generateInstSeq
Found by UBSan.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366398
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Alex Bradbury [Thu, 18 Jul 2019 03:23:47 +0000 (03:23 +0000)]
[RISCV] Don't acccess an invalidated iterator in RISCVInstrInfo::removeBranch
Issue found by ASan.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366397
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Fangrui Song [Thu, 18 Jul 2019 01:53:08 +0000 (01:53 +0000)]
[AArch64] Add dependency from AArch64CodeGen to TransformUtils to fix -DBUILD_SHARED_LIBS=on link error after D64173/r366361
This fixes:
ld.lld: error: undefined symbol: llvm::findAllocaForValue(llvm::Value*, llvm::DenseMap<llvm::Value*, llvm::Alloc aInst*, llvm::DenseMapInfo<llvm::Value*>, llvm::detail::DenseMapPair<llvm::Value*, llvm::AllocaInst*> >&)
>>> referenced by AArch64StackTagging.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366396
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Philip Reames [Thu, 18 Jul 2019 00:26:03 +0000 (00:26 +0000)]
[Tests] Add a test showing how we handle overaligned allocas w/ no-realign-stack
(At the moment, we ignore the alignment requirement.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366393
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Nilanjana Basu [Wed, 17 Jul 2019 23:43:58 +0000 (23:43 +0000)]
Changes to display code view debug info type records in hex format
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366390
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Evgeniy Stepanov [Wed, 17 Jul 2019 23:31:59 +0000 (23:31 +0000)]
Make DT a transitive dependency of LI.
Summary:
LoopInfoWrapperPass::verify uses DT, which means DT must be alive
even if it has no direct users.
Fixes a crash in expensive checks mode.
Reviewers: pcc, leonardchan
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D64896
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366388
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Denis Bakhvalov [Wed, 17 Jul 2019 23:28:39 +0000 (23:28 +0000)]
[llvm-bcanalyzer] Fixed error 'Expected<T> must be checked before access or destruction'
After rL365286 I had failing test:
LLVM :: tools/gold/X86/v1.12/thinlto_emit_linked_objects.ll
It was failing with the output:
$ llvm-bcanalyzer --dump llvm/test/tools/gold/X86/v1.12/Output/thinlto_emit_linked_objects.ll.tmp3.o.thinlto.bc
Expected<T> must be checked before access or destruction.
Unchecked Expected<T> contained error:
Unexpected end of file reading 0 of 0 bytesStack dump:
Change-Id: I07e03262074ea5e0aae7a8d787d5487c87f914a2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366387
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Nico Weber [Wed, 17 Jul 2019 22:59:52 +0000 (22:59 +0000)]
llvm-pdbdump: Fix several smaller issues with injected source compression handling
- getCompression() used to return a PDB_SourceCompression even though
the docs for IDiaInjectedSource are explicit about the return value
being compiler-dependent. Return an uint32_t instead, and make the
printing code handle unknown values better by printing "Unknown" and
the int value instead of not printing any compression.
- Print compressed contents as hex dump, not as string.
- Add compression type "DotNet", which is used (at least) by csc.exe,
the C# compiler. Also add a lengthy comment describing the stream
contents (derived from looking at the raw hex contents long enough
to see the GUIDs, which led me to the roslyn and mono implementations
for handling this).
- The native injected source dumper was dumping the contents of the
whole data stream -- but csc.exe writes a stream that's padded with
zero bytes to the next 512 boundary, and the dia api doesn't display
those padding bytes. So make NativeInjectedSource::getCode() do the
same thing.
Differential Revision: https://reviews.llvm.org/D64879
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366386
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Stanislav Mekhanoshin [Wed, 17 Jul 2019 22:58:43 +0000 (22:58 +0000)]
[AMDGPU] Simplify AMDGPUInstPrinter::printRegOperand()
Differential Revision: https://reviews.llvm.org/D64892
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366385
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Matt Arsenault [Wed, 17 Jul 2019 22:41:53 +0000 (22:41 +0000)]
AMDGPU: Set inaccessiblememonly on sendmsg intrinsics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366384
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Craig Topper [Wed, 17 Jul 2019 22:26:00 +0000 (22:26 +0000)]
[X86] Make sure we mark 128/256 MLOAD as Legal with VLX when min-legal-vector-width=256 is in effect.
This started triggering an assertion after r364718 when we made
these Custom under AVX2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366382
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Peter Collingbourne [Wed, 17 Jul 2019 21:45:34 +0000 (21:45 +0000)]
gn build: Merge r366361.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366380
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Peter Collingbourne [Wed, 17 Jul 2019 21:45:19 +0000 (21:45 +0000)]
hwasan: Initialize the pass only once.
This will let us instrument globals during initialization. This required
making the new PM pass a module pass, which should still provide access to
analyses via the ModuleAnalysisManager.
Differential Revision: https://reviews.llvm.org/D64843
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366379
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Stanislav Mekhanoshin [Wed, 17 Jul 2019 21:35:11 +0000 (21:35 +0000)]
[AMDGPU] Stop special casing flat_scratch for register name
Differential Revision: https://reviews.llvm.org/D64885
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366376
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Evgeniy Stepanov [Wed, 17 Jul 2019 21:27:44 +0000 (21:27 +0000)]
Speculative fix for stack-tagging.ll failure.
Depending on the evaluation order of function call arguments,
the current code may insert a use before def.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366375
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Hideto Ueno [Wed, 17 Jul 2019 21:11:02 +0000 (21:11 +0000)]
[Attributor][NFC] Remove unnecessary debug output
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366373
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Nilanjana Basu [Wed, 17 Jul 2019 21:01:12 +0000 (21:01 +0000)]
Adding inline comments to code view type record directives for better readability
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366372
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Francis Visoiu Mistrih [Wed, 17 Jul 2019 20:46:19 +0000 (20:46 +0000)]
[PEI] Don't re-allocate a pre-allocated stack protector slot
The LocalStackSlotPass pre-allocates a stack protector and makes sure
that it comes before the local variables on the stack.
We need to make sure that later during PEI we don't re-allocate a new
stack protector slot. If that happens, the new stack protector slot will
end up being **after** the local variables that it should be protecting.
Therefore, we would have two slots assigned for two different stack
protectors, one at the top of the stack, and one at the bottom. Since
PEI will overwrite the assigned slot for the stack protector, the load
that is used to compare the value of the stack protector will use the
slot assigned by PEI, which is wrong.
For this, we need to check if the object is pre-allocated, and re-use
that pre-allocated slot.
Differential Revision: https://reviews.llvm.org/D64757
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366371
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Francis Visoiu Mistrih [Wed, 17 Jul 2019 20:46:16 +0000 (20:46 +0000)]
[CodeGen] Add stack protector tests where the guard gets re-assigned
In preparation of a fix, add tests for multiple backends.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366370
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Francis Visoiu Mistrih [Wed, 17 Jul 2019 20:46:09 +0000 (20:46 +0000)]
[CodeGen][NFC] Simplify checks for stack protector index checking
Use `hasStackProtectorIndex()` instead of `getStackProtectorIndex() >=
0`.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366369
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Matt Arsenault [Wed, 17 Jul 2019 20:22:44 +0000 (20:22 +0000)]
GlobalISel: Handle widenScalar of arbitrary G_MERGE_VALUES sources
Extract the sources to the GCD of the original size and target size,
padding with implicit_def as necessary.
Also fix the case where the requested source type is wider than the
original result type. This was ignoring the type, and just using the
destination. Do the operation in the requested type and truncate back.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366367
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Matt Arsenault [Wed, 17 Jul 2019 20:22:38 +0000 (20:22 +0000)]
GlobalISel: Handle more cases for widenScalar of G_MERGE_VALUES
Use an anyext to the requested type for the leftover operand to
produce a slightly wider type, and then truncate the final merge.
I have another implementation almost ready which handles arbitrary
widens, but I think it produces worse code in this example (which I
think is 90% due to not folding redundant copies or folding out
implicit_def users), so I wanted to add this as a baseline first.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366366
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Evgeniy Stepanov [Wed, 17 Jul 2019 19:24:12 +0000 (19:24 +0000)]
Basic MTE stack tagging instrumentation.
Summary:
Use MTE intrinsics to tag stack variables in functions with
sanitize_memtag attribute.
Reviewers: pcc, vitalybuka, hctim, ostannard
Subscribers: srhines, mgorny, javed.absar, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D64173
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366361
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Evgeniy Stepanov [Wed, 17 Jul 2019 19:24:02 +0000 (19:24 +0000)]
Basic codegen for MTE stack tagging.
Implement IR intrinsics for stack tagging. Generated code is very
unoptimized for now.
Two special intrinsics, llvm.aarch64.irg.sp and llvm.aarch64.tagp are
used to implement a tagged stack frame pointer in a virtual register.
Differential Revision: https://reviews.llvm.org/D64172
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366360
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Momchil Velikov [Wed, 17 Jul 2019 17:43:32 +0000 (17:43 +0000)]
Revert [AArch64] Add support for Transactional Memory Extension (TME)
This reverts r366322 (git commit
4b8da3a503e434ddbc08ecf66582475765f449bc)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366355
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Daniil Fukalov [Wed, 17 Jul 2019 16:51:29 +0000 (16:51 +0000)]
[AMDGPU] Tune inlining parameters for AMDGPU target
Summary:
Since the target has no significant advantage of vectorization,
vector instructions bous threshold bonus should be optional.
amdgpu-inline-arg-alloca-cost parameter default value and the target
InliningThresholdMultiplier value tuned then respectively.
Reviewers: arsenm, rampitec
Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, eraman, hiraditya, haicheng, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D64642
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366348
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Lang Hames [Wed, 17 Jul 2019 16:40:52 +0000 (16:40 +0000)]
[ORC] Add deprecation warnings to ORCv1 layers and utilities.
Summary:
ORCv1 is deprecated. The current aim is to remove it before the LLVM 10.0
release. This patch adds deprecation attributes to the ORCv1 layers and
utilities to warn clients of the change.
Reviewers: dblaikie, sgraenitz, AlexDenisov
Subscribers: llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D64609
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366344
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Alex Bradbury [Wed, 17 Jul 2019 16:14:52 +0000 (16:14 +0000)]
[RISCV] Revert r366331 as it exposed some sanitizer failures
See <http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-fast/builds/33612>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366343
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Matt Arsenault [Wed, 17 Jul 2019 15:35:36 +0000 (15:35 +0000)]
AMDGPU: Use getTargetConstant
Avoids creating an extra intermediate mov.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366340
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Hideto Ueno [Wed, 17 Jul 2019 15:15:43 +0000 (15:15 +0000)]
[Attributor] Deduce "willreturn" function attribute
Summary:
Deduce the "willreturn" attribute for functions.
For now, intrinsics are not willreturn. More annotation will be done in another patch.
Reviewers: jdoerfert
Subscribers: jvesely, nhaehnle, nicholas, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63046
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366335
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Owen Reynolds [Wed, 17 Jul 2019 15:10:02 +0000 (15:10 +0000)]
[llvm-ar][test] Add tests failing on Darwin
These tests that failed on Darwin but passed on other machines due to the default archive format differing
on a Darwin machine, and what looks to be bugs in the output of this format.
I can not investigate these issue further so the tests are considered expected failures on Darwin.
Differential Revision: https://reviews.llvm.org/D64802
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366334
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Alex Bradbury [Wed, 17 Jul 2019 14:32:25 +0000 (14:32 +0000)]
[RISCV] Add RISCV to LLVM_ALL_TARGETS so it s built by default
This follows the RFC <http://lists.llvm.org/pipermail/llvm-dev/2019-July/133724.html>.
Follow-on commits will add appropriate release notes changes etc.
Pushing this now and in a minimal form so there is reasonable time before 9.0
branches to resolve any issues arising from e.g. the backend being exposed on
different sanitizer setups.
The current builder for RISC-V is on the staging build-bot
<http://lab.llvm.org:8014/builders/llvm-riscv-linux>, however with the RISCV
backend being built by default it won't provide any real additional coverage.
We will shortly set up a builder that runs the test-suite in qemu-user.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366331
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Alex Bradbury [Wed, 17 Jul 2019 14:04:48 +0000 (14:04 +0000)]
[RISCV][NFC] Remove outdated TODO from test/CodeGen/RISCV/dwarf-eh.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366330
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Alex Bradbury [Wed, 17 Jul 2019 14:00:35 +0000 (14:00 +0000)]
[AsmPrinter] Make the encoding of call sites in .gcc_except_table configurable and use for RISC-V
The original behavior was to always emit the offsets to each call site in the
call site table as uleb128 values, however on some architectures (eg RISCV)
these uleb128 offsets into the code cannot always be resolved until link time
(because relaxation will invalidate any calculated offsets), and there are no
appropriate relocations for uleb128 values. As a consequence it needs to be
possible to specify an alternative.
This also switches RISCV to use DW_EH_PE_udata4 for call side encodings in
.gcc_except_table
Differential Revision: https://reviews.llvm.org/D63415
Patch by Edward Jones.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366329
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Matt Arsenault [Wed, 17 Jul 2019 13:55:01 +0000 (13:55 +0000)]
Mips: Remove immarg from copy and insert intrinsics
These intrinsics do in fact work with non-constant index arguments.
These are lowered to either the generic
ISD::INSERT_VECTOR_ELT/ISD::EXTRACT_VECTOR_ELT, or to
VEXTRACT_SEXT_ELT. The handling of these all accept variable
indexes. Turning these into generic instructions which do allow
variables introduces complications in a future change to immarg
handling.
Since these just turn into generic instructions, these are kind of
pointless and should probably just be autoupgraded to
extractelement/insertelement.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366328
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Alex Bradbury [Wed, 17 Jul 2019 13:54:38 +0000 (13:54 +0000)]
[RISCV] Set correct encodings for DWARF exception handling
This patch sets correct encodings for DWARF exception handling for RISC-V
(other than call site encoding, which must be udata4 rather than uleb128 and
is handled by D63415).
This has the same intend as D63409, except this version matches GCC/binutils
behaviour which uses the same encodings regardless of PIC/non-PIC and
medlow/medany code model.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366327
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Alex Bradbury [Wed, 17 Jul 2019 13:48:49 +0000 (13:48 +0000)]
[RISCV][NFC] Add tests that capture current encodings for DWARF EH
Items which are known to be wrong/different vs GCC are marked as TODO and will
be address in follow-up patches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366326
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Fangrui Song [Wed, 17 Jul 2019 13:40:42 +0000 (13:40 +0000)]
[llvm-ar][test] \r\n -> \n
Also simplify some empty output tests with 'count 0'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366324
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Jay Foad [Wed, 17 Jul 2019 13:40:03 +0000 (13:40 +0000)]
[AMDGPU] Optimize atomic AND/OR/XOR
Summary: Extend the atomic optimizer to handle AND, OR and XOR.
Reviewers: arsenm, sheredom
Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, jfb, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D64809
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366323
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Momchil Velikov [Wed, 17 Jul 2019 13:23:27 +0000 (13:23 +0000)]
[AArch64] Add support for Transactional Memory Extension (TME)
TME is a future architecture technology, documented in
https://developer.arm.com/architectures/cpu-architecture/a-profile/exploration-tools
https://developer.arm.com/docs/ddi0601/a
More about the future architectures:
https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/new-technologies-for-the-arm-a-profile-architecture
This patch adds support for the TME instructions TSTART, TTEST, TCOMMIT, and
TCANCEL and the target feature/arch extension "tme".
It also implements TME builtin functions, defined in ACLE Q2 2019
(https://developer.arm.com/docs/101028/latest)
Patch by Javed Absar and Momchil Velikov
Differential Revision: https://reviews.llvm.org/D64416
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366322
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Justin Hibbits [Wed, 17 Jul 2019 12:30:48 +0000 (12:30 +0000)]
PowerPC: Fix register spilling for SPE registers
Summary:
Missed in the original commit, use the correct callee-saved register
list for spilling, instead of the standard SVR432 list. This avoids
needlessly spilling the SPE non-volatile registers when they're not used.
As part of this, also add where missing, and sort, the spill opcode
checks for SPE and SPE4 register classes.
Reviewers: nemanjai, hfinkel, joerg
Subscribers: kbarton, jsji, llvm-commits
Differential Revision: https://reviews.llvm.org/D56703
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366319
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Justin Hibbits [Wed, 17 Jul 2019 12:30:04 +0000 (12:30 +0000)]
PowerPC/SPE: Fix load/store handling for SPE
Summary:
Pointed out in a comment for D49754, register spilling will currently
spill SPE registers at almost any offset. However, the instructions
`evstdd` and `evldd` require a) 8-byte alignment, and b) a limit of 256
(unsigned) bytes from the base register, as the offset must fix into a
5-bit offset, which ranges from 0-31 (indexed in double-words).
The update to the register spill test is taken partially from the test
case shown in D49754.
Additionally, pointed out by Kei Thomsen, globals will currently use
evldd/evstdd, though the offset isn't known at compile time, so may
exceed the 8-bit (unsigned) offset permitted. This fixes that as well,
by forcing it to always use evlddx/evstddx when accessing globals.
Part of the patch contributed by Kei Thomsen.
Reviewers: nemanjai, hfinkel, joerg
Subscribers: kbarton, jsji, llvm-commits
Differential Revision: https://reviews.llvm.org/D54409
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366318
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Petar Avramovic [Wed, 17 Jul 2019 12:08:01 +0000 (12:08 +0000)]
[MIPS GlobalISel] ClampScalar and select pointer G_ICMP
Add narrowScalar to half of original size for G_ICMP.
ClampScalar G_ICMP's operands 2 and 3 to to s32.
Select G_ICMP for pointers for MIPS32. Pointer compare is same
as for integers, it is enough to declare them as legal type.
Differential Revision: https://reviews.llvm.org/D64856
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366317
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Nicolai Haehnle [Wed, 17 Jul 2019 11:22:57 +0000 (11:22 +0000)]
AMDGPU/GFX10: Apply the VMEM-to-scalar-write hazard also to writes to EXEC
Summary: Change-Id: I854fbf7d48e937bef9f8f3f5d0c8aeb970652630
Reviewers: rampitec, mareko
Subscribers: arsenm, kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D64807
Change-Id: I4405b3a7f84186acea5a78d291bff71056e745fc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366314
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Nicolai Haehnle [Wed, 17 Jul 2019 11:22:19 +0000 (11:22 +0000)]
AMDGPU: Improve alias analysis for GDS
Summary: GDS cannot alias anything else.
Original patch by: Marek Olšák
Reviewers: arsenm, mareko
Subscribers: kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, t-tye, Petar.Avramovic, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D64114
Change-Id: I07bfbd96f5d5c37a6dfba7997df12f291dd794b0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366313
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Momchil Velikov [Wed, 17 Jul 2019 10:53:13 +0000 (10:53 +0000)]
[TableGen] Do not set ReadNone attribute on intrinsics with side effects
If an intrinsic is defined without outputs, but having side effects,
it still can be removed completely from the program. This patch makes
TableGen not set Attribute::ReadNone for intrinsics which
are declared with IntrHasSideEffects.
Differential Revision: https://reviews.llvm.org/D64414
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366312
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Owen Reynolds [Wed, 17 Jul 2019 10:16:44 +0000 (10:16 +0000)]
[llvm-ar][test] Add coverage for replace and update key letters
Some more tests to increase llvm-ar test coverage, this time for replace 'r' and update 'u'.
Differential Revision: https://reviews.llvm.org/D64803
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366309
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Diana Picus [Wed, 17 Jul 2019 10:01:27 +0000 (10:01 +0000)]
[ARM GlobalISel] Cleanup CallLowering. NFC
Migrate CallLowering::lowerReturnVal to use the same infrastructure as
lowerCall/FormalArguments and remove the now obsolete code path from
splitToValueTypes.
Forgot to push this earlier.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366308
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Simon Atanasyan [Wed, 17 Jul 2019 08:12:03 +0000 (08:12 +0000)]
[mips] Remove redundant test case. NFC
The `inlineasm-constraint-reg64.ll` test checks the same functionality.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366303
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Simon Atanasyan [Wed, 17 Jul 2019 08:11:57 +0000 (08:11 +0000)]
[mips] Name inline asm constraint test cases in a uniform manner. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366302
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Simon Atanasyan [Wed, 17 Jul 2019 08:11:40 +0000 (08:11 +0000)]
[mips] Use mult/mflo pattern on 64-bit targets prior to MIPS64
The `MUL` instruction is available starting from the MIPS32/MIPS64 targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366301
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Simon Atanasyan [Wed, 17 Jul 2019 08:11:31 +0000 (08:11 +0000)]
[mips] Implement .cplocal directive
This directive forces to use the alternate register for context pointer.
For example, this code:
.cplocal $4
jal foo
expands to:
ld $25, %call16(foo)($4)
jalr $25
Differential Revision: https://reviews.llvm.org/D64743
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366300
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Simon Atanasyan [Wed, 17 Jul 2019 08:11:15 +0000 (08:11 +0000)]
[mips] Support the "o" inline asm constraint
As well as other LLVM targets we do not handle "offsettable"
memory addresses in any special way. In other words, the "o" constraint
is an exact equivalent of the "m" one. But some existing code require
the "o" constraint support.
This fixes PR42589.
Differential Revision: https://reviews.llvm.org/D64792
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366299
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Serguei Katkov [Wed, 17 Jul 2019 07:09:20 +0000 (07:09 +0000)]
[LoopInfo] Fix getUniqueNonLatchExitBlocks
It is possible that exit block has two predecessors and one of them is a latch
block while another is not.
Current algorithm is based on the assumption that all exits are dedicated
and therefore we can check only first predecessor of loop exit to find all unique
exits.
However if we do not consider latch block and it is first predecessor of some
exit then this exit will be found.
Regression test is added.
As a side effect of algorithm re-writing, the restriction that all exits are dedicated
is eliminated.
Reviewers: reames, fhahn, efriedma
Reviewed By: efriedma
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D64787
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366294
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Qiu Chaofan [Wed, 17 Jul 2019 07:02:02 +0000 (07:02 +0000)]
Update email address.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366291
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Nico Weber [Wed, 17 Jul 2019 01:21:14 +0000 (01:21 +0000)]
gn build: Merge r366265
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366289
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Nico Weber [Wed, 17 Jul 2019 01:19:30 +0000 (01:19 +0000)]
gn build: Merge r366216
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366288
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Stanislav Mekhanoshin [Tue, 16 Jul 2019 23:44:21 +0000 (23:44 +0000)]
[AMDGPU] Autogenerate register asm names
Differential Revision: https://reviews.llvm.org/D64839
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366283
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Matt Arsenault [Tue, 16 Jul 2019 22:41:38 +0000 (22:41 +0000)]
ARM: Fix missing immarg for space intrinsic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366280
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Matt Arsenault [Tue, 16 Jul 2019 22:41:34 +0000 (22:41 +0000)]
GlobalISel: Add overload of handleAssignments with CCState
AMDGPU needs to allocate special argument registers separately from
the user function argument list, so needs direct control over the
CCState.
The ArgLocs argument is only really necessary because CCState doesn't
allow access to it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366279
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Justin Bogner [Tue, 16 Jul 2019 22:39:18 +0000 (22:39 +0000)]
[TableGen] Generate offsets into a flat array for getOperandType
Rather than an array of std::initializer_list, generate a table of
offsets and a flat array of the operands for getOperandType. This is a
bit more efficient on platforms that don't manage to get the array of
inintializer_lists initialized at link time (I'm looking at you
macOS). It's also quite quite a bit faster to compile.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366278
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Guanzhong Chen [Tue, 16 Jul 2019 22:22:08 +0000 (22:22 +0000)]
[WebAssembly] Compile all TLS on Emscripten as local-exec
Summary:
Currently, on Emscripten, dynamic linking is not supported with threads.
This means that if thread-local storage is used, it must be used in a
statically-linked executable. Hence, local-exec is the only possible model.
This diff compiles all TLS variables to use local-exec on Emscripten as a
temporary measure until dynamic linking is supported with threads.
The goal for this is to allow C++ types with constructors to be thread-local.
Currently, when `clang` compiles a `thread_local` variable with a constructor,
it generates `__tls_guard` variable:
@__tls_guard = internal thread_local global i8 0, align 1
As no TLS model is specified, this is treated as general-dynamic, which we do
not support (and cannot support without implementing dynamic linking support
with threads in Emscripten). As a result, any C++ constructor in `thread_local`
variables would not compile.
By compiling all `thread_local` as local-exec, `__tls_guard` will compile and
we can support C++ constructors with TLS without implementing dynamic linking
with threads.
Depends on D64537
Reviewers: tlively, aheejin, sbc100
Reviewed By: aheejin
Subscribers: dschuff, jgravelle-google, hiraditya, sunfish, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D64776
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366275
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Justin Bogner [Tue, 16 Jul 2019 22:10:16 +0000 (22:10 +0000)]
[TableGen] Add "getOperandType" to get operand types from opcode/opidx
The InstrInfoEmitter outputs an enum called "OperandType" which gives
numerical IDs to each operand type. This patch makes use of this enum
to define a function called "getOperandType", which allows looking up
the type of an operand given its opcode and operand index.
Patch by Nicolas Guillemot. Thanks!
Differential Revision: https://reviews.llvm.org/D63320
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366274
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Guanzhong Chen [Tue, 16 Jul 2019 22:00:45 +0000 (22:00 +0000)]
[WebAssembly] Implement thread-local storage (local-exec model)
Summary:
Thread local variables are placed inside a `.tdata` segment. Their symbols are
offsets from the start of the segment. The address of a thread local variable
is computed as `__tls_base` + the offset from the start of the segment.
`.tdata` segment is a passive segment and `memory.init` is used once per thread
to initialize the thread local storage.
`__tls_base` is a wasm global. Since each thread has its own wasm instance,
it is effectively thread local. Currently, `__tls_base` must be initialized
at thread startup, and so cannot be used with dynamic libraries.
`__tls_base` is to be initialized with a new linker-synthesized function,
`__wasm_init_tls`, which takes as an argument a block of memory to use as the
storage for thread locals. It then initializes the block of memory and sets
`__tls_base`. As `__wasm_init_tls` will handle the memory initialization,
the memory does not have to be zeroed.
To help allocating memory for thread-local storage, a new compiler intrinsic
is introduced: `__builtin_wasm_tls_size()`. This instrinsic function returns
the size of the thread-local storage for the current function.
The expected usage is to run something like the following upon thread startup:
__wasm_init_tls(malloc(__builtin_wasm_tls_size()));
Reviewers: tlively, aheejin, kripken, sbc100
Subscribers: dschuff, jgravelle-google, hiraditya, sunfish, jfb, cfe-commits, llvm-commits
Tags: #clang, #llvm
Differential Revision: https://reviews.llvm.org/D64537
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366272
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Matt Arsenault [Tue, 16 Jul 2019 22:00:10 +0000 (22:00 +0000)]
AMDGPU: Partially revert r366250
GCCBuiltin doesn't work for these, because they have a mangled type
(although they arguably should not).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366271
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Lang Hames [Tue, 16 Jul 2019 21:41:43 +0000 (21:41 +0000)]
[ORC][docs] Fix an RST error: the code-block directive needs a newline after it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366270
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Lang Hames [Tue, 16 Jul 2019 21:34:59 +0000 (21:34 +0000)]
[ORC][docs] Trim ORCv1 to ORCv2 transition section, add a how-to section.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366269
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Sanjay Patel [Tue, 16 Jul 2019 21:30:41 +0000 (21:30 +0000)]
[x86] use more phadd for reductions
This is part of what is requested by PR42023:
https://bugs.llvm.org/show_bug.cgi?id=42023
There's an extension needed for FP add, but exactly how we would specify
that using flags is not clear to me, so I left that as a TODO.
We're still missing patterns for partial reductions when the input vector
is 256-bit or 512-bit, but I think that's a failure of vector narrowing.
If we can reduce the widths, then this matching should work on those tests.
Differential Revision: https://reviews.llvm.org/D64760
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366268
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David Blaikie [Tue, 16 Jul 2019 21:15:19 +0000 (21:15 +0000)]
DWARF: Skip zero column for inline call sites
D64033 <https://reviews.llvm.org/D64033> added DW_AT_call_column for
inline sites. However, that change wasn't aware of "-gno-column-info".
To avoid adding column info when "-gno-column-info" is used, now
DW_AT_call_column is only added when we have non-zero column (when
"-gno-column-info" is used, column will be zero).
Patch by Wenlei He!
Differential Revision: https://reviews.llvm.org/D64784
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366264
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Matt Arsenault [Tue, 16 Jul 2019 20:31:25 +0000 (20:31 +0000)]
AMDGPU/GlobalISel: Select G_ASHR
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366257
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Matt Arsenault [Tue, 16 Jul 2019 20:25:43 +0000 (20:25 +0000)]
AMDGPU/GlobalISel: Select G_LSHR
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366256
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Jinsong Ji [Tue, 16 Jul 2019 20:24:33 +0000 (20:24 +0000)]
[PowerPC][HTM] Fix impossible reg-to-reg copy assert with ttest builtin
Summary:
This is exposed by our internal testing.
The reduced testcase will assert with "Impossible reg-to-reg copy"
We can't use COPY to do 32-bit to 64-bit conversion.
Reviewers: kbarton, hfinkel, nemanjai
Reviewed By: hfinkel
Subscribers: hiraditya, MaskRay, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D64499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366255
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Matt Arsenault [Tue, 16 Jul 2019 20:15:30 +0000 (20:15 +0000)]
AMDGPU/GlobalISel: Select G_SHL
I think this manages to not break the DAG handling with the divergent
predicates because the stadalone divergent patterns end up with a
higher priority than the pattern on the instruction definition.
The 16-bit versions don't work yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366254
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Stanislav Mekhanoshin [Tue, 16 Jul 2019 20:06:00 +0000 (20:06 +0000)]
[AMDGPU] Change register type for v32 vectors
When it is AReg_1024 this results in unnecessary copying into
AGPRs of a 32 element vectors even though they are not intended
for an mfma instruction.
Differential Revision: https://reviews.llvm.org/D64815
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366252
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Michael Liao [Tue, 16 Jul 2019 19:59:08 +0000 (19:59 +0000)]
Fix -Wreturn-type warning. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366251
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Matt Arsenault [Tue, 16 Jul 2019 19:44:14 +0000 (19:44 +0000)]
AMDGPU: Fix some missing GCCBuiltin declarations
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366250
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Matt Arsenault [Tue, 16 Jul 2019 19:27:44 +0000 (19:27 +0000)]
AMDGPU/GlobalISel: Fix selection of private stores
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366249
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Matt Arsenault [Tue, 16 Jul 2019 19:22:21 +0000 (19:22 +0000)]
AMDGPU/GlobalISel: Select private loads
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366248
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Matt Arsenault [Tue, 16 Jul 2019 18:42:53 +0000 (18:42 +0000)]
AMDGPU/GlobalISel: Select flat stores
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366246
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Matt Arsenault [Tue, 16 Jul 2019 18:26:42 +0000 (18:26 +0000)]
AMDGPU: Add register classes to flat store patterns
For some reason GlobalISelEmitter needs register classes to import
these, although it works for the load patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366242
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Philip Reames [Tue, 16 Jul 2019 18:23:49 +0000 (18:23 +0000)]
[IndVars] Speculative fix for an assertion failure seen in bots
I don't have an IR sample which is actually failing, but the issue described in the comment is theoretically possible, and should be guarded against even if there's a different root cause for the bot failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366241
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Matt Arsenault [Tue, 16 Jul 2019 18:21:25 +0000 (18:21 +0000)]
AMDGPU: Replace store PatFrags
Convert the easy cases to formats understood for GlobalISel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366240
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Matt Arsenault [Tue, 16 Jul 2019 18:05:29 +0000 (18:05 +0000)]
AMDGPU/GlobalISel: Select flat loads
Now that the patterns use the new PatFrag address space support, the
only blocker to importing most load patterns is the addressing mode
complex patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366237
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Nico Weber [Tue, 16 Jul 2019 18:04:26 +0000 (18:04 +0000)]
Teach `llvm-pdbutil pretty -native` about `-injected-sources`
`pretty -native -injected-sources -injected-source-content` works with
this patch, and produces identical output to the dia version.
Differential Revision: https://reviews.llvm.org/D64428
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366236
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Jay Foad [Tue, 16 Jul 2019 17:44:54 +0000 (17:44 +0000)]
[AMDGPU] Optimize atomic max/min
Summary:
Extend the atomic optimizer to handle signed and unsigned max and min
operations, as well as add and subtract.
Reviewers: arsenm, sheredom, critson, rampitec
Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, jfb, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D64328
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366235
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Matt Arsenault [Tue, 16 Jul 2019 17:38:50 +0000 (17:38 +0000)]
AMDGPU: Redefine load PatFrags
Rewrite PatFrags using the new PatFrag address space matching in
tablegen. These will now work with both SelectionDAG and GlobalISel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366234
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Matt Arsenault [Tue, 16 Jul 2019 17:22:21 +0000 (17:22 +0000)]
AMDGPU: Fix missing immarg for mfma intrinsics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366230
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Michael Liao [Tue, 16 Jul 2019 15:57:12 +0000 (15:57 +0000)]
[AMDGPU] Add the adjusted FP as a livein register.
Reviewers: arsenm, rampitec
Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D64145
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366223
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Ulrich Weigand [Tue, 16 Jul 2019 15:55:45 +0000 (15:55 +0000)]
[Strict FP] Allow more relaxed scheduling
Reimplement scheduling constraints for strict FP instructions in
ScheduleDAGInstrs::buildSchedGraph to allow for more relaxed
scheduling. Specifially, allow one strict FP instruction to
be scheduled across another, as long as it is not moved across
any global barrier.
Differential Revision: https://reviews.llvm.org/D64412
Reviewed By: cameron.mcinally
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366222
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Alex Brachet [Tue, 16 Jul 2019 15:33:43 +0000 (15:33 +0000)]
Revert [tools] [llvm-nm] Default to reading from stdin not a.out
This reverts r365889 (git commit
60c81354b1d3fced1bd284d334f118d2d792ab4b)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366219
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Amara Emerson [Tue, 16 Jul 2019 15:28:29 +0000 (15:28 +0000)]
Add missing test for r366215
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366218
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Francis Visoiu Mistrih [Tue, 16 Jul 2019 15:25:05 +0000 (15:25 +0000)]
[Remarks] Simplify and refactor the RemarkParser interface
Before, everything was based on some kind of type erased parser
implementation which container a lot of boilerplate code when multiple
formats were to be supported.
This simplifies it by:
* the remark now owns its arguments
* *always* returning an error from the implementation side
* working around the way the YAML parser reports errors: catch them through
callbacks and re-insert them in a proper llvm::Error
* add a CParser wrapper that is used when implementing the C API to
avoid cluttering the C++ API with useless state
* LLVMRemarkParserGetNext now returns an object that needs to be
released to avoid leaking resources
* add a new API to dispose of a remark entry: LLVMRemarkEntryDispose
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366217
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