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Alex Deucher [Thu, 28 Mar 2019 15:12:39 +0000 (10:12 -0500)]
Revert "drm/amdgpu: more descriptive message if HMM not enabled"
This reverts commit
194f87ddffe26bbbd124c549a9bf12a96a7f2919.
This depends on an HMM fix which is not upstream yet.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Tue, 26 Mar 2019 09:16:36 +0000 (17:16 +0800)]
drm/amd/powerplay: update current profile mode only when it's really applied
No need to update current profile mode if the new profile mode
does not take effect in fact.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kent Russell <kent.russell@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dmytro Laktyushkin [Fri, 15 Mar 2019 17:59:25 +0000 (13:59 -0400)]
drm/amd/display: fix odm output gamma programming
Currently only top pipe gets output tf programmed. This change
makes all odm head pipes get output tf programmed.
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Joshua Aberback [Mon, 18 Mar 2019 17:40:47 +0000 (13:40 -0400)]
drm/amd/display: Populate macro_tile_size field for dml
Create a functions to return swizzle types for dml
Signed-off-by: Joshua Aberback <joshua.aberback@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Eric Bernstein [Thu, 28 Feb 2019 19:45:13 +0000 (14:45 -0500)]
drm/amd/display: use dc_is_virtual instead of ENUM
Signed-off-by: Eric Bernstein <eric.bernstein@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Nevenko Stupar <Nevenko.Stupar@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aric Cyr [Sat, 16 Mar 2019 20:06:58 +0000 (16:06 -0400)]
drm/amd/display: 3.2.24
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nikola Cornij [Wed, 13 Mar 2019 00:11:37 +0000 (20:11 -0400)]
drm/amd/display: Pass SDP spliting in parameters
pass SDP splitting when setting stream attributes for future use
Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Eryk Brol [Wed, 13 Mar 2019 15:51:15 +0000 (11:51 -0400)]
drm/amd/display: Create clock funcs
Create dccg_init and init_clocks for future use
Signed-off-by: Eryk Brol <eryk.brol@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Fatemeh Darbehani [Tue, 12 Mar 2019 17:57:36 +0000 (13:57 -0400)]
drm/amd/display: Clean up old pplib interface functions
[Why]
set_display_requirement, dcn1_pplib_apply_display_requirements
are no longer used and should be removed.
Signed-off-by: Fatemeh Darbehani <fatemeh.darbehani@amd.com>
Reviewed-by: Hersen Wu <hersenxs.wu@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Harry Wentland [Wed, 13 Feb 2019 21:20:27 +0000 (16:20 -0500)]
drm/amd/display: Pass init_data into DCN resource creation
[WHY]
The resource constructor currently needs num_virtual_links from
init_data but will need access to other items provided by DM.
[HOW]
Pass init_data into DCN create_resource_pool functions.
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Acked-by: Hersen Wu <hersenxs.wu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hugo Hu [Mon, 25 Feb 2019 11:16:52 +0000 (19:16 +0800)]
drm/amd/display: Handle branch device with DFP count = 0 case.
[Why]
When you have a SST branch device the driver, Even no sink device connected,
it also send HPD with a valid EDID. Driver will config it to DP sink.
Therefore, there're two displays in display setting.
DPCD 0x05, DFP_PRESENT = 1 (branch device),
DFP_TYPE = 00 (Display Port)
[How]
Driver determine DPCD 0x05 DFP_PRESENT = 1(branch) as an active dongle
And check DFP count.
Signed-off-by: Hugo Hu <hugo.hu@amd.com>
Reviewed-by: Hugo Hu <Hugo.Hu@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
hersen wu [Fri, 1 Mar 2019 16:54:02 +0000 (11:54 -0500)]
drm/amd/display: program default output gamma
program default output gamma if no user specific gamma
parameters passed.
Signed-off-by: hersen wu <hersenxs.wu@amd.com>
Reviewed-by: Sun peng Li <Sunpeng.Li@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jun Lei [Tue, 12 Mar 2019 19:12:41 +0000 (15:12 -0400)]
drm/amd/display: add preferred pipe split logic
[why]
existing logic finds "first free pipe from 5 -> 0" to split
this will cause certain sequences to require DC to move
an MPCC from one tree to another, which is unsupported
this leads to blackscreen
to mitigate this problem, we will always try to acquire the
"preferred" pipe, and each pipe has a unique preferred pipe
this means we avoid most of the scenarios where
pipe splitting leads to moving MPCC from one tree
to another
Signed-off-by: Jun Lei <Jun.Lei@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Wed, 27 Mar 2019 10:34:24 +0000 (11:34 +0100)]
drm/amdgpu: don't put the root PD into the relocated list
Instead of skipping the root PD while processing the relocated list just never
put it on the list in the first place.
This avoids walking the list all together when the root PD is the only entry
and so also avoids trying to submit a zero sized IB to the SDMA.
Signed-off-by: Christian König <christian.koenig@amd.com>
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Thu, 21 Mar 2019 15:43:39 +0000 (16:43 +0100)]
drm/amdgpu: drop the ib from the VM update parameters
It is redundant with the job pointer.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Thu, 21 Mar 2019 15:34:18 +0000 (16:34 +0100)]
drm/amdgpu: move VM table mapping into the backend as well
Clean that up further and also fix another case where the BO
wasn't kmapped for CPU based updates.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
shaoyunl [Wed, 20 Mar 2019 20:14:56 +0000 (16:14 -0400)]
drm/amdgpu: XGMI pstate switch initial support
Driver vote low to high pstate switch whenever there is an outstanding
XGMI mapping request. Driver vote high to low pstate when all the
outstanding XGMI mapping is terminated.
Signed-off-by: shaoyunl <shaoyun.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Mon, 18 Mar 2019 20:15:57 +0000 (21:15 +0100)]
drm/amdgpu: use the new VM backend for clears
And remove the existing code when it is unused.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Fri, 15 Mar 2019 08:25:15 +0000 (16:25 +0800)]
drm/amdgpu: defer cmd/fence/fw buffers destroy on hw_init failure
As the cleanup jobs performed in pre_fini may still need these
buffers. NULL pointer dereference will be triggered without them.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Fri, 15 Mar 2019 02:26:49 +0000 (10:26 +0800)]
drm/amdgpu: add more debug friendly prompts
Large piece of codes share one error prompt. That
is not friendly for debugging.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Fri, 15 Mar 2019 02:02:59 +0000 (10:02 +0800)]
drm/amdgpu: error out on mode1 reset failure
The error return value should be correctly reflected.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Fri, 15 Mar 2019 02:04:34 +0000 (10:04 +0800)]
drm/amdgpu: trivial typo fix
"error" was not correctly spelled.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
xinhui pan [Thu, 21 Mar 2019 07:00:47 +0000 (15:00 +0800)]
drm/amdgpu: remove per obj debugfs write
there is ras_control node which can do its job.
Signed-off-by: xinhui pan <xinhui.pan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
xinhui pan [Thu, 21 Mar 2019 07:13:38 +0000 (15:13 +0800)]
drm/amdgpu: Fix amdgpu ras to ta enums conversion
Add helpes to transalte the two enums. And it will catch bugs
easily.
Signed-off-by: xinhui pan <xinhui.pan@amd.com>
Signed-off-by: Nathan Chancellor <natechancellor@gmail.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
xinhui pan [Thu, 21 Mar 2019 04:47:07 +0000 (12:47 +0800)]
drm/amdgpu: use macro instead of enum for flags
better to use macro.
Signed-off-by: xinhui pan <xinhui.pan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
xinhui pan [Tue, 19 Mar 2019 03:16:32 +0000 (11:16 +0800)]
drm/amdgpu: Fix some sanity check
ras context might be NULL, so move con->h_data after check !con
also fix sizeof wrong type while at it.
Signed-off-by: xinhui pan <xinhui.pan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dan Carpenter [Thu, 21 Mar 2019 06:28:22 +0000 (09:28 +0300)]
drm/amd/powerplay: Fix double unlock bug in smu_sys_set_pp_table()
We already unlocked a few lines earlier so this code unlocks twice on
the success path.
Fixes:
289921b03fe5e ("drm/amd/powerplay: implement sysfs of pp_table for smu11 (v2)")
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dan Carpenter [Thu, 21 Mar 2019 09:19:57 +0000 (12:19 +0300)]
drm/amd/powerplay: Off by one in vega20_get_smu_msg_index()
The > should be >= so that we don't read one element beyond the end of
the vega20_message_map[] array.
Fixes:
78031c2c4dcd ("drm/amd/powerplay: implement smu vega20_message_map for vega20")
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dan Carpenter [Thu, 21 Mar 2019 06:27:07 +0000 (09:27 +0300)]
drm/amd/powerplay: delete some dead code
The "size" variable is unsigned. We never pass invalid sizes to this
function and we already used it as an array offset earlier so it's
too late to check here.
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Wed, 20 Mar 2019 21:15:22 +0000 (16:15 -0500)]
drm/amdgpu/display: fix build when DCN KCONFIG is not set
Leads to an undefined symbol otherwise.
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Tue, 19 Mar 2019 12:03:45 +0000 (13:03 +0100)]
drm/amdgpu: revert "XGMI pstate switch initial support"
This reverts commit
9b638f9751308ae3ae8f28e0c6e9decffd97f5f9.
Adding this to the mapping is complete nonsense and the whole
implementation looks racy. This patch wasn't thoughtfully reviewed
and should be reverted for now.
Signed-off-by: Christian König <christian.koenig@amd.com>
Acked-by: Liu, Shaoyun <Shaoyun.Liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Mon, 18 Mar 2019 19:19:36 +0000 (20:19 +0100)]
drm/amdgpu: use the new VM backend for PTEs
And remove the existing code when it is unused.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Mon, 18 Mar 2019 13:26:24 +0000 (14:26 +0100)]
drm/amdgpu: use the new VM backend for PDEs
And remove the existing code when it is unused.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Mon, 18 Mar 2019 12:16:03 +0000 (13:16 +0100)]
drm/amdgpu: new VM update backends
Separate out all functions for SDMA and CPU based page table
updates into separate backends.
This way we can keep most of the complexity of those from the
core VM code.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Mon, 18 Mar 2019 14:28:25 +0000 (15:28 +0100)]
drm/amdgpu: reserve less memory for PDE updates
Allocating 16KB was way to much, just use 2KB as a start for now.
Signed-off-by: Christian König <christian.koenig@amd.com>
Acked-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Mon, 18 Mar 2019 11:27:35 +0000 (12:27 +0100)]
drm/amdgpu: move and rename amdgpu_pte_update_params
Move the update parameter into the VM header and rename them.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Mon, 18 Mar 2019 11:24:03 +0000 (12:24 +0100)]
drm/amdgpu: always set and check dma addresses in the VM code
Clean that up a bit and allow to always have the DMA addresses around.
Signed-off-by: Christian König <christian.koenig@amd.com>
Acked-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Mon, 18 Mar 2019 14:27:20 +0000 (15:27 +0100)]
drm/amdgpu: remove some unused VM defines
Not needed any more.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Tue, 19 Mar 2019 13:25:12 +0000 (21:25 +0800)]
drm/amdgpu: add one rlc version into gfxoff blacklist
RLC #53815 ucode has the noise issue on 4k playback while gfxoff enabled.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Tested-by: Tom St Denis <tom.stdenis@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Wed, 13 Mar 2019 12:21:00 +0000 (20:21 +0800)]
drm/amdgpu: enable gfxoff again on raven series (v2)
This patch enables gfxoff and stutter mode again, since we take more testing on
raven series. For raven2 and picasso, we can enable it directly. And for raven,
we need check the RLC/SMC ucode version cannot be less than #531/0x1e45.
v2: add smc version checking for raven.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> (v1)
Tested-by: Likun Gao <Likun.Gao@amd.com> (v2)
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Colin Ian King [Wed, 20 Mar 2019 17:29:09 +0000 (17:29 +0000)]
drm/amd/powerplay: fix spelling mistake "unknow" -> "unknown"
There is a spelling mistake in pr_warn message; fix it.
Signed-off-by: Colin Ian King <colin.king@canonical.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nathan Chancellor [Wed, 20 Mar 2019 00:58:42 +0000 (17:58 -0700)]
drm/amd/powerplay: Zero initialize num_of_levels in vega20_set_single_dpm_table
When building with -Wsometimes-uninitialized, Clang warns:
drivers/gpu/drm/amd/amdgpu/../powerplay/vega20_ppt.c:456:2: warning:
variable 'num_of_levels' is used uninitialized whenever '?:' condition
is false [-Wsometimes-uninitialized]
smu_read_smc_arg(smu, &num_of_levels);
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../powerplay/inc/amdgpu_smu.h:608:3: note:
expanded from macro 'smu_read_smc_arg'
((smu)->funcs->read_smc_arg? (smu)->funcs->read_smc_arg((smu), (arg)) : 0)
^~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../powerplay/vega20_ppt.c:457:7: note:
uninitialized use occurs here
if (!num_of_levels) {
^~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../powerplay/vega20_ppt.c:456:2: note: remove
the '?:' if its condition is always true
smu_read_smc_arg(smu, &num_of_levels);
^
drivers/gpu/drm/amd/amdgpu/../powerplay/inc/amdgpu_smu.h:608:3: note:
expanded from macro 'smu_read_smc_arg'
((smu)->funcs->read_smc_arg? (smu)->funcs->read_smc_arg((smu), (arg)) : 0)
^
drivers/gpu/drm/amd/amdgpu/../powerplay/vega20_ppt.c:446:27: note:
initialize the variable 'num_of_levels' to silence this warning
uint32_t i, num_of_levels, clk;
^
= 0
1 warning generated.
The if statement it mentions as potentially problematic is currently
always true because the read_smc_arg callback is assigned at the
bottom of this file but Clang can't tell that. If the callback were
ever to disappear, num_of_levels would never be initialized. Just
zero initialize it to ensure that the intent behind this code
remains the same.
Link: https://github.com/ClangBuiltLinux/linux/issues/425
Signed-off-by: Nathan Chancellor <natechancellor@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
YueHaibing [Wed, 20 Mar 2019 12:59:39 +0000 (12:59 +0000)]
drm/ttm: remove set but not used variable 'rdev'
Fixes gcc '-Wunused-but-set-variable' warning:
drivers/gpu/drm/radeon/radeon_ttm.c: In function 'radeon_move_vram_ram':
drivers/gpu/drm/radeon/radeon_ttm.c:254:24: warning:
variable 'rdev' set but not used [-Wunused-but-set-variable]
drivers/gpu/drm/radeon/radeon_ttm.c: In function 'radeon_move_ram_vram':
drivers/gpu/drm/radeon/radeon_ttm.c:301:24: warning:
variable 'rdev' set but not used [-Wunused-but-set-variable]
It's not used since
a987fcaa805f ("ttm: Make parts of a struct ttm_bo_device
global.")
Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nicholas Kazlauskas [Thu, 14 Mar 2019 16:53:12 +0000 (12:53 -0400)]
drm/amd/display: Only put primary planes into the mode_info->planes list
We want DRM planes to be initialized in the following order:
- primary planes
- overlay planes
- cursor planes
to support existing userspace expectations for plane z-ordering. This
means that we also need to register CRTCs after all planes have been
initialized since overlay planes can be placed on any CRTC.
So the only reason why we have the mode_info->planes list is to
remember the primary planes for use later when we need to register
the CRTC.
Overlay planes have no purpose being in this list. DRM will cleanup
any planes that we've registered for us, so the only planes that need to
be explicitly cleaned up are the ones that have failed to register.
By dropping the explicit free on every plane in the mode_info->planes
list this patch also fixes a double-free in the case where we fail to
initialize only some of the planes.
Cc: Leo Li <sunpeng.li@amd.com>
Cc: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
David Francis [Tue, 5 Mar 2019 15:04:15 +0000 (10:04 -0500)]
drm/amd/display: Add debugfs dpcd interface
[Why]
We need arbitrary read/write over DP AUX DPCD
for debugging
[How]
Three debugfs entries
Set the target address by writing to
"aux_dpcd_address"
(The first four bytes written are used)
Set the transaction size in bytes by writing to
"aux_dpcd_size"
(The first four bytes written are used)
Start a transaction by reading/writing
"aux_dpcd_data"
Do note: there is no concerrency protection at all
Accessing these entries in quick succession can lead
to strange behaviour
Signed-off-by: David Francis <David.Francis@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leo (Hanghong) Ma [Thu, 7 Mar 2019 21:18:12 +0000 (16:18 -0500)]
drm/amd/display: Generic SDP message access in amdgpu
[Why]
We need to add DP SDP message test debugfs to make sdp message test
more convenient and efficient.
[How]
Add sdp_message debugfs entry in amdgpu.
Signed-off-by: Leo (Hanghong) Ma <hanghong.ma@amd.com>
Reviewed-by: Sun peng Li <Sunpeng.Li@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Acked-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leo (Hanghong) Ma [Thu, 7 Mar 2019 20:31:11 +0000 (15:31 -0500)]
drm/amd/display: Expose generic SDP message access interface
[Why]
We need to add DP SDP message test debugfs to make sdp message test
more convenient and efficient.
[How]
Add a DM accessible SDP interface for custom data.
Signed-off-by: Leo (Hanghong) Ma <hanghong.ma@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Roman Li <Roman.Li@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dmytro Laktyushkin [Sat, 9 Mar 2019 01:16:45 +0000 (20:16 -0500)]
drm/amd/display: fix odm pipe management
There are issues removing surfaces/streams when odm is active.
This is a step to fix that
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dmytro Laktyushkin [Fri, 8 Mar 2019 22:09:46 +0000 (17:09 -0500)]
drm/amd/display: add missing opp programming for odm
A number of places opp programming was missing for odm second pipe.
This change fixes the oversight.
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dmytro Laktyushkin [Fri, 8 Mar 2019 21:44:53 +0000 (16:44 -0500)]
drm/amd/display: fix odm combine pipe reset
We fail to reset the second odm combine pipe. This change fixes
odm pointer management.
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dmytro Laktyushkin [Thu, 7 Mar 2019 18:26:13 +0000 (13:26 -0500)]
drm/amd/display: fix releasing planes when exiting odm
Releasing planes should not release the 2nd odm pipe right away,
this change leaves us with 2 pipes with null planes and same stream
when planes are released during odm.
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aric Cyr [Fri, 8 Mar 2019 22:37:17 +0000 (17:37 -0500)]
drm/amd/display: 3.2.23
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reza Amini [Thu, 7 Mar 2019 22:36:29 +0000 (17:36 -0500)]
drm/amd/display: Fix VTEM InfoPacket programming
Refactor setting bit fields. Correcting the offset of MD0.
Initializing the InfoPacket header fields. Defining the field offsets
and masks.
Signed-off-by: Reza Amini <Reza.Amini@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Samson Tam [Mon, 4 Mar 2019 21:21:06 +0000 (16:21 -0500)]
drm/amd/display: Link train only when link is DP and backend is enabled
[Why]
In certain cases we do link training when we don't have a backend.
[How]
In dc_link_set_preferred_link_settings(), store preferred link settings
first and then verify that the link is DP and the link stream's backend is
enabled. If either is false, then we will not do any link retraining.
Signed-off-by: Samson Tam <Samson.Tam@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Wenjing Liu [Wed, 6 Mar 2019 00:28:10 +0000 (19:28 -0500)]
drm/amd/display: add global master update lock interfaces
Add these interfacese for future use
setup_global_lock()
lock_global()
pipe_control_lock_global()
Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Eric Bernstein [Fri, 22 Feb 2019 16:11:07 +0000 (11:11 -0500)]
drm/amd/display: Use dc_is_hdmi_signal() instead of ENUM
Signed-off-by: Eric Bernstein <eric.bernstein@amd.com>
Reviewed-by: Nevenko Stupar <Nevenko.Stupar@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Harmanprit Tatla [Fri, 1 Mar 2019 16:47:35 +0000 (11:47 -0500)]
drm/amd/display: cache additional dpcd caps for HDR capability check
[Why]
Currently we are missing a few checks to see if HDR10 is allowed.
In particular we never check for the extended colorimetry bit (whether its
present or set to 1). Further we don't read in the dpcd block in DC that
would provide these bits.
[How]
- Added in DC code to read in the block containing the extended colorimetry
bit.
Signed-off-by: Harmanprit Tatla <Harmanprit.Tatla@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
David Francis [Mon, 4 Mar 2019 15:31:31 +0000 (10:31 -0500)]
drm/amd/display: Update ABM crtc state on non-modeset
[Why]
Somewhere in the atomic check reshuffle ABM got lost.
ABM is a crtc property (copied from a connector property).
It can change without a modeset, just like underscan.
[How]
In the skip_modeset branch of atomic check crtc updates,
copy over the abm property.
Signed-off-by: David Francis <David.Francis@amd.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hugo Hu [Wed, 27 Feb 2019 07:18:08 +0000 (15:18 +0800)]
drm/amd/display: Programming correct VRR_EN bit in VTEM structure
[Why]
In HDMI plugfest, MTK report our EMP with VRR_EN bit = 0.
VRR_EN bit is EMP-MD0-bit 0. Currently driver set 1 to bit 3.
[How]
Programming correct VRR_EN bit in EMP-MD0-bit0.
Signed-off-by: Hugo Hu <hugo.hu@amd.com>
Reviewed-by: Reza Amini <Reza.Amini@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aric Cyr [Sun, 3 Mar 2019 03:35:45 +0000 (22:35 -0500)]
drm/amd/display: 3.2.22
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jun Lei [Fri, 1 Mar 2019 16:21:17 +0000 (11:21 -0500)]
drm/amd/display: extend EDID support to 1kb
[why]
There exist displays with EDIDs > 512 bytes, existing code
will cause us to ignore all extension blocks.
Signed-off-by: Jun Lei <Jun.Lei@amd.com>
Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Wesley Chalmers [Fri, 1 Mar 2019 19:28:19 +0000 (14:28 -0500)]
drm/amd/display: Fix DP audio regression
Audio was unmuted for HDMI only, need to do so for DP as well.
Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com>
Reviewed-by: Chris Park <Chris.Park@amd.com>
Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aric Cyr [Fri, 1 Mar 2019 15:24:37 +0000 (10:24 -0500)]
drm/amd/display: Add a hysteresis to BTR frame multiplier
[Why]
Flickering is observed on some displays when the number of inserted BTR
frames changes frequently.
[How]
Add in a margin of drift to prevent the inserted number of frames from
jumping around too frequently.
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Charlene Liu [Fri, 1 Mar 2019 16:12:50 +0000 (11:12 -0500)]
drm/amd/display: fix DP 422 VID_M half the rate issue.
[Description]
when programming VID_TIMING, we were using the original VESA timing for DP_VIDM/N.
for YCbCr420 or compressed YCbCr422, using half rate as YCbCr444.
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Eric Bernstein [Fri, 17 Aug 2018 21:57:44 +0000 (17:57 -0400)]
drm/amd/display: Fix setting DP_VID_N_MUL
[Why]
Need to set VID_N_MUL for 4:2:0 cases
[How]
Move setting to enc1_stream_encoder_dp_unblank and
ensure it is also set for non-4:2:0 cases.
Signed-off-by: Eric Bernstein <eric.bernstein@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yongqiang Sun [Thu, 28 Feb 2019 20:14:39 +0000 (15:14 -0500)]
drm/amd/display: Move dm_read_reg_func to dc_helper.
Move out of header to dc_helper.c, in preparation for future
implementations.
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nicholas Kazlauskas [Thu, 28 Feb 2019 18:38:13 +0000 (13:38 -0500)]
drm/amd/display: Use drm helper for resetting plane state
[Why]
To help prevent plane state not being set to the correct default
value if any new properties are added in the future.
[How]
Use the drm helper - which seems to be the common solution among other
DRM drivers.
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Sun peng Li <Sunpeng.Li@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yongqiang Sun [Tue, 26 Feb 2019 15:52:22 +0000 (10:52 -0500)]
drm/amd/display: change generic_reg_wait to void.
we were only checking the return value in one place, thus changing
generic_reg_wait from int to void and reading the register instead of
getting it from generic_reg_wait, when we need the return value.
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nicholas Kazlauskas [Thu, 28 Feb 2019 17:57:59 +0000 (12:57 -0500)]
drm/amd/display: Reset alpha state for planes to the correct values
[Why]
The plane_reset callback is subclassed but hasn't been updated since
the drm helper got updated to include resetting alpha related state
(state->alpha and state->pixel_blend_mode). The overlay planes
exposed by amdgpu_dm were therefore being rendered as invisible by
default ever since supported was exposed for alpha blending properties
on overlays.
This caused regressions in igt@kms_plane_multiple@atomic-tiling-none
and igt@kms_plane@plane-position-covered-pipe tests.
[How]
Reset the plane state values to their correct values as defined in
the drm helper.
This fixes the IGT test regression.
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Wed, 6 Mar 2019 15:10:45 +0000 (16:10 +0100)]
drm/amdgpu: use more entries for the first paging queue
To aid recoverable page faults.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Wed, 5 Dec 2018 13:24:21 +0000 (14:24 +0100)]
drm/amdgpu: free up the first paging queue v2
We need the first paging queue to handle page faults.
v2: handle any number of SDMA instances gracefully
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Mon, 5 Nov 2018 14:24:27 +0000 (15:24 +0100)]
drm/amdgpu: re-enable retry faults
Now that we have re-reoute faults to the other IH
ring we can enable retries again.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Wentao Lou [Wed, 13 Mar 2019 10:01:42 +0000 (18:01 +0800)]
drm/amdkfd/sriov:Put the pre and post reset in exclusive mode v2
add amdgpu_amdkfd_pre_reset and amdgpu_amdkfd_post_reset inside amdgpu_device_reset_sriov.
Signed-off-by: Wentao Lou <Wentao.Lou@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nicholas Kazlauskas [Wed, 13 Mar 2019 16:35:20 +0000 (12:35 -0400)]
drm/amd/display: Respect DRM framebuffer info for video surfaces
[Why]
Incorrect hardcoded assumptions are made regarding luma and chroma
alignment. The actual values set for the DRM framebuffer should be used
when programming the address.
[How]
Respect the given pitch for both luma and chroma planes - it's not like
we can force the alignment to anything else at this point anyway.
Use the FB offset for the chroma planes directly. DRM already
provides this to us so there's no need to calculate it manually.
While we don't actually use the chroma surface size parameters on Raven,
these should have technically been fb->width / 2 and fb->height / 2
since the chroma plane is half size of the luma plane for NV12.
Leave a TODO indicating that those should be set based on the actual
surface format instead since this is only correct for YUV420 formats.
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Felix Kuehling [Wed, 13 Mar 2019 12:30:48 +0000 (08:30 -0400)]
drm/amdgpu: Wait for newly allocated PTs to be idle
When page table are updated by the CPU, synchronize with the
allocation and initialization of newly allocated page tables.
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Philip Yang [Mon, 4 Mar 2019 15:37:55 +0000 (10:37 -0500)]
drm/amdgpu: more descriptive message if HMM not enabled
If using old kernel config file, CONFIG_ZONE_DEVICE is not selected,
so CONFIG_HMM and CONFIG_HMM_MIRROR is not enabled, the current driver
error message "Failed to register MMU notifier" is not clear. Inform
user with more descriptive message on how to fix the missing kernel
config option.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109808
Signed-off-by: Philip Yang <Philip.Yang@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Philip Yang [Mon, 4 Mar 2019 19:41:03 +0000 (14:41 -0500)]
drm/amdgpu: support userptr cross VMAs case with HMM
userptr may cross two VMAs if the forked child process (not call exec
after fork) malloc buffer, then free it, and then malloc larger size
buf, kerenl will create new VMA adjacent to old VMA which was cloned
from parent process, some pages of userptr are in the first VMA, the
rest pages are in the second VMA.
HMM expects range only have one VMA, loop over all VMAs in the address
range, create multiple ranges to handle this case. See
is_mergeable_anon_vma in mm/mmap.c for details.
Signed-off-by: Philip Yang <Philip.Yang@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Philip Yang [Mon, 4 Mar 2019 19:10:12 +0000 (14:10 -0500)]
drm/amdkfd: support concurrent userptr update for HMM
Userptr restore may have concurrent userptr invalidation after
hmm_vma_fault adds the range to the hmm->ranges list, needs call
hmm_vma_range_done to remove the range from hmm->ranges list first,
then reschedule the restore worker. Otherwise hmm_vma_fault will add
same range to the list, this will cause loop in the list because
range->next point to range itself.
Add function untrack_invalid_user_pages to reduce code duplication.
Signed-off-by: Philip Yang <Philip.Yang@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Wed, 7 Nov 2018 12:55:01 +0000 (13:55 +0100)]
drm/amdgpu: stop evicting busy PDs/PTs
Otherwise we won't be able to cleanly handle page faults.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Thu, 10 Jan 2019 15:48:23 +0000 (16:48 +0100)]
drm/amdgpu: wait for VM to become idle during flush
Make sure that not only the entities are flush, but that
we also wait for the HW to finish all processing.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Thu, 10 Jan 2019 15:40:42 +0000 (16:40 +0100)]
drm/amdgpu: remove non-sense NULL ptr check
It's a bug having a dead pointer in the IDR, silently returning
is the worst we can do.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Wed, 7 Nov 2018 12:55:01 +0000 (13:55 +0100)]
drm/amdgpu: remove chash
Remove the chash implementation for now since it isn't used any more.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Wed, 7 Nov 2018 12:55:01 +0000 (13:55 +0100)]
drm/amdgpu: use ring/hash for fault handling on GMC9 v3
Further testing showed that the idea with the chash doesn't work as expected.
Especially we can't predict when we can remove the entries from the hash again.
So replace the chash with a ring buffer/hash mix where entries in the container
age automatically based on their timestamp.
v2: use ring buffer / hash mix
v3: check the timeout to make sure all entries age
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> (v2)
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Tue, 5 Mar 2019 14:13:52 +0000 (15:13 +0100)]
drm/amdgpu: limit the number of IVs processed at once
Only process a maximum of 32 IVs before writing back the RPTR. This improves
hw handling when we get close to an overflow in the ring buffer.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Mon, 4 Mar 2019 18:59:36 +0000 (19:59 +0100)]
drm/amdgpu: enable IH ring 1&2 for Vega20 as well
That doesn't seem to have any negative effects.
Signed-off-by: Christian König <christian.koenig@amd.com>
Acked-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Wed, 27 Feb 2019 14:05:20 +0000 (15:05 +0100)]
drm/amdgpu: enable IH doorbell for ring 1&2 on Vega
The doorbells should already be reserved, just enable them.
Signed-off-by: Christian König <christian.koenig@amd.com>
Acked-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Wed, 27 Feb 2019 13:54:23 +0000 (14:54 +0100)]
drm/amdgpu: change Vega IH ring 1 config
Disable overflow and enable full drain. This makes fault handling on ring 1
much more reliable since we don't generate back pressure any more.
Signed-off-by: Christian König <christian.koenig@amd.com>
Acked-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nicholas Kazlauskas [Mon, 11 Mar 2019 18:16:29 +0000 (14:16 -0400)]
drm/amdgpu: Only clear dumb buffers if ring is enabled
The buffers should be cleared when possible but we also don't want
buffer creation to fail in the rare case where the ring isn't ready
during the call. This could happen during some suspend/resume sequences.
Cc: Christian König <ckoenig.leichtzumerken@gmail.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nicholas Kazlauskas [Fri, 8 Mar 2019 15:38:16 +0000 (10:38 -0500)]
drm/amdgpu: Clear VRAM for DRM dumb_create buffers
The dumb_create API isn't intended for high performance rendering
and it's more useful for userspace (ie. IGT) to have them precleared.
The bonus here is that we also won't needlessly leak whatever was
previously in VRAM, but it also probably wasn't sensitive if it was
going through this API.
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
kbuild test robot [Wed, 6 Mar 2019 05:26:11 +0000 (13:26 +0800)]
drm/amdgpu: fix semicolon.cocci warnings
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c:405:2-3: Unneeded semicolon
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c:435:2-3: Unneeded semicolon
Remove unneeded semicolon.
Generated by: scripts/coccinelle/misc/semicolon.cocci
CC: xinhui pan <xinhui.pan@amd.com>
Signed-off-by: kbuild test robot <fengguang.wu@intel.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
xinhui pan [Mon, 11 Mar 2019 07:23:00 +0000 (15:23 +0800)]
drm/amdgpu: add new ras workflow control flags
add ras post init function.
Do some initialization after all IP have finished their late init.
Add new member flags which will control the ras work flow.
For now, vbios enable ras for us on boot. That might change in the
future.
So there should be a flag from vbios to tell us if ras is enabled or not
on boot. Looks like there is no such info now.
Other bits of the flags are reserved to control other parts of ras.
Signed-off-by: xinhui pan <xinhui.pan@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
xinhui pan [Tue, 12 Mar 2019 09:15:57 +0000 (17:15 +0800)]
drm/amdgpu: let ras initialization a little noticeable
add drm info output if ras initialized successfully.
add ras atomfirmware sanity check.
Signed-off-by: xinhui pan <xinhui.pan@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
xinhui pan [Mon, 11 Mar 2019 11:34:23 +0000 (19:34 +0800)]
drm/amdgpu: Fix lockdep warning more gracely
lockdep need a static key.
Previously we set ignore bit to avoid the warning.
Now call sysfs_attr_init to initialize the static key.
Signed-off-by: xinhui pan <xinhui.pan@amd.com>
Reviewed-and-Tested-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
xinhui pan [Mon, 11 Mar 2019 10:10:57 +0000 (18:10 +0800)]
drm/amdgpu: Fix ras debugfs data parse
Unzero char is accepted by sscanf, so when data is structure but
unexpectedly return error invalid;
Signed-off-by: xinhui pan <xinhui.pan@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
xinhui pan [Mon, 11 Mar 2019 06:12:40 +0000 (14:12 +0800)]
drm/amdgpu: add new member hw_supported
Currently, it is not clear how ras is supported. Both software and
hardware can set the supported. That is confusing.
Fix it by adding new member hw_supported.
Signed-off-by: xinhui pan <xinhui.pan@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
xinhui pan [Mon, 11 Mar 2019 06:28:06 +0000 (14:28 +0800)]
drm/amdgpu: Fix warning when lockdep is enabled
Set ignore bit to satisfy locpdep.
Signed-off-by: xinhui pan <xinhui.pan@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
xinhui pan [Mon, 11 Mar 2019 04:17:14 +0000 (12:17 +0800)]
drm/amdgpu: Fix NULL pointer when ta is missing
Ta is optional, so check if ta firmware is loaded or not.
Signed-off-by: xinhui pan <xinhui.pan@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Thu, 7 Mar 2019 06:46:38 +0000 (14:46 +0800)]
drm/amdgpu: fix ras parameter descriptions
The descriptions of modinfo wrongly show two parameters
for each feature(see below). This patch can fix this
incorrect outputs.
parm: amdgpu_ras_enable:Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))
parm: ras_enable:int
parm: amdgpu_ras_mask:Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1
parm: ras_mask:uint
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: xinhui pan <xinhui.pan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
xinhui pan [Thu, 7 Mar 2019 06:01:11 +0000 (14:01 +0800)]
drm/amdgpu: export both supported and enabled ras features
Signed-off-by: xinhui pan <xinhui.pan@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
xinhui pan [Thu, 7 Mar 2019 03:49:26 +0000 (11:49 +0800)]
drm/amdgpu: lookup vbios table to check ecc capability
Signed-off-by: xinhui pan <xinhui.pan@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>