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Aleksandr Urakov [Mon, 22 Oct 2018 07:18:08 +0000 (07:18 +0000)]
[PDB] Extend IPDBSession's interface to retrieve frame data
Summary:
This patch just extends the `IPDBSession` interface to allow retrieving
of frame data through it, and adds an implementation over DIA. It is needed
for an implementation (for now with DIA) of the conversion from FPO programs
to DWARF expressions mentioned in D53086.
Reviewers: zturner, asmith, rnk
Reviewed By: asmith
Subscribers: mgorny, aprantl, JDevlieghere, llvm-commits
Differential Revision: https://reviews.llvm.org/D53324
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344886
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Craig Topper [Mon, 22 Oct 2018 06:30:22 +0000 (06:30 +0000)]
[X86] Add patterns for vector and/or/xor/andn with other types than vXi64.
This makes fast isel treat all legal vector types the same way. Previously only vXi64 was in the fast-isel tables.
This unfortunately prevents matching of andn by fast-isel for these types since the requires SelectionDAG. But we already had this issue for vXi64. So at least we're consistent now.
Interestinly it looks like fast-isel can't handle instructions with constant vector arguments so the the not part of the andn patterns is selected with SelectionDAG. This explains why VPTERNLOG shows up in some of the tests.
This is a subset of D53268. As I make progress on that, I will try to reduce the number of lines in the tablegen files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344884
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Dorit Nuzman [Mon, 22 Oct 2018 06:17:09 +0000 (06:17 +0000)]
[IAI,LV] Avoid creating a scalar epilogue due to gaps in interleave-groups when
optimizing for size
LV is careful to respect -Os and not to create a scalar epilog in all cases
(runtime tests, trip-counts that require a remainder loop) except for peeling
due to gaps in interleave-groups. This patch fixes that; -Os will now have us
invalidate such interleave-groups and vectorize without an epilog.
The patch also removes a related FIXME comment that is now obsolete, and was
also inaccurate:
"FIXME: return None if loop requiresScalarEpilog(<MaxVF>), or look for a smaller
MaxVF that does not require a scalar epilog."
(requiresScalarEpilog() has nothing to do with VF).
Reviewers: Ayal, hsaito, dcaballe, fhahn
Reviewed By: Ayal
Differential Revision: https://reviews.llvm.org/D53420
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344883
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Craig Topper [Sun, 21 Oct 2018 21:30:26 +0000 (21:30 +0000)]
[X86] Stop promoting integer loads to vXi64
Summary:
Theoretically this was done to simplify the amount of isel patterns that were needed. But it also meant a substantial number of our isel patterns have to match an explicit bitcast. By making the vXi32/vXi16/vXi8 types legal for loads, DAG combiner should be able to change the load type to remove the bitcast.
I had to add some additional plain load instruction patterns and a few other special cases, but overall the isel table has reduced in size by ~12000 bytes. So it looks like this promotion was hurting us more than helping.
I still have one crash in vector-trunc.ll that I'm hoping @RKSimon can help with. It seems to relate to using getTargetConstantFromNode on a load that was shrunk due to an extract_subvector combine after the constant pool entry was created. So we end up decoding more mask elements than the load size.
I'm hoping this patch will simplify the number of patterns needed to remove the and/or/xor promotion.
Reviewers: RKSimon, spatel
Reviewed By: RKSimon
Subscribers: llvm-commits, RKSimon
Differential Revision: https://reviews.llvm.org/D53306
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344877
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Craig Topper [Sun, 21 Oct 2018 21:08:37 +0000 (21:08 +0000)]
Revert r344873 "foo"
Rebase gone wrong left this in my tree.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344875
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Craig Topper [Sun, 21 Oct 2018 21:07:27 +0000 (21:07 +0000)]
[X86] Remove SDIVREM8_SEXT_HREG/UDIVREM8_ZEXT_HREG and their associated DAG combine and target bits support. Use a post isel peephole instead.
Summary:
These nodes exist to overcome an isel problem where we can generate a zero extend of an AH register followed by an extract subreg, and another zero extend. The first zero extend exists to avoid a partial register update copying the AH register into the low 8-bits. The second zero extend exists if the user wanted the remainder zero extended.
To make this work we had a DAG combine to morph the DIVREM opcode to a special opcode that included the extend. But then we had to add the new node to computeKnownBits and computeNumSignBits to process the extension portion.
This patch instead removes all of that and adds a late peephole to detect the two extends.
Reviewers: RKSimon, spatel
Reviewed By: RKSimon
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D53449
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344874
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Craig Topper [Sun, 21 Oct 2018 21:07:25 +0000 (21:07 +0000)]
foo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344873
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Sanjay Patel [Sun, 21 Oct 2018 20:13:29 +0000 (20:13 +0000)]
[DAGCombiner] reduce insert+bitcast+extract vector ops to truncate (PR39016)
This is a late backend subset of the IR transform added with:
D52439
We can confirm that the conversion to a 'trunc' is correct by running:
$ opt -instcombine -data-layout="e"
(assuming the IR transforms are correct; change "e" to "E" for big-endian)
As discussed in PR39016:
https://bugs.llvm.org/show_bug.cgi?id=39016
...the pattern may emerge during legalization, so that's we are waiting for an
insertelement to become a scalar_to_vector in the pattern matching here.
The DAG allows for fun variations that are not possible in IR. Result types for
extracts and scalar_to_vector don't necessarily match input types, so that means
we have to be a bit more careful in the transform (see code comments).
The tests show that we don't handle cases that require a shift (as we did in the
IR version). I've left that as a potential follow-up because I'm not sure if
that's a real concern at this late stage.
Differential Revision: https://reviews.llvm.org/D53201
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344872
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Aditya Kumar [Sun, 21 Oct 2018 18:11:56 +0000 (18:11 +0000)]
Schedule Hot Cold Splitting pass after most optimization passes
Summary:
In the new+old pass manager, hot cold splitting was schedule too early.
Thanks to Vedant for pointing this out.
Reviewers: sebpop, vsk
Reviewed By: sebpop, vsk
Subscribers: mehdi_amini, llvm-commits
Differential Revision: https://reviews.llvm.org/D53437
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344869
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Simon Pilgrim [Sun, 21 Oct 2018 17:07:50 +0000 (17:07 +0000)]
[X86][AVX] Enable lowerVectorShuffleAsLanePermuteAndPermute v16i16/v32i8 unary shuffle lowering
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344868
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Simon Pilgrim [Sun, 21 Oct 2018 11:55:56 +0000 (11:55 +0000)]
[X86] Only extract constant pool shuffle mask data with zero offsets
D53306 exposes an issue where we sometimes use constant pool data from bigger vectors than the target shuffle mask. This should be safe to do, but we have to be certain that we're using the bottom most part of the vector as the shuffle mask decoders have no way to peek into subvectors with non-zero offsets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344867
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Heejin Ahn [Sun, 21 Oct 2018 11:16:50 +0000 (11:16 +0000)]
[WebAssembly] Change tabs to spaces in basic-assembly.s
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344866
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Lang Hames [Sat, 20 Oct 2018 20:39:53 +0000 (20:39 +0000)]
[ORC] Add some more basic sanity tests for the LLJIT.
minimal.ll contains a main function that returns zero, and
single-function-call.ll contains a main function that calls a foo function that
returns zero. These minimal tests can help to rule out some trivial JIT bugs
when other tests fail.
This commit also renames hello.ll to global-ctors-and-dtors.ll, which better
reflects what it is actually testing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344863
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Sanjay Patel [Sat, 20 Oct 2018 18:18:55 +0000 (18:18 +0000)]
[InstCombine] add test for possible shuffle fold; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344860
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Simon Pilgrim [Sat, 20 Oct 2018 17:38:33 +0000 (17:38 +0000)]
[CostModel][X86] Add some initial extract/insert subvector shuffle cost tests
Just f64/i64 tests initially to demonstrate PR39368
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344857
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Sanjay Patel [Sat, 20 Oct 2018 17:15:57 +0000 (17:15 +0000)]
[InstCombine] use 'match' to simplify code; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344855
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Sanjay Patel [Sat, 20 Oct 2018 16:58:27 +0000 (16:58 +0000)]
[InstCombine] make code more flexible with lambda; NFC
I couldn't tell from svn history when these checks were added,
but it pre-dates the split of instcombine into its own directory
at rL92459.
The motivation for changing the check is partly shown by the
code in PR34724:
https://bugs.llvm.org/show_bug.cgi?id=34724
There are also existing regression tests for SLPVectorizer with
sequences of extract+insert that are likely assumed to become
shuffles by the vectorizer cost models.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344854
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Sanjay Patel [Sat, 20 Oct 2018 16:25:55 +0000 (16:25 +0000)]
[InstCombine] add explanatory comment for strange vector logic; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344852
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Simon Pilgrim [Sat, 20 Oct 2018 15:17:27 +0000 (15:17 +0000)]
[SLPVectorizer][X86] Add mul/and/or/xor unrolled reduction tests
We miss arithmetic reduction for everything but Add/FAdd (I assume because that's the only cases which x86 has horizontal ops for.....)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344849
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Sanjay Patel [Sat, 20 Oct 2018 14:53:07 +0000 (14:53 +0000)]
[SLPVectorizer] regenerate test checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344848
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Simon Pilgrim [Sat, 20 Oct 2018 14:29:59 +0000 (14:29 +0000)]
[CostModel][X86] Add integer vector reduction cost tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344846
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Simon Pilgrim [Sat, 20 Oct 2018 13:16:31 +0000 (13:16 +0000)]
Replace setFeature macro with lambda to fix MSVC "shift count negative or too big" warnings. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344843
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David Blaikie [Sat, 20 Oct 2018 09:16:49 +0000 (09:16 +0000)]
DebugInfo: Use base address specifiers more aggressively
Using a base address specifier even for a single-element range is a size
win for object files (7 words versus 8 words - more significant savings
if the debug info is compressed (since it's 3 words of uncompressable
reloc + 4 compressable words compared to 6 uncompressable reloc + 2
compressable words) - does trade off executable size increase though.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344841
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David Blaikie [Sat, 20 Oct 2018 08:55:51 +0000 (08:55 +0000)]
Add missed file from previous commit (r344838)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344839
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David Blaikie [Sat, 20 Oct 2018 08:54:05 +0000 (08:54 +0000)]
DebugInfo: Use DW_OP_addrx in DWARFv5
Reuse addresses in the address pool, even in non-split cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344838
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David Blaikie [Sat, 20 Oct 2018 08:12:36 +0000 (08:12 +0000)]
DebugInfo: Implement debug_rnglists.dwo
Save space/relocations in .o files by keeping dwo ranges in the dwo
file rather than the .o file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344837
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David Blaikie [Sat, 20 Oct 2018 07:36:39 +0000 (07:36 +0000)]
DebugInfo: Use address pool forms in debug_rnglists
Save no relocations by reusing addresses from the address pool.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344836
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David Blaikie [Sat, 20 Oct 2018 06:16:25 +0000 (06:16 +0000)]
llvm-dwarfdump: Support RLE_addressx and RLE_startx_length in .debug_rnglists
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344835
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David Blaikie [Sat, 20 Oct 2018 06:02:15 +0000 (06:02 +0000)]
DebugInfo: Use debug_addr for non-dwo addresses in DWARF 5
Putting addresses in the address pool, even with non-fission, can reduce
relocations - reusing the addresses from debug_info and debug_rnglists
(the latter coming soon)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344834
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Craig Topper [Sat, 20 Oct 2018 03:51:43 +0000 (03:51 +0000)]
[X86] Add additional CPUs and features to Host.cpp and X86TargetParser.def to match compiler-rt and enable __builtin_cpu_supports/__builtin_cpu_is support in clang
Summary: This matches LLVM to D53461 for compiler-rt.
Reviewers: echristo, erichkeane
Reviewed By: echristo
Subscribers: dberris, llvm-commits
Differential Revision: https://reviews.llvm.org/D53462
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344831
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Thomas Lively [Sat, 20 Oct 2018 01:35:23 +0000 (01:35 +0000)]
[WebAssembly] Implement vector sext_inreg and tests with comparisons
Summary: Depends on D53251.
Reviewers: aheejin, dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D53252
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344826
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Thomas Lively [Sat, 20 Oct 2018 01:31:18 +0000 (01:31 +0000)]
[WebAssembly] Custom lower i64x2 constant shifts to avoid wrap
Summary: Depends on D53057.
Reviewers: aheejin, dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D53251
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344825
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Roman Tereshin [Sat, 20 Oct 2018 00:06:15 +0000 (00:06 +0000)]
[MachineCSE][GlobalISel] Making sure MachineCSE works mid-GlobalISel (again)
Change of approach, it looks like it's a much better idea to deal with
the vregs that have LLTs and reg classes both properly, than trying to
avoid creating those across all GlobalISel passes and all targets.
The change mostly touches MachineRegisterInfo::constrainRegClass,
which is apparently only used by MachineCSE. The changes are NFC for
any pipeline but one that contains MachineCSE mid-GlobalISel.
NOTE on isCallerPreservedOrConstPhysReg change in MachineCSE:
There is no test covering it as the only way to insert a new pass
(MachineCSE) from a command line I know of is llc's -run-pass option,
which only works with MIR, but MIRParser freezes reserved registers upon
MachineFunctions creation, making it impossible to reproduce the state
that exposes the issue.
Reviwed By: aditya_nandakumar
Differential Revision: https://reviews.llvm.org/D53144
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344822
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Petar Jovanovic [Fri, 19 Oct 2018 22:16:49 +0000 (22:16 +0000)]
[llvm-objdump] Fix --file-headers (-f) option
Changed the format call to match the surrounding code. Previously it was
printing an unsigned int while the return type being printed was
long unsigned int or wider. This caused problems for big-endian systems
which were discovered on mips64.
Also, the printed address had less characters than it should because the
character count was directly obtained from the number of bytes in the
address.
The tests were adapted to fit this fix and now use longer addresses.
Patch by Milos Stojanovic.
Differential Revision: https://reviews.llvm.org/D53403
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344818
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Thomas Lively [Fri, 19 Oct 2018 21:11:43 +0000 (21:11 +0000)]
[LoopVectorize] Loop vectorization for minimum and maximum
Summary: Depends on D52766.
Reviewers: aheejin, dschuff
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D52767
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344816
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Changpeng Fang [Fri, 19 Oct 2018 21:09:21 +0000 (21:09 +0000)]
AMDGPU: Add support pattern for SUB of one bit
Summary:
Add selection patterns to support one bit Sub.
Reviewers:
rampitec, arsenm
Differential Revision:
https://reviews.llvm.org/D52946
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344815
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Evandro Menezes [Fri, 19 Oct 2018 20:57:45 +0000 (20:57 +0000)]
[NFC][InstCombine] Undo stray change
Undo stray change introduced by r344725.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344814
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Craig Topper [Fri, 19 Oct 2018 20:44:33 +0000 (20:44 +0000)]
[X86] Remove some left over code from when MVT:i1 was a legal type for AVX512.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344813
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Matt Arsenault [Fri, 19 Oct 2018 20:17:05 +0000 (20:17 +0000)]
Fix typos in assert message
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344812
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Aditya Nandakumar [Fri, 19 Oct 2018 20:11:52 +0000 (20:11 +0000)]
[GISel]: Allow PHIs to be DCEd
https://reviews.llvm.org/D53304
Currently dead phis are not cleaned up during DCE. This patch allows
dead PHI and G_PHI insts to be deleted.
Reviewed by: dsanders
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344811
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Craig Topper [Fri, 19 Oct 2018 19:24:42 +0000 (19:24 +0000)]
[X86] In PostprocessISelDAG, start from allnodes_end, not the root.
There is no guarantee the root is at the end if isel created any nodes without morphing them. This includes the nodes created by manual isel from C++ code in X86ISelDAGToDAG.
This is similar to r333415 from PowerPC which is where I originally stole the peephole loop from.
I don't have a test case, but without this a future patch doesn't work which is how I found it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344808
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Wolfgang Pieb [Fri, 19 Oct 2018 19:23:16 +0000 (19:23 +0000)]
[DWARF] Make llvm-dwarfdump display location lists in a .dwp file correctly. Fixes PR38990.
Considers the index when extracting location lists from a .dwp file.
Majority of the patch by David Blaikie.
Reviewers: dblaikie
Differential revision: https://reviews.llvm.org/D53155
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344807
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Thomas Lively [Fri, 19 Oct 2018 19:08:06 +0000 (19:08 +0000)]
[WebAssembly] Handle undefined lane indices in SIMD patterns
Summary:
Undefined indices in shuffles can be used when not all lanes of the
output vector will be used. This happens for example in the expansion
of vector reduce operations. Regardless, undefs are legal as lane
indices in IR and should be supported.
Reviewers: aheejin, dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D53057
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344803
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Krzysztof Pszeniczny [Fri, 19 Oct 2018 19:02:16 +0000 (19:02 +0000)]
Fix a use-after-RAUW bug in large GEP splitting
Summary:
Large GEP splitting, introduced in rL332015, uses a `DenseMap<AssertingVH<Value>, ...>`. This causes an assertion to fail (in debug builds) or undefined behaviour to occur (in release builds) when a value is RAUWed.
This manifested itself in the 7zip benchmark from the llvm test suite built on ARM with `-fstrict-vtable-pointers` enabled while RAUWing invariant group launders and splits in CodeGenPrepare.
This patch merges the large offsets of the argument and the result of an invariant.group strip/launder intrinsic before RAUWing.
Reviewers: Prazek, javed.absar, haicheng, efriedma
Reviewed By: Prazek, efriedma
Subscribers: kristof.beyls, hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D51936
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344802
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Thomas Lively [Fri, 19 Oct 2018 19:01:26 +0000 (19:01 +0000)]
[InstCombine] InstCombine and InstSimplify for minimum and maximum
Summary: Depends on D52765
Reviewers: aheejin, dschuff
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D52766
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344799
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Andrea Di Biagio [Fri, 19 Oct 2018 18:39:29 +0000 (18:39 +0000)]
[llvm-mca] Remove a stale TODO comment. NFC
Starting from revision r344334, we can now describe optimizable
register-register moves in the machine scheduling models.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344797
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Thomas Lively [Fri, 19 Oct 2018 18:15:32 +0000 (18:15 +0000)]
[ConstantFolding] Constant fold minimum and maximum intrinsics
Summary: Depends on D52764
Reviewers: aheejin, dschuff
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D52765
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344796
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Jonas Devlieghere [Fri, 19 Oct 2018 17:57:53 +0000 (17:57 +0000)]
[dwarfdump] Hide ranges in diff-mode.
llvm-dwarfdump --diff should not print DW_AT_ranges. This patch fixes
that.
Differential revision: https://reviews.llvm.org/D53353
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344794
91177308-0d34-0410-b5e6-
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Sanjay Patel [Fri, 19 Oct 2018 17:54:53 +0000 (17:54 +0000)]
[InstCombine] use m_Neg() in dyn_castNegVal() to match vectors with undef elts
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344793
91177308-0d34-0410-b5e6-
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Krzysztof Parzyszek [Fri, 19 Oct 2018 17:31:11 +0000 (17:31 +0000)]
[Hexagon] Remove support for V4
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344791
91177308-0d34-0410-b5e6-
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Sanjay Patel [Fri, 19 Oct 2018 17:26:22 +0000 (17:26 +0000)]
[InstCombine] move/add tests for sub/neg; NFC
These should all be handled using "dyn_castNegVal",
but that misses vectors with undef elements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344790
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Clement Courbet [Fri, 19 Oct 2018 12:24:49 +0000 (12:24 +0000)]
[llvm-exegesis] Mark second-form X87 instructions as unsupported.
Summary:
We only support the first form because we rely on information that is
only available there.
Reviewers: gchatelet
Subscribers: tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D53430
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344782
91177308-0d34-0410-b5e6-
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Kristina Brooks [Fri, 19 Oct 2018 12:14:30 +0000 (12:14 +0000)]
[MC][DWARF][AsmParser] Ensure nested CFI frames are diagnosed.
This avoids a crash (with asserts) or bad codegen (without asserts)
in Dwarf streamer later on. This patch fixes this condition in
MCStreamer and propogates SMLoc down when it's available with an
added bonus of source locations for those specific types of errors.
Further patches could use similar improvements as currently most
non-Windows CFI directives lack an SMLoc parameter.
Modified an existing test to verify source location propogation and
added an object-file version of it to verify that it does not crash in
addition to a standalone test to only ensure it does not crash.
Differential Revision: https://reviews.llvm.org/D51695
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344781
91177308-0d34-0410-b5e6-
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Clement Courbet [Fri, 19 Oct 2018 12:08:05 +0000 (12:08 +0000)]
[llvm-exegesis] Re-enable liveliness tracker.
Reviewers: gchatelet
Subscribers: tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D53429
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344780
91177308-0d34-0410-b5e6-
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Clement Courbet [Fri, 19 Oct 2018 09:56:54 +0000 (09:56 +0000)]
[llvm-exegesis] X87 RFP setup code.
Summary:
This was lost during refactoring in rL342644.
Fix and simplify simplify value size handling: always go through a 80 bit value,
because the value can be 1 byte). Add unit tests.
Reviewers: gchatelet
Subscribers: tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D53423
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344779
91177308-0d34-0410-b5e6-
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Fangrui Song [Fri, 19 Oct 2018 06:20:01 +0000 (06:20 +0000)]
[pipeliner] Fix test added in rL344748 to require asserts
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344775
91177308-0d34-0410-b5e6-
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Fangrui Song [Fri, 19 Oct 2018 06:12:02 +0000 (06:12 +0000)]
Use llvm::{all,any,none}_of instead std::{all,any,none}_of. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344774
91177308-0d34-0410-b5e6-
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Hsiangkai Wang [Fri, 19 Oct 2018 01:52:54 +0000 (01:52 +0000)]
[CodeGen] Fix for PR39094.
When using MachineInstr to get SlotIndex, the MI could not be a debug
instruction. mi2iMap does not contain debug instructions in it.
After enabling DBG_LABEL in the generated code, the first instruction in
the bundle may be a debug instruction. In this patch, I use the first
non-debug instruction in the bundle to query SlotIndex in mi2iMap.
Bugzilla report: https://bugs.llvm.org/show_bug.cgi?id=39094
Differential revision: https://reviews.llvm.org/D52927
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344770
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Chandler Carruth [Fri, 19 Oct 2018 00:22:37 +0000 (00:22 +0000)]
[TI removal] Remove `TerminatorInst` from the IR type system!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344769
91177308-0d34-0410-b5e6-
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Chandler Carruth [Fri, 19 Oct 2018 00:22:10 +0000 (00:22 +0000)]
[TI removal] Switch some newly added code over to use `Instruction`
directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344768
91177308-0d34-0410-b5e6-
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Chandler Carruth [Thu, 18 Oct 2018 23:03:55 +0000 (23:03 +0000)]
[TI removal] Update the C API for the move away from `TerminatorInst`.
This updates the C API for the removal of `TerminatorInst`. It converts
the type query to a predicate query and moves the generic methods to
work on `Instruction` instances that satisfy this predicate rather than
requiring a specific type. It also clarifies that the C API wrapping
`BasicBlock::getTerminator` just returns an `Instruction`. Because this
was always wrapped opaquely as a value and the functions consuming these
values will work on `Instruction` objects, this shouldn't break any
clients.
This is a completely compatible change to the C API.
Differential Revision: https://reviews.llvm.org/D52968
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344764
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Lang Hames [Thu, 18 Oct 2018 22:42:32 +0000 (22:42 +0000)]
[ORC] Add a createJITDylib method to LLJIT.
Because I'm about to get on stage at the dev meeting and claim that it exists.
This method creates a JITDylib instance with the given name and returns a
reference to it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344763
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Sylvestre Ledru [Thu, 18 Oct 2018 20:07:44 +0000 (20:07 +0000)]
Support of hurd in llvm-shlib
Svante Signell
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344756
91177308-0d34-0410-b5e6-
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Mircea Trofin [Thu, 18 Oct 2018 19:49:44 +0000 (19:49 +0000)]
Make Function::getInstructionCount const
Summary: Function::getInstructionCount can be const.
Reviewers: davidxl, paquette
Reviewed By: davidxl
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D53378
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344754
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Eli Friedman [Thu, 18 Oct 2018 19:34:30 +0000 (19:34 +0000)]
Revert r344693 ("[ARM] bottom-top mul support in ARMParallelDSP")
Still causing failures on the polly-aosp buildbot; I'll follow up
with a reduced testcase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344752
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Sumanth Gundapaneni [Thu, 18 Oct 2018 15:51:16 +0000 (15:51 +0000)]
[Pipeliner] copyToPhi DAG Mutation to improve scheduling.
In a loop, create artificial dependences between the source of a
COPY/REG_SEQUENCE to the use in next iteration.
Eg:
SRC ----Data Dep--> COPY
COPY ---Anti Dep--> PHI (implies, to be used in next iteration)
PHI ----Data Dep--> USE
This patches creates
USE ----Artificial Dep---> SRC
This will effectively schedule the COPY late to eliminate additional copies.
Before this patch, the schedule can be
SRC, COPY, USE : The COPY is used in next iteration and it needs to be
preserved.
After this patch, the schedule can be
USE, SRC, COPY : The COPY is used in next iteration and the live interval is
reduced.
Differential Revision: https://reviews.llvm.org/D53303
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344748
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Ayal Zaks [Thu, 18 Oct 2018 15:03:15 +0000 (15:03 +0000)]
[LV] Fold tail by masking to vectorize loops of arbitrary trip count under opt for size
When optimizing for size, a loop is vectorized only if the resulting vector loop
completely replaces the original scalar loop. This holds if no runtime guards
are needed, if the original trip-count TC does not overflow, and if TC is a
known constant that is a multiple of the VF. The last two TC-related conditions
can be overcome by
1. rounding the trip-count of the vector loop up from TC to a multiple of VF;
2. masking the vector body under a newly introduced "if (i <= TC-1)" condition.
The patch allows loops with arbitrary trip counts to be vectorized under -Os,
subject to the existing cost model considerations. It also applies to loops with
small trip counts (under -O2) which are currently handled as if under -Os.
The patch does not handle loops with reductions, live-outs, or w/o a primary
induction variable, and disallows interleave groups.
(Third, final and main part of -)
Differential Revision: https://reviews.llvm.org/D50480
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344743
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Nicolai Haehnle [Thu, 18 Oct 2018 12:54:39 +0000 (12:54 +0000)]
DivergenceAnalysisTest: fix use of uninitialized memory
Thanks to Simon Moll for chasing it down.
Change-Id: If188f07c4aaec217f40a7a2ca029818f9202f1cb
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344738
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Nicolai Haehnle [Thu, 18 Oct 2018 09:38:44 +0000 (09:38 +0000)]
[DA] DivergenceAnalysis for unstructured, reducible CFGs
Summary:
This is patch 2 of the new DivergenceAnalysis (https://reviews.llvm.org/D50433).
This patch contains a generic divergence analysis implementation for
unstructured, reducible Control-Flow Graphs. It contains two new classes.
The `SyncDependenceAnalysis` class lazily computes sync dependences, which
relate divergent branches to points of joining divergent control. The
`DivergenceAnalysis` class contains the generic divergence analysis
implementation.
Reviewers: nhaehnle
Reviewed By: nhaehnle
Subscribers: sameerds, kristina, nhaehnle, xbolva00, tschuett, mgorny, llvm-commits
Differential Revision: https://reviews.llvm.org/D51491
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344734
91177308-0d34-0410-b5e6-
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Sam McCall [Thu, 18 Oct 2018 08:47:24 +0000 (08:47 +0000)]
[Support] json::Value construction from std::vector<T> and std::map<string,T>.
Summary: Previously this required a conversion to json::Array/json::Object first.
Reviewers: ioeric
Subscribers: kristina, llvm-commits
Differential Revision: https://reviews.llvm.org/D53385
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344732
91177308-0d34-0410-b5e6-
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Guillaume Chatelet [Thu, 18 Oct 2018 08:20:50 +0000 (08:20 +0000)]
[llvm-exegesis] Fix off by one error
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344731
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Chandler Carruth [Thu, 18 Oct 2018 07:40:24 +0000 (07:40 +0000)]
[TI removal] Remove discussion of `TerminatorInst` from the LLVM
documentation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344727
91177308-0d34-0410-b5e6-
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Chandler Carruth [Thu, 18 Oct 2018 07:40:03 +0000 (07:40 +0000)]
[TI removal] Remove TerminatorInst references from bindings.
For the Go bindings, this just removes the no longer useful "isa"-style
wrapper. If there is a user that is interested, they can add a wrapper
for `Instruction::isTerminator`.
For the OCaml bindings, this is just a documentation update.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344726
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Mikael Holmen [Thu, 18 Oct 2018 06:27:53 +0000 (06:27 +0000)]
Add a emitUnaryFloatFnCall version that fetches the function name from TLI
Summary:
In several places in the code we use the following pattern:
if (hasUnaryFloatFn(&TLI, Ty, LibFunc_tan, LibFunc_tanf, LibFunc_tanl)) {
[...]
Value *Res = emitUnaryFloatFnCall(X, TLI.getName(LibFunc_tan), B, Attrs);
[...]
}
In short, we check if there is a lib-function for a certain type, and then
we _always_ fetch the name of the "double" version of the lib function and
construct a call to the appropriate function, that we just checked exists,
using that "double" name as a basis.
This is of course a problem in cases where the target doesn't support the
"double" version, but e.g. only the "float" version.
In that case TLI.getName(LibFunc_tan) returns "", and
emitUnaryFloatFnCall happily appends an "f" to "", and we erroneously end
up with a call to a function called "f".
To solve this, the above pattern is changed to
if (hasUnaryFloatFn(&TLI, Ty, LibFunc_tan, LibFunc_tanf, LibFunc_tanl)) {
[...]
Value *Res = emitUnaryFloatFnCall(X, &TLI, LibFunc_tan, LibFunc_tanf,
LibFunc_tanl, B, Attrs);
[...]
}
I.e instead of first fetching the name of the "double" version and then
letting emitUnaryFloatFnCall() add the final "f" or "l", we let
emitUnaryFloatFnCall() fetch the right name from TLI.
Reviewers: eli.friedman, efriedma
Reviewed By: efriedma
Subscribers: efriedma, bjope, llvm-commits
Differential Revision: https://reviews.llvm.org/D53370
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344725
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Kristina Brooks [Thu, 18 Oct 2018 03:14:37 +0000 (03:14 +0000)]
[X86] Support for the mno-tls-direct-seg-refs flag
Allows to disable direct TLS segment access (%fs or %gs). GCC supports
a similar flag, it can be useful in some circumstances, e.g. when a thread
context block needs to be updated directly from user space. More info
and specific use cases: https://bugs.llvm.org/show_bug.cgi?id=16145
There is another revision for clang as well.
Related: D53102
All X86 CodeGen tests appear to pass:
```
[46/47] Running lit suite /SourceCache/llvm-trunk-8.0/test/CodeGen
Testing Time: 23.17s
Expected Passes : 3801
Expected Failures : 15
Unsupported Tests : 8021
```
Reviewed by: Craig Topper.
Patch by nruslan (Ruslan Nikolaev).
Differential Revision: https://reviews.llvm.org/D53103
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344723
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Krasimir Georgiev [Thu, 18 Oct 2018 02:06:16 +0000 (02:06 +0000)]
[llvm-exegesis] Mark destructor virtual after r344695
This was causing a -Wnon-virtual-dtor warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344721
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Lang Hames [Thu, 18 Oct 2018 00:51:38 +0000 (00:51 +0000)]
[BuildingAJIT] Update the Ch1 KaleidoscopeJIT class to expose errors to clients.
Returning the error to clients provides an opportunity to introduce readers to
the Expected and Error APIs and makes the tutorial more useful as a starting
point for a real JIT class, while only slightly complicating the code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344720
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Chandler Carruth [Thu, 18 Oct 2018 00:40:26 +0000 (00:40 +0000)]
[TI removal] Switch simple loop unswitch to `Instruction`.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344719
91177308-0d34-0410-b5e6-
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Chandler Carruth [Thu, 18 Oct 2018 00:39:46 +0000 (00:39 +0000)]
[TI removal] Switch NewGVN to directly use `Instruction`.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344718
91177308-0d34-0410-b5e6-
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Chandler Carruth [Thu, 18 Oct 2018 00:39:18 +0000 (00:39 +0000)]
[TI removal] Use `Instruction` instead of `TerminatorInst` for
a variable's type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344717
91177308-0d34-0410-b5e6-
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Chandler Carruth [Thu, 18 Oct 2018 00:38:54 +0000 (00:38 +0000)]
[TI removal] Update CodeExtractor to use Instruction directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344716
91177308-0d34-0410-b5e6-
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Chandler Carruth [Thu, 18 Oct 2018 00:38:34 +0000 (00:38 +0000)]
[TI removal] Switch ObjCARC code to directly use the nice range-based
successors API or directly build the iterators out of the terminator
instruction and avoid requiring a TerminatorInst variable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344715
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Chandler Carruth [Thu, 18 Oct 2018 00:37:37 +0000 (00:37 +0000)]
[TI removal] Switch MergeFunctions to directly use Instruction API.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344714
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Chandler Carruth [Thu, 18 Oct 2018 00:36:15 +0000 (00:36 +0000)]
[TI removal] Switch an analysis to just use Instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344713
91177308-0d34-0410-b5e6-
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Lang Hames [Wed, 17 Oct 2018 22:27:09 +0000 (22:27 +0000)]
[BuildingAJIT] Simplify a tutorial example and fix a syntax error.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344712
91177308-0d34-0410-b5e6-
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Lang Hames [Wed, 17 Oct 2018 19:35:38 +0000 (19:35 +0000)]
[BuildingAJIT] Fix a function signature in the documentation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344705
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Pavel Labath [Wed, 17 Oct 2018 18:50:25 +0000 (18:50 +0000)]
Port libcxxabi r344607 into llvm
Summary:
The original commit message was:
This uses CRTP (for performance reasons) to allow a user the override
demangler functions to implement custom parsing logic. The motivation
for this is LLDB, which needs to occasionaly modify the mangled names.
One such instance is already implemented via the TypeCallback member,
but this is very specific functionality which does not help with any
other use case. Currently we have a use case for modifying the
constructor flavours, which would require adding another callback. This
approach does not scale.
With CRTP, the user (LLDB) can override any function it needs without
any special support from the demangler library. After LLDB is ported to
use this instead of the TypeCallback mechanism, the callback can be
removed.
The only difference here is the addition of a unit test which exercises
the CRTP mechanism to override a function in the parser.
Reviewers: erik.pilkington, rsmith, EricWF
Subscribers: mgorny, kristina, llvm-commits
Differential Revision: https://reviews.llvm.org/D53300
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344703
91177308-0d34-0410-b5e6-
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Nicolai Haehnle [Wed, 17 Oct 2018 15:37:48 +0000 (15:37 +0000)]
AMDGPU: Avoid selecting ds_{read,write}2_b32 on SI
Summary:
To workaround a hardware issue in the (base + offset) calculation
when base is negative. The impact on code quality should be limited
since SILoadStoreOptimizer still runs afterwards and is able to
combine loads/stores based on known sign information.
This fixes visible corruption in Hitman on SI (easily reproducible
by running benchmark mode).
Change-Id: Ia178d207a5e2ac38ae7cd98b532ea2ae74704e5f
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99923
Reviewers: arsenm, mareko
Subscribers: jholewinski, kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D53160
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344698
91177308-0d34-0410-b5e6-
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Nicolai Haehnle [Wed, 17 Oct 2018 15:37:41 +0000 (15:37 +0000)]
StructurizeCFG: Simplify inserted PHI nodes
Summary:
This improves subsequent divergence analysis in some cases.
Change-Id: I5e95e7ec7fd3fa80d414d1a53a02fea23e3d67d3
Reviewers: arsenm, rampitec
Subscribers: jvesely, wdng, llvm-commits
Differential Revision: https://reviews.llvm.org/D53316
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344697
91177308-0d34-0410-b5e6-
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Nicolai Haehnle [Wed, 17 Oct 2018 15:37:30 +0000 (15:37 +0000)]
AMDGPU: Divergence-driven selection of scalar buffer load intrinsics
Summary:
Moving SMRD to VMEM in SIFixSGPRCopies is rather bad for performance if
the load is really uniform. So select the scalar load intrinsics directly
to either VMEM or SMRD buffer loads based on divergence analysis.
If an offset happens to end up in a VGPR -- either because a floating
point calculation was involved, or due to other remaining deficiencies
in SIFixSGPRCopies -- we use v_readfirstlane.
There is some unrelated churn in tests since we now select MUBUF offsets
in a unified way with non-scalar buffer loads.
Change-Id: I170e6816323beb1348677b358c9d380865cd1a19
Reviewers: arsenm, alex-t, rampitec, tpr
Subscribers: kzhuravl, jvesely, wdng, yaxunl, dstuttard, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D53283
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344696
91177308-0d34-0410-b5e6-
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Clement Courbet [Wed, 17 Oct 2018 15:04:15 +0000 (15:04 +0000)]
[llvm-exegesis] Allow measuring several instructions in a single run.
Summary:
We try to recover gracefully on instructions that would crash the
program.
This includes some refactoring of runMeasurement() implementations.
Reviewers: gchatelet
Subscribers: tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D53371
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344695
91177308-0d34-0410-b5e6-
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Sam Parker [Wed, 17 Oct 2018 13:02:48 +0000 (13:02 +0000)]
[ARM] bottom-top mul support in ARMParallelDSP
Previously reverted in rL343082.
Original commit message:
On failing to find sequences that can be converted into dual macs,
try to find sequential 16-bit loads that are used by muls which we
can then use smultb, smulbt, smultt with a wide load.
Differential Revision: https://reviews.llvm.org/D51983
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344693
91177308-0d34-0410-b5e6-
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Guillaume Chatelet [Wed, 17 Oct 2018 12:27:46 +0000 (12:27 +0000)]
Fix uninitialized variable
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344692
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Nicolai Haehnle [Wed, 17 Oct 2018 12:14:26 +0000 (12:14 +0000)]
AMDGPU: Remove dead TableGen code
Summary: Change-Id: Ic1f2c1d0cf9e90a0baa9fc6bacd0d3c386069fb0
Reviewers: tpr
Subscribers: arsenm, kzhuravl, jvesely, wdng, yaxunl, dstuttard, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D53318
Change-Id: Ib4d143c898801e5cf6cb9999a495d62c91ae77fb
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344691
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Guillaume Chatelet [Wed, 17 Oct 2018 12:09:21 +0000 (12:09 +0000)]
BuildBot fix, compiler complains about array decay to pointer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344690
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Guillaume Chatelet [Wed, 17 Oct 2018 11:37:28 +0000 (11:37 +0000)]
[llvm-exegeis] Computing Latency configuration upfront so we can generate many CodeTemplates at once.
Summary: LatencyGenerator now computes all possible mode of serial execution for an Instruction upfront and generates CodeTemplate for the ones that give the best results (e.g. no need to generate a two instructions snippet when repeating a single one would do). The next step is to generate even more configurations for cases (e.g. for XOR we should generate "XOR EAX, EAX, EAX" and "XOR EAX, EAX, EBX")
Reviewers: courbet
Reviewed By: courbet
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D53320
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344689
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Max Kazantsev [Wed, 17 Oct 2018 11:16:25 +0000 (11:16 +0000)]
[NFC] Remove GOTO from SCEV
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344687
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Fedor Sergeev [Wed, 17 Oct 2018 11:01:15 +0000 (11:01 +0000)]
[NewPM] Fixing test failure on Windows - removed opt binary name from pattern
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344686
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Fedor Sergeev [Wed, 17 Oct 2018 10:36:23 +0000 (10:36 +0000)]
[NewPM] teach -passes= to emit meaningful error messages
All the PassBuilder::parse interfaces now return descriptive StringError
instead of a plain bool. It allows to make -passes/aa-pipeline parsing
errors context-specific and thus less confusing.
TODO: ideally we should also make suggestions for misspelled pass names,
but that requires some extensions to PassBuilder.
Reviewed By: philip.pfaffe, chandlerc
Differential Revision: https://reviews.llvm.org/D53246
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344685
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Petar Jovanovic [Wed, 17 Oct 2018 10:30:03 +0000 (10:30 +0000)]
[MIPS GlobalISel] Legalize constants
Legalize s1, s8, s16 and s64 G_CONSTANT for MIPS32.
Patch by Petar Avramovic.
Differential Revision: https://reviews.llvm.org/D53077
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344684
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