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Matt Turner [Sat, 6 Dec 2014 22:16:13 +0000 (14:16 -0800)]
i965: Add missing opcode names.
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Matt Turner [Sat, 6 Dec 2014 21:34:13 +0000 (13:34 -0800)]
i965: Add opcode names for set_omask and set_sample_id.
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Chad Versace [Thu, 20 Nov 2014 18:26:38 +0000 (10:26 -0800)]
egl: Expose EGL_KHR_get_all_proc_addresses and its client extension
Mesa already implements the behavior of EGL_KHR_get_all_proc_addresses
and EGL_KHR_client_get_all_proc_addresses. This patch just exposes the
extension strings.
See: https://www.khronos.org/registry/egl/extensions/KHR/EGL_KHR_get_all_proc_addresses.txt
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
Emil Velikov [Fri, 5 Dec 2014 19:10:39 +0000 (19:10 +0000)]
docs: add news item and link release notes for mesa 10.3.5
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Emil Velikov [Fri, 5 Dec 2014 18:43:47 +0000 (18:43 +0000)]
docs: Add sha256 sums for the 10.3.5 release
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
(cherry picked from commit
1ba2029184d3e7b013e3fc322e80a761604495d4)
Emil Velikov [Fri, 5 Dec 2014 18:21:51 +0000 (18:21 +0000)]
Add release notes for the 10.3.5 release
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
(cherry picked from commit
c90b0db1aef8f439b52b38ad58aac4ca202232a7)
Ilia Mirkin [Thu, 4 Dec 2014 03:12:39 +0000 (22:12 -0500)]
freedreno/a2xx: silence warning about missing DEPTH32X
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Rob Clark <robclark@freedesktop.org>
Ilia Mirkin [Thu, 4 Dec 2014 05:45:45 +0000 (00:45 -0500)]
freedreno/a3xx: handle index_bias (i.e. base_vertex)
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Rob Clark <robclark@freedesktop.org>
Ilia Mirkin [Thu, 4 Dec 2014 01:43:22 +0000 (20:43 -0500)]
freedreno/a3xx: add bgr565 texturing and rendering
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Rob Clark <robclark@freedesktop.org>
Ilia Mirkin [Fri, 28 Nov 2014 19:10:50 +0000 (14:10 -0500)]
freedreno/a3xx: add support for SRGB render targets
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Rob Clark <robclark@freedesktop.org>
Ilia Mirkin [Tue, 2 Dec 2014 06:00:47 +0000 (01:00 -0500)]
freedreno/a3xx: output RGBA16_FLOAT from fs for certain outputs
Fixes R11G11B10F rendering, and is required for SRGB format support.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Rob Clark <robclark@freedesktop.org>
Ilia Mirkin [Wed, 3 Dec 2014 02:31:33 +0000 (21:31 -0500)]
freedreno/a3xx: re-enable rgb10_a2 render targets
There were previously regressions regarding border colors, which the
updated swizzle logic resolves.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Rob Clark <robclark@freedesktop.org>
Ilia Mirkin [Wed, 3 Dec 2014 04:27:03 +0000 (23:27 -0500)]
freedreno/a3xx: fix border color swizzle to match texture format desc
This is a hack since it uses the texture information together with the
sampler, but I don't see a better way to do it. In OpenGL, there is a
1:1 correspondence.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Rob Clark <robclark@freedesktop.org>
Ilia Mirkin [Wed, 3 Dec 2014 02:32:01 +0000 (21:32 -0500)]
freedreno/a3xx: fix alpha-blending on RGBX formats
Expert debugging assistance provided by Chris Forbes.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Rob Clark <robclark@freedesktop.org>
Chris Forbes [Sat, 6 Dec 2014 22:49:28 +0000 (11:49 +1300)]
glcpp: Fix `can not` to `cannot` in error message
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Chris Forbes [Sat, 29 Nov 2014 20:54:59 +0000 (09:54 +1300)]
glcpp: Disallow undefining GL_* builtin macros.
Fixes the piglit test: spec/glsl-es-3.00/compiler/undef-GL_ES.vert
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Chris Forbes [Fri, 5 Dec 2014 06:43:13 +0000 (19:43 +1300)]
i965/Gen6-7: Fix point sprites with PolygonMode(GL_POINT)
This was an oversight in the original patch. When PolygonMode is
used, then front faces, back faces, or both may be rendered as
points and are affected by point sprite state.
Note that SNB/IVB can't actually be fully conformant here, for
a legacy context -- we don't have separate sets of pointsprite
enables for front and back faces. Haswell ignores pointsprite
state correctly in hardware for non-point rasterization, so can
do this correctly, but it doesn't seem worth it.
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Cc: "10.4" <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=86764
Reviewed-by: Matt Turner <mattst88@gmail.com>
Chris Forbes [Sat, 6 Dec 2014 21:12:36 +0000 (10:12 +1300)]
i965: Fix regs read for FS_OPCODE_INTERP_PER_SLOT_OFFSET
Dead code elimination was eating the Y offset.
Fixes the piglit test:
spec/ARB_gpu_shader5/arb_gpu_shader5-interpolateAtOffset-nonconst
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Chris Forbes [Sat, 6 Dec 2014 21:07:16 +0000 (10:07 +1300)]
i965: Add opcode names for FS interpolation opcodes
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Roland Scheidegger [Fri, 5 Dec 2014 22:08:34 +0000 (23:08 +0100)]
mesa/st: don't use CMP / I2F for conditional assignments with native integers
The original idea was to optimize away the condition by integrating it directly
into the CMP instruction. However, with native integers this requires an extra
I2F instruction. It is also fishy because the negation used didn't really honor
ieee754 float comparison rules, not to mention the CMP instruction itself
(being pretty much a legacy instruction) doesn't really have defined special
float value behavior in any case.
So, use UCMP and adjust the code trying to optimize the condition away
accordingly (I have absolutely no idea if such conditions are actually hit
or would be translated away somewhere else already).
v2: cosmetic changes
No piglit regressions on llvmpipe.
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Roland Scheidegger [Wed, 3 Dec 2014 02:57:15 +0000 (03:57 +0100)]
llvmpipe: decrease MAX_SCENES from 2 to 1
Multiple scenes per context are meant to be used so a new scene can be built
while another one is processed in rasterization. However, quite surprisingly,
this does not actually work (and according to git log, possibly never did,
though maybe it did at some point further back (5 years+) but was buggy)
because we always wait immediately on the rasterizer to finish the scene when
contexts (and hence setup/scene) is flushed. This means when we try to get
an empty scene later, any old one is already empty again.
Thus using multiple scenes is just a waste of memory (not too bad, since the
additional scenes are guaranteed to be empty, which means their size ought to
be one data block (64kB) plus the size of some structs), without actually
really doing anything. (There is also quite some code for the whole concept of
multiple scenes which doesn't really do much in practice, but keep it hoping
the wait-on-scene-flush can be fixed some day.)
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Roland Scheidegger [Tue, 2 Dec 2014 01:27:56 +0000 (02:27 +0100)]
draw: use the prim type from prim_info not emit in passthrough emit
The prim assembler may change the prim type when injecting prim ids now,
which isn't reflected by what's stored in emit.
This looks brittle and potentially dangerous (it is not obvious if such prim
type changes are really supported by pt emit, the prim type is actually also
set in prepare which would then be different).
This fixes piglit primitive-id-no-gs-first-vertex.shader_test.
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Roland Scheidegger [Mon, 1 Dec 2014 22:40:31 +0000 (23:40 +0100)]
draw: use correct output prim for non-adjacent topologies in prim assembler.
The decomposition done in the prim assembler will turn tri fans into tris,
but this wasn't reflected in the output prim type. Meaning with a tri fan
with 6 verts input, the output was a tri fan with 12 vertices instead of a
tri list with 12 vertices (not as bad as it sounds, since the additional tris
created would all be degenerate since they'd all have two times vertex zero
but still bogus).
This is because the prim assembler is used if either the input topology is
something with adjacency, or if prim id needs to be injected, and for the
latter case topologies without adjacency can be converted to basic ones.
Unfortunately decomposition here for inserting prim ids is necessary, at
least for the indexed case where we can't just insert the prim id at the
right place depending on provoking vertex.
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Roland Scheidegger [Mon, 1 Dec 2014 22:13:55 +0000 (23:13 +0100)]
draw: kill off unneded prim assembler code for handling adjacency verts
The default macros when the adjacency macros aren't defined will already
exactly do that (that is, drop the adjacent vertices and call the non-adjacent
macro).
Reviewed-by: Jose Fonseca <jfonseca@vmwarec.com>
Roland Scheidegger [Mon, 1 Dec 2014 16:03:47 +0000 (17:03 +0100)]
gallium/docs: (trivial) remove STR opcode description.
The opcode was removed alongside SFL by commit
ecfe9e2ad2b5f178ef09420f8d95d49937137cd9.
Matt Turner [Thu, 3 Apr 2014 21:29:30 +0000 (14:29 -0700)]
i965/fs: Perform CSE on MOV ..., VF instructions.
Safe from causing optimization loops, since we don't constant propagate
VF arguments.
(for this and the previous patch):
total instructions in shared programs:
4289075 ->
4271932 (-0.40%)
instructions in affected programs:
1616779 ->
1599636 (-1.06%)
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Matt Turner [Tue, 1 Apr 2014 23:49:13 +0000 (16:49 -0700)]
i965/fs: Try to emit LINE instructions on Gen <= 5.
The LINE instruction performs a multiply-add instruction (a * b + c)
where b and c are scalar arguments. It reads b and c from offsets in
src0 such that you can load them (it they're representable) as a
vector-float immediate with a single instruction.
Hurts some programs, but that'll all get better once we CSE the
vector-float MOVs in the next patch.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=77544
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Matt Turner [Wed, 2 Apr 2014 00:25:12 +0000 (17:25 -0700)]
i965/fs: Add support for generating the LINE instruction.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Matt Turner [Tue, 19 Aug 2014 06:14:44 +0000 (23:14 -0700)]
i965: Set the region of LINE's src0 to <0,1,0>.
The PRMs say that
<src0> region must be a replicated scalar
(with HorzStride = VertStride = 0).
but apparently that doesn't actually apply to all generations. I did
notice when implementing the optimization later in this series that G45
and ILK needed this regioning.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Matt Turner [Fri, 14 Nov 2014 20:46:44 +0000 (12:46 -0800)]
i965: Give compile stats through KHR_debug.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Matt Turner [Fri, 14 Nov 2014 01:35:58 +0000 (17:35 -0800)]
mesa: Add a source parameter to _mesa_gl_debug.
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Eric Anholt [Fri, 5 Dec 2014 21:23:17 +0000 (13:23 -0800)]
vc4: Try swapping the regfile A to B to pair instructions.
total instructions in shared programs: 56995 -> 56087 (-1.59%)
instructions in affected programs: 40503 -> 39595 (-2.24%)
Eric Anholt [Fri, 5 Dec 2014 20:34:30 +0000 (12:34 -0800)]
vc4: Allow pairing of some instructions that disagree about the WS bit.
No difference on shader-db because we tend to have a lot of other
conflicts going on as well (like RADDR_A disagreements)
Matt Turner [Fri, 5 Dec 2014 21:06:01 +0000 (13:06 -0800)]
configure.ac: Replace contraction to fix syntax highlighting.
Ben Widawsky [Thu, 4 Dec 2014 23:37:17 +0000 (15:37 -0800)]
i965/gs: Avoid DW * DW mul
The GS has an interesting use for mul. Because the GS can emit multiple
vertices per input vertex, and it also has a unique count at the top of the URB
payload, the GS unit needs to be able to dynamically specify URB write offsets
(relative to the global offset). The documentation in the function has a very
good explanation from Paul on the mechanics.
This fixes around 2000 piglit tests on BSW.
v2:
Reworded commit message (Ben) no mention of CHV (Matt)
Change SHRT_MAX to USHRT_MAX (Ken, and Matt)
Update comment in code to reflect the use of UW (Ben)
Add Gen7+ assertion for the relevant GS code, since it won't work on Gen6- (Ken)
Drop the bogus hunk in emit_control_data_bits() (Ken)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=84777 (with many dupes)
Cc: "10.4 10.3 10.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Eric Anholt [Tue, 2 Dec 2014 23:42:58 +0000 (15:42 -0800)]
vc4: Add separate write-after-read dependency tracking for pairing.
If an operation is the last one to read a register, the instruction
containing it can also include the op that has the next write to that
register.
total instructions in shared programs: 57486 -> 56995 (-0.85%)
instructions in affected programs: 43004 -> 42513 (-1.14%)
Eric Anholt [Wed, 3 Dec 2014 00:31:29 +0000 (16:31 -0800)]
vc4: Fix inverted priority of instructions for QPU scheduling.
We were scheduling TLB operations as early as possible, and texture setup
as late as possible. When I introduced prioritization, I visually
inspected that an independent operation got moved above texture results
collection, which tricked me into thinking it was working (but it was just
because texture setup was being pushed late).
total instructions in shared programs: 57651 -> 57486 (-0.29%)
instructions in affected programs: 18532 -> 18367 (-0.89%)
Eric Anholt [Wed, 3 Dec 2014 00:23:40 +0000 (16:23 -0800)]
vc4: Refuse to merge two ops that both access shared functions.
Avoids assertion failures in vc4_qpu_validate.c if we happen to find the
right set of operations available.
Eric Anholt [Tue, 2 Dec 2014 20:58:27 +0000 (12:58 -0800)]
vc4: Allow dead code elimination of color reads.
This might happen if the blending functions are set up to not actually use
the destination color/alpha, for example.
Eric Anholt [Tue, 2 Dec 2014 21:18:56 +0000 (13:18 -0800)]
vc4: Add a debug flag for waiting for sync on submit.
This is nice when you're tracking down which command list is hanging the
GPU.
Matt Turner [Fri, 5 Dec 2014 17:53:11 +0000 (09:53 -0800)]
i965/fs: Move brw_file_from_reg() higher in the file.
This was supposed to be part of the previous commit.
Matt Turner [Fri, 28 Nov 2014 20:21:03 +0000 (12:21 -0800)]
i965/fs: Make brw_reg_from_fs_reg static and remove prototype.
And move it above its first use in brw_fs_generator.cpp.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Matt Turner [Tue, 2 Dec 2014 20:28:13 +0000 (12:28 -0800)]
i965: Use ~0 to represent true on all generations.
Jason realized that we could fix the result of the CMP instruction on
Gen <= 5 by doing -(result & 1). Also do the resolves in the vec4
backend before use, rather than when the bool was created. The FS does
this and it saves some unnecessary resolves.
On Ironlake:
total instructions in shared programs:
4289762 ->
4287277 (-0.06%)
instructions in affected programs: 619430 -> 616945 (-0.40%)
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Matt Turner [Tue, 2 Dec 2014 20:30:27 +0000 (12:30 -0800)]
i965: Change the type of booleans to D.
This is a revert of commit
4656c14e ("i965/fs: Change the type of
booleans to UD and emit correct immediates") plus some small additional
fixes, like casting ctx->Const.UniformBooleanTrue to int and changing UD
to D in the ir_unop_b2f cases. Note that it's safe to leave 0x3f800000
as UD and as a literal it's more recognizable than
1065353216.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Matt Turner [Thu, 4 Dec 2014 21:35:25 +0000 (13:35 -0800)]
i965/fs: Add a negate() function.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Matt Turner [Thu, 4 Dec 2014 07:32:30 +0000 (23:32 -0800)]
i965/vec4: Don't DCE flag-writing insts because dest was unused.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Matt Turner [Fri, 24 Oct 2014 06:22:09 +0000 (23:22 -0700)]
i965/vec4: Allow CSE on uniform-vec4 expansion MOVs.
Three source instructions cannot directly source a packed vec4 (<0,4,1>
regioning) like vec4 uniforms, so we emit a MOV that expands the vec4 to
both halves of a register.
If these uniform values are used by multiple three-source instructions,
we'll emit multiple expansion moves, which we cannot combine in CSE
(because CSE emits moves itself).
So emit a virtual instruction that we can CSE.
Sometimes we demote a uniform to to a pull constant after emitting an
expansion move for it. In that case, recognize in opt_algebraic that if
the .file of the new instruction is GRF then it's just a real move that
we can copy propagate and such.
total instructions in shared programs:
5822418 ->
5812335 (-0.17%)
instructions in affected programs: 351841 -> 341758 (-2.87%)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Matt Turner [Fri, 22 Aug 2014 21:30:38 +0000 (14:30 -0700)]
glsl: Optimize scalar all_equal/any_nequal into equal/nequal.
Cuts an instruction from two shaders in Tesseract, by allowing the
(x+y) cmp 0 -> x cmp -y optimization to take place.
instructions in affected programs: 1198 -> 1194 (-0.33%)
Reviewed-by: Eric Anholt <eric@anholt.net>
José Fonseca [Tue, 2 Dec 2014 20:20:43 +0000 (20:20 +0000)]
mesa: Ensure stack is realigned on x86.
Nowadays GCC assumes stack pointer is 16-byte aligned even on 32-bits,
but that is an assumption OpenGL drivers (or any dynamic library for
that matter) can't afford to make as there are many closed- and open-
source application binaries out there that only assume 4-byte stack
alignment.
This fix uses force_align_arg_pointer GCC attribute, and is only a
stop-gap measure.
The right fix would be to pass -mstackrealign or
-mincoming-stack-boundary=2 to all source fails that use any -msse*
option, as there is no way to guarantee if/when GCC will decide to spill
SSE registers to the stack.
https://bugs.freedesktop.org/show_bug.cgi?id=86788
Reviewed-by: Brian Paul <brianp@vmware.com>
José Fonseca [Fri, 5 Dec 2014 14:15:02 +0000 (14:15 +0000)]
util/primconvert: Avoid point arithmetic; apply offset on all cases.
Matches what u_vbuf_get_minmax_index() does.
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Thu, 4 Dec 2014 23:56:36 +0000 (18:56 -0500)]
util/primconvert: take ib offset into account
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.4 10.3" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Rob Clark <robclark@freedesktop.org>
Ilia Mirkin [Sun, 30 Nov 2014 06:20:01 +0000 (01:20 -0500)]
util/primconvert: support instanced rendering
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.3 10.4" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Rob Clark <robclark@freedesktop.org>
Ilia Mirkin [Thu, 4 Dec 2014 05:36:00 +0000 (00:36 -0500)]
util/primconvert: pass index bias through
The index_bias (aka base_vertex) applies to the downstream draw just as
much, since the actual index values are never modified.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.3 10.4" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Rob Clark <robclark@freedesktop.org>
Kenneth Graunke [Wed, 3 Dec 2014 22:26:48 +0000 (14:26 -0800)]
i965: Compute VS attribute WA bits earlier and check if they changed.
BRW_NEW_VERTICES is flagged every time we draw a primitive. Having
the brw_vs_prog atom depend on BRW_NEW_VERTICES meant that we had to
compute the VS program key and do a program cache lookup for every
single primitive. This is painfully expensive.
The workaround bit computation is almost entirely based on the vertex
attribute arrays (brw->vb.inputs[i]), which are set by brw_merge_inputs.
The only thing it uses the VS program for is to see which VS inputs are
actually read. brw_merge_inputs() happens once per primitive, and can
safely look at the currently bound vertex program, as it doesn't change
in the middle of a draw.
This patch moves the workaround bit computation to brw_merge_inputs(),
right after assigning brw->vb.inputs[i], and stores the previous WA bit
values in the context. If they've actually changed from the last draw
(which is uncommon), we signal that we need a new vertex program,
causing brw_vs_prog to compute a new key.
Improves performance in Gl32Batch7 by 13.6123% +/- 0.739652% (n=166)
on Haswell GT3e. I'm told Baytrail shows similar gains.
v2: Introduce a new BRW_NEW_VS_ATTRIB_WORKAROUNDS dirty bit, rather
than reusing BRW_NEW_VERTEX_PROGRAM (suggested by Chris Forbes).
This prevents unnecessary re-emission of surface/sampler related
atoms (and an SOL atom on Sandybridge).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Matt Turner [Thu, 4 Dec 2014 00:32:39 +0000 (16:32 -0800)]
egl/dri2: Log a warning if no platforms are enabled.
If you hit this, you didn't compile with --with-egl-platforms=...
Recompile with something like --with-egl-platforms=x11,drm and make
clean and make again.
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Kenneth Graunke [Mon, 1 Dec 2014 05:26:43 +0000 (21:26 -0800)]
i965: Drop BRW_NEW_VERTEX_PROGRAM and _NEW_TRANSFORM from Gen4 VS state.
These stopped being necessary in commit
ab973403e445cd8211dba4e87e0.
v2: Update commit message with a better explanation (thanks to Eric
Anholt for doing the git archaeology).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Kenneth Graunke [Sun, 30 Nov 2014 10:11:29 +0000 (02:11 -0800)]
i965: Drop BRW_NEW_VERTEX_PROGRAM from Gen7+ 3DSTATE_VS atoms.
We don't access brw->vertex_program or ctx->_Shader since the previous
commit, so we don't need this dirty bit.
I think it's still necessary on Gen6 because it still conflates
constant uploading with unit state uploading. We can fix that later.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Kenneth Graunke [Sun, 30 Nov 2014 09:35:14 +0000 (01:35 -0800)]
i965: Store floating point mode choice in brw_stage_prog_data.
We use IEEE mode for GLSL programs, but need to use ALT mode for ARB
programs so that 0^0 == 1. The choice is based entirely on the shader
source language.
Previously, our code to determine which mode we wanted was duplicated
in 8 different places (VS and FS for Gen4-5, Gen6, Gen7, and Gen8).
The ctx->_Shader->CurrentProgram[stage] == NULL check was confusing
as well - we use CurrentProgram (non-derived state), but _Shader
(derived state). It also relies on knowing that ARB programs don't
use gl_shader_program structures today. The compiler already makes
this assumption in a few places, but I'd rather keep that assumption
out of the state upload code.
With this patch, we select the mode at compile time, and store that
choice in prog_data. The state upload code simply uses that decision.
This eliminates a BRW_NEW_*_PROGRAM dependency in the state upload code.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Kenneth Graunke [Sun, 30 Nov 2014 09:41:15 +0000 (01:41 -0800)]
i965: Make Gen4-5 and Gen8+ ALT checks use ctx->_Shader too.
Commit
c0347705 changed the Gen6-7 code to use ctx->_Shader rather than
ctx->Shader, but neglected to change the Gen4-5 or Gen8+ code.
This might fix SSO related bugs, but ALT mode is only used for ARB
programs, so if there's an actual problem, it's likely no one would
run into it.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Kenneth Graunke [Sun, 30 Nov 2014 09:14:17 +0000 (01:14 -0800)]
i965: Move PSCDEPTH calculations from draw time to compile time.
The "Pixel Shader Computed Depth Mode" value is entirely based on the
shader program, so we can easily do it at compile time. This avoids the
if+switch on every 3DSTATE_WM (Gen7)/3DSTATE_PS_EXTRA (Gen8+) upload,
and shares a bit more code.
This also simplifies the PMA stall code, making it match the formula
more closely, and drops a BRW_NEW_FRAGMENT_PROGRAM dependency. (Note
that the previous comment was wrong - the code and the documentation
have != PSCDEPTH_OFF, not ==.)
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Rob Clark [Wed, 3 Dec 2014 23:47:39 +0000 (18:47 -0500)]
freedreno/a4xx: unify vertex/texture formats into a single table
Similar to the scheme that Ilia put in place for a3xx.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Wed, 3 Dec 2014 23:02:38 +0000 (18:02 -0500)]
freedreno/a4xx: fd4_util -> fd4_format
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Wed, 3 Dec 2014 22:54:36 +0000 (17:54 -0500)]
freedreno: update generated headers / a4xx fmt rename
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Kenneth Graunke [Mon, 1 Dec 2014 21:44:04 +0000 (13:44 -0800)]
i965: Add var->location != -1 assertions.
We shouldn't receive variables with invalid locations set - adding these
assertions should help catch problems before they cause crashes later.
Inspired by similar code in st_glsl_to_tgsi.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Matt Turner [Fri, 29 Aug 2014 21:41:21 +0000 (14:41 -0700)]
i965/fs: Don't offset uniform registers in half().
Half gives you the second half of a SIMD16 register, but if the register
is a uniform it would incorrectly give you the next register.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Rob Clark [Wed, 3 Dec 2014 20:13:41 +0000 (15:13 -0500)]
freedreno/a4xx: frag-depth fixes
Also seems to fix kill/discard.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Ian Romanick [Mon, 1 Dec 2014 22:07:30 +0000 (14:07 -0800)]
linker: Assign varying locations geometry shader inputs for SSO
Previously only geometry shader outputs would be assigned locations if
the geometry shader was the only stage in the linked program.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Cc: pavol@klacansky.com
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82585
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Ian Romanick [Mon, 1 Dec 2014 22:16:24 +0000 (14:16 -0800)]
linker: Wrap access of producer_var with a NULL check
producer_var could be NULL if consumer_var is not NULL and
consumer_is_fs is false. This will occur when the producer is NULL and
the consumer is the geometry shader for a program that contains only a
geometry shader. This will occur starting with the next patch.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Cc: pavol@klacansky.com
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82585
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Jan Vesely [Tue, 2 Dec 2014 20:14:16 +0000 (15:14 -0500)]
st/xvmc: Fix compiler warnings
Mostly signed/unsigned comparison
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Christian König <christian.koenig@amd.com>
Axel Davy [Wed, 26 Nov 2014 21:32:57 +0000 (22:32 +0100)]
st/nine: Fix vertex declarations for non-standard (usage/index)
Nine code to match vertex declaration to vs inputs was limiting
the number of possible combinations.
Some sm3 games have issues with that, because arbitrary (usage/index)
can be used.
This patch does the following changes to fix the problem:
. Change the numbers given to (usage/index) combinations to uint16
. Do not put limits on the indices when it doesn't make sense
. change the conversion rule (usage/index) -> number to fit all combinations
. Instead of having a table usage_map mapping a (usage/index) number to
an input index, usage_map maps input indices to their (usage/index)
Cc: "10.4" <mesa-stable@lists.freedesktop.org>
Tested-by: Yaroslav Andrusyak <pontostroy@gmail.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Axel Davy <axel.davy@ens.fr>
Axel Davy [Wed, 26 Nov 2014 19:52:53 +0000 (20:52 +0100)]
st/nine: sm1_declusage_to_tgsi, do not restrict indices with TGSI_SEMANTIC_GENERIC
With sm3, you can declare an input/output with an usage and an usage index.
Nine code hardcodes the translation usage/index to a corresponding TGSI code.
The translation was limited to a few usage/index combinations that were corresponding
to most of the needs of games, but some games did not work.
This patch rewrites that Nine code to map all possible usage/index combination
to TGSI code. The index associated to TGSI_SEMANTIC_GENERIC doesn't need to be low
for good performance, as the old code was supposing, and is not particularly bounded
(it's UINT16). Given the index is BYTE, we can map all combinations.
Cc: "10.4" <mesa-stable@lists.freedesktop.org>
Tested-by: Yaroslav Andrusyak <pontostroy@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Axel Davy <axel.davy@ens.fr>
Axel Davy [Mon, 24 Nov 2014 22:32:18 +0000 (23:32 +0100)]
st/nine: Queries: Always return D3D_OK when issuing with D3DISSUE_BEGIN
This is the behaviour that Wine tests.
Reviewed-by: David Heidelberg <david@ixit.cz>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Axel Davy <axel.davy@ens.fr>
Axel Davy [Tue, 2 Dec 2014 21:01:44 +0000 (22:01 +0100)]
st/nine: Queries: always succeed for D3DQUERYTYPE_TIMESTAMP when flushing
This is the behaviour that Wine tests
Tested-by: David Heidelberg <david@ixit.cz>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Axel Davy <axel.davy@ens.fr>
Axel Davy [Tue, 2 Dec 2014 20:56:51 +0000 (21:56 +0100)]
st/nine: Queries: allow app to call GetData without Issuing first
Nine was allowing that behaviour, but was not filling the result.
Tested-by: David Heidelberg <david@ixit.cz>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Axel Davy <axel.davy@ens.fr>
Axel Davy [Mon, 24 Nov 2014 22:26:46 +0000 (23:26 +0100)]
st/nine: Queries: Fix D3DISSUE_END behaviour.
Issuing D3DISSUE_END should:
. reset previous queries if possible
. end the query
Previous behaviour wasn't calling end_query for
queries not needing D3DISSUE_BEGIN, nor resetting
previous queries.
This fixes several applications not launching properly.
Cc: "10.4" <mesa-stable@lists.freedesktop.org>
Tested-by: David Heidelberg <david@ixit.cz>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Axel Davy <axel.davy@ens.fr>
Axel Davy [Sun, 23 Nov 2014 10:44:59 +0000 (11:44 +0100)]
st/nine: Queries: return S_FALSE instead of INVALIDCALL when in building query state
It is the same behaviour as wine has.
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: David Heidelberg <david@ixit.cz>
Signed-off-by: Axel Davy <axel.davy@ens.fr>
Axel Davy [Mon, 24 Nov 2014 21:59:21 +0000 (22:59 +0100)]
st/nine: Queries: Use gallium caps to get if queries are supported. (v2)
Some queries need the driver to advertise a cap to be supported.
For example r300 doesn't support them.
v2 (David): check also for PIPE_CAP_QUERY_PIPELINE_STATISTICS, fix wine
tests on r300g
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: David Heidelberg <david@ixit.cz>
Signed-off-by: Axel Davy <axel.davy@ens.fr>
Axel Davy [Mon, 24 Nov 2014 22:14:54 +0000 (23:14 +0100)]
st/nine: Queries: Remove flush logic
get_query_result flushes automatically, we don't need to flush.
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Axel Davy <axel.davy@ens.fr>
Axel Davy [Mon, 24 Nov 2014 21:40:04 +0000 (22:40 +0100)]
st/nine: Queries: remove dummy queries
Applications are supposed to call CreateQuery with a NULL
ppQuery to know if the query is supported. We supported that.
However when ppQuery was not NULL, we were accepting to create the
query and were creating a dummy query even when the query is not
supported.
Wine has different behaviour. This patch drops the dummy queries
support and matches wine behaviour.
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: David Heidelberg <david@ixit.cz>
Signed-off-by: Axel Davy <axel.davy@ens.fr>
Ilia Mirkin [Tue, 2 Dec 2014 05:27:09 +0000 (00:27 -0500)]
freedreno/a3xx: implement anisotropic filtering
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Rob Clark [Tue, 2 Dec 2014 22:17:02 +0000 (17:17 -0500)]
freedreno/a4xx: rect textures
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Tue, 2 Dec 2014 22:14:46 +0000 (17:14 -0500)]
freedreno: update generated headers
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Tue, 2 Dec 2014 22:38:12 +0000 (17:38 -0500)]
freedreno: fix signed vs unsigned lols
Signed-off-by: Rob Clark <robclark@freedesktop.org>
José Fonseca [Wed, 3 Dec 2014 07:48:26 +0000 (07:48 +0000)]
gallivm: Update for RTDyldMemoryManager becoming an unique_ptr.
Trivial.
Fixes https://bugs.freedesktop.org/show_bug.cgi?id=86958
Tapani Pälli [Tue, 4 Nov 2014 12:20:15 +0000 (14:20 +0200)]
glsl: throw error when using invariant(all) in a fragment shader
Note that some of the GLSL specifications explicitly state this as
compile error, some simply state that 'it is an error'.
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Ben Widawsky [Sat, 22 Nov 2014 23:22:15 +0000 (15:22 -0800)]
i965/skl: Fix SBE state upload code.
The state upload code was incorrectly shifting the attribute swizzles. The
effect of this is we're likely to get the default swizzle values, which disables
the component.
This doesn't technically fix any bugs since Skylake support is still disabled by
default (no PCI IDs).
While here, since VARYING_SLOT_MAX can be greater than the number of attributes
we have available, add a warning to the code to make sure we never do the wrong
thing (and hopefully prevent further static analysis from finding this).
Admittedly I am a bit confused. It seems to me like the moment a user has
greater than 8 varyings we will hit this condition. CC Ken to clarify.
v2: Forgot to git add the warning message in v1
v3: Change the > 31 varyings to an assertion (Ken)
Reported-by: Ilia Mirkin <imirkin@alum.mit.edu> (via Coverity)
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jan Vesely [Tue, 2 Dec 2014 19:47:53 +0000 (14:47 -0500)]
r600, llvm: Don't leak global symbol offsets
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Matt Turner [Tue, 2 Dec 2014 19:18:47 +0000 (11:18 -0800)]
i965: Avoid union literal, for old gcc compatibility.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=86939
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Matt Turner [Wed, 12 Nov 2014 18:17:36 +0000 (10:17 -0800)]
i965: Remove tabs from instruction scheduler.
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Kenneth Graunke [Mon, 1 Dec 2014 09:09:35 +0000 (01:09 -0800)]
i965/vs: Set brw_vs_prog_key::clamp_vertex_color to 0 when irrelevant.
Vertex color clamping is only relevant if the shader writes to
the built-in gl_[Secondary]{Front,Back}Color varyings. Otherwise,
brw_vs_prog_key::clamp_vertex_color is never used, so we can simply
leave it set to 0.
This enables us to correctly predict the clamp_vertex_color key value
in the precompile for shaders which don't use those varyings.
Eliminates virtually all VS recompiles in Serious Sam 3's intro.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Kenneth Graunke [Mon, 1 Dec 2014 09:01:02 +0000 (01:01 -0800)]
i965: Make vertex color clamp handling code VS specific.
Vertex color clamping only applies to gl_[Secondary]{Front,Back}Color,
which are compatibility-only built-in varyings. We only support GS in
core profile, so they can't exist in geometry shaders.
We can drop several dirty bits from the GS program key - they're
unnecessary for a core profile implementation.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Kenneth Graunke [Mon, 1 Dec 2014 08:53:02 +0000 (00:53 -0800)]
i965/vs: Handle vertex color clamping in emit_urb_slot().
Vertex color clamping only applies to a few specific built-ins: COL0/1
and BFC0/1 (aka gl_[Secondary]{Front,Back}Color). It seems weird to
handle special cases in a function called emit_generic_urb_slot().
emit_urb_slot() is all about handling special cases, so it makes more
sense to handle this there.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Kenneth Graunke [Tue, 2 Dec 2014 06:23:22 +0000 (22:23 -0800)]
i965: Use the enum type for gen6_gather_wa sampler key field.
Requested by Matt Turner.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Kenneth Graunke [Wed, 29 Oct 2014 01:48:49 +0000 (18:48 -0700)]
i965: Drop use of GL types in program keys.
This is really far removed from the API; we should just use C types.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Kenneth Graunke [Wed, 29 Oct 2014 01:13:49 +0000 (18:13 -0700)]
i965: Move program key structures to brw_program.h.
With fs_visitor/fs_generator being reused for SIMD8 VS/GS programs,
we're running into weird #include patterns, where scalar code #includes
brw_vec4.h and such.
Program keys aren't really related to SIMD4X2/SIMD8 execution - they
mostly capture NOS for a particular shader stage. Consolidating them
all in one place that's vec4/scalar neutral should help avoid problems.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Kenneth Graunke [Tue, 25 Nov 2014 08:35:31 +0000 (00:35 -0800)]
i965: Delete brw_state_flags::cache and related code.
It's been merged into brw_state_flags::brw for simplicity and
efficiency.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Kenneth Graunke [Tue, 25 Nov 2014 07:57:48 +0000 (23:57 -0800)]
i965: Move BRW_NEW_*_PROG_DATA flags to .brw (not .cache).
I put the BRW_NEW_*_PROG_DATA flags at the beginning so that
brw_state_cache.c can still continue using 1 << brw_cache_id.
I also added a comment explaining the difference between
BRW_NEW_*_PROG_DATA and BRW_NEW_*_PROGRAM, as it took me a long time
to remember it.
Non-mechanical changes:
- brw_state_cache.c and brw_ff_gs.c now signal .brw, not .cache.
- brw_state_upload.c - INTEL_DEBUG=state changes.
- brw_context.h - bit definition merging.
v2: Correct the explanation of BRW_NEW_*_PROG_DATA to mention
state-based recompiles, and nix the "proper subset" claim,
as it's false. (Caught by Kristian Høgsberg).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Kenneth Graunke [Tue, 25 Nov 2014 07:30:51 +0000 (23:30 -0800)]
i965: Rename CACHE_NEW_*_PROG to BRW_NEW_*_PROG_DATA.
Now that we've moved a bunch of CACHE_NEW_* bits to BRW_NEW_*, the only
ones that are left are legitimately related to the program cache. Yet,
it seems a bit wasteful to have an entire bitfield for only 7 bits.
State upload is one of the hottest paths in the driver. For each atom
in the list, we call check_state() to see if it needs to be emitted.
Currently, this involves comparing three separate bitfields (mesa, brw,
and cache). Consolidating the brw and cache bitfields would save a
small amount of CPU overhead per atom. Broadwell, for example, has
57 state atoms, so this small savings can add up.
CACHE_NEW_*_PROG covers the brw_*_prog_data structures, as well as the
offset into the program cache BO (prog_offset). Since most uses refer
to brw_*_prog_data, I decided to use BRW_NEW_*_PROG_DATA as the name.
Removing "cache" completely is a bit painful, so I decided to do it in
several patches for easier review, and to separate mechanical changes
from manual ones. This one simply renames things, and was made via:
$ for file in *.[ch]; do
sed -i -e 's/CACHE_NEW_\([A-Z_\*]*\)_PROG/BRW_NEW_\1_PROG_DATA/g' \
-e 's/BRW_NEW_WM_PROG_DATA/BRW_NEW_FS_PROG_DATA/g' $file
done
Note that BRW_NEW_*_PROG_DATA is still in .cache, not .brw!
The next patch will remedy this flaw. It will also fix the
alphabetization issues.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Acked-by: Matt Turner <mattst88@gmail.com>
Kenneth Graunke [Mon, 1 Dec 2014 05:58:03 +0000 (21:58 -0800)]
i965: Remove "disable_derivative_optimization" driconf option.
This was added in September 2013 when we first implemented the fast
(but lower quality) derivatives. A quick Google search didn't turn
up anyone using or recommending the option, so I suspect no one does.
Applications that want to control the quality of their derivatives can
use the new GL_ARB_derivative_control extension, or use the glHint
mechanism. The driconf option seems superfluous.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Ian Romanick [Tue, 11 Nov 2014 14:10:06 +0000 (14:10 +0000)]
i965: Just return void from brw_try_draw_prims
Note from Ken:
"We used to use the return value to indicate whether software
fallbacks were necessary, but we haven't in years."
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>