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Andrea Di Biagio [Fri, 13 Jul 2018 16:46:51 +0000 (16:46 +0000)]
[llvm-mca][BtVer2] Add tests for dependency breaking instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337024
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Ulrich Weigand [Fri, 13 Jul 2018 16:42:15 +0000 (16:42 +0000)]
[TableGen] Suppress type validation when parsing pattern fragments
Currently, any attempt to define a PatFrag involving any floating-point
only (or vector only) node causes a hard assertion failure in TableGen
if the current target does not have any floating-point (or vector)
types.
This is annoying if you want to provide convenience fragments in common
code (e.g. include/llvm/Target/TargetSelectionDAG.td) that is parsed on
all platforms, including those that miss such types.
But really, there's no reason not accept this when parsing the fragment
-- of course it would be an error for such a target to actually *use*
such a fragment anywhere, but as long as it doesn't, I think TableGen
shouldn't error out.
The immediate cause of the assertion failure is the test inside the
ValidateOnExit destructor. This patch simply disables that check while
infering types during parsing of pattern fragments (only).
Reviewed By: hfinkel, kparzysz
Differential Revision: https://reviews.llvm.org/D48887
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337023
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Matt Arsenault [Fri, 13 Jul 2018 16:40:37 +0000 (16:40 +0000)]
AMDGPU: Properly handle shader inputs with split arguments
This needs to refer to arguments by their original argument
index, not the argument split index which depends on what
the type splitting decides to do.
Also avoid increment PSInputNum for each split piece.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337022
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Matt Arsenault [Fri, 13 Jul 2018 16:40:25 +0000 (16:40 +0000)]
AMDGPU: Fix handling of alignment padding in DAG argument lowering
This was completely broken if there was ever a struct argument, as
this information is thrown away during the argument analysis.
The offsets as passed in to LowerFormalArguments are not useful,
as they partially depend on the legalized result register type,
and they don't consider the alignment in the first place.
Ignore the Ins array, and instead figure out from the raw IR type
what we need to do. This seems to fix the padding computation
if the DAG lowering is forced (and stops breaking arguments
following padded arguments if the arguments were only partially
lowered in the IR)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337021
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Marcello Maggioni [Fri, 13 Jul 2018 16:36:14 +0000 (16:36 +0000)]
[Tablegen] Optimize isSubsetOf() in AsmMatcherEmitter.cpp. NFC
isSubsetOf() could be very slow if the hierarchy of the RegisterClasses
of the target is very complicated.
This is mainly caused by the fact that isSubset() is called
multiple times over the same SuperClass of a register class
if this ends up being the super class of a register class
from multiple paths.
Differential Revision: https://reviews.llvm.org/D49124
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337020
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Evgeniy Stepanov [Fri, 13 Jul 2018 16:32:31 +0000 (16:32 +0000)]
Revert "CallGraphSCCPass: iterate over all functions."
This reverts commit r336419: use-after-free on CallGraph::FunctionMap elements
due to the use of a stale iterator in CGPassManager::runOnModule.
The iterator may be invalidated if a pass removes a function, ex.:
llvm::LegacyInlinerBase::inlineCalls
inlineCallsImpl
llvm::CallGraph::removeFunctionFromModule
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337018
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Roman Lebedev [Fri, 13 Jul 2018 16:14:37 +0000 (16:14 +0000)]
[NFC][X86][AArch64] Negative tests for 'check for [no] signed truncation' pattern
See D49247, D49266
I'm only adding the sane negative tests, and not
adding the one-use tests yet. Also, not adding
negative tests for the second pattern with inverted operands yet,
since it's handling will be added in later differential.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337014
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Joel Galenson [Fri, 13 Jul 2018 16:09:19 +0000 (16:09 +0000)]
[cfi-verify] Only run AArch64 tests when it is a supported target
This stops the tests I added in r337007 from running when AArch64 is not a supported target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337012
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Jonas Devlieghere [Fri, 13 Jul 2018 16:06:17 +0000 (16:06 +0000)]
[dwarfdump] Pretty print DW_AT_APPLE_runtime_class
Instead of printing
DW_AT_APPLE_runtime_class (0x10)
we now print
DW_AT_APPLE_runtime_class (DW_LANG_ObjC)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337011
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Sjoerd Meijer [Fri, 13 Jul 2018 15:25:42 +0000 (15:25 +0000)]
[AArch64] Armv8.4-A: LDAPR & STLR with immediate offset instructions (cont'd)
Follow up of rL336913: fix base class description. Thanks to Ahmed Bougacha
for pointing this out.
Differential Revision: https://reviews.llvm.org/D49284
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337009
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Nemanja Ivanovic [Fri, 13 Jul 2018 15:21:03 +0000 (15:21 +0000)]
[PowerPC] Materialize more constants with CR-field set in late peephole
Revision r322373 fixed a bug in how we materialize constants when the CR-field
needs to be set.
However the fix is overly conservative. It will only do the transform if
AND-ing the input with the new constant produces the same new constant.
This is of course correct, but not necessarily required.
If there are no futher uses of the constant, the constant can be changed.
If there are no uses of the GPR result, the final result of the materialization
isn't important other than it needs to compare to zero correctly (lt, gt, eq).
Differential revision: https://reviews.llvm.org/D42109
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337008
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Joel Galenson [Fri, 13 Jul 2018 15:19:33 +0000 (15:19 +0000)]
[cfi-verify] Support AArch64.
This patch adds support for AArch64 to cfi-verify.
This required three changes to cfi-verify. First, it generalizes checking if an instruction is a trap by adding a new isTrap flag to TableGen (and defining it for x86 and AArch64). Second, the code that ensures that the operand register is not clobbered between the CFI check and the indirect call needs to allow a single dereference (in x86 this happens as part of the jump instruction). Third, we needed to ensure that return instructions are not counted as indirect branches. Technically, returns are indirect branches and can be covered by CFI, but LLVM's forward-edge CFI does not protect them, and x86 does not consider them, so we keep that behavior.
In addition, we had to improve AArch64's code to evaluate the branch target of a MCInst to handle calls where the destination is not the first operand (which it often is not).
Differential Revision: https://reviews.llvm.org/D48836
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337007
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Stella Stamenova [Fri, 13 Jul 2018 15:10:53 +0000 (15:10 +0000)]
[json, test] Fix the json.td test - the path to python could contain spaces
Summary: The path to the python executable can contain spaces, so it should be specified with quotes.
Reviewers: asmith, simon_tatham
Reviewed By: simon_tatham
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D49258
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337006
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Simon Atanasyan [Fri, 13 Jul 2018 15:03:24 +0000 (15:03 +0000)]
[mips] Add microMIPS case to the tests and regenerate assertions using update_llc_test_checks.py. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337004
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Andrea Di Biagio [Fri, 13 Jul 2018 14:55:47 +0000 (14:55 +0000)]
[llvm-mca] Improve a few debug prints. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337003
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Erich Keane [Fri, 13 Jul 2018 14:43:20 +0000 (14:43 +0000)]
Add parens to silence Wparentheses warning, introduced by 336990
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337002
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Erich Keane [Fri, 13 Jul 2018 14:41:15 +0000 (14:41 +0000)]
[NFC] Silence Wparentheses warning in DomTreeUpdater, introduced by 336968
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337001
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Ulrich Weigand [Fri, 13 Jul 2018 13:18:00 +0000 (13:18 +0000)]
[TableGen] Support multi-alternative pattern fragments
A TableGen instruction record usually contains a DAG pattern that will
describe the SelectionDAG operation that can be implemented by this
instruction. However, there will be cases where several different DAG
patterns can all be implemented by the same instruction. The way to
represent this today is to write additional patterns in the Pattern
(or usually Pat) class that map those extra DAG patterns to the
instruction. This usually also works fine.
However, I've noticed cases where the current setup seems to require
quite a bit of extra (and duplicated) text in the target .td files.
For example, in the SystemZ back-end, there are quite a number of
instructions that can implement an "add-with-overflow" operation.
The same instructions also need to be used to implement just plain
addition (simply ignoring the extra overflow output). The current
solution requires creating extra Pat pattern for every instruction,
duplicating the information about which particular add operands
map best to which particular instruction.
This patch enhances TableGen to support a new PatFrags class, which
can be used to encapsulate multiple alternative patterns that may
all match to the same instruction. It operates the same way as the
existing PatFrag class, except that it accepts a list of DAG patterns
to match instead of just a single one. As an example, we can now define
a PatFrags to match either an "add-with-overflow" or a regular add
operation:
def z_sadd : PatFrags<(ops node:$src1, node:$src2),
[(z_saddo node:$src1, node:$src2),
(add node:$src1, node:$src2)]>;
and then use this in the add instruction pattern:
defm AR : BinaryRRAndK<"ar", 0x1A, 0xB9F8, z_sadd, GR32, GR32>;
These SystemZ target changes are implemented here as well.
Note that PatFrag is now defined as a subclass of PatFrags, which
means that some users of internals of PatFrag need to be updated.
(E.g. instead of using PatFrag.Fragment you now need to use
!head(PatFrag.Fragments).)
The implementation is based on the following main ideas:
- InlinePatternFragments may now replace each original pattern
with several result patterns, not just one.
- parseInstructionPattern delays calling InlinePatternFragments
and InferAllTypes. Instead, it extracts a single DAG match
pattern from the main instruction pattern.
- Processing of the DAG match pattern part of the main instruction
pattern now shares most code with processing match patterns from
the Pattern class.
- Direct use of main instruction patterns in InferFromPattern and
EmitResultInstructionAsOperand is removed; everything now operates
solely on DAG match patterns.
Reviewed by: hfinkel
Differential Revision: https://reviews.llvm.org/D48545
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336999
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Tim Renouf [Fri, 13 Jul 2018 13:13:30 +0000 (13:13 +0000)]
DivergenceAnalysis: added debug output
Summary:
This commit does two things:
1. modified the existing DivergenceAnalysis::dump() so it dumps the
whole function with added DIVERGENT: annotations;
2. added code to do that dump if the appropriate -debug-only option is
on.
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D47700
Change-Id: Id97b605aab1fc6f5a11a20c58a99bbe8c565bf83
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336998
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Chandler Carruth [Fri, 13 Jul 2018 11:13:58 +0000 (11:13 +0000)]
[SLH] Introduce a new pass to do Speculative Load Hardening to mitigate
Spectre variant #1 for x86.
There is a lengthy, detailed RFC thread on llvm-dev which discusses the
high level issues. High level discussion is probably best there.
I've split the design document out of this patch and will land it
separately once I update it to reflect the latest edits and updates to
the Google doc used in the RFC thread.
This patch is really just an initial step. It isn't quite ready for
prime time and is only exposed via debugging flags. It has two major
limitations currently:
1) It only supports x86-64, and only certain ABIs. Many assumptions are
currently hard-coded and need to be factored out of the code here.
2) It doesn't include any options for more fine-grained control, either
of which control flow edges are significant or which loads are
important to be hardened.
3) The code is still quite rough and the testing lighter than I'd like.
However, this is enough for people to begin using. I have had numerous
requests from people to be able to experiment with this patch to
understand the trade-offs it presents and how to use it. We would also
like to encourage work to similar effect in other toolchains.
The ARM folks are actively developing a system based on this for
AArch64. We hope to merge this with their efforts when both are far
enough along. But we also don't want to block making this available on
that effort.
Many thanks to the *numerous* people who helped along the way here. For
this patch in particular, both Eric and Craig did a ton of review to
even have confidence in it as an early, rough cut at this functionality.
Differential Revision: https://reviews.llvm.org/D44824
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336990
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Simon Pilgrim [Fri, 13 Jul 2018 11:09:52 +0000 (11:09 +0000)]
[SLPVectorizer] Add initial alternate opcode support for cast instructions. (REAPPLIED-2)
We currently only support binary instructions in the alternate opcode shuffles.
This patch is an initial attempt at adding cast instructions as well, this raises several issues that we probably want to address as we continue to generalize the alternate mechanism:
1 - Duplication of cost determination - we should probably add scalar/vector costs helper functions and get BoUpSLP::getEntryCost to use them instead of determining costs directly.
2 - Support alternate instructions with the same opcode (e.g. casts with different src types) - alternate vectorization of calls with different IntrinsicIDs will require this.
3 - Allow alternates to be a different instruction type - mixing binary/cast/call etc.
4 - Allow passthrough of unsupported alternate instructions - related to PR30787/D28907 'copyable' elements.
Reapplied with fix to only accept 2 different casts if they come from the same source type (PR38154).
Differential Revision: https://reviews.llvm.org/D49135
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336989
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Chandler Carruth [Fri, 13 Jul 2018 10:29:23 +0000 (10:29 +0000)]
[UpdateTestChecks] Teach the x86 asm parser to skip over the function
begin label emitted for some routines with personality functions and
such.
Without this, we don't even recognize such functions as appearing in the
output and so don't attach any assertions to them. Happy to tweak this
or improve it if folks w/ deeper knowledge of the asm sequences that
show up here want.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336987
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Chandler Carruth [Fri, 13 Jul 2018 09:48:04 +0000 (09:48 +0000)]
[x86] Fix a capitalization that I failed to save in my editor before
landing the patch. =/
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336986
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Chandler Carruth [Fri, 13 Jul 2018 09:39:10 +0000 (09:39 +0000)]
[x86] Teach the EFLAGS copy lowering to handle much more complex control
flow patterns including forks, merges, and even cyles.
This tries to cover a reasonably comprehensive set of patterns that
still don't require PHIs or PHI placement. The coverage was inspired by
the amazing variety of patterns produced when copy EFLAGS and restoring
it to implement Speculative Load Hardening. Without this patch, we
simply cannot make such complex and invasive changes to x86 instruction
sequences due to EFLAGS.
I've added "just" one test, but this test covers many different
complexities and corner cases of this approach. It is actually more
comprehensive, as far as I can tell, than anything that I have
encountered in the wild on SLH.
Because the test is so complex, I've tried to give somewhat thorough
comments and an ASCII-art diagram of the control flows to make it a bit
easier to read and maintain long-term.
Differential Revision: https://reviews.llvm.org/D49220
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336985
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Andrea Di Biagio [Fri, 13 Jul 2018 09:31:02 +0000 (09:31 +0000)]
[llvm-mca] Simplify the Pipeline constructor. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336984
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Andrea Di Biagio [Fri, 13 Jul 2018 09:27:34 +0000 (09:27 +0000)]
[llvm-mca] Removed unused arguments from methods in class Pipeline. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336983
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Sander de Smalen [Fri, 13 Jul 2018 09:25:43 +0000 (09:25 +0000)]
[AArch64][SVE] Asm: Vector Unpack Low/High instructions.
This patch adds support for the following unpack instructions:
- PUNPKLO, PUNPKHI Unpack elements from low/high half and
place into elements of twice their size.
e.g. punpklo p0.h, p0.b
- UUNPKLO, UUNPKHI Unpack elements from low/high half and
SUNPKLO, SUNPKHI place into elements of twice their size
after zero- or sign-extending the values.
e.g. uunpklo z0.h, z0.b
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336982
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Simon Pilgrim [Fri, 13 Jul 2018 09:25:32 +0000 (09:25 +0000)]
[AArch64] Updated bigendian buildvector tests
As suggested by @efriedma on D49262 - changed the extractelement to a store to prevent SimplifyDemandedVectorElts from simplifying the build vectors - this keeps the immediate generation which was the point of the tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336981
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Simon Pilgrim [Fri, 13 Jul 2018 09:16:56 +0000 (09:16 +0000)]
[ARM] Regenerated arg endian test
As requested on D49262
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336980
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Sander de Smalen [Fri, 13 Jul 2018 08:51:57 +0000 (08:51 +0000)]
[AArch64][SVE] Asm: Support for insert element (INSR) instructions.
Insert general purpose register into shifted vector, e.g.
insr z0.s, w0
insr z0.d, x0
Insert SIMD&FP scalar register into shifted vector, e.g.
insr z0.b, b0
insr z0.h, h0
insr z0.s, s0
insr z0.d, d0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336979
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Petar Jovanovic [Fri, 13 Jul 2018 08:24:26 +0000 (08:24 +0000)]
[LiveDebugValues] Tracking copying value between registers
During the execution of long functions or functions that have a lot of
inlined code it could come to the situation where tracked value could be
transferred from one register to another. The transfer is recognized only if
destination register is a callee saved register and if source register is
killed. We do not salvage caller-saved registers since there is a great
chance that killed register would outlive it.
Patch by Nikola Prica.
Differential Revision: https://reviews.llvm.org/D44016
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336978
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Craig Topper [Fri, 13 Jul 2018 06:25:31 +0000 (06:25 +0000)]
[X86] Prefer MOVSS/SD over BLEND under optsize in isel.
Previously we iseled to blend, commuted to another blend, and then commuted back to movss/movsd or blend depending on optsize. Now we do it directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336976
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Dean Michael Berris [Fri, 13 Jul 2018 05:38:22 +0000 (05:38 +0000)]
[XRay][compiler-rt] Add PID field to llvm-xray tool and add PID metadata record entry in FDR mode
Summary:
llvm-xray changes:
- account-mode - process-id {...} shows after thread-id
- convert-mode - process {...} shows after thread
- parses FDR and basic mode pid entries
- Checks version number for FDR log parsing.
Basic logging changes:
- Update header version from 2 -> 3
FDR logging changes:
- Update header version from 2 -> 3
- in writeBufferPreamble, there is an additional PID Metadata record (after thread id record and tsc record)
Test cases changes:
- fdr-mode.cc, fdr-single-thread.cc, fdr-thread-order.cc modified to catch process id output in the log.
Reviewers: dberris
Reviewed By: dberris
Subscribers: hiraditya, llvm-commits, #sanitizers
Differential Revision: https://reviews.llvm.org/D49153
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336974
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Craig Topper [Fri, 13 Jul 2018 04:50:39 +0000 (04:50 +0000)]
[X86] Remove isel patterns that turns packed add/sub/mul/div+movss/sd into scalar intrinsic instructions.
This is not an optimization we should be doing in isel. This is more suitable for a DAG combine.
My main concern is a future time when we support more FPENV. Changing a packed op to a scalar op could cause us to miss some exceptions that should have occured if we had done a packed op. A DAG combine would be better able to manage this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336971
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Chijun Sima [Fri, 13 Jul 2018 04:02:13 +0000 (04:02 +0000)]
[DomTreeUpdater] Ignore updates when both DT and PDT are nullptrs
Summary:
Previously, when both DT and PDT are nullptrs and the UpdateStrategy is Lazy, DomTreeUpdater still pends updates inside.
After this patch, DomTreeUpdater will ignore all updates from(`applyUpdates()/insertEdge*()/deleteEdge*()`) in this case. (call `delBB()` still pends BasicBlock deletion until a flush event according to the doc).
The behavior of DomTreeUpdater previously documented won't change after the patch.
Reviewers: dmgreen, davide, kuhar, brzycki, grosser
Reviewed By: kuhar
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D48974
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336968
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Joel E. Denny [Fri, 13 Jul 2018 03:08:23 +0000 (03:08 +0000)]
[FileCheck] Implement -v and -vv for tracing matches
-v prints all directive pattern matches.
-vv additionally prints info that might be noise to users but that can
be helpful to FileCheck developers.
To maximize code reuse and to make diagnostics more consistent, this
patch also adjusts and extends some of the existing diagnostics.
CHECK-NOT failures now report variables uses. Many more diagnostics
now report the check prefix and kind of directive.
Reviewed By: probinson
Differential Revision: https://reviews.llvm.org/D47114
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336967
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Sanjay Patel [Fri, 13 Jul 2018 01:18:07 +0000 (01:18 +0000)]
[InstCombine] return when SimplifyAssociativeOrCommutative makes a change
This bug was created by rL335258 because we used to always call instsimplify
after trying the associative folds. After that change it became possible
for subsequent folds to encounter unsimplified code (and potentially assert
because of it).
Instead of carrying changed state through instcombine, we can just return
immediately. This allows instsimplify to run, so we can continue assuming
that easy folds have already occurred.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336965
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Matthias Braun [Fri, 13 Jul 2018 00:08:38 +0000 (00:08 +0000)]
CodeGen: Remove pipeline dependencies on StackProtector; NFC
This re-applies r336929 with a fix to accomodate for the Mips target
scheduling multiple SelectionDAG instances into the pass pipeline.
PrologEpilogInserter and StackColoring depend on the StackProtector analysis
being alive from the point it is run until PEI, which requires that they are all
scheduled in the same FunctionPassManager. Inserting a (machine) ModulePass
between StackProtector and PEI results in these passes being in separate
FunctionPassManagers and the StackProtector is not available for PEI.
PEI and StackColoring don't use much information from the StackProtector pass,
so transfering the required information to MachineFrameInfo is cleaner than
keeping the StackProtector pass around. This commit moves the SSP layout
information to MFI instead of keeping it in the pass.
This patch set (D37580, D37581, D37582, D37583, D37584, D37585, D37586, D37587)
is a first draft of the pagerando implementation described in
http://lists.llvm.org/pipermail/llvm-dev/2017-June/113794.html.
Patch by Stephen Crane <sjc@immunant.com>
Differential Revision: https://reviews.llvm.org/D49256
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336964
91177308-0d34-0410-b5e6-
96231b3b80d8
Piotr Padlewski [Thu, 12 Jul 2018 23:55:20 +0000 (23:55 +0000)]
Simplify recursive launder.invariant.group and strip
Summary:
This patch is crucial for proving equality laundered/stripped
pointers. eg:
bool foo(A *a) {
return a == std::launder(a);
}
Clang with -fstrict-vtable-pointers will emit something like:
define dso_local zeroext i1 @_Z3fooP1A(%struct.A* %a) {
entry:
%c = bitcast %struct.A* %a to i8*
%call = tail call i8* @llvm.launder.invariant.group.p0i8(i8* %c)
%0 = bitcast %struct.A* %a to i8*
%1 = tail call i8* @llvm.strip.invariant.group.p0i8(i8* %0)
%2 = tail call i8* @llvm.strip.invariant.group.p0i8(i8* %call)
%cmp = icmp eq i8* %1, %2
ret i1 %cmp
}
and because %2 can be replaced with @llvm.strip.invariant.group(%0)
and that %2 and %1 will produce the same value (because strip is readnone)
we can replace compare with true.
Reviewers: rsmith, hfinkel, majnemer, amharc, kuhar
Subscribers: llvm-commits, hiraditya
Differential Revision: https://reviews.llvm.org/D47423
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336963
91177308-0d34-0410-b5e6-
96231b3b80d8
Matt Davis [Thu, 12 Jul 2018 23:19:30 +0000 (23:19 +0000)]
[llvm-mca] Constify SourceMgr::hasNext. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336961
91177308-0d34-0410-b5e6-
96231b3b80d8
Matt Davis [Thu, 12 Jul 2018 22:59:53 +0000 (22:59 +0000)]
[llvm-mca] Add cycleBegin/cycleEnd callbacks to mca::Stage.
Summary:
This patch clears up some of the semantics within the Stage class. Now, preExecute
can be called multiple times per simulated cycle. Previously preExecute was
only called once per cycle, and postExecute could have been called multiple
times.
Now, cycleStart/cycleEnd are called only once per simulated cycle.
preExecute/postExecute can be called multiple times per cycle. This
occurs because multiple execution events can occur during a single cycle.
When stages are executed (Pipeline::runCycle), the postExecute hook will
be called only if all Stages return a success from their 'execute' callback.
Reviewers: andreadb, courbet, RKSimon
Reviewed By: andreadb
Subscribers: tschuett, gbedwell, llvm-commits
Differential Revision: https://reviews.llvm.org/D49250
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336959
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Thu, 12 Jul 2018 22:59:03 +0000 (22:59 +0000)]
[X86] Regenerate checks in sse-scalar-fp-arith.ll.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336958
91177308-0d34-0410-b5e6-
96231b3b80d8
Fangrui Song [Thu, 12 Jul 2018 22:56:23 +0000 (22:56 +0000)]
[InstCombine] Simplify isKnownNegation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336957
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Thu, 12 Jul 2018 22:14:10 +0000 (22:14 +0000)]
[X86] Add AVX512 equivalents of some isel patterns so we get EVEX instructions.
These are the patterns for matching fceil, ffloor, and sqrt to intrinsic instructions if they have a MOVSS/SD.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336954
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Thu, 12 Jul 2018 21:58:03 +0000 (21:58 +0000)]
Revert r336950 and r336951 "[X86] Add AVX512 equivalents of some isel patterns so we get EVEX instructions." and "foo"
One of them had a bad title and they should have been squashed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336953
91177308-0d34-0410-b5e6-
96231b3b80d8
George Burgess IV [Thu, 12 Jul 2018 21:56:31 +0000 (21:56 +0000)]
Remove redundant *_or_null checks; NFC
For the first one, we dereference `NewDef` right before the `if` anyway.
For the second, we shouldn't have NULL users().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336952
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Thu, 12 Jul 2018 21:53:23 +0000 (21:53 +0000)]
[X86] Add AVX512 equivalents of some isel patterns so we get EVEX instructions.
These are the patterns for matching fceil, ffloor, and sqrt to intrinsic instructions if they have a MOVSS/SD.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336951
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Thu, 12 Jul 2018 21:53:07 +0000 (21:53 +0000)]
foo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336950
91177308-0d34-0410-b5e6-
96231b3b80d8
Martin Storsjo [Thu, 12 Jul 2018 21:33:42 +0000 (21:33 +0000)]
Revert "[SLPVectorizer] Add initial alternate opcode support for cast instructions. (REAPPLIED)"
This reverts commit r336812, which broke compilation of a number
of projects, see PR38154.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336949
91177308-0d34-0410-b5e6-
96231b3b80d8
Bill Wendling [Thu, 12 Jul 2018 20:35:58 +0000 (20:35 +0000)]
[gold-plugin] Disable section ordering for relocatable links
Not all programs want section ordering when compiled with LTO.
In particular, the Linux kernel is very sensitive when it comes to linking, and
doesn't boot when each function is placed in its own sections.
Reviewed By: pcc
Differential Revision: https://reviews.llvm.org/D48756
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336943
91177308-0d34-0410-b5e6-
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Matt Morehouse [Thu, 12 Jul 2018 20:24:58 +0000 (20:24 +0000)]
[SanitizerCoverage] Add associated metadata to 8-bit counters.
Summary:
This allows counters associated with unused functions to be
dead-stripped along with their functions. This approach is the same one
we used for PC tables.
Fixes an issue where LLD removes an unused PC table but leaves the 8-bit
counter.
Reviewers: eugenis
Reviewed By: eugenis
Subscribers: llvm-commits, hiraditya, kcc
Differential Revision: https://reviews.llvm.org/D49264
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336941
91177308-0d34-0410-b5e6-
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Stefan Pintilie [Thu, 12 Jul 2018 20:18:57 +0000 (20:18 +0000)]
[PowerPC] [NFC] Update __float128 tests
Add the two options -ppc-vsr-nums-as-vr and -ppc-asm-full-reg-names to
the __float128 tests. Then modify the tests as required.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336940
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Thu, 12 Jul 2018 19:58:06 +0000 (19:58 +0000)]
[X86][FastISel] Support EVEX version of sqrt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336939
91177308-0d34-0410-b5e6-
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Craig Topper [Thu, 12 Jul 2018 19:58:01 +0000 (19:58 +0000)]
[X86] Add show-mc-encoding to some fast-isel intrinsic tests so we can observe a failure to select EVEX instructions.
The one I noticed is sqrtsss/sd, but there could be others.
I had to add a couple new tests that don't have insertelement in there to catch this on the fast-isel path. Otherwise we trigger an abort and use SelectionDAG.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336938
91177308-0d34-0410-b5e6-
96231b3b80d8
Matt Arsenault [Thu, 12 Jul 2018 19:40:16 +0000 (19:40 +0000)]
AMDGPU: Fix assert in truncate combine with vectors
The piece above probably has the same problem, but I need
to try to come up with a test for it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336935
91177308-0d34-0410-b5e6-
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Matthias Braun [Thu, 12 Jul 2018 19:27:01 +0000 (19:27 +0000)]
Revert "(HEAD -> master, origin/master, arcpatch-D37582) CodeGen: Remove pipeline dependencies on StackProtector; NFC"
This was triggering pass scheduling failures.
This reverts commit r336929.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336934
91177308-0d34-0410-b5e6-
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Matthias Braun [Thu, 12 Jul 2018 18:33:32 +0000 (18:33 +0000)]
CodeGen: Remove pipeline dependencies on StackProtector; NFC
PrologEpilogInserter and StackColoring depend on the StackProtector analysis
being alive from the point it is run until PEI, which requires that they are all
scheduled in the same FunctionPassManager. Inserting a (machine) ModulePass
between StackProtector and PEI results in these passes being in separate
FunctionPassManagers and the StackProtector is not available for PEI.
PEI and StackColoring don't use much information from the StackProtector pass,
so transfering the required information to MachineFrameInfo is cleaner than
keeping the StackProtector pass around. This commit moves the SSP layout
information to MFI instead of keeping it in the pass.
This patch set (D37580, D37581, D37582, D37583, D37584, D37585, D37586, D37587)
is a first draft of the pagerando implementation described in
http://lists.llvm.org/pipermail/llvm-dev/2017-June/113794.html.
Patch by Stephen Crane <sjc@immunant.com>
Differential Revision: https://reviews.llvm.org/D49256
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336929
91177308-0d34-0410-b5e6-
96231b3b80d8
Wolfgang Pieb [Thu, 12 Jul 2018 18:18:21 +0000 (18:18 +0000)]
[DWARF v5] Generate range list tables into the .debug_rnglists section. No support for split DWARF
and no use of DW_FORM_rnglistx with the DW_AT_ranges attribute.
Reviewer: aprantl
Differential Revision: https://reviews.llvm.org/D49214
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336927
91177308-0d34-0410-b5e6-
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Craig Topper [Thu, 12 Jul 2018 18:04:05 +0000 (18:04 +0000)]
[X86] Connect the flags user from PCMPISTR instructions to the correct node from the instruction.
We were accidentally connecting it to result 0 instead of result 1. This was caught by the machine verifier that noticed the flags were dead, but we were using them somehow. I'm still not clear what actually happened downstream.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336925
91177308-0d34-0410-b5e6-
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Craig Topper [Thu, 12 Jul 2018 18:03:56 +0000 (18:03 +0000)]
[X86][FastISel] Choose EVEX instructions when possible when lowering x86_sse_cvttss2si and similar intrinsics.
This should fix a machine verifier error.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336924
91177308-0d34-0410-b5e6-
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Galina Kistanova [Thu, 12 Jul 2018 17:58:10 +0000 (17:58 +0000)]
Reverted r336805 as it broke llvm-clang-x86_64-expensive-checks-win build bot
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336923
91177308-0d34-0410-b5e6-
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Stephen Hines [Thu, 12 Jul 2018 17:42:17 +0000 (17:42 +0000)]
Add --strip-all option back to llvm-strip.
Summary:
This option appears to have been dropped as part of the refactoring in
r331663. Unfortunately, if we want to use llvm-strip as a drop-in
replacement for strip, this option should still be available.
Reviewers: alexshap
Reviewed By: alexshap
Subscribers: meikeb, kongyi, chh, jakehehrlich, llvm-commits, pirama
Differential Revision: https://reviews.llvm.org/D49226
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336921
91177308-0d34-0410-b5e6-
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Roman Lebedev [Thu, 12 Jul 2018 17:00:11 +0000 (17:00 +0000)]
[NFC][X86][AArch64] Add tests for the 'check for [no] signed truncation' pattern
Summary:
[[ https://bugs.llvm.org/show_bug.cgi?id=38149 | PR38149 ]]
As discussed in https://reviews.llvm.org/D49179#
1158957 and later,
the IR can be improved:
https://rise4fun.com/Alive/gBf
^ that pattern will be produced by Implicit Integer Truncation sanitizer,
https://reviews.llvm.org/D48958
https://bugs.llvm.org/show_bug.cgi?id=21530
in signed case, therefore it is probably a good idea to improve it.
But as it looks from these tests,
i think we want to revert at least some cases in DAGCombine.
Reviewers: spatel, craig.topper, RKSimon, javed.absar
Reviewed By: spatel
Subscribers: kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D49247
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336917
91177308-0d34-0410-b5e6-
96231b3b80d8
Matt Davis [Thu, 12 Jul 2018 16:56:17 +0000 (16:56 +0000)]
[llvm-mca] Simplify eventing by adding an onEvent templated method.
Summary:
This patch eliminates some redundancy in iterating across Listeners for the
Instruction and Stall HWEvents, by introducing a template onEvent routine.
This change was suggested by @courbet in https://reviews.llvm.org/D48576. I
hope that this patch addresses that suggestion appropriately. I do like this
change better than what we had previously.
Reviewers: andreadb, courbet, RKSimon
Reviewed By: andreadb, courbet
Subscribers: javed.absar, tschuett, gbedwell, llvm-commits, courbet
Differential Revision: https://reviews.llvm.org/D48672
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336916
91177308-0d34-0410-b5e6-
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Sjoerd Meijer [Thu, 12 Jul 2018 14:59:02 +0000 (14:59 +0000)]
Follow up of r336913: forgot to add the new test files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336914
91177308-0d34-0410-b5e6-
96231b3b80d8
Sjoerd Meijer [Thu, 12 Jul 2018 14:57:59 +0000 (14:57 +0000)]
[AArch64] Armv8.4-A: LDAPR & STLR with immediate offset instructions
These instructions are added to AArch64 only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336913
91177308-0d34-0410-b5e6-
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Roman Lebedev [Thu, 12 Jul 2018 14:56:17 +0000 (14:56 +0000)]
[InstCombine] icmp-logical.ll: restore the original intention of the test.
While that fold is clearly not happening [anymore],
we do now have separate test cases for these cases,
so we should be ok to slightly adjust these tests
to not potentially loose test coverage.
As suggested by Hiroshi Yamauchi in
https://reviews.llvm.org/D49179#
1159345
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336912
91177308-0d34-0410-b5e6-
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Roman Lebedev [Thu, 12 Jul 2018 14:56:12 +0000 (14:56 +0000)]
[InstCombine] Fold x & (-1 >> y) != x to x u> (-1 >> y)
Summary:
A complementary fold to D49179.
https://bugs.llvm.org/show_bug.cgi?id=38123
https://rise4fun.com/Alive/Rny
Caveat: one more thing in `test/Transforms/InstCombine/icmp-logical.ll` breaks.
Reviewers: spatel, craig.topper
Reviewed By: spatel
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D49205
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336911
91177308-0d34-0410-b5e6-
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Andrew Ng [Thu, 12 Jul 2018 14:40:21 +0000 (14:40 +0000)]
[ThinLTO] Escape module paths when printing
We have located a bug in AssemblyWriter::printModuleSummaryIndex(). This
function outputs path strings incorrectly. Backslashes in the strings
are not correctly escaped.
Consequently, if a path name contains a backslash followed by two
hexadecimal characters, the sequence is incorrectly interpreted when the
output is read by another component. This mangles the path and results
in error.
This patch fixes this issue by calling printEscapedString() to output
the module paths.
Patch by Chris Jackson.
Differential Revision: https://reviews.llvm.org/D49090
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336908
91177308-0d34-0410-b5e6-
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Francis Visoiu Mistrih [Thu, 12 Jul 2018 14:36:48 +0000 (14:36 +0000)]
[DebugInfo][X86] Add start-after flags to MIR tests
These tests would fail with -verify-machineinstrs because the MI
generated from the IR would be merged with the one already in the MIR
files, and we get the following error:
```
*** Bad machine code: Function has NoVRegs property but there are VReg operands ***
- function: f
```
Differential Revision: https://reviews.llvm.org/D49191
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336907
91177308-0d34-0410-b5e6-
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Francis Visoiu Mistrih [Thu, 12 Jul 2018 14:36:43 +0000 (14:36 +0000)]
[XRay] Fix machine verifier issues in X86
I'm not sure if this fix is the right thing to do, but it seemed to me
that PATCHABLE_RET and PATCHABLE_TAIL_CALL don't have any defs.
Running the following:
```
LLVM_ENABLE_MACHINE_VERIFIER=1 ./build/bin/llvm-lit -v -a test/CodeGen/X86/xray-*
```
results in the following tests to fail (along others):
```
LLVM :: CodeGen/X86/xray-attribute-instrumentation.ll
LLVM :: CodeGen/X86/xray-custom-log.ll
LLVM :: CodeGen/X86/xray-log-args.ll
LLVM :: CodeGen/X86/xray-loop-detection.ll
LLVM :: CodeGen/X86/xray-multiplerets-in-blocks.mir
LLVM :: CodeGen/X86/xray-section-group.ll
LLVM :: CodeGen/X86/xray-selective-instrumentation.ll
LLVM :: CodeGen/X86/xray-tail-call-sled.ll
LLVM :: CodeGen/X86/xray-typed-event-log.ll
```
The errors are:
```
*** Bad machine code: Explicit definition must be a register ***
- function: fn
- basic block: %bb.0 (0x7fa31a84d908)
- instruction: PATCHABLE_RET 2560, $eax
- operand 0: 2560
```
and
```
*** Bad machine code: Explicit definition must be a register ***
- function: caller
- basic block: %bb.0 (0x7fbff3044108)
- instruction: PATCHABLE_TAIL_CALL 3009, @callee, <regmask $bh $bl $bp $bph $bpl $bx $ebp $ebx $hbp $hbx $rbp $rbx $r12 $r13 $r14 $r15 $r12b $r13b $r14b $r15b $r12bh $r13bh $r14bh $r15bh $r12d $r13d $r14d $r15d $r12w $r13w $r14w $r15w $r12wh and 3 more...>, implicit $rsp, implicit $ssp, implicit $rsp, implicit $ssp, implicit $edi
- operand 0: 3009
```
Differential Revision: https://reviews.llvm.org/D49187
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336906
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Thu, 12 Jul 2018 13:29:41 +0000 (13:29 +0000)]
[X86][SSE] Utilize ZeroableElements for canWidenShuffleElements
canWidenShuffleElements can do a better job if given a mask with ZeroableElements info. Apparently, ZeroableElements was being only used to identify AllZero candidates, but possibly we could plug it into more shuffle matchers.
Original Patch by Zvi Rackover @zvi
Differential Revision: https://reviews.llvm.org/D42044
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336903
91177308-0d34-0410-b5e6-
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Chen Zheng [Thu, 12 Jul 2018 13:28:20 +0000 (13:28 +0000)]
[InstCombine]add testcases for folding more SPFofSPF pattern
Differential Revision: https://reviews.llvm.org/D49222
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336902
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Thu, 12 Jul 2018 13:03:58 +0000 (13:03 +0000)]
[X86][AVX] Use Zeroable mask to improve shuffle mask widening
Noticed while updating D42044, lowerV2X128VectorShuffle can improve the shuffle mask with the zeroable data to create a target shuffle mask to recognise more 'zero upper 128' patterns.
NOTE: lowerV4X128VectorShuffle could benefit as well but the code needs refactoring first to discriminate between SM_SentinelUndef and SM_SentinelZero for negative shuffle indices.
Differential Revision: https://reviews.llvm.org/D49092
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336900
91177308-0d34-0410-b5e6-
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David Green [Thu, 12 Jul 2018 10:44:47 +0000 (10:44 +0000)]
[UnJ] Use SmallPtrSets for block collections. NFC
We no longer care about the order of blocks in these collections,
so can change to SmallPtrSets, making contains checks quicker.
Differential revision: https://reviews.llvm.org/D49060
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336897
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Thu, 12 Jul 2018 09:10:55 +0000 (09:10 +0000)]
Fix -Wdocumentation warnings. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336895
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Thu, 12 Jul 2018 09:04:28 +0000 (09:04 +0000)]
[X86] Add UDIV by uniform/non-uniform constant tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336894
91177308-0d34-0410-b5e6-
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Simon Atanasyan [Thu, 12 Jul 2018 08:50:11 +0000 (08:50 +0000)]
[mips] Mark standard encoded instructions as not being in MIPS16e
Mark standard encoded instructions and pseudo "standard encoded"
as not being in MIPS16e by default.
Patch by Simon Dardis.
Differential revision: https://reviews.llvm.org/D48379
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336893
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Thu, 12 Jul 2018 07:30:01 +0000 (07:30 +0000)]
[X86] Remove i128 type from FR128 regclass.
i128 isn't a legal type in our x86 implementation today. So remove this and the few patterns that used it until it becomes necessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336889
91177308-0d34-0410-b5e6-
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Sam McCall [Thu, 12 Jul 2018 07:11:28 +0000 (07:11 +0000)]
[Support] Require llvm::Error passed to formatv() to be wrapped in fmt_consume()
Summary:
Someone must be responsible for handling an Error. When formatv takes
ownership of an Error, the formatv_object destructor must take care of this.
Passing an error by value to formatv() is not considered explicit enough to mark
the error as handled (see D49013), so we require callers to use a format adapter
to confirm this intent.
Reviewers: zturner
Subscribers: llvm-commits, lhames
Differential Revision: https://reviews.llvm.org/D49170
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336888
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Stefan Granitz [Thu, 12 Jul 2018 06:41:41 +0000 (06:41 +0000)]
Fix few typos in comments (write access test commit)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336887
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Chijun Sima [Thu, 12 Jul 2018 04:08:14 +0000 (04:08 +0000)]
[Dominators] Add isUpdateLazy() method to the DomTreeUpdater
Summary:
Previously, when people need to deal with DTU with different UpdateStrategy using different actions, they need to
```
if (DTU.getUpdateStrategy() == DomTreeUpdater::UpdateStrategy::Lazy) {
...
}
if (DTU.getUpdateStrategy() == DomTreeUpdater::UpdateStrategy::Eager) {
...
}
```
After the patch, they can avoid code patterns above
```
if (DTU.isUpdateLazy()){
...
}
if (!DTU.isUpdateLazy()){
...
}
```
Reviewers: kuhar, brzycki, dmgreen
Reviewed By: kuhar
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D49056
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336886
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Craig Topper [Thu, 12 Jul 2018 03:42:41 +0000 (03:42 +0000)]
[X86] Remove patterns and ISD nodes for the old scalar FMA intrinsic lowering.
We now use llvm.fma.f32/f64 or llvm.x86.fmadd.f32/f64 intrinsics that use scalar types rather than vector types. So we don't these special ISD nodes that operate on the lowest element of a vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336883
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Chen Zheng [Thu, 12 Jul 2018 03:06:04 +0000 (03:06 +0000)]
[InstSimplify] simplify add instruction if two operands are negative
Differential Revision: https://reviews.llvm.org/D49216
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336881
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Fangrui Song [Thu, 12 Jul 2018 02:03:53 +0000 (02:03 +0000)]
[AsmParser] Fix inconsistent declaration parameter name
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336879
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Eric Christopher [Thu, 12 Jul 2018 01:53:21 +0000 (01:53 +0000)]
Temporarily revert "Recommit r328307: [IPSCCP] Use constant range information for comparisons of parameters." as it's causing miscompiles.
A testcase was provided in the original review thread.
This reverts commit r336098.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336877
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Chandler Carruth [Thu, 12 Jul 2018 01:43:21 +0000 (01:43 +0000)]
[x86] Fix another trivial bug in x86 flags copy lowering that has been
there for a long time.
The boolean tracking whether we saw a kill of the flags was supposed to
be per-block we are scanning and instead was outside that loop and never
cleared. It requires a quite contrived test case to hit this as you have
to have multiple levels of successors and interleave them with kills.
I've included such a test case here.
This is another bug found testing SLH and extracted to its own focused
patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336876
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Craig Topper [Thu, 12 Jul 2018 00:54:40 +0000 (00:54 +0000)]
[X86] Add patterns to use VMOVSS/SD zero masking for scalar f32/f64 select with zero.
These showed up in some of the upgraded FMA code. We really need to improve these test cases more, but this helps for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336875
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Chandler Carruth [Thu, 12 Jul 2018 00:52:50 +0000 (00:52 +0000)]
[x86] Fix EFLAGS copy lowering to correctly handle walking past uses in
multiple successors where some of the uses end up killing the EFLAGS
register.
There was a bug where rather than skipping to the next basic block
queued up with uses once we saw a kill, we stopped processing the blocks
entirely. =/
Test case produces completely nonsensical code w/o this tiny fix.
This was found testing Speculative Load Hardening and split out of that
work.
Differential Revision: https://reviews.llvm.org/D49211
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336874
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Craig Topper [Thu, 12 Jul 2018 00:29:56 +0000 (00:29 +0000)]
[X86] Remove and autoupgrade the scalar fma intrinsics with masking.
This converts them to what clang is now using for codegen. Unfortunately, there seem to be a few kinks to work out still. I'll try to address with follow up patches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336871
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Eric Christopher [Thu, 12 Jul 2018 00:01:51 +0000 (00:01 +0000)]
Add -allow-deprecated-dag-overlap to one of the experimental webassembly target tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336870
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Duncan P. N. Exon Smith [Wed, 11 Jul 2018 23:30:25 +0000 (23:30 +0000)]
IR: Skip -print-*-all after -print-*
This changes `-print-*` from transformation passes to analysis passes so
that `-print-after-all` and `-print-before-all` don't trigger. This
avoids some redundant output.
Patch by Son Tuan Vu!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336869
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Eli Friedman [Wed, 11 Jul 2018 23:26:35 +0000 (23:26 +0000)]
[CodeGen] Emit more precise AssertZext/AssertSext nodes.
This is marginally helpful for removing redundant extensions, and the
code is easier to read, so it seems like an all-around win. In the new
test i8-phi-ext.ll, we used to emit an AssertSext i8; now we emit an
AssertZext i2, which allows the extension of the return value to be
eliminated.
Differential Revision: https://reviews.llvm.org/D49004
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336868
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Craig Topper [Wed, 11 Jul 2018 22:35:28 +0000 (22:35 +0000)]
[LoopIdiomRecognize] Don't convert a do while loop to ctlz.
This commit suppresses turning loops like this into "(bitwidth - ctlz(input))".
unsigned foo(unsigned input) {
unsigned num = 0;
do {
++num;
input >>= 1;
} while (input != 0);
return num;
}
The loop version returns a value of 1 for both an input of 0 and an input of 1. Converting to a naive ctlz does not preserve that.
Theoretically we could do better if we checked isKnownNonZero or we could insert a select to handle the divergence. But until we have motivating cases for that, this is the easiest solution.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336864
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Craig Topper [Wed, 11 Jul 2018 22:17:26 +0000 (22:17 +0000)]
[LoopIdiomRecognize] Add a test case showing a loop we turn into ctlz that we shouldn't.
This loop executes one iteration without checking the input value. This produces a count of 1 for an input of 0 and 1. We are turning this into 32 - ctlz(n), but that returns 0 if n is 0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336862
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Tom Stellard [Wed, 11 Jul 2018 22:15:15 +0000 (22:15 +0000)]
AMDGPU/SI: Initialize InstrInfo before TargetLoweringInfo in GCNSubtarget
SITargetLowering queries SIInstrInfo in its constructor, so SIInstrInfo
must be initialized first. This fixes msan buildbot failures and was
introduced by r336851.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336861
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Alina Sbirlea [Wed, 11 Jul 2018 22:11:46 +0000 (22:11 +0000)]
[MemorySSA] Add APIs to move memory accesses between blocks, following CFG changes.
Summary:
The move APIs added in this patch will be used to update MemorySSA when CFG changes merge or split blocks, by moving memory accesses accordingly in MemorySSA's internal data structures.
[Split from D45299 for easier review]
Reviewers: george.burgess.iv
Subscribers: sanjoy, jlebar, Prazek, llvm-commits
Differential Revision: https://reviews.llvm.org/D48897
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336860
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Bill Wendling [Wed, 11 Jul 2018 21:47:55 +0000 (21:47 +0000)]
Temporarily reverting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336858
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Roman Lebedev [Wed, 11 Jul 2018 21:28:42 +0000 (21:28 +0000)]
[NFC][InstCombine] Tests for x & (-1 >> y) != x -> x u> (-1 >> y) fold
https://bugs.llvm.org/show_bug.cgi?id=38123
https://rise4fun.com/Alive/Rny
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336857
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Tom Stellard [Wed, 11 Jul 2018 21:12:03 +0000 (21:12 +0000)]
AMDGPU: Remove duplicate call to initializeSubtargetDependencies()
This was added in r336851.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336853
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