OSDN Git Service
Chad Rosier [Thu, 27 Jun 2013 19:38:13 +0000 (19:38 +0000)]
Improve the compression of the tablegen DiffLists by introducing a new sort
algorithm when assigning EnumValues to the synthesized registers.
The current algorithm, LessRecord, uses the StringRef compare_numeric
function. This function compares strings, while handling embedded numbers.
For example, the R600 backend registers are sorted as follows:
T1
T1_W
T1_X
T1_XYZW
T1_Y
T1_Z
T2
T2_W
T2_X
T2_XYZW
T2_Y
T2_Z
In this example, the 'scaling factor' is dEnum/dN = 6 because T0, T1, T2
have an EnumValue offset of 6 from one another. However, in other parts
of the register bank, the scaling factors are different:
dEnum/dN = 5:
KC0_128_W
KC0_128_X
KC0_128_XYZW
KC0_128_Y
KC0_128_Z
KC0_129_W
KC0_129_X
KC0_129_XYZW
KC0_129_Y
KC0_129_Z
The diff lists do not work correctly because different kinds of registers have
different 'scaling factors'. This new algorithm, LessRecordRegister, tries to
enforce a scaling factor of 1. For example, the registers are now sorted as
follows:
T1
T2
T3
...
T0_W
T1_W
T2_W
...
T0_X
T1_X
T2_X
...
KC0_128_W
KC0_129_W
KC0_130_W
...
For the Mips and R600 I see a 19% and 6% reduction in size, respectively. I
did see a few small regressions, but the differences were on the order of a
few bytes (e.g., AArch64 was 16 bytes). I suspect there will be even
greater wins for targets with larger register files.
Patch reviewed by Jakob.
rdar://
14006013
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185094
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Argyrios Kyrtzidis [Thu, 27 Jun 2013 17:57:40 +0000 (17:57 +0000)]
[Support/Registry.h] Include llvm/Support/Compiler.h.
Because Registry.h is using the LLVM_DELETED_FUNCTION macro.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185087
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Nadav Rotem [Thu, 27 Jun 2013 17:54:10 +0000 (17:54 +0000)]
Get rid of the unused class member.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185086
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Nadav Rotem [Thu, 27 Jun 2013 17:52:04 +0000 (17:52 +0000)]
CostModel: improve the cost model for load/store of non power-of-two types such as <3 x float>, which are popular in graphics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185085
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Tom Stellard [Thu, 27 Jun 2013 17:00:38 +0000 (17:00 +0000)]
R600: Remove alu-split.ll test
The purpose of this test was to check boundary conditions for the size
of an ALU clause. This test is very sensitive to changes to the
optimizer or scheduler, because it requires an exact number of ALU
instructions in order to remain valid. It's not good to have a test
this sensitive, because it is confusing to developers who implement
optimizations and then 'break' the test.
I'm not sure if there is a good way to test these limits using lit, but
if I can come up with replacement test that isn't as sensitive I'll add
it back to the tree.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185084
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Arnold Schwaighofer [Thu, 27 Jun 2013 15:11:55 +0000 (15:11 +0000)]
LoopVectorize: Use vectorized loop invariant gep index anchored in loop
Use vectorized instruction instead of original instruction anchored in the
original loop.
Fixes PR16452 and t2075.c of PR16455.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185081
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Serge Pavlov [Thu, 27 Jun 2013 14:35:03 +0000 (14:35 +0000)]
Use MCFillFragment for zero-initialized data.
It fixes PR16338 (ICE when compiling very large two-dimensional array).
Differential Revision: http://llvm-reviews.chandlerc.com/D1043
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185080
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Joey Gouly [Thu, 27 Jun 2013 11:49:26 +0000 (11:49 +0000)]
Add a Subtarget feature 'v8fp' to the ARM backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185073
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Benjamin Kramer [Thu, 27 Jun 2013 11:26:41 +0000 (11:26 +0000)]
Remove unused variable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185072
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Benjamin Kramer [Thu, 27 Jun 2013 11:07:42 +0000 (11:07 +0000)]
Don't cast away constness.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185071
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Richard Sandiford [Thu, 27 Jun 2013 09:49:34 +0000 (09:49 +0000)]
[SystemZ] Fix some embarrassing test typos
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185070
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Richard Sandiford [Thu, 27 Jun 2013 09:42:10 +0000 (09:42 +0000)]
[SystemZ] Allow LA and LARL to be rematerialized
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185069
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Richard Sandiford [Thu, 27 Jun 2013 09:38:48 +0000 (09:38 +0000)]
[SystemZ] Allow immediate moves to be rematerialized
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185068
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Richard Sandiford [Thu, 27 Jun 2013 09:27:40 +0000 (09:27 +0000)]
[SystemZ] Add conditional store patterns
Add pseudo conditional store instructions, so that we use:
branch foo:
store
foo:
instead of:
load
branch foo:
move
foo:
store
z196 has real 32-bit and 64-bit conditional stores, but we don't use
any z196 instructions yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185065
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Kostya Serebryany [Thu, 27 Jun 2013 08:47:12 +0000 (08:47 +0000)]
Add more owners to CODE_OWNERS.TXT (Kostya Serebryany: AddressSanitizer and ThreadSanitizer; Evgeniy Stepanov: MemorySanitizer)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185064
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Manman Ren [Thu, 27 Jun 2013 06:40:18 +0000 (06:40 +0000)]
Update testing case to make DI nodes have the correct format.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185061
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Bob Wilson [Thu, 27 Jun 2013 06:09:14 +0000 (06:09 +0000)]
Add CXXFLAGS back to the Link command.
This is essentially reverting one piece of 184793 to try to fix one of Apple's
buildbots. I will check with Eric to see if this is OK or if we need to find
some other solution.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185060
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Rafael Espindola [Thu, 27 Jun 2013 03:45:31 +0000 (03:45 +0000)]
Add a convenience createUniqueDirectory function.
There are a few valid situation where we care about the structure inside a
directory, but not about the directory itself. A simple example is for unit
testing directory traversal.
PathV1 had a function like this, add one to V2 and port existing users of the
created temp file and delete it hack to using it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185059
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Arnold Schwaighofer [Thu, 27 Jun 2013 01:01:11 +0000 (01:01 +0000)]
Fix spelling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185052
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Arnold Schwaighofer [Thu, 27 Jun 2013 00:45:41 +0000 (00:45 +0000)]
LoopVectorize: Don't store a reversed value in the vectorized value map
When we store values for reversed induction stores we must not store the
reversed value in the vectorized value map. Another instruction might use this
value.
This fixes 3 test cases of PR16455.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185051
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Michael Gottesman [Thu, 27 Jun 2013 00:42:00 +0000 (00:42 +0000)]
[APFloat] Added unittest for APFloat.divide that checks special cases, result categories, and result statuses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185050
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Michael Gottesman [Thu, 27 Jun 2013 00:25:01 +0000 (00:25 +0000)]
Added support for the Builtin attribute.
The Builtin attribute is an attribute that can be placed on function call site that signal that even though a function is declared as being a builtin,
rdar://problem/
13727199
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185049
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Nadav Rotem [Thu, 27 Jun 2013 00:14:13 +0000 (00:14 +0000)]
No need to use a Set when a vector would do.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185047
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Michael Gottesman [Thu, 27 Jun 2013 00:00:45 +0000 (00:00 +0000)]
Removed two logging printf statements from the APFloat tests... = /.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185045
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Michael Gottesman [Wed, 26 Jun 2013 23:55:26 +0000 (23:55 +0000)]
[APFloat] Added unittest for APFloat.multiply that checks special cases, result categories, and result status.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185044
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Michael Gottesman [Wed, 26 Jun 2013 23:55:23 +0000 (23:55 +0000)]
[APFloat] Added unittest for APFloat.subtract that checks special cases, result categories, and result status.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185043
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Nadav Rotem [Wed, 26 Jun 2013 23:44:45 +0000 (23:44 +0000)]
SLP: When searching for vectorization opportunities scan the blocks in post-order because we grow chains upwards.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185041
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Nadav Rotem [Wed, 26 Jun 2013 23:43:23 +0000 (23:43 +0000)]
SLP: Dont erase instructions during vectorization because it prevents the outerloops from iterating over the instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185040
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Michael Gottesman [Wed, 26 Jun 2013 23:17:31 +0000 (23:17 +0000)]
In InstCombine{AddSub,MulDivRem} convert APFloat.isFiniteNonZero() && !APFloat.isDenormal => APFloat.isNormal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185037
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Michael Gottesman [Wed, 26 Jun 2013 23:17:28 +0000 (23:17 +0000)]
[APFloat] Convert all references to fcNormal to references to isFiniteNonZero().
Currently inside APFloat fcNormal still implies the old definition of Normal
(i.e. isFiniteNonZero) instead of the proper IEEE-754R definition that the
external method isNormal() uses.
This patch prepares for the internal switch inside APFloat by converting all
references that check if a category is fcNormal directly with an indirect call
via isFiniteNonZero().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185036
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Eric Christopher [Wed, 26 Jun 2013 22:44:57 +0000 (22:44 +0000)]
Revert "Debug Info: clean up usage of Verify." as it's breaking bots.
This reverts commit r185020
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185032
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Reid Kleckner [Wed, 26 Jun 2013 22:43:37 +0000 (22:43 +0000)]
Fix a crash bug in dumping options with groups
Option groups don't have prefixes. Option dumping is basically dead
code unless there is something wrong with the option table, so this
isn't an important crasher.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185031
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Stephen Lin [Wed, 26 Jun 2013 22:27:50 +0000 (22:27 +0000)]
Clarify and doxygen-ify comments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185030
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Chad Rosier [Wed, 26 Jun 2013 22:23:32 +0000 (22:23 +0000)]
[Mips Disassembler] Have the DecodeCCRRegisterClass function use the getReg
function to lookup the proper tablegen'ed register enumeration. Previously,
it was using the encoded value directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185026
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Stephen Lin [Wed, 26 Jun 2013 21:42:14 +0000 (21:42 +0000)]
ARM: Proactively ensure that the LowerCallResult hack for 'this'-returns is not used for incompatible calling conventions.
(Currently, ARM 'this'-returns are handled in the standard calling convention case by treating R0 as preserved and doing some extra magic in LowerCallResult; this may not apply to calling conventions added in the future so this patch provides and documents an interface for indicating such)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185024
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Manman Ren [Wed, 26 Jun 2013 21:26:10 +0000 (21:26 +0000)]
Debug Info: clean up usage of Verify.
No functionality change.
It should suffice to check the type of a debug info metadata, instead of
calling Verify.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185020
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Stephen Lin [Wed, 26 Jun 2013 20:19:06 +0000 (20:19 +0000)]
Minor formatting fix to ARMBaseRegisterInfo::getCalleeSavedRegs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185016
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Rafael Espindola [Wed, 26 Jun 2013 19:33:03 +0000 (19:33 +0000)]
Rename PathV2 to just Path now that it is the only one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185015
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Akira Hatanaka [Wed, 26 Jun 2013 19:08:49 +0000 (19:08 +0000)]
[mips] Do not emit ".option pic0" if target is mips64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185012
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Akira Hatanaka [Wed, 26 Jun 2013 18:48:17 +0000 (18:48 +0000)]
[mips] Improve code generation for constant multiplication using shifts, adds and
subs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185011
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Michael Gottesman [Wed, 26 Jun 2013 17:59:36 +0000 (17:59 +0000)]
[APFloat] Removed debugging cruft that snuck in.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184974
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Nadav Rotem [Wed, 26 Jun 2013 17:59:35 +0000 (17:59 +0000)]
The SLP Vectorizer works across basic blocks. Update the docs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184973
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Rafael Espindola [Wed, 26 Jun 2013 17:28:04 +0000 (17:28 +0000)]
Use enums instead of raw octal values.
Patch by 罗勇刚(Yonggang Luo).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184971
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Nadav Rotem [Wed, 26 Jun 2013 17:16:09 +0000 (17:16 +0000)]
Erase all of the instructions that we RAUWed
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184969
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Joey Gouly [Wed, 26 Jun 2013 16:58:26 +0000 (16:58 +0000)]
Add a subtarget feature 'v8' to the ARM backend.
This allows for targeting the ARMv8 AArch32 variant.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184967
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Nadav Rotem [Wed, 26 Jun 2013 16:54:53 +0000 (16:54 +0000)]
Do not add cse-ed instructions into the visited map because we dont want to consider them as a candidate for replacement of instructions to be visited.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184966
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Tim Northover [Wed, 26 Jun 2013 16:52:40 +0000 (16:52 +0000)]
ARM: fix more cases where predication may or may not be allowed
Unfortunately this addresses two issues (by the time I'd disentangled the logic
it wasn't worth putting it back to half-broken):
+ Coprocessor instructions should all be predicable in Thumb mode.
+ BKPT should never be predicable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184965
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Tim Northover [Wed, 26 Jun 2013 16:52:32 +0000 (16:52 +0000)]
ARM: allow predicated barriers in Thumb mode
The barrier instructions are only "always-execute" in ARM mode, they can quite
happily sit inside an IT block in Thumb.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184964
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Joey Gouly [Wed, 26 Jun 2013 16:39:06 +0000 (16:39 +0000)]
Remove the 'generic' CPU from the ARM eabi attributes printer.
Make v4 the default ARM architecture attribute, to match CodeGen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184962
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Rafael Espindola [Wed, 26 Jun 2013 16:24:35 +0000 (16:24 +0000)]
PathV1 is deprecated since the 18th of Dec 2010. Remove it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184960
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Rafael Espindola [Wed, 26 Jun 2013 15:21:13 +0000 (15:21 +0000)]
Add a convenience functions that don't return if the directory existed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184955
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Rafael Espindola [Wed, 26 Jun 2013 13:54:34 +0000 (13:54 +0000)]
Remove unused includes.
llvm itself is now PathV1 clean.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184947
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Ulrich Weigand [Wed, 26 Jun 2013 13:49:53 +0000 (13:49 +0000)]
[PowerPC] Accept 17-bit signed immediates for addis
The assembler currently strictly verifies that immediates for
s16imm operands are in range (-32768 ... 32767). This matches
the behaviour of the GNU assembler, with one exception: gas
allows, as a special case, operands in an extended range
(-65536 .. 65535) for the addis instruction only (and its
extended mnemonic lis).
The main reason for this seems to be to allow using unsigned
16-bit operands for lis, e.g. like lis %r1, 0xfedc.
Since this has been supported by gas for a long time, and
assembler source code seen "in the wild" actually exploits
this feature, this patch adds equivalent support to LLVM
for compatibility reasons.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184946
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Ulrich Weigand [Wed, 26 Jun 2013 13:49:15 +0000 (13:49 +0000)]
[PowerPC] Support symbolic u16imm operands
Currently, all instructions taking s16imm operands support symbolic
operands. However, for u16imm operands, we only support actual
immediate integers. This causes the assembler to reject code like
ori %r5, %r5, symbol@l
This patch changes the u16imm operand definition to likewise
accept symbolic operands. In fact, s16imm and u16imm can
share the same encoding routine, now renamed to getImm16Encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184944
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Amaury de la Vieuville [Wed, 26 Jun 2013 13:39:07 +0000 (13:39 +0000)]
ARM: operands should be explicit when disassembled
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184943
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Venkatraman Govindaraju [Wed, 26 Jun 2013 12:40:16 +0000 (12:40 +0000)]
[Sparc]: Add memory operands for the frame references in the storeRegToStackSlot
and loadRegFromStackSlot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184935
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Elena Demikhovsky [Wed, 26 Jun 2013 12:15:53 +0000 (12:15 +0000)]
Fixed a comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184933
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NAKAMURA Takumi [Wed, 26 Jun 2013 10:56:44 +0000 (10:56 +0000)]
Suppress llvm/test/Other/can-execute.txt on msys bash.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184932
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Elena Demikhovsky [Wed, 26 Jun 2013 10:55:03 +0000 (10:55 +0000)]
Optimized integer vector multiplication operation by replacing it with shift/xor/sub when it is possible. Fixed a bug in SDIV, where the const operand is not a splat constant vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184931
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Kostya Serebryany [Wed, 26 Jun 2013 09:49:52 +0000 (09:49 +0000)]
[asan] workaround for PR16277: don't instrument AllocaInstr with alignment more than the redzone size
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184928
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Kostya Serebryany [Wed, 26 Jun 2013 09:18:17 +0000 (09:18 +0000)]
[asan] add option -asan-keep-uninstrumented-functions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184927
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Andy Gibbs [Wed, 26 Jun 2013 08:05:08 +0000 (08:05 +0000)]
Provide bootstrap support to build only llvm+clang when using cmake.
Where a source tree is complete with lld, lldb and polly, it may not be possible to use cmake to configure build scripts if the host compiler it not capable of compiling these sub-projects. This change makes it possible to first build a bootstrap clang compiler when can then be used to build a complete llvm toolchain. An example bootstrap build sequence could be as follows:
$ mkdir bootstrap
$ cd bootstrap
$ cmake -G 'Unix Makefiles'
-DCMAKE_BUILD_TYPE:STRING=Release
-DCMAKE_PREFIX_PATH:STRING=$(pwd)
-DLLVM_TARGETS_TO_BUILD:STRING=host
-DLLVM_INCLUDE_TOOLS:STRING=bootstrap-only
../source
$ make clang # build clang only for host
$ cd ..
$ export CC=$(realpath bootstrap/bin)/clang
$ export CXX=$(realpath bootstrap/bin)/clang++
$ mkdir final
$ cd final
$ cmake -G 'Unix Makefiles' ../source
$ make all check-all
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184924
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Andy Gibbs [Wed, 26 Jun 2013 07:57:53 +0000 (07:57 +0000)]
Support using "host" as a target in LLVM_TARGETS_TO_BUILD when using cmake.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184923
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Rafael Espindola [Wed, 26 Jun 2013 06:10:32 +0000 (06:10 +0000)]
Remove calls to Path in #ifdefs that don't seem to be used in any of the bots :-(
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184920
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Rafael Espindola [Wed, 26 Jun 2013 06:06:54 +0000 (06:06 +0000)]
Add a simpler version of remove_all.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184919
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Rafael Espindola [Wed, 26 Jun 2013 05:25:44 +0000 (05:25 +0000)]
Fix the build when __APPLE__ is defined.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184917
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Rafael Espindola [Wed, 26 Jun 2013 05:05:37 +0000 (05:05 +0000)]
Remove sys::GetMainExecutable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184916
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Rafael Espindola [Wed, 26 Jun 2013 05:01:35 +0000 (05:01 +0000)]
Port GetMainExecutable over to PathV2.
I will remove the V1 version as soon as I change clang in the next commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184914
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Rafael Espindola [Wed, 26 Jun 2013 04:15:55 +0000 (04:15 +0000)]
Remove PathWithStatus.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184910
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Nick Lewycky [Wed, 26 Jun 2013 00:30:18 +0000 (00:30 +0000)]
dbgs() << Instruction doesn't print a newline on the end any more. Update these
debug statements to add a missing newline. Also canonicalize to '\n' instead of
"\n"; the latter calls a function with a loop the former does not.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184897
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Adrian Prantl [Tue, 25 Jun 2013 23:42:37 +0000 (23:42 +0000)]
s/C++0x/C++11/
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184892
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Jakob Stoklund Olesen [Tue, 25 Jun 2013 23:32:10 +0000 (23:32 +0000)]
Merge isReachable into isBackedge.
Prefer using RPO.lookup() instead of RPO[] which can mutate the map.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184891
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Nadav Rotem [Tue, 25 Jun 2013 23:04:09 +0000 (23:04 +0000)]
SLPVectorizer: support slp-vectorization of PHINodes between basic blocks
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184888
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Jakob Stoklund Olesen [Tue, 25 Jun 2013 21:57:38 +0000 (21:57 +0000)]
Print block frequencies in decimal form.
This is easier to read than the internal fixed-point representation.
If anybody knows the correct algorithm for converting fixed-point
numbers to base 10, feel free to fix it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184881
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Tom Stellard [Tue, 25 Jun 2013 21:22:18 +0000 (21:22 +0000)]
R600: Use new getNamedOperandIdx function generated by TableGen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184880
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Tom Stellard [Tue, 25 Jun 2013 21:22:09 +0000 (21:22 +0000)]
TableGen: Generate a function for getting operand indices based on their defined names
This patch modifies TableGen to generate a function in
${TARGET}GenInstrInfo.inc called getNamedOperandIdx(), which can be used
to look up indices for operands based on their names.
In order to activate this feature for an instruction, you must set the
UseNamedOperandTable bit.
For example, if you have an instruction like:
def ADD : TargetInstr <(outs GPR:$dst), (ins GPR:$src0, GPR:$src1)>;
You can look up the operand indices using the new function, like this:
Target::getNamedOperandIdx(Target::ADD, Target::OpName::dst) => 0
Target::getNamedOperandIdx(Target::ADD, Target::OpName::src0) => 1
Target::getNamedOperandIdx(Target::ADD, Target::OpName::src1) => 2
The operand names are case sensitive, so $dst and $DST are considered
different operands.
This change is useful for R600 which has instructions with a large number
of operands, many of which model single bit instruction configuration
values. These configuration bits are common across most instructions,
but may have a different operand index depending on the instruction type.
It is useful to have a convenient way to look up the operand indices,
so these bits can be generically set on any instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184879
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Arnold Schwaighofer [Tue, 25 Jun 2013 19:14:09 +0000 (19:14 +0000)]
X86 cost model: Vectorizing integer division is a bad idea
radar://
14057959
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184872
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Bob Wilson [Tue, 25 Jun 2013 19:09:50 +0000 (19:09 +0000)]
Fix SROA to avoid unnecessary scalar conversions for 1-element vectors.
When a 1-element vector alloca is promoted, a store instruction can often be
rewritten without converting the value to a scalar and using an insertelement
instruction to stuff it into the new alloca. This patch just adds a check
to skip that conversion when it is unnecessary. This turns out to be really
important for some ARM Neon operations where <1 x i64> is used to get around
the fact that i64 is not a legal type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184870
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Manman Ren [Tue, 25 Jun 2013 18:49:55 +0000 (18:49 +0000)]
Remove unused code. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184866
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Bill Wendling [Tue, 25 Jun 2013 18:13:52 +0000 (18:13 +0000)]
The GCDA 402 format won't have a second checksum either.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184864
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Ulrich Weigand [Tue, 25 Jun 2013 16:49:50 +0000 (16:49 +0000)]
[PowerPC] Support @got modifier
Add VK_... values and relocation types necessary to support
the @got family of modifiers. Used by the asm parser only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184860
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Rafael Espindola [Tue, 25 Jun 2013 14:42:30 +0000 (14:42 +0000)]
Move GetEXESuffix to the one place it is used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184853
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Rafael Espindola [Tue, 25 Jun 2013 14:32:45 +0000 (14:32 +0000)]
Remove sys::PathSeparator.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184852
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Aaron Watry [Tue, 25 Jun 2013 13:55:57 +0000 (13:55 +0000)]
R600: Consolidate expansion of v2i32/v4i32 ops for EG/SI
By default, we expand these operations for both EG and SI. Move the
duplicated code into a common space for now. If the targets ever actually
implement these operations as instructions, we can override that in the relevant
target.
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184848
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Aaron Watry [Tue, 25 Jun 2013 13:55:54 +0000 (13:55 +0000)]
R600: Add v2i32 test for vselect
Note: Only adding test for evergreen, not SI yet.
When I attempted to expand vselect for SI, I got the following:
llc: /home/awatry/src/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp:522:
llvm::SDValue llvm::DAGTypeLegalizer::PromoteIntRes_SETCC(llvm::SDNode*):
Assertion `SVT.isVector() == N->getOperand(0).getValueType().isVector() &&
"Vector compare must return a vector result!"' failed.
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184847
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Aaron Watry [Tue, 25 Jun 2013 13:55:52 +0000 (13:55 +0000)]
R600/SI: Expand xor v2i32/v4i32
Add test cases for both vector sizes on SI and also add v2i32 test for EG.
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184846
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Aaron Watry [Tue, 25 Jun 2013 13:55:49 +0000 (13:55 +0000)]
R600: Add v2i32 test for setcc on evergreen
No test/expansion for SI has been added yet. Attempts to expand this
operation for SI resulted in a stacktrace in (IIRC) LegalizeIntegerTypes
which was complaining about vector comparisons being required to return
a vector type.
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184845
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Aaron Watry [Tue, 25 Jun 2013 13:55:46 +0000 (13:55 +0000)]
R600/SI: Expand urem of v2i32/v4i32 for SI
Also add lit test for both cases on SI, and v2i32 for evergreen.
Note: I followed the guidance of the v4i32 EG check... UREM produces really
complex code, so let's just check that the instruction was lowered
successfully.
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184844
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Aaron Watry [Tue, 25 Jun 2013 13:55:43 +0000 (13:55 +0000)]
R600/SI: Expand udiv v[24]i32 for SI and v2i32 for EG
Also add lit test for both cases on SI, and v2i32 for evergreen.
Note: I followed the guidance of the v4i32 EG check... UDIV produces really
complex code, so let's just check that the instruction was lowered
successfully.
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184843
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Aaron Watry [Tue, 25 Jun 2013 13:55:40 +0000 (13:55 +0000)]
R600/SI: Expand ashr of v2i32/v4i32 for SI
Also add lit test for both cases on SI, and v2i32 for evergreen.
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184842
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Aaron Watry [Tue, 25 Jun 2013 13:55:37 +0000 (13:55 +0000)]
R600/SI: Expand srl of v2i32/v4i32 for SI
Also add lit test for both cases on SI, and v2i32 for evergreen.
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184841
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Aaron Watry [Tue, 25 Jun 2013 13:55:32 +0000 (13:55 +0000)]
R600/SI: Expand shl of v2i32/v4i32 for SI
Also add lit test for both cases on SI, and v2i32 for evergreen.
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184840
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Aaron Watry [Tue, 25 Jun 2013 13:55:29 +0000 (13:55 +0000)]
R600/SI: Expand or of v2i32/v4i32 for SI
Also add lit test for both cases on SI, and v2i32 for evergreen.
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184839
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Aaron Watry [Tue, 25 Jun 2013 13:55:26 +0000 (13:55 +0000)]
R600/SI: Expand mul of v2i32/v4i32 for SI
Also add lit test for both cases on SI, and v2i32 for evergreen.
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184838
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Aaron Watry [Tue, 25 Jun 2013 13:55:23 +0000 (13:55 +0000)]
R600/SI: Expand and of v2i32/v4i32 for SI
Also add lit test for both cases on SI, and v2i32 for evergreen.
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184837
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Benjamin Kramer [Tue, 25 Jun 2013 13:34:40 +0000 (13:34 +0000)]
BlockFrequency: Bump up the entry frequency a bit.
This is a band-aid to fix the most severe regressions we're seeing from basing
spill decisions on block frequencies, until we have a better solution.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184835
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Ulrich Weigand [Tue, 25 Jun 2013 13:17:41 +0000 (13:17 +0000)]
[PowerPC] Add extended rotate/shift mnemonics
This adds all missing extended rotate/shift mnemonics to the asm parser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184834
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Ulrich Weigand [Tue, 25 Jun 2013 13:17:10 +0000 (13:17 +0000)]
[PowerPC] Add rldcr/rldic instructions
This adds pattern for the rldcr and rldic instructions (the last instruction
from the rotate/shift family that were missing). They are currently used
only by the asm parser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184833
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Ulrich Weigand [Tue, 25 Jun 2013 13:16:48 +0000 (13:16 +0000)]
[PowerPC] Add extended subtract mnemonics
This adds support for the extended subtract mnemonics to the asm parser:
subi
subis
subic
subic.
sub
sub.
subc
subc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184832
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Justin Holewinski [Tue, 25 Jun 2013 12:22:21 +0000 (12:22 +0000)]
[NVPTX] Default pointer type doesn't make sense for getParamSymbol()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184831
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