OSDN Git Service
Craig Topper [Thu, 5 Feb 2015 08:51:02 +0000 (08:51 +0000)]
[X86] Remove two feature flags that covered sets of instructions that have no patterns or intrinsics. Since we don't check feature flags in the assembler parser for any instruction sets, these flags don't provide any value. This frees up 2 of the fully utilized feature flags.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228282
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Matt Arsenault [Thu, 5 Feb 2015 06:05:13 +0000 (06:05 +0000)]
R600/SI: Fix i64 truncate to i1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228273
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Larisse Voufo [Thu, 5 Feb 2015 04:54:51 +0000 (04:54 +0000)]
Disable enumeral mismatch warning when compiling llvm with gcc.
Tested with gcc 4.9.2.
Compiling with -Werror was producing:
.../llvm/lib/Target/X86/X86ISelLowering.cpp: In function 'llvm::SDValue lowerVectorShuffleAsBitMask(llvm::SDLoc, llvm::MVT, llvm::SDValue, llvm::SDValue, llvm::ArrayRef<int>, llvm::SelectionDAG&)':
.../llvm/lib/Target/X86/X86ISelLowering.cpp:7771:40: error: enumeral mismatch in conditional expression: 'llvm::X86ISD::NodeType' vs 'llvm::ISD::NodeType' [-Werror=enum-compare]
V = DAG.getNode(VT.isFloatingPoint() ? X86ISD::FAND : ISD::AND, DL, VT, V,
^
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228271
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Matt Arsenault [Thu, 5 Feb 2015 03:35:34 +0000 (03:35 +0000)]
Add addrspacecast node to tablegen
The node is still defined oddly so that the
address spaces are not operands and not accessible
from tablegen, but as-is this can now be used to write
a ComplexPattern with an addrspacecast root node.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228270
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Matt Arsenault [Thu, 5 Feb 2015 03:30:08 +0000 (03:30 +0000)]
Add support for double / float to EndianStream
Also add new unit tests for endian::Writer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228269
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Michael Zolotukhin [Thu, 5 Feb 2015 02:34:00 +0000 (02:34 +0000)]
Implement new heuristic for complete loop unrolling.
Complete loop unrolling can make some loads constant, thus enabling a
lot of other optimizations. To catch such cases, we look for loads that
might become constants and estimate number of instructions that would be
simplified or become dead after substitution.
Example:
Suppose we have:
int a[] = {0, 1, 0};
v = 0;
for (i = 0; i < 3; i ++)
v += b[i]*a[i];
If we completely unroll the loop, we would get:
v = b[0]*a[0] + b[1]*a[1] + b[2]*a[2]
Which then will be simplified to:
v = b[0]* 0 + b[1]* 1 + b[2]* 0
And finally:
v = b[1]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228265
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Cameron Esfahani [Thu, 5 Feb 2015 02:09:33 +0000 (02:09 +0000)]
Value soft float calls as more expensive in the inliner.
Summary: When evaluating floating point instructions in the inliner, ask the TTI whether it is an expensive operation. By default, it's not an expensive operation. This keeps the default behavior the same as before. The ARM TTI has been updated to return back TCC_Expensive for targets which don't have hardware floating point.
Reviewers: chandlerc, echristo
Reviewed By: echristo
Subscribers: t.p.northover, aemerson, llvm-commits
Differential Revision: http://reviews.llvm.org/D6936
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228263
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Ahmed Bougacha [Thu, 5 Feb 2015 01:52:19 +0000 (01:52 +0000)]
[ARM] Use patterns instead of hardcoded regs in test. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228259
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Ahmed Bougacha [Thu, 5 Feb 2015 01:45:28 +0000 (01:45 +0000)]
[ARM] Make testcase more explicit. NFC.
The q8/d16 thing is silly; I'd be happy to hear about a better
way to write those tests where simple substitution isn't enough..
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228258
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Reid Kleckner [Thu, 5 Feb 2015 01:23:14 +0000 (01:23 +0000)]
Try to fix the build in MCValue.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228256
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Sean Silva [Thu, 5 Feb 2015 01:13:47 +0000 (01:13 +0000)]
Fixup.
Didn't see these calls in my release build locally when testing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228254
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Duncan P. N. Exon Smith [Thu, 5 Feb 2015 01:07:47 +0000 (01:07 +0000)]
IR: Split out getOperandAs(), NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228250
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Sean Silva [Thu, 5 Feb 2015 00:58:51 +0000 (00:58 +0000)]
[MC] Remove various unused MCAsmInfo parameters.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228244
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Duncan P. N. Exon Smith [Thu, 5 Feb 2015 00:51:35 +0000 (00:51 +0000)]
IR: Rename 'operator ==()' to 'isKeyOf()', NFC
`isKeyOf()` is a clearer name than overloading `operator==()`.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228242
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Duncan P. N. Exon Smith [Thu, 5 Feb 2015 00:17:43 +0000 (00:17 +0000)]
ADT: Add int64_t interoperability to APSInt
Add some API to `APSInt` to make it easier to compare with `int64_t`.
- `APSInt::compareValues(APSInt, APSInt)` returns 1, -1 or 0 for
greater, lesser, or equal, doing the right thing for mismatched
"has-sign" and bitwidths. This is just like `isSameValue()` (and is
now the implementation of it).
- `APSInt::get(int64_t)` gets a signed `APSInt`.
- `operator<(int64_t)`, etc., are implemented trivially via `get()`
and `compareValues()`.
- Also added `APSInt::getUnsigned(uint64_t)` to make it easier to test
`compareValues()`.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228239
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Colin LeMahieu [Thu, 5 Feb 2015 00:10:16 +0000 (00:10 +0000)]
[Hexagon] Deleting unused instructions and adding isCodeGenOnly to some defs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228238
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Colin LeMahieu [Wed, 4 Feb 2015 23:55:16 +0000 (23:55 +0000)]
[Hexagon] Updating load extend to i64 patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228237
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Kostya Serebryany [Wed, 4 Feb 2015 23:42:42 +0000 (23:42 +0000)]
[fuzzer] add flag prefer_small_during_initial_shuffle, be a bit more verbose
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228235
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Colin LeMahieu [Wed, 4 Feb 2015 23:27:48 +0000 (23:27 +0000)]
[Hexagon] Cleaning up i1 load and extension patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228232
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Colin LeMahieu [Wed, 4 Feb 2015 23:23:16 +0000 (23:23 +0000)]
[Hexagon] Simplifying more load and store patterns and using new addressing patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228231
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Reid Kleckner [Wed, 4 Feb 2015 23:17:19 +0000 (23:17 +0000)]
Remove useless call to isOSCygMing()
This used to do something when we modeled the Cygwin and MinGW
environments as distinct OSs, but now it is not needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228229
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Tom Stellard [Wed, 4 Feb 2015 23:14:18 +0000 (23:14 +0000)]
R600/SI: Enable subreg liveness by default
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228228
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Colin LeMahieu [Wed, 4 Feb 2015 23:10:21 +0000 (23:10 +0000)]
[Hexagon] Simplifying some load and store patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228227
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Duncan P. N. Exon Smith [Wed, 4 Feb 2015 22:59:18 +0000 (22:59 +0000)]
AsmParser: Split out LineField, NFC
Split out `LineField`, which restricts the legal line numbers. This
will make it easier to be consistent between different node parsers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228226
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Colin LeMahieu [Wed, 4 Feb 2015 22:54:51 +0000 (22:54 +0000)]
[Hexagon] Converting absolute-address load patterns to use AddrGP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228225
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Colin LeMahieu [Wed, 4 Feb 2015 22:40:36 +0000 (22:40 +0000)]
[Hexagon] Converting atomic store/load to use AddrGP addressing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228223
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Reid Kleckner [Wed, 4 Feb 2015 22:36:52 +0000 (22:36 +0000)]
Don't warn or note if bash is missing
We haven't needed bash on Windows to run the test suite for a long time
now.
Patch by Michael Edwards!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228221
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Colin LeMahieu [Wed, 4 Feb 2015 22:36:28 +0000 (22:36 +0000)]
[Hexagon] Simplifying some store patterns. Adding AddrGP addressing forms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228220
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Filipe Cabecinhas [Wed, 4 Feb 2015 22:33:31 +0000 (22:33 +0000)]
Handle LLVM_USE_SANITIZER=Address;Undefined (and the other way around)
Summary:
Handle LLVM_USE_SANITIZER=Address;Undefined to enable ASan and UBSan
If UBSan is compatible with more of the other sanitizers, maybe we should
deal with this in a better way where we allow combining UBSan with any of
the other sanitizers.
Reviewers: samsonov
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D7024
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228219
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Kostya Serebryany [Wed, 4 Feb 2015 22:20:09 +0000 (22:20 +0000)]
[fuzzer] add -runs=N to limit the number of runs per session. Also, make sure we do some mutations w/o cross over.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228214
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Duncan P. N. Exon Smith [Wed, 4 Feb 2015 22:13:28 +0000 (22:13 +0000)]
Fix GCC error caused by r228211
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228213
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Duncan P. N. Exon Smith [Wed, 4 Feb 2015 22:08:30 +0000 (22:08 +0000)]
IR: Reduce boilerplate in DenseMapInfo overrides, NFC
Minimize the boilerplate required for the `MDNode` subclass
`DenseMapInfo<>` overrides in `LLVMContextImpl`.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228212
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Duncan P. N. Exon Smith [Wed, 4 Feb 2015 22:05:21 +0000 (22:05 +0000)]
AsmParser: Move MDField details to source file, NFC
Move all the types of `MDField` to an anonymous namespace in the source
file. This also eliminates the duplication of `ParseMDField()`
declarations in the header for each new field type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228211
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Duncan P. N. Exon Smith [Wed, 4 Feb 2015 22:02:18 +0000 (22:02 +0000)]
AsmParser: Simplify assertion, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228209
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Duncan P. N. Exon Smith [Wed, 4 Feb 2015 22:00:59 +0000 (22:00 +0000)]
AsmParser: Remove dead code, NFC
This condition is checked in the generic `ParseMDField()`.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228208
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Duncan P. N. Exon Smith [Wed, 4 Feb 2015 21:57:52 +0000 (21:57 +0000)]
AsmParser: Simplify MDUnsignedField
We only need `uint64_t` for storage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228205
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Duncan P. N. Exon Smith [Wed, 4 Feb 2015 21:54:12 +0000 (21:54 +0000)]
IR: Initialize MDNode abbreviations en masse, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228203
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Duncan P. N. Exon Smith [Wed, 4 Feb 2015 21:46:12 +0000 (21:46 +0000)]
IR: Define MDNode uniquing sets automatically, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228200
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Kevin Enderby [Wed, 4 Feb 2015 21:38:42 +0000 (21:38 +0000)]
Add code to llvm-objdump so the -section option with -macho will dump ‘C’ string
sections with the Mach-O S_CSTRING_LITERALS section type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228198
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Rafael Espindola [Wed, 4 Feb 2015 21:27:24 +0000 (21:27 +0000)]
Don' try to make sections in comdats SHF_MERGE.
Parts of llvm were not expecting it and we wouldn't print
the entity size of the section.
Given what comdats are used for, having SHF_MERGE sections would be
just a small improvement, so just disable it for now.
Fixes pr22463.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228196
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Sean Silva [Wed, 4 Feb 2015 20:51:19 +0000 (20:51 +0000)]
[docs] Put an explicit link to InAlloca.rst
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228192
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Tom Stellard [Wed, 4 Feb 2015 20:49:52 +0000 (20:49 +0000)]
R600/SI: Expand misaligned 16-bit memory accesses
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228190
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Tom Stellard [Wed, 4 Feb 2015 20:49:51 +0000 (20:49 +0000)]
R600/SI: Make more store operations legal
v2i32, i32, trunc i32 to i16, and truc i32 to i8 stores are legal for
all address spaces. We had marked them as custom in order to lower
them for the private address space, but this is no longer necessary.
This enables lowering of misaligned stores of these types in the
DAGLegalizer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228189
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Tom Stellard [Wed, 4 Feb 2015 20:49:49 +0000 (20:49 +0000)]
R600: Don't promote i64 stores to v2i32 during DAG legalization
We take care of this during instruction selection now. This
fixes a potential infinite loop when lowering misaligned stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228188
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Tom Stellard [Wed, 4 Feb 2015 20:49:47 +0000 (20:49 +0000)]
StructurizeCFG: Remove obsolete fix for loop backedge detection
This is no longer needed now that we are using a reverse post-order
traversal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228187
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Tom Stellard [Wed, 4 Feb 2015 20:49:44 +0000 (20:49 +0000)]
StructurizeCFG: Use a reverse post-order traversal
We were previously doing a post-order traversal and operating on the
list in reverse, however this would occasionaly cause backedges for
loops to be visited before some of the other blocks in the loop.
We know use a reverse post-order traversal, which avoids this issue.
The reverse post-order traversal is not completely ideal, so we need
to manually fixup the list to ensure that inner loop backedges are
visited before outer loop backedges.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228186
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Colin LeMahieu [Wed, 4 Feb 2015 20:38:01 +0000 (20:38 +0000)]
[Hexagon] Adding selection for GlobalAddress and converting [z/i]ext load patterns to make use of them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228184
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Bill Schmidt [Wed, 4 Feb 2015 20:00:04 +0000 (20:00 +0000)]
Add missing test case from r228046
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228182
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Duncan P. N. Exon Smith [Wed, 4 Feb 2015 19:44:34 +0000 (19:44 +0000)]
Utils: Resolve cycles under distinct MDNodes
Track unresolved nodes under distinct `MDNode`s during `MapMetadata()`,
and resolve them at the end. Previously, these cycles wouldn't get
resolved.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228180
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Matthias Braun [Wed, 4 Feb 2015 19:35:16 +0000 (19:35 +0000)]
MachineCSE: Clear dead-def flag on CSE.
In case CSE reuses a previoulsy unused register the dead-def flag has to
be cleared on the def operand, as exposed by the arm64-cse.ll test.
This fixes PR22439 and the corresponding rdar://
19694987
Differential Revision: http://reviews.llvm.org/D7395
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228178
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Reid Kleckner [Wed, 4 Feb 2015 19:14:57 +0000 (19:14 +0000)]
Add range adapters predecessors() and successors() for BBs
Use them in two isolated transforms so we know they work and aren't dead
code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228173
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Kostya Serebryany [Wed, 4 Feb 2015 19:10:20 +0000 (19:10 +0000)]
[fuzzer] make multi-process execution more verbose; fix mutation to actually respect mutation depth and to never produce empty units
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228170
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Colin LeMahieu [Wed, 4 Feb 2015 19:05:32 +0000 (19:05 +0000)]
[Hexagon] Replacing some load patterns with cleaner versions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228169
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Michael Kuperstein [Wed, 4 Feb 2015 18:54:01 +0000 (18:54 +0000)]
Fixes a bug in vector load legalization that confused bits and bytes.
Differential Revision: http://reviews.llvm.org/D7400
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228168
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Ismail Donmez [Wed, 4 Feb 2015 18:46:00 +0000 (18:46 +0000)]
Revert test commit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228167
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Ismail Donmez [Wed, 4 Feb 2015 18:45:43 +0000 (18:45 +0000)]
Test commit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228166
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Juergen Ributzka [Wed, 4 Feb 2015 18:16:53 +0000 (18:16 +0000)]
Add missing include.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228161
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Colin LeMahieu [Wed, 4 Feb 2015 18:11:32 +0000 (18:11 +0000)]
[Hexagon] Adding missing isCodeGenOnly = 0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228160
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Colin LeMahieu [Wed, 4 Feb 2015 17:52:06 +0000 (17:52 +0000)]
[Hexagon] Adding encoding information for absolute-reg mode stores. Xfailing a test until constant extenders are correctly put in the same packet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228158
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Alexey Samsonov [Wed, 4 Feb 2015 17:39:48 +0000 (17:39 +0000)]
SpecialCaseList: Add support for parsing multiple input files.
Summary:
This change allows users to create SpecialCaseList objects from
multiple local files. This is needed to implement a proper support
for -fsanitize-blacklist flag (allow users to specify multiple blacklists,
in addition to default blacklist, see PR22431).
DFSan can also benefit from this change, as DFSan instrumentation pass now
accepts ABI-lists both from -fsanitize-blacklist= and -mllvm -dfsan-abilist flags.
Go bindings are fixed accordingly.
Test Plan: regression test suite
Reviewers: pcc
Subscribers: llvm-commits, axw, kcc
Differential Revision: http://reviews.llvm.org/D7367
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228155
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Colin LeMahieu [Wed, 4 Feb 2015 17:24:04 +0000 (17:24 +0000)]
[Hexagon] Adding encoding information for absolute-set stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228154
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Colin LeMahieu [Wed, 4 Feb 2015 16:56:46 +0000 (16:56 +0000)]
[Hexagon] Adding encoding bits for indirect long load instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228152
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Bradley Smith [Wed, 4 Feb 2015 16:23:24 +0000 (16:23 +0000)]
[ARM] Fix subtarget feature set truncation when using .cpu directive
This is a bug that was caused due to storing the feature bitset in a 32-bit
variable when it is a 64-bit mask, discarding the top half of the feature set.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228151
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Zoran Jovanovic [Wed, 4 Feb 2015 15:43:17 +0000 (15:43 +0000)]
[mips][microMIPS] Implement CodeGen support for SW16 and LW16 instructions
Differential Revision: http://reviews.llvm.org/D6581
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228149
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Daniel Sanders [Wed, 4 Feb 2015 15:18:11 +0000 (15:18 +0000)]
[mips] Make MipsSubtarget::hasMips*() functions consistent. NFC.
Reviewers: vmedic
Reviewed By: vmedic
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D7377
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228147
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Daniel Sanders [Wed, 4 Feb 2015 14:48:39 +0000 (14:48 +0000)]
[mips] Remove unused check prefix from tests. NFC.
Reviewers: vmedic
Reviewed By: vmedic
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D7376
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228145
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Aaron Ballman [Wed, 4 Feb 2015 14:01:08 +0000 (14:01 +0000)]
Fixing a -Wsign-compare warning; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228142
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Renato Golin [Wed, 4 Feb 2015 13:31:29 +0000 (13:31 +0000)]
Adding support to LLVM for targeting Cortex-A72
Currently, Cortex-A72 is modelled as an Cortex-A57 except the fp
load balancing pass isn't enabled for Cortex-A72 as it's not
profitable to have it enabled for this core.
Patch by Ranjeet Singh.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228140
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Rafael Espindola [Wed, 4 Feb 2015 13:30:28 +0000 (13:30 +0000)]
Fix warning: "function declaration isn’t a prototype"
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228139
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Justin Bogner [Wed, 4 Feb 2015 11:19:16 +0000 (11:19 +0000)]
InstrProf: std::to_string needs to #include <string>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228136
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Chandler Carruth [Wed, 4 Feb 2015 10:58:53 +0000 (10:58 +0000)]
[x86] Give movss and movsd execution domains in the x86 backend.
This associates movss and movsd with the packed single and packed double
execution domains (resp.). While this is largely cosmetic, as we now
don't have weird ping-pong-ing between single and double precision, it
is also useful because it avoids the domain fixing algorithm from seeing
domain breaks that don't actually exist. It will also be much more
important if we have an execution domain default other than packed
single, as that would cause us to mix movss and movsd with integer
vector code on a regular basis, a very bad mixture.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228135
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Chandler Carruth [Wed, 4 Feb 2015 10:47:34 +0000 (10:47 +0000)]
[x86] Remove a low-value test that was just checking how we cleared
a register. We have lots of tests covering this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228133
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Chandler Carruth [Wed, 4 Feb 2015 10:46:53 +0000 (10:46 +0000)]
[x86] Mechanically update a bunch of tests' check lines using the latest
version of the script.
Changes include:
- Using the VEX prefix
- Skipping more detail when we have useful shuffle comments to match
- Matching more shuffle comments that have been added to the printer
(yay!)
- Matching the destination registers of some AVX instructions
- Stripping trailing whitespace that crept in
- Fixing indentation issues
Nothing interesting going on here. I'm just trying really hard to ensure
these changes don't show up in the diffs with actual changes to the
backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228132
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Chandler Carruth [Wed, 4 Feb 2015 10:46:48 +0000 (10:46 +0000)]
[x86] Teach the test update script to strip trailing whitespace.
This is done in a bit of a strange way to use a multiline RE instead of
looping over the lines. Suggestions welcome here for a more pythonic way
of doing this as long as its reasonably fast.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228131
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Renato Golin [Wed, 4 Feb 2015 10:11:59 +0000 (10:11 +0000)]
Reverting VLD1/VST1 base-updating/post-incrementing combining
This reverts patches 223862, 224198, 224203, and 224754, which were all
related to the vector load/store combining and were reverted/reaplied
a few times due to the same alignment problems we're seeing now.
Further tests, mainly self-hosting Clang, will be needed to reapply this
patch in the future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228129
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Chandler Carruth [Wed, 4 Feb 2015 09:18:27 +0000 (09:18 +0000)]
[x86] Include the destination register in the check-lines for AVX
instructions.
No actual change here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228127
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Chandler Carruth [Wed, 4 Feb 2015 09:15:46 +0000 (09:15 +0000)]
[x86] Add some tests I missed in the prior commit to cover blends with
zero for v8i16 as well.
These exhibit the same domain badness, but also exhibit other weaknesses
in our blend lowering. More fixes to come.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228126
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Chandler Carruth [Wed, 4 Feb 2015 09:06:05 +0000 (09:06 +0000)]
[x86] Start to introduce bit-masking based blend lowering.
This is the simplest form of bit-math based blending which only fires
when we are blending with zero and is relatively profitable. I've only
enabled this path on very specific lowering strategies. I'm planning to
widen its applicability in subsequent patches, but so far you'll notice
that even though we get fewer shufps instructions, we *still* do the bit
math in the FP execution port. I'm looking into why this is still
happening.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228124
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Chandler Carruth [Wed, 4 Feb 2015 09:06:01 +0000 (09:06 +0000)]
[x86] Add missing patterns for andps, orps, xorps, and andnps.
Specifically, the existing patterns were scalar-only. These cover the
packed vector bitwise operations when specifically requested with pseudo
instructions. This is particularly important in SSE1 where we can't
actually emit a logical operation on a v2i64 as that isn't a legal type.
This will be tested in subsequent patches which form the floating point
and patterns in more places.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228123
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Chandler Carruth [Wed, 4 Feb 2015 09:05:58 +0000 (09:05 +0000)]
[x86] Add tests for blends-with-zero on 4-element vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228122
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Bill Schmidt [Wed, 4 Feb 2015 06:14:38 +0000 (06:14 +0000)]
Replace tabs with spaces from r228116. Oops.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228117
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Bill Schmidt [Wed, 4 Feb 2015 05:51:56 +0000 (05:51 +0000)]
[PowerPC] Handle 32-bit targets properly in PPCTLSDynamicCall.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228116
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Philip Reames [Wed, 4 Feb 2015 05:11:20 +0000 (05:11 +0000)]
Fix a warning in non-asserts builds
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228114
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Frederic Riss [Wed, 4 Feb 2015 03:10:03 +0000 (03:10 +0000)]
Fix some unnoticed/unwanted behavior change from r222319.
The ARM assembler allows register alias redefinitions as long as it
targets the same register. r222319 broke that. In the AArch64 case
it would just produce a new warning, but in the ARM case it would
error out on previously accepted assembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228109
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Kostya Serebryany [Wed, 4 Feb 2015 01:22:57 +0000 (01:22 +0000)]
[fuzzer]: fix exit code, add more diagnostics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228103
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Kostya Serebryany [Wed, 4 Feb 2015 01:21:45 +0000 (01:21 +0000)]
[sanitizer] add another workaround for PR 17409: when over a threshold emit coverage instrumentation as calls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228102
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Kevin Enderby [Wed, 4 Feb 2015 01:01:38 +0000 (01:01 +0000)]
Add code to llvm-objdump so the -section option with -macho will disassemble sections
that have attributes indicating they contain instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228101
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Chandler Carruth [Wed, 4 Feb 2015 00:58:42 +0000 (00:58 +0000)]
[x86] Refresh the checks of a number of tests using
update_llc_test_checks.py.
The exact format of the checks has changed over time. This includes
different indenting rules, new shuffle comments that have been added,
and more operand hiding behind regular expressions.
No functional change to the tests are expected here, but this will make
subsequent patches have a clean diff as they change shuffle lowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228097
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Chandler Carruth [Wed, 4 Feb 2015 00:58:40 +0000 (00:58 +0000)]
[x86] Switch to using the long '--check-prefix' form which the
update_llc_test_checks.py script uses, and refresh the checks in this
test.
No functionality changed here, just bringing this test up to work with
automated updates using the python script.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228096
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Chandler Carruth [Wed, 4 Feb 2015 00:58:37 +0000 (00:58 +0000)]
[x86] Port this test to use utils/update_llc_test_checks.py.
This will make it easy to update as I change some parts of the X86
backend, makes it more clear what instruction differences are
introduced, and I find it makes it a bit easier to read as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228095
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Peter Collingbourne [Wed, 4 Feb 2015 00:42:45 +0000 (00:42 +0000)]
Misc documentation/comment fixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228093
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Philip Reames [Wed, 4 Feb 2015 00:39:57 +0000 (00:39 +0000)]
Clang format of a file introduced in 228090 (NFC)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228091
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Philip Reames [Wed, 4 Feb 2015 00:37:33 +0000 (00:37 +0000)]
Add a pass for inserting safepoints into (nearly) arbitrary IR
This pass is responsible for figuring out where to place call safepoints and safepoint polls. It doesn't actually make the relocations explicit; that's the job of the RewriteStatepointsForGC pass (http://reviews.llvm.org/D6975).
Note that this code is not yet finalized. Its moving in tree for incremental development, but further cleanup is needed and will happen over the next few days. It is not yet part of the standard pass order.
Planned changes in the near future:
- I plan on restructuring the statepoint rewrite to use the functions add to the IRBuilder a while back.
- In the current pass, the function "gc.safepoint_poll" is treated specially but is not an intrinsic. I plan to make identifying the poll function a property of the GCStrategy at some point in the near future.
- As follow on patches, I will be separating a collection of test cases we have out of tree and submitting them upstream.
- It's not explicit in the code, but these two patches are introducing a new state for a statepoint which looks a lot like a patchpoint. There's no a transient form which doesn't yet have the relocations explicitly represented, but does prevent reordering of memory operations. Once this is in, I need to update actually make this explicit by reserving the 'unused' argument of the statepoint as a flag, updating the docs, and making the code explicitly check for such a thing. This wasn't really planned, but once I split the two passes - which was done for other reasons - the intermediate state fell out. Just reminds us once again that we need to merge statepoints and patchpoints at some point in the not that distant future.
Future directions planned:
- Identifying more cases where a backedge safepoint isn't required to ensure timely execution of a safepoint poll.
- Tweaking the insertion process to generate easier to optimize IR. (For example, investigating making SplitBackedge) the default.
- Adding opt-in flags for a GCStrategy to use this pass. Once done, add this pass to the actual pass ordering.
Differential Revision: http://reviews.llvm.org/D6981
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228090
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Sanjay Patel [Wed, 4 Feb 2015 00:24:06 +0000 (00:24 +0000)]
improved CHECK
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228086
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Galina Kistanova [Wed, 4 Feb 2015 00:20:52 +0000 (00:20 +0000)]
Added missing header for the explicit dependency on MDNode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228085
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Justin Bogner [Wed, 4 Feb 2015 00:15:12 +0000 (00:15 +0000)]
InstrProf: Add some unit tests for CoverageMapping
The llvm-level tests for coverage mapping need a binary input file,
which means they're hard to understand, hard to update, and it's
difficult to add new ones. By adding some unit tests that build up the
coverage data structures in C++, we can write more meaningful and
targeted tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228084
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Justin Bogner [Wed, 4 Feb 2015 00:12:18 +0000 (00:12 +0000)]
InstrProf: Use a stable sort when reading coverage regions
Keeping regions that start at the same location in insertion order
makes this logic easier to test / more deterministic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228083
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Colin LeMahieu [Wed, 4 Feb 2015 00:09:23 +0000 (00:09 +0000)]
[Hexagon] Revert change to isCodeGenOnly = 1 in r228080
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228082
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Colin LeMahieu [Wed, 4 Feb 2015 00:07:26 +0000 (00:07 +0000)]
[Hexagon] Changing some isCodeGenOnly to isAsmParserOnly since we want them to asm parse but not cause decode conflicts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228080
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Owen Anderson [Wed, 4 Feb 2015 00:02:59 +0000 (00:02 +0000)]
Remove a gross usage of environment variables in MachineVerifier, replacing it with support for setting the -verify-machineinstrs flag via an environment variable in LIT.
This preserves the handy functionality of force-enabling the MachineVerifier, without the need to embed usage of environment variables in LLVM client applications.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228079
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