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Nico Weber [Mon, 2 Apr 2018 17:17:29 +0000 (17:17 +0000)]
Remove HAVE_DIRENT_H.
The autoconf manual: "This macro is obsolescent, as all current systems with
directory libraries have <dirent.h>. New programs need not use this macro."
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328989
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Dmitry Preobrazhensky [Mon, 2 Apr 2018 17:09:20 +0000 (17:09 +0000)]
[AMDGPU][MC][GFX9] Added instructions v_cvt_norm_*16_f16, v_sat_pk_u8_i16
See bug 36847: https://bugs.llvm.org/show_bug.cgi?id=36847
Differential Revision: https://reviews.llvm.org/D45097
Reviewers: artem.tamazov, arsenm, timcorringham
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328988
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Gor Nishanov [Mon, 2 Apr 2018 16:55:12 +0000 (16:55 +0000)]
[coroutines] Add support for llvm.coro.noop intrinsics
Summary:
A recent addition to Coroutines TS (https://wg21.link/p0913) adds a pre-defined coroutine noop_coroutine that does nothing.
To implement this feature, we implemented an llvm.coro.noop intrinsic that returns a coroutine handle to a coroutine that does nothing when resumed or destroyed.
Reviewers: EricWF, modocache, rnk, lewissbaker
Reviewed By: modocache
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D45114
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328986
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Dmitry Preobrazhensky [Mon, 2 Apr 2018 16:10:25 +0000 (16:10 +0000)]
[AMDGPU][MC][GFX9] Added s_atomic_* and s_buffer_atomic_* instructions
Fixed a bug which caused Tablegen crash.
See bug 36837: https://bugs.llvm.org/show_bug.cgi?id=36837
Differential Revision: https://reviews.llvm.org/D45085
Reviewers: artem.tamazov, arsenm, timcorringham
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328983
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Krzysztof Parzyszek [Mon, 2 Apr 2018 15:06:55 +0000 (15:06 +0000)]
[Hexagon] Clean up some code in HexagonAsmPrinter, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328981
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Alexey Bataev [Mon, 2 Apr 2018 14:51:37 +0000 (14:51 +0000)]
[SLP] Fix PR36481: vectorize reassociated instructions.
Summary:
If the load/extractelement/extractvalue instructions are not originally
consecutive, the SLP vectorizer is unable to vectorize them. Patch
allows reordering of such instructions.
Reviewers: RKSimon, spatel, hfinkel, mkuper, Ayal, ashahid
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D43776
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328980
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Nico Weber [Mon, 2 Apr 2018 14:36:34 +0000 (14:36 +0000)]
Remove stro(u?)ll() config checks. Those were needed pre-MSVC2013, but we require 2015 nowadays.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328979
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Nico Weber [Mon, 2 Apr 2018 14:20:23 +0000 (14:20 +0000)]
Revert r328975, it makes TableGen assert on the bots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328978
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Nico Weber [Mon, 2 Apr 2018 14:18:13 +0000 (14:18 +0000)]
Remove HAVE_WRITEV that's unused after r255837.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328977
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Nico Weber [Mon, 2 Apr 2018 13:55:56 +0000 (13:55 +0000)]
More fixes after r328970.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328976
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Dmitry Preobrazhensky [Mon, 2 Apr 2018 13:52:23 +0000 (13:52 +0000)]
[AMDGPU][MC][GFX9] Added s_atomic_* and s_buffer_atomic_* instructions
See bug 36837: https://bugs.llvm.org/show_bug.cgi?id=36837
Differential Revision: https://reviews.llvm.org/D45085
Reviewers: artem.tamazov, arsenm, timcorringham
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328975
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Nico Weber [Mon, 2 Apr 2018 13:49:35 +0000 (13:49 +0000)]
Attempt to heal bots after r328970.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328974
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Lama Saba [Mon, 2 Apr 2018 13:48:28 +0000 (13:48 +0000)]
[X86] Reduce Store Forward Block issues in HW - Recommit after fixing Bug 36346
If a load follows a store and reloads data that the store has written to memory, Intel microarchitectures can in many cases forward the data directly from the store to the load, This "store forwarding" saves cycles by enabling the load to directly obtain the data instead of accessing the data from cache or memory.
A "store forward block" occurs in cases that a store cannot be forwarded to the load. The most typical case of store forward block on Intel Core microarchiticutre that a small store cannot be forwarded to a large load.
The estimated penalty for a store forward block is ~13 cycles.
This pass tries to recognize and handle cases where "store forward block" is created by the compiler when lowering memcpy calls to a sequence
of a load and a store.
The pass currently only handles cases where memcpy is lowered to XMM/YMM registers, it tries to break the memcpy into smaller copies.
breaking the memcpy should be possible since there is no atomicity guarantee for loads and stores to XMM/YMM.
Differential revision: https://reviews.llvm.org/D41330
Change-Id: Ib48836ccdf6005989f7d4466fa2035b7b04415d9
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328973
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Andrea Di Biagio [Mon, 2 Apr 2018 13:46:49 +0000 (13:46 +0000)]
[llvm-mca] Do not assume that implicit reads cannot be associated with ReadAdvance entries.
Before, the instruction builder incorrectly assumed that only explicit reads
could have been associated with ReadAdvance entries.
This patch fixes the issue and adds a test to verify it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328972
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Nico Weber [Mon, 2 Apr 2018 13:45:39 +0000 (13:45 +0000)]
Attempt to fix papertrail-warnings.test on Windows bots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328971
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Nico Weber [Mon, 2 Apr 2018 13:22:26 +0000 (13:22 +0000)]
Assume existence of inttypes.h and stdint.h in DataTypes.h.
These should exist in all toolchains LLVM supports nowadays.
Enables making DataTypes.h a regular header instead of a .h.cmake file and
allows deleting a bunch of cmake goop (which should also speed up cmake
configure time a bit).
All the code this removes is 9+ years old.
https://reviews.llvm.org/D45155
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328970
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Hiroshi Inoue [Mon, 2 Apr 2018 12:18:21 +0000 (12:18 +0000)]
[PowerPC] fix assertion failure due to missing instruction in P9InstrResources.td
This patch adds L(D|W|H|B)XTLS instructions introduced by https://reviews.llvm.org/rL327635 in P9InstrResources.td.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328969
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Jonas Devlieghere [Mon, 2 Apr 2018 10:40:43 +0000 (10:40 +0000)]
[dsymutil] Upstream emitting of papertrail warnings.
When running dsymutil as part of your build system, it can be desirable
for warnings to be part of the end product, rather than just being
emitted to the output stream. This patch upstreams that functionality.
Differential revision: https://reviews.llvm.org/D44639
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328965
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Simon Pilgrim [Mon, 2 Apr 2018 10:34:39 +0000 (10:34 +0000)]
Wdocumentation fix. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328964
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Simon Pilgrim [Mon, 2 Apr 2018 10:21:51 +0000 (10:21 +0000)]
Wdocumentation fixes. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328963
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Craig Topper [Mon, 2 Apr 2018 06:34:16 +0000 (06:34 +0000)]
[X86][Silvermont] Use correct latency and throughput information for divide and square root in the scheduler model.
Data taken from Table 16-17 in the Intel Optimization Manual.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328962
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Craig Topper [Mon, 2 Apr 2018 05:54:34 +0000 (05:54 +0000)]
[X86][SkylakeServer] Correct throughput for 512-bit sqrt and divide.
Data taken from the AVX512_SKX_PortAssign spreadsheet at http://instlatx64.atw.hu/
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328961
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Craig Topper [Mon, 2 Apr 2018 05:33:28 +0000 (05:33 +0000)]
[X86] Correct the throughput for divide instructions in Sandy Bridge/Haswell/Broadwell/Skylake scheduler models.
Fixes most of PR36898. Still need to fix the 512-bit instructions, but Agner's tables don't have those.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328960
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Craig Topper [Mon, 2 Apr 2018 03:15:02 +0000 (03:15 +0000)]
[X86] Fix the SchedRW for AVX512 shift instructions.
It was being inadvertently defaulted to an FADD scheduler class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328959
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Craig Topper [Mon, 2 Apr 2018 02:44:55 +0000 (02:44 +0000)]
[X86] Give the AVX512 VEXTRACT instructions the same SchedRWs as the SSE/AVX versions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328958
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Nico Weber [Mon, 2 Apr 2018 01:46:08 +0000 (01:46 +0000)]
Remove a few unreferenced config.h defines.
Found by looking through the output of
for f in $(grep -o '\bHAVE_[A-Z0-9_]*\b' llvm/cmake/config-ix.cmake); do
echo $f $(git grep $f '*' | wc -l);
done
in the monorepo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328957
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Craig Topper [Mon, 2 Apr 2018 01:12:34 +0000 (01:12 +0000)]
[X86] Add an itinerary to BTR64rr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328956
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Craig Topper [Mon, 2 Apr 2018 01:12:32 +0000 (01:12 +0000)]
[X86] Make sure all the classes declare in the Haswell scheduler model are prefixed with HW.
The tablegen files all share a namespace so we shouldn't use a generic names in a specific scheduler model.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328955
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Craig Topper [Mon, 2 Apr 2018 00:48:11 +0000 (00:48 +0000)]
[X86] Give VINSERTPS the same intinerary as INSERTPS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328954
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Harlan Haskins [Mon, 2 Apr 2018 00:17:40 +0000 (00:17 +0000)]
Add C API bindings for DIBuilder 'Type' APIs
This patch adds a set of unstable C API bindings to the DIBuilder interface for
creating structure, function, and aggregate types.
This patch also removes the existing implementations of these functions from
the Go bindings and updates the Go API to fit the new C APIs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328953
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Craig Topper [Sun, 1 Apr 2018 23:58:50 +0000 (23:58 +0000)]
[X86] Cleanup ADCX/ADOX instruction definitions.
Give them both the same itineraries. Add hasSideEffects = 0 to ADOX since they don't have patterns. Rename source operands to $src1 and $src2 instead of $src0 and $src. Add ReadAfterLd to the memory form SchedRW.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328952
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Petr Hosek [Sun, 1 Apr 2018 23:44:04 +0000 (23:44 +0000)]
[AArch64] Reserve x18 register on Fuchsia
This register is reserved as a platform register on Fuchsia.
Differential Revision: https://reviews.llvm.org/D45105
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328950
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Craig Topper [Sun, 1 Apr 2018 22:16:52 +0000 (22:16 +0000)]
[DebugCounter] Make -debug-counter cl::Hidden.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328948
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Craig Topper [Sun, 1 Apr 2018 21:54:26 +0000 (21:54 +0000)]
[LegacyPassManager] Make 'print-module-scope' cl::Hidden like the rest of the printing options.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328947
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Craig Topper [Sun, 1 Apr 2018 21:54:24 +0000 (21:54 +0000)]
[X86] Give ADC8/16/32/64mi the same scheduling information as ADC8/16/32/64mr and SBB8/16/32/64mi.
It doesn't make a lot of sense that it would be different.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328946
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Chandler Carruth [Sun, 1 Apr 2018 21:53:18 +0000 (21:53 +0000)]
[x86] Correct the operand structure of the ADOX instruction.
This also moves to define it in the same way as ADCX which seems to use
constraints a bit better.
This is pulled out of the review for reducing the use of popf for
restoring EFLAGS, but is independent. There are still more problems with
our definitions for these instructions that Craig is going to look at
but this is at least less broken and he can start from this to improve
them more fully.
Thanks to Craig for the review here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328945
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Chandler Carruth [Sun, 1 Apr 2018 21:47:55 +0000 (21:47 +0000)]
[x86] Expose more of the condition conversion routines in the public API
for X86's instruction information. I've now got a second patch under
review that needs these same APIs. This bit is nicely orthogonal and
obvious, so landing it. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328944
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Mandeep Singh Grang [Sun, 1 Apr 2018 21:24:53 +0000 (21:24 +0000)]
[tools] Change std::sort to llvm::sort in response to r327219
Summary:
r327219 added wrappers to std::sort which randomly shuffle the container before sorting.
This will help in uncovering non-determinism caused due to undefined sorting
order of objects having the same key.
To make use of that infrastructure we need to invoke llvm::sort instead of std::sort.
Note: This patch is one of a series of patches to replace *all* std::sort to llvm::sort.
Refer the comments section in D44363 for a list of all the required patches.
Reviewers: JDevlieghere, zturner, echristo, dberris, friss
Reviewed By: echristo
Subscribers: gbedwell, llvm-commits
Differential Revision: https://reviews.llvm.org/D45141
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328943
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Mandeep Singh Grang [Sun, 1 Apr 2018 18:39:50 +0000 (18:39 +0000)]
[include] Change std::sort to llvm::sort in response to r327219
Summary:
r327219 added wrappers to std::sort which randomly shuffle the container before sorting.
This will help in uncovering non-determinism caused due to undefined sorting
order of objects having the same key.
To make use of that infrastructure we need to invoke llvm::sort instead of std::sort.
Note: This patch is one of a series of patches to replace *all* std::sort to llvm::sort.
Refer the comments section in D44363 for a list of all the required patches.
Reviewers: echristo, zturner, mzolotukhin, lhames
Reviewed By: echristo
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D45135
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328940
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Nicolai Haehnle [Sun, 1 Apr 2018 17:09:14 +0000 (17:09 +0000)]
AMDGPU: Make isIntrinsicSourceOfDivergence table-driven
Summary:
This is in preparation for the new dimension-aware image intrinsics,
which I'd rather not have to list here by hand.
Change-Id: Iaa16e3a635a11283918ce0d9e1e618591b0bf6fa
Reviewers: arsenm, rampitec, b-sumner
Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, llvm-commits, t-tye
Differential Revision: https://reviews.llvm.org/D44938
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328939
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Nicolai Haehnle [Sun, 1 Apr 2018 17:09:07 +0000 (17:09 +0000)]
AMDGPU: Make getTgtMemIntrinsic table-driven for resource-based intrinsics
Summary:
Avoids having to list all intrinsics manually.
This is in preparation for the new dimension-aware image intrinsics,
which I'd rather not have to list here by hand.
Change-Id: If7ced04998397ef68c4cb8f7de66b5050fb767e5
Reviewers: arsenm, rampitec, b-sumner
Subscribers: kzhuravl, wdng, mgorny, yaxunl, dstuttard, tpr, llvm-commits, t-tye
Differential Revision: https://reviews.llvm.org/D44937
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328938
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Nicolai Haehnle [Sun, 1 Apr 2018 17:08:58 +0000 (17:08 +0000)]
TableGen: Support Intrinsic values in SearchableTable
Summary:
We will use this in the AMDGPU backend in a subsequent patch
in the stack to lookup target-specific per-intrinsic information.
The generic CodeGenIntrinsic machinery is used to ensure that,
even though we don't calculate actual enum values here, we do
get the intrinsics in the right order for the binary search
index.
Change-Id: If61cd5587963a4c5a1cc53df1e59c5e4dec1f9dc
Reviewers: arsenm, rampitec, b-sumner
Subscribers: wdng, tpr, llvm-commits
Differential Revision: https://reviews.llvm.org/D44935
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328937
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Nicolai Haehnle [Sun, 1 Apr 2018 17:08:49 +0000 (17:08 +0000)]
TableGen: More helpful error messages
Summary: Change-Id: I3c23f6f6597912423762780cd8c5315870412bbe
Reviewers: arsenm, rampitec, b-sumner
Subscribers: wdng, llvm-commits
Differential Revision: https://reviews.llvm.org/D44936
Change-Id: Ie62614a3e2d7774f46e4034478b28f57100a2c92
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328936
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Mandeep Singh Grang [Sun, 1 Apr 2018 16:18:49 +0000 (16:18 +0000)]
[DebugInfo] Change std::sort to llvm::sort in response to r327219
Summary:
r327219 added wrappers to std::sort which randomly shuffle the container before sorting.
This will help in uncovering non-determinism caused due to undefined sorting
order of objects having the same key.
To make use of that infrastructure we need to invoke llvm::sort instead of std::sort.
Note: This patch is one of a series of patches to replace *all* std::sort to llvm::sort.
Refer the comments section in D44363 for a list of all the required patches.
Reviewers: echristo, zturner, samsonov
Reviewed By: echristo
Subscribers: JDevlieghere, llvm-commits
Differential Revision: https://reviews.llvm.org/D45134
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328935
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Teresa Johnson [Sun, 1 Apr 2018 15:54:40 +0000 (15:54 +0000)]
[ThinLTO] Add an import cutoff for debugging/triaging
Summary:
Adds -import-cutoff=N which will stop importing during the thin link
after N imports. Default is -1 (no limit).
Reviewers: wmi
Subscribers: inglorion, llvm-commits
Differential Revision: https://reviews.llvm.org/D45127
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328934
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David Green [Sun, 1 Apr 2018 12:48:24 +0000 (12:48 +0000)]
[LoopRotate] Rotate loops with loop exiting latches
If a loop has a loop exiting latch, it can be profitable
to rotate the loop if it leads to the simplification of
a phi node. Perform rotation in these cases even if loop
rotate itself didnt simplify the loop to get there.
Differential Revision: https://reviews.llvm.org/D44199
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328933
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Craig Topper [Sun, 1 Apr 2018 06:29:32 +0000 (06:29 +0000)]
[X86] Don't check for folding into a store when deciding if we can promote an i16 mul.
There's no RMW mul operation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328931
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Craig Topper [Sun, 1 Apr 2018 06:29:28 +0000 (06:29 +0000)]
[X86] Check if the load and store are to the same pointer before preventing i16 RMW shifts and subtracts from being promoted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328930
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Craig Topper [Sun, 1 Apr 2018 06:29:27 +0000 (06:29 +0000)]
[X86] Add test case to show failure to promote i16 subtract when the LHS is a load and the result is stored to a different address.
We mistakenly believe we might be able to fold this as a RMW operation, but that doesn't end up happening.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328929
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Craig Topper [Sun, 1 Apr 2018 06:29:25 +0000 (06:29 +0000)]
[X86] Allow i16 subtracts to be promoted if the load is on the LHS and its not being stored.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328928
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Craig Topper [Sun, 1 Apr 2018 06:29:23 +0000 (06:29 +0000)]
[X86] Add test case to show failure to promote i16 subtract because we mistakenly believe the load can be folded. NFC
The left hand side of the subtract is a load, but we cna't fold those unless we also have a store.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328927
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Craig Topper [Sun, 1 Apr 2018 06:29:21 +0000 (06:29 +0000)]
[X86] Remove unneeded temporary variable. NFC
This Promote flag was alwasys set to true except in the default case. But in the default case we don't need to set PVT and can just return false.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328926
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Mandeep Singh Grang [Sun, 1 Apr 2018 01:46:51 +0000 (01:46 +0000)]
[Analysis] Change std::sort to llvm::sort in response to r327219
Summary:
r327219 added wrappers to std::sort which randomly shuffle the container before sorting.
This will help in uncovering non-determinism caused due to undefined sorting
order of objects having the same key.
To make use of that infrastructure we need to invoke llvm::sort instead of std::sort.
Note: This patch is one of a series of patches to replace *all* std::sort to llvm::sort.
Refer D44363 for a list of all the required patches.
Reviewers: sanjoy, dexonsmith, hfinkel, RKSimon
Reviewed By: dexonsmith
Subscribers: david2050, llvm-commits
Differential Revision: https://reviews.llvm.org/D44944
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328925
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Sanjay Patel [Sat, 31 Mar 2018 17:55:44 +0000 (17:55 +0000)]
[DAGCombine] (float)((int) f) --> ftrunc (PR36617)
fptosi / fptoui round towards zero, and that's the same behavior as ISD::FTRUNC,
so replace a pair of casts with the equivalent node. We don't have to account for
special cases (NaN, INF) because out-of-range casts are undefined.
Differential Revision: https://reviews.llvm.org/D44909
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328921
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Lang Hames [Sat, 31 Mar 2018 16:01:01 +0000 (16:01 +0000)]
[llvm-rtdyld] Fix the InputFileList cl::opt description: it accepts multiple
input files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328920
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Simon Pilgrim [Sat, 31 Mar 2018 09:15:54 +0000 (09:15 +0000)]
[X86][Btver2] Add MMX_PSHUFB to the JWritePSHUFB InstRW entries
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328918
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Simon Pilgrim [Sat, 31 Mar 2018 09:14:14 +0000 (09:14 +0000)]
Fix trailing whitespace. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328917
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Benjamin Kramer [Sat, 31 Mar 2018 07:41:25 +0000 (07:41 +0000)]
Unbreak the build of the go bindings after r328839.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328916
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Puyan Lotfi [Sat, 31 Mar 2018 05:48:51 +0000 (05:48 +0000)]
[MIR-Canon] Adding support for local idempotent instruction hoisting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328915
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Craig Topper [Sat, 31 Mar 2018 04:54:32 +0000 (04:54 +0000)]
[X86] Add SchedRW for PMULLD
Summary:
It seems many CPUs don't implement this instruction as well as the other vector multiplies. Often using a multi uop flow. Silvermont in particular has a 7 uop flow with 11 cycle throughput. Sandy Bridge implements it as a single uop with 5 cycle latency and 1 cycle throughput. But Haswell and later use 2 uops with 10 cycle latency and 2 cycle throughput.
This patch adds a new X86SchedWritePair we can use to tag this instruction separately. I've provided correct information for Silvermont, Btver2, and Sandy Bridge. I've removed the InstRWs for SandyBridge. I've left Haswell/Broadwell/Skylake InstRWs in place because I wasn't sure how to account for the different load latency between 128 and 256 bits. I also left Znver1 InstRWs in place because the existing values don't match Agner's spreadsheet.
I also left a FIXME in the SandyBridge model because it being used for the "generic" model is too optimistic for the 256/512-bit versions since those are multiple uops on all known CPUs.
Reviewers: RKSimon, GGanesh, courbet
Reviewed By: RKSimon
Subscribers: gchatelet, gbedwell, andreadb, llvm-commits
Differential Revision: https://reviews.llvm.org/D44972
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328914
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Teresa Johnson [Sat, 31 Mar 2018 00:18:08 +0000 (00:18 +0000)]
[ThinLTO] Add an option to force summary call edges cold for debugging
Summary:
Useful to selectively disable importing into specific modules for
debugging/triaging/workarounds.
Reviewers: eraman
Subscribers: inglorion, llvm-commits
Differential Revision: https://reviews.llvm.org/D45062
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328909
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Fangrui Song [Fri, 30 Mar 2018 22:22:31 +0000 (22:22 +0000)]
Fix a bunch of typoes. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328907
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Ekaterina Romanova [Fri, 30 Mar 2018 21:35:42 +0000 (21:35 +0000)]
Prevent data races in concurrent ThinLTO processes.
Make sure ThinLTO with caching doesn't use non-atomic writes to the cache file (to prevent data races and cache files corruption).
1. Place temp file to the same place where the caching directory is (instead of creating it the directory pointed to by TMP/TEMP variable). This will help to prevent using non-atomic rename and falling back to non-atomic "direct" write to the cache file.
2. if rename failed do not write to the cache file directly (direct write to the file is non-atomic and could cause data race conditions).
3. if cache file doesn't exist (e.g., because 'rename' failed or because some other reasons), bypass using the cache altogether.
Differential Revision: https://reviews.llvm.org/D45076
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328904
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Jacob Gravelle [Fri, 30 Mar 2018 20:36:58 +0000 (20:36 +0000)]
[WebAssembly] Register wasm passes with the PassRegistry
Summary:
This exposes WebAssembly passes for use on the command line (as
arguments to -print-before and the like).
Reviewers: dschuff, sunfish
Subscribers: MatzeB, jfb, sbc100, llvm-commits, aheejin
Differential Revision: https://reviews.llvm.org/D45103
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328901
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Krzysztof Parzyszek [Fri, 30 Mar 2018 19:46:28 +0000 (19:46 +0000)]
[Hexagon] Fix testcase
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328899
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Krzysztof Parzyszek [Fri, 30 Mar 2018 19:30:28 +0000 (19:30 +0000)]
[Hexagon] Reduce excessive indentation in .s output
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328898
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Krzysztof Parzyszek [Fri, 30 Mar 2018 19:28:37 +0000 (19:28 +0000)]
[Hexagon] Avoid creating invalid offsets in packetizer
Two memory instructions with a dependency only on the address register
between the two (the first one of them being post-incrememnt) can be
packetized together after the offset on the second was updated to the
incremement value. Make sure that the new offset is valid for the
instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328897
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Andrea Di Biagio [Fri, 30 Mar 2018 18:53:47 +0000 (18:53 +0000)]
[X86][BtVer2] Fixed the number of micro opcodes for AVX vector converts and
VSQRT instructions.
There were still a few AVX instructions with an incorrect number of opcodes.
These should be fixed now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328892
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Peter Collingbourne [Fri, 30 Mar 2018 18:37:55 +0000 (18:37 +0000)]
DataFlowSanitizer: wrappers of functions with local linkage should have the same linkage as the function being wrapped
This patch resolves link errors when the address of a static function is taken, and that function is uninstrumented by DFSan.
This change resolves bug 36314.
Patch by Sam Kerner!
Differential Revision: https://reviews.llvm.org/D44784
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328890
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Puyan Lotfi [Fri, 30 Mar 2018 18:15:54 +0000 (18:15 +0000)]
[MIR] Adding support for Named Virtual Registers in MIR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328887
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Andrea Di Biagio [Fri, 30 Mar 2018 18:15:30 +0000 (18:15 +0000)]
[X86][BtVer2] Fix the number of uOps for horizontal operations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328886
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Tim Shen [Fri, 30 Mar 2018 17:51:03 +0000 (17:51 +0000)]
[NVPTX] Enable StructuredCFG for NVPTX
Summary:
Make NVPTX require structured CFG. Added a temporary flag to
"roll back" the behavior for easy deployment.
Combined with D45008, this fixes several internal Nvidia GPU test
failures that we suspect to be ptxas miscompiles (PR27738).
Reviewers: jlebar
Subscribers: jholewinski, sanjoy, llvm-commits, hiraditya
Differential Revision: https://reviews.llvm.org/D45070
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328885
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Tim Shen [Fri, 30 Mar 2018 17:51:00 +0000 (17:51 +0000)]
[BlockPlacement] Disable block placement tail duplciation in structured CFG.
Summary:
Tail duplication easily breaks the structure of CFG, e.g. duplicating on
a region entry. If the structure is intended to be preserved, then we
may want to configure tail duplication, or disable it for structured
CFG. From our benchmark results disabling it doesn't cause performance
regression.
Notice that this currently affects AMDGPU backend. In the next patch, I
also plan to turn on requiresStructuredCFG for NVPTX.
All unit tests still pass.
Reviewers: jlebar, arsenm
Subscribers: jholewinski, sanjoy, wdng, tpr, hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D45008
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328884
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Robert Widmann [Fri, 30 Mar 2018 17:49:53 +0000 (17:49 +0000)]
[LLVM-C] Finish exception instruction bindings - Round 2
Summary:
Previous revision caused a leak in the echo test that got caught by the ASAN bots because of missing free of the handlers array and was reverted in r328759. Resubmitting the patch with that correction.
Add support for cleanupret, catchret, catchpad, cleanuppad and catchswitch and their associated accessors.
Test is modified from SimplifyCFG because it contains many diverse usages of these instructions.
Reviewers: whitequark, deadalnix
Reviewed By: whitequark
Subscribers: llvm-commits, vlad.tsyrklevich
Differential Revision: https://reviews.llvm.org/D45100
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328883
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Zachary Turner [Fri, 30 Mar 2018 17:28:35 +0000 (17:28 +0000)]
Fix some signed / unsigned conversion problems.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328881
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Zachary Turner [Fri, 30 Mar 2018 17:16:50 +0000 (17:16 +0000)]
[llvm-pdbutil] Dig deeper into the PDB and DBI streams when explaining.
This will show more detail when using `llvm-pdbutil explain` on an
offset in the DBI or PDB streams. Specifically, it will dig into
individual header fields and substreams to give a more precise
description of what the byte represents.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328878
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Derek Schuff [Fri, 30 Mar 2018 17:02:50 +0000 (17:02 +0000)]
[WebAssembly] Refactor tablegen for store instructions (NFC)
Summary: Add patterns similar to loads.
Differential Revision: https://reviews.llvm.org/D45064
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328876
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Krzysztof Parzyszek [Fri, 30 Mar 2018 16:55:44 +0000 (16:55 +0000)]
Revert "peel loops with runtime small trip counts"
This reverts commit r328854, it breaks some Hexagon tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328875
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Stanislav Mekhanoshin [Fri, 30 Mar 2018 16:19:13 +0000 (16:19 +0000)]
[AMDGPU] Fixed some instructions latencies
Differential Revision: https://reviews.llvm.org/D45073
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328874
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Sanjay Patel [Fri, 30 Mar 2018 15:42:52 +0000 (15:42 +0000)]
[SelectionDAG] Removing FABS folding from DAGCombiner
The code has bugs dealing with -0.0.
Since D44550 introduced FABS pattern folding in InstCombine,
this patch removes the now-redundant code that causes
https://bugs.llvm.org/show_bug.cgi?id=36600.
Patch by Mikhail Dvoretckii!
Differential Revision: https://reviews.llvm.org/D44683
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328872
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Krzysztof Parzyszek [Fri, 30 Mar 2018 15:29:47 +0000 (15:29 +0000)]
[Hexagon] Recognize and handle :endloop01
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328870
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Krzysztof Parzyszek [Fri, 30 Mar 2018 15:09:05 +0000 (15:09 +0000)]
[Hexagon] Fix printing :mem_noshuf on compiler-generated packets
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328869
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Krzysztof Parzyszek [Fri, 30 Mar 2018 14:57:01 +0000 (14:57 +0000)]
[Hexagon] Fix flags for store-related intrinsics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328868
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Andrea Di Biagio [Fri, 30 Mar 2018 14:48:08 +0000 (14:48 +0000)]
[X86][BtVer2] Add missing ReadAfterLd to RM variants of AVX horizontal adds and
most vector logic instructions.
Fixed a few InstRW that forgot to specify a ReadAfterLd for the register input
operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328867
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Krzysztof Parzyszek [Fri, 30 Mar 2018 14:34:32 +0000 (14:34 +0000)]
[Hexagon] Remove unused scheduling classes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328866
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Andrea Di Biagio [Fri, 30 Mar 2018 14:29:33 +0000 (14:29 +0000)]
[X86][BtVer2] Add tests that show how ReadAfterLd is missing for some
instructions.
In the Btver2 model, there are a few InstRW overrides that don't specify a
ReadAfterLd for the register input operand.
As a result, a few AVX variants of horizontal operations and most vector logic
operations with a folded memory operand don't have a ReadAdvance info associated
to their input register operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328865
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Krzysztof Parzyszek [Fri, 30 Mar 2018 14:29:15 +0000 (14:29 +0000)]
[Hexagon] Pass pointer to SelectionDAG to dump functions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328864
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Andrea Di Biagio [Fri, 30 Mar 2018 13:38:37 +0000 (13:38 +0000)]
[X86] Add llvm-mca tests for r328834.
Verify that the ReadAfterLd is correctly applied to FMA and 4-ops variable blend
instructions.
As Craig pointed out in D44726, some Intel models still have to be fixed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328861
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Andrea Di Biagio [Fri, 30 Mar 2018 11:44:48 +0000 (11:44 +0000)]
[X86] Add tests to verify the presence of "ReadAfterLd" after r328823.
This change adds a couple of tests to verify the change introduced by revision
328823 ([X86] Correct the placement of ReadAfterLd in BEXTR and BZHI).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328859
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Vlad Tsyrklevich [Fri, 30 Mar 2018 06:21:28 +0000 (06:21 +0000)]
Revert "[LLVM-C] Finish exception instruction bindings"
This reverts commit r328759. It was causing LSan failures on sanitizer-x86_64-linux-bootstrap
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328858
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Michael Bedy [Fri, 30 Mar 2018 05:03:36 +0000 (05:03 +0000)]
[AMDGPU] Fix the SDWA Peephole phase to handle src for dst:UNUSED_PRESERVE.
Summary:
The phase attempts to transform operations that extract a portion of a value
into an SDWA src operand in cases where that value is used only once. It
was not prepared for this use to be the preserved portion of a value for
dst:UNUSED_PRESERVE, resulting in a crash or assert.
This change either rejects the illegal SDWA attempt, or in the case where
dst:WORD_1 and the src_sel would be WORD_0, removes the unneeded
extract instruction.
Reviewers: arsenm, #amdgpu
Reviewed By: arsenm, #amdgpu
Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D44364
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328856
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Ikhlas Ajbar [Fri, 30 Mar 2018 03:32:24 +0000 (03:32 +0000)]
[Hexagon] add missing lit config file
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328855
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Ikhlas Ajbar [Fri, 30 Mar 2018 03:05:34 +0000 (03:05 +0000)]
peel loops with runtime small trip counts
For Hexagon, peeling loops with small runtime trip count is beneficial for our
benchmarks. We set PeelCount in HexagonTargetInfo.cpp and we use PeelCount set
by the target for computing the desired peel count.
Differential Revision: https://reviews.llvm.org/D44880
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328854
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Eli Friedman [Fri, 30 Mar 2018 00:56:03 +0000 (00:56 +0000)]
[MachineCopyPropagation] Handle COPY with overlapping source/dest.
MachineCopyPropagation::CopyPropagateBlock has a bunch of special
handling for COPY instructions. This handling assumes that COPY
instructions do not modify the source of the copy; this is wrong if
the COPY destination overlaps the source.
To fix the bug, check explicitly for this situation, and fall back to
the generic instruction handling.
This bug can't happen for most register classes because they don't
have this sort of overlap, but there are a few register classes
where this is possible. The testcase uses the AArch64 QQQQ register
class.
Differential Revision: https://reviews.llvm.org/D44911
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328851
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Eugene Zelenko [Fri, 30 Mar 2018 00:47:31 +0000 (00:47 +0000)]
[IR] Fix some Clang-tidy modernize-use-auto warnings; other minor fixes (NFC).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328850
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Rafael Espindola [Thu, 29 Mar 2018 23:32:54 +0000 (23:32 +0000)]
Style update. NFC.
Rename 3 functions to start with lowercase letters. Don't repeat the
name in the comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328848
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David Blaikie [Thu, 29 Mar 2018 22:42:08 +0000 (22:42 +0000)]
Fix some layering in StripNonLineTableDebugInfo, moving its declaration from IPO.h to Utils.h to match its implementation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328844
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David Blaikie [Thu, 29 Mar 2018 22:35:59 +0000 (22:35 +0000)]
Remove unused header to fix layering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328842
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David Blaikie [Thu, 29 Mar 2018 22:31:39 +0000 (22:31 +0000)]
Remove unused headers to fix layering
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328840
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David Blaikie [Thu, 29 Mar 2018 22:31:38 +0000 (22:31 +0000)]
llvm-c: Split Utils out of Scalar.h
To fix layering (so that Scalar.h, a libScalarOpts header, isn't
included from Utils - which libScalarOpts depends on).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328839
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