OSDN Git Service
Dave Airlie [Wed, 14 Feb 2018 03:59:09 +0000 (13:59 +1000)]
r600: fix regression in gl_FragColor drawing
This fixes a regression in the broadcast color to all color bufs case.
Fixes:
6c691081a (r600: fixup sparse color exports.)
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 12 Feb 2018 04:46:50 +0000 (14:46 +1000)]
r600: fix array spill if temp[0] is before all arrays
I found a shader with
DCL TEMP[0], LOCAL
DCL TEMP[1..256], ARRAY(1), LOCAL
DCL TEMP[257..512], ARRAY(2), LOCAL
DCL TEMP[513..768], ARRAY(3), LOCAL
DCL TEMP[769], LOCAL
This would remap badly, as it would add up all the spilled sizes
and subtract it from the temp for 0. If the current temp is less
than the array start break out.
Fixes:
1d871aa6 (r600g: Implement spilling of temp arrays (v2))
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Tue, 13 Feb 2018 04:08:14 +0000 (14:08 +1000)]
virgl: add ARB_sample_shading support.
This enable ARB_sample_shading if the renderer supports it.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Tue, 13 Feb 2018 03:57:28 +0000 (13:57 +1000)]
virgl: add ARB_draw_indirect support.
This relies on the renderer code landing first.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Roland Scheidegger [Tue, 13 Feb 2018 17:56:34 +0000 (18:56 +0100)]
tgsi: Recognize RET in main for tgsi_transform
Shaders coming from dx10 state trackers have a RET before the END.
And the epilog needs to be placed before the RET (otherwise it will
get ignored).
Hence figure out if a RET is in main, in this case we'll place
the epilog there rather than before the END.
(At a closer look, there actually seem to be problems with control
flow in general with output redirection, that would need another
look. It's enough however to fix draw's aa line emulation in some
internal bug - lines tend to be drawn with trivial shaders, moving
either a constant color or a vertex color directly to the output).
v2: add assert so buggy handling of RET in main is detected
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Bas Nieuwenhuizen [Tue, 13 Feb 2018 22:25:30 +0000 (23:25 +0100)]
ac: Use the renumbered const address space for LLVM 7.
The LLVM AMDGPU backend decided to renumber the constant address
space ....
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Dave Airlie [Mon, 12 Feb 2018 19:21:12 +0000 (05:21 +1000)]
gallium: drop all the guard band float caps.
Nobody queries these and nobody sets them to anything useful,
the docs say TODO.
Drop them until a use appears.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Vadym Shovkoplias [Tue, 13 Feb 2018 18:38:22 +0000 (11:38 -0700)]
mesa: add glsl version query (v4)
Add support for GL_NUM_SHADING_LANGUAGE_VERSIONS
and glGetStringi for GL_SHADING_LANGUAGE_VERSION
v2:
- Combine similar functionality into
_mesa_get_shading_language_version() function.
- Change GLSL version return mechanism.
v3:
- Add return of empty string for GLSL ver 1.10.
- Move _mesa_get_shading_language_version() function
to src/mesa/main/version.c.
v4:
- Add OpenGL version check.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104915
Signed-off-by: Andriy Khulap <andriy.khulap@globallogic.com>
Signed-off-by: Vadym Shovkoplias <vadym.shovkoplias@globallogic.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Brian Paul [Tue, 13 Feb 2018 16:21:45 +0000 (09:21 -0700)]
mesa: add missing switch case for EXTRA_VERSION_40 in check_extra()
The EXTRA_VERSION_40 predicate is tested as part of
extra_gl40_ARB_sample_shading but there was no switch case for it.
Fixes:
77b440e42d8e7247c2295 ("mesa: Add new functions and enums required
by GL_ARB_sample_shading")
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Mark Janes [Tue, 13 Feb 2018 07:19:35 +0000 (23:19 -0800)]
mesa: fix compile failure
Missing header triggered a failure in i965 CI buildtest project.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105067
Fixes:
e149a0253c12d103805230bc7bc0a36887c3b8df
Mark Janes [Tue, 13 Feb 2018 06:15:47 +0000 (22:15 -0800)]
Partially revert "mesa: use GLenum16 in a few more places"
This reverts part of commit
ca721b3d894a49d7342f5aa053ed132017e9352a.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105067
Mark Janes [Tue, 13 Feb 2018 07:47:18 +0000 (23:47 -0800)]
Revert "mesa: reduce the size of gl_texture_image"
This reverts commit
f4ea2b2a9e99d93fbf36c3f0e5f6f384be3cdb89.
Several members reduced in size by the offending commit are not large
enough to store the data needed by the i965 driver.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105067
Dave Airlie [Tue, 13 Feb 2018 02:21:07 +0000 (12:21 +1000)]
i965: fix tessellation regressions with gl_state_index16
Looks like one conversion was missed.
Fixes:
e149a0253 (mesa,glsl,nir: reduce gl_state_index size to 2 bytes)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105067
Signed-off-by: Dave Airlie <airlied@redhat.com>
Tested-by: Mark Janes <mark.a.janes@intel.com>
Stéphane Marchesin [Sat, 10 Feb 2018 01:21:59 +0000 (17:21 -0800)]
virgl: Support v2 caps struct (v2)
This struct allows us to report:
- accurate max point size/line width.
- accurate texel and texture gather offsets
- vertex/geometry limits.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Timothy Arceri [Thu, 8 Feb 2018 00:10:26 +0000 (11:10 +1100)]
ac/nir: add nir_intrinsic_{load,store}_shared support
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Timothy Arceri [Fri, 2 Feb 2018 02:42:22 +0000 (13:42 +1100)]
ac/nir_to_llvm: add support for nir_intrinsic_shared_atomic_*
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Timothy Arceri [Mon, 5 Feb 2018 04:47:05 +0000 (15:47 +1100)]
radeonsi: make si_declare_compute_memory() more generic and call for nir
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Timothy Arceri [Mon, 5 Feb 2018 04:45:32 +0000 (15:45 +1100)]
st/glsl: set req_local_mem earlier for compute shaders
Without this change it will never be set for backends using nir.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Marek Olšák [Thu, 16 Nov 2017 15:19:22 +0000 (16:19 +0100)]
mesa: move STATE_LENGTH to shader_enums.h and use it everywhere
Reviewed-by: Brian Paul <brianp@vmware.com>
Marek Olšák [Thu, 16 Nov 2017 03:46:02 +0000 (04:46 +0100)]
mesa: reduce the size of gl_texture_image
80 -> 40 bytes.
Reviewed-by: Brian Paul <brianp@vmware.com>
Marek Olšák [Thu, 16 Nov 2017 03:32:33 +0000 (04:32 +0100)]
mesa: reduce the size of gl_program_parameter
40 -> 24 bytes, which includes the gl_state_index16 change.
Reviewed-by: Brian Paul <brianp@vmware.com>
Marek Olšák [Thu, 16 Nov 2017 03:29:35 +0000 (04:29 +0100)]
mesa,glsl,nir: reduce gl_state_index size to 2 bytes
Let's use the new gl_state_index16 type everywhere and remove
the typecasts.
This helps reduce the size of gl_program_parameter.
Reviewed-by: Brian Paul <brianp@vmware.com>
Marek Olšák [Thu, 16 Nov 2017 00:46:40 +0000 (01:46 +0100)]
mesa: reduce the size of gl_viewport_attrib
All drivers convert these to float, so there is no reason to use double.
The piglit test that expects double precision from glGet will be adjusted
not to require it (there is a piglit patch).
gl_context::ViewportArray: 512 -> 384 bytes
Reviewed-by: Mathias Fröhlich <mathias.froehlich@web.de>
Reviewed-by: Brian Paul <brianp@vmware.com>
Marek Olšák [Thu, 16 Nov 2017 00:44:10 +0000 (01:44 +0100)]
mesa: reduce the size of gl_texture_object
Reviewed-by: Brian Paul <brianp@vmware.com>
Marek Olšák [Thu, 16 Nov 2017 00:10:27 +0000 (01:10 +0100)]
mesa: reduce the size of gl_program
gl_program: 1456 -> 976 bytes
Reviewed-by: Brian Paul <brianp@vmware.com>
Marek Olšák [Wed, 15 Nov 2017 23:44:43 +0000 (00:44 +0100)]
mesa: reduce the size of gl_image_unit (v2)
gl_context::ImageUnits: 6144 -> 4608 bytes
v2: use ASSERT_BITFIELD_SIZE
Reviewed-by: Brian Paul <brianp@vmware.com>
Marek Olšák [Wed, 15 Nov 2017 21:41:12 +0000 (22:41 +0100)]
mesa: further reduce the size of ctx->Texture
Reviewed-by: Brian Paul <brianp@vmware.com>
Marek Olšák [Wed, 15 Nov 2017 21:10:43 +0000 (22:10 +0100)]
mesa: decrease the array size of ctx->Texture.FixedFuncUnit to 8
GL allows doing glTexEnv on 192 texture units, while in reality,
only MaxTextureCoordUnits units are used by fixed-func shaders.
There is a piglit patch that adjusts piglits/texunits to check only
MaxTextureCoordUnits units.
Reviewed-by: Brian Paul <brianp@vmware.com>
Marek Olšák [Wed, 15 Nov 2017 21:02:51 +0000 (22:02 +0100)]
mesa: separate legacy stuff from gl_texture_unit into gl_fixedfunc_texture_unit
Reviewed-by: Brian Paul <brianp@vmware.com>
Marek Olšák [Wed, 15 Nov 2017 16:50:33 +0000 (17:50 +0100)]
mesa: inline init_texture_unit
because this is going to be changed
Reviewed-by: Brian Paul <brianp@vmware.com>
Marek Olšák [Tue, 30 Jan 2018 21:25:25 +0000 (22:25 +0100)]
mesa: use GLenum16 in a few more places
Reviewed-by: Brian Paul <brianp@vmware.com>
Jason Ekstrand [Mon, 12 Feb 2018 16:17:57 +0000 (08:17 -0800)]
anv: Move setting current_pipeline to cmd_state_init
We were setting current_pipeline to UINT32_MAX and then calling
cmd_cmd_state_reset which memsets the entire state struct to 0 which
implicitly resets current_pipeline to 3D. I have no idea how this
hasn't caused everything to explode.
Fixes:
cd3feea74582 "anv/cmd_buffer: Rework anv_cmd_state_reset"
cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Mon, 12 Feb 2018 17:48:12 +0000 (09:48 -0800)]
anv: Don't resolve or ambiguate non-existent layers
The previous code was trying to avoid non-existent layers by taking a
MAX with anv_image_aux_layers. Unfortunately, it wasn't taking into
account that layer_count starts at base_layer which may not be zero.
Instead, we need to subtract base_layer from anv_image_aux_layers with
a guard against roll-over.
Fixes:
de3be6180169f9 "anv/cmd_buffer: Rework aux tracking"
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Daniel Stone [Mon, 12 Feb 2018 17:54:41 +0000 (17:54 +0000)]
i965: Fix bugs in intel_from_planar
This commit fixes two bugs in intel_from_planar. First, if the planar
format was non-NULL but only had a single plane, we were falling through
to the planar case. If we had a CCS modifier and plane == 1, we would
return NULL instead of the CCS plane. Second, if we did end up in the
planar_format == NULL case and the modifier was DRM_FORMAT_MOD_INVALID,
we would end up segfaulting in isl_drm_modifier_has_aux.
Cc: mesa-stable@lists.freedesktop.org
Fixes:
8f6e54c92966bb94a3f05f2cc7ea804273e125ad
Signed-off-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Eric Anholt [Sat, 10 Feb 2018 11:06:45 +0000 (11:06 +0000)]
radv: Fix compiler warning about uninitialized 'set'
The compiler doesn't figure out that we only get result == VK_SUCCESS if
set got initialized.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Eric Anholt [Sat, 10 Feb 2018 11:01:20 +0000 (11:01 +0000)]
glsl/tests: Fix strict aliasing warning about int64/double.
Fixes:
4bf986274728 ("glsl/tests: Add UINT64 and INT64 types")
Reviewed-by: Rhys Kidd <rhyskidd@gmail.com>
Eric Anholt [Sat, 10 Feb 2018 10:37:37 +0000 (10:37 +0000)]
ac/nir: Fix compiler warning about uninitialized dw_addr.
Even switching the def's condition to be the same chip revision check as
the use, the compiler doesn't figure it out. Just NULL-init it.
Fixes:
ec53e527421d ("ac/nir: Add ES output to LDS for GFX9.")
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Eric Anholt [Sat, 10 Feb 2018 10:24:14 +0000 (10:24 +0000)]
gallium/llvmpipe: Fix compiler warnings about ddx/ddy/ddmax.
My gcc doesn't figure out that dims >= 1 (seems reasonable), and doesn't
notice that ddmax is used from the same no_rho_opt as its initialization.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Kenneth Graunke [Sun, 11 Feb 2018 22:52:27 +0000 (14:52 -0800)]
anv: Drop I915_EXEC_CONSTANTS_REL_GENERAL from execbuf.
The kernel used to have execbuf parameters to program the INSTPM bit
for whether 3DSTATE_CONSTANT_* should be relative to dynamic state
base address or an absolute address. However, they never worked in
the presence of hardware contexts, so I deleted them a while back.
It doesn't make sense to set this flag, as it doesn't exist anymore.
It also never did anything anyway - the flag is zero, so |'ing it in
did nothing. The default is relative anyway.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Eric Engestrom [Fri, 9 Feb 2018 11:38:43 +0000 (11:38 +0000)]
r200: remove left over dead code
0aaa27f29187ffb739c7 removed the references to this array without
removing the array itself
Cc: Ian Romanick <ian.d.romanick@intel.com>
Fixes:
0aaa27f29187ffb739c7 "mesa: Pass the translated color logic op dd_function_table::LogicOpcode"
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Elie Tournier <elie.tournier@collabora.com>
Samuel Pitoiset [Fri, 9 Feb 2018 12:54:35 +0000 (13:54 +0100)]
ac/nir: remove backlink to nir_to_llvm_context
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Fri, 9 Feb 2018 12:54:34 +0000 (13:54 +0100)]
ac/nir: remove nir_to_llvm_context::module
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Fri, 9 Feb 2018 12:54:33 +0000 (13:54 +0100)]
ac/nir: remove nir_to_llvm_context::builder
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Fri, 9 Feb 2018 12:54:32 +0000 (13:54 +0100)]
ac/nir: drop nir_to_llvm_context from glsl_to_llvm_type()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Fri, 9 Feb 2018 12:54:31 +0000 (13:54 +0100)]
ac/nir: drop nir_to_llvm_context from visit_var_atomic()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Fri, 9 Feb 2018 12:54:30 +0000 (13:54 +0100)]
ac/nir: drop nir_to_llvm_context from visit_vulkan_resource_reindex()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Fri, 9 Feb 2018 12:54:29 +0000 (13:54 +0100)]
ac/nir: drop nir_to_llvm_context from visit_load_push_constant()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Fri, 9 Feb 2018 12:54:28 +0000 (13:54 +0100)]
ac/nir: drop nir_to_llvm_context from cast_ptr()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Fri, 9 Feb 2018 12:54:27 +0000 (13:54 +0100)]
ac/nir: drop nir_to_llvm_context from visit_load_local_invocation_index()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Fri, 9 Feb 2018 12:54:26 +0000 (13:54 +0100)]
ac/nir: drop nir_to_llvm_context from emit_f2f16()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Fri, 9 Feb 2018 12:54:25 +0000 (13:54 +0100)]
ac: remove unused parameters in abi::load_tess_coord()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Fri, 9 Feb 2018 12:54:24 +0000 (13:54 +0100)]
ac/nir: remove useless bitcast in load_tess_coord()
nir_intrinsic_load_tess_coord always returns a v3i32.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Fri, 9 Feb 2018 12:54:23 +0000 (13:54 +0100)]
ac: add load_resource() to the ABI
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Fri, 9 Feb 2018 12:54:22 +0000 (13:54 +0100)]
ac: add load_sample_mask_in() to the ABI
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Fri, 9 Feb 2018 12:54:21 +0000 (13:54 +0100)]
ac: move view_index to the ABI
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Fri, 9 Feb 2018 12:54:20 +0000 (13:54 +0100)]
ac: move push_constants to the ABI
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Fri, 9 Feb 2018 12:54:19 +0000 (13:54 +0100)]
ac: move tg_size to the ABI
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Fri, 9 Feb 2018 12:54:18 +0000 (13:54 +0100)]
ac/nir: remove unused nir_to_llvm_context:{defs,phis}
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Eric Anholt [Sat, 10 Feb 2018 16:32:57 +0000 (16:32 +0000)]
egl/gbm: Fix compiler warning about visual matching.
The compiler doesn't know that num_visuals > 0.
Fixes:
37a8d907cc16 ("egl/gbm: Ensure EGLConfigs match GBM surface format")
Reviewed-by: Daniel Stone <daniels@collabora.com>
Rob Clark [Sat, 10 Feb 2018 19:12:11 +0000 (14:12 -0500)]
freedreno: small fix for flushing dependent batches
Flush a resource's previous write_batch synchronously. Because a
resource's associated batches are not updated until after the flush
thread submits rendering to the kernel, this was causing a bit of
confusion in the following loop. This fixes a bug that appeared with
recent stk.
Perhaps we need to re-work things a bit to clear out dependent patches
in the ctx's thread and use a fence to deal with the period between
when a flush is queued and when it is submitted to the kernel. But
this will do until time permits a larger refactor.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Mon, 5 Feb 2018 13:45:29 +0000 (08:45 -0500)]
freedreno/ir3: intra-block scheduling
Because of loops, we can't schedule all of a block's predecessors first.
Instead just assume that the result consumed in a block was written far
enough away in all paths into a block. And do an intra-block scheduling
pass to figure out if there are any cases where we need to insert extra
nop's. This works out better than always assuming the worst case (ie.
that a value live into a block was written in the last instruction in
the predecessor block).
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Sun, 4 Feb 2018 17:52:24 +0000 (12:52 -0500)]
freedreno/ir3: "boost" the depth of if/else condition
Account for the move to predicate register, to try to avoid needing to
insert extra NOPs later.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Sun, 4 Feb 2018 17:42:19 +0000 (12:42 -0500)]
freedreno/ir3: account for arrays in delayslot calc
Normally false-deps are not something to consider, since they mostly
exist for delay-slot related reasons:
* barriers
* ordering writes after read
* SSBO/image access ordering
The exception is a false-dependency on an array store.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Thu, 1 Feb 2018 14:08:39 +0000 (09:08 -0500)]
freedreno/ir3: more clever legalize algorithm
Previously we didn't handle flow control in legalize, and instead just
set (ss)(sy) on the first instruction in every block. Which isn't very
clever.
Instead, consider output state of all predecessor blocks, so we only
set a sync bit if needed for any possible path leading into a block.
Because of loops, we can't require that all successor blocks are
legalized before a given block, so instead run in a loop until results
converge.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Wed, 31 Jan 2018 17:58:05 +0000 (12:58 -0500)]
freedreno/ir3: track block predecessors
Useful in the following patches.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Mon, 29 Jan 2018 20:59:55 +0000 (15:59 -0500)]
freedreno/ir3: clean up dangling false-dep's
Maybe there is a better way for this.. where it comes useful is "array"
loads, which end up as a false-dep for a later array store.
If all the uses of an array load are CP'd into their consumer, it still
leaves the dangling array load, leading to funny things like:
mov.u32u32 r5.y, r0.y
mov.u32u32 r5.y, r0.z
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Tue, 30 Jan 2018 17:18:13 +0000 (12:18 -0500)]
freedreno/ir3: handle IMMED for mad 2nd src special case
Consider also immediates for swapping the first two srcs, because they
can be lowered to constant.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Mon, 29 Jan 2018 21:22:26 +0000 (16:22 -0500)]
freedreno/ir3: remove ir3 phi instruction
Now that we convert phi webs to ssa, we can drop all this.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Mon, 29 Jan 2018 21:09:44 +0000 (16:09 -0500)]
freedreno/ir3: remove lower_if_else pass
Now that it is unused.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Mon, 29 Jan 2018 19:53:13 +0000 (14:53 -0500)]
freedreno/ir3: add experimental GCM pass
Generally seems to do worse on instruction count and register usage,
according to shader-db. But shader-db also doesn't do a very good job
of weighting loop bodies, so that might not be totally valid.
So add an env variable to enable GCM pass for easier experimentation.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Fri, 26 Jan 2018 15:43:48 +0000 (10:43 -0500)]
freedreno/ir3: change opt passes
There are more useful nir passes added since initial conversion to nir.
But ir3 was never updated to use them.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Fri, 19 Jan 2018 21:13:09 +0000 (16:13 -0500)]
freedreno/ir3: use peephole select pass
Agressively lowering all if/else to selects in some extreme cases
results in much higher register pressure. Using peephole select instead
with a modest threshold speeds up alu2 4x!
16 seems like a good limit, low enough to help alu2 but not too low that
it penalizes everything else. With a bit better scheduling of the
instruction that moves a value into a predicate register, we might be
able to lower this limit a bit more in the future, but since we need 6
cycles from the move to predicate register to predicated branch, that
puts some sort of lower bound on how far we can lower this threshold.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Thu, 18 Jan 2018 13:32:22 +0000 (08:32 -0500)]
freedreno/ir3: lower phi webs to regs
nir's from_ssa pass is much better at avoiding inserting extra moves
than our logic is. And lowering phi webs to regs just treats anything
involved in a phi web as an array of length=1. Which with previous
array related fixes in RA/etc ends up working out quite well. This cuts
down on extra instructions and also helps with register pressure.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Mon, 29 Jan 2018 17:32:24 +0000 (12:32 -0500)]
freedreno/ir3: separate arrays from groups
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Mon, 29 Jan 2018 14:54:07 +0000 (09:54 -0500)]
freedreno/ir3: make block/instruction serialno per-shader
Makes it easier to compare values seen in-game (where there are many
shaders) to cmdline standalone compiler.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Tue, 23 Jan 2018 14:28:44 +0000 (09:28 -0500)]
freedreno/ir3: add spirv support to cmdline compiler
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Sun, 21 Jan 2018 17:31:51 +0000 (12:31 -0500)]
freedreno/ir3: don't lower fsat
Instead, if possible fold (sat) flag into src, otherwise use:
(sat)max.f rD, rS, rS
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Sun, 21 Jan 2018 17:20:01 +0000 (12:20 -0500)]
freedreno/ir3: add encoding/decoding for (sat) bit
Seems to be there since a3xx, but we always lowered fsat. But we can
shave some instructions, especially in shaders that use lots of
clamp(foo, 0.0, 1.0) by not lowering fsat.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Sun, 21 Jan 2018 16:13:44 +0000 (11:13 -0500)]
freedreno/ir3: extend liverange of arrays
Use livein state of other blocks to extend liverange of arrays when they
are still needed by successor blocks.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Fri, 19 Jan 2018 20:45:37 +0000 (15:45 -0500)]
freedreno/ir3: avoid extra mov's for "arrays"
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Mon, 29 Jan 2018 21:01:42 +0000 (16:01 -0500)]
freedreno/ir3: a couple more array fixes
(Plus a couple TODOs)
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Mon, 29 Jan 2018 20:58:49 +0000 (15:58 -0500)]
freedreno/ir3: keep array stores
Since these are not in SSA form, add to block's keeps so it doesn't
appear unused.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Mon, 29 Jan 2018 20:38:06 +0000 (15:38 -0500)]
freedreno/ir3: propagate barrier information
When eliminating movs, the instruction that is now directly using the
src of the mov has the same scheduling order constraints as the original
mov instruction.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Mon, 29 Jan 2018 20:35:12 +0000 (15:35 -0500)]
freedreno/ir3: remove pointless statement
Function ends after this if/else ladder, so it was pointless.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Mon, 29 Jan 2018 20:33:55 +0000 (15:33 -0500)]
freedreno/ir3: some more debug prints
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Mon, 29 Jan 2018 20:24:17 +0000 (15:24 -0500)]
freedreno/ir3: fix printing of relative branch offsets
The number of bits depends on generation. But printing negative values
with a5xx encoding (largest size) but compiling for a3xx or a4xx, would
result in negative values printed as large positive values.
I guess in practice huge negative branch offsets aren't likely (and if
that is the case, the shader is probably too big to grok by reading the
assembly). So just print using smallest bitfield size.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Mon, 15 Jan 2018 20:57:52 +0000 (15:57 -0500)]
freedreno/ir3: be more clever with if/else jumps
Try to clean up things like:
br !p0.x #2
br p0.x #something
to eliminate the first branch.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Mon, 15 Jan 2018 19:58:41 +0000 (14:58 -0500)]
freedreno/ir3: avoid some spurious sync bits
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Mon, 29 Jan 2018 20:28:10 +0000 (15:28 -0500)]
freedreno/ir3: print # of sync bits for shaderdb
When trying to optimize to reduce stalls, it is nice to see this info.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Mon, 29 Jan 2018 14:53:30 +0000 (09:53 -0500)]
freedreno: add debug trace for flush
Signed-off-by: Rob Clark <robdclark@gmail.com>
Grazvydas Ignotas [Sat, 3 Feb 2018 21:59:05 +0000 (23:59 +0200)]
intel/compiler: fix 64bit value prints on 32bit
Fix the following:
warning: format ‘%lx’ expects argument of type ‘long unsigned int’, but
argument 3 has type ‘uint64_t {aka long long unsigned int}.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Timothy Arceri [Sat, 10 Feb 2018 00:06:55 +0000 (11:06 +1100)]
st/glsl_to_nir: remove unused options variable
Timothy Arceri [Tue, 23 Jan 2018 05:00:31 +0000 (16:00 +1100)]
st/radeonsi: enable disk cache for nir
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Timothy Arceri [Wed, 24 Jan 2018 00:12:51 +0000 (11:12 +1100)]
st: add nir shader disk cache support
v2: include compute shader support
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Timothy Arceri [Tue, 30 Jan 2018 00:56:57 +0000 (11:56 +1100)]
st/glsl_to_tgsi: move nir detection earlier
We move the nir check before the shader cache call so that we can
call a nir based caching function in a following patch.
Also with this change we simply check if vertex shaders support
NIR rather than looping over the stages as mixing of shader types
is not supported anyway.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Timothy Arceri [Fri, 9 Feb 2018 01:02:27 +0000 (12:02 +1100)]
radeonsi: stop returning PIPE_SHADER_IR_NATIVE for PIPE_SHADER_CAP_PREFERRED_IR
Clover now checks PIPE_SHADER_CAP_SUPPORTED_IRS for native support instead.
This change indirectly enables NIR support for compute shaders
on radeonsi.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Timothy Arceri [Fri, 9 Feb 2018 01:01:04 +0000 (12:01 +1100)]
r600: always return PIPE_SHADER_IR_TGSI for PIPE_SHADER_CAP_PREFERRED_IR
We now use PIPE_SHADER_CAP_SUPPORTED_IRS to check for native support
in clover.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Timothy Arceri [Fri, 9 Feb 2018 01:03:57 +0000 (12:03 +1100)]
clover: use PIPE_SHADER_CAP_SUPPORTED_IRS to discover IR
PIPE_SHADER_CAP_PREFERRED_IR was conflicting with PIPE_SHADER_IR_NIR
for compute shaders, so we let clover pick the one it wants to use.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Timothy Arceri [Fri, 9 Feb 2018 00:59:54 +0000 (11:59 +1100)]
r600: add PIPE_SHADER_IR_NATIVE to supported shaders for cs
Acked-by: Pierre Moreau <pierre.morrow@free.fr>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Timothy Arceri [Fri, 9 Feb 2018 10:09:35 +0000 (21:09 +1100)]
radeonsi/nir: add depth layout to scan pass
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>