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Matt Arsenault [Tue, 31 Jul 2018 19:17:47 +0000 (19:17 +0000)]
AMDGPU: Split wide vectors of i16/f16 into 32-bit regs on calls
This improves code for the same reasons as scalarizing 32-bit
element vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338418
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Alexandre Ganea [Tue, 31 Jul 2018 19:15:50 +0000 (19:15 +0000)]
[CodeView] Minimal support for S_UNAMESPACE records
Differential Revision: https://reviews.llvm.org/D50007
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338417
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Matt Arsenault [Tue, 31 Jul 2018 19:05:14 +0000 (19:05 +0000)]
AMDGPU: Scalarize vector argument types to calls
When lowering calling conventions, prefer to decompose vectors
into the constitute register types. This avoids artifical constraints
to satisfy a wide super-register.
This improves code quality because now optimizations don't need to
deal with the super-register constraint. For example the immediate
folding code doesn't deal with 4 component reg_sequences, so by
breaking the register down earlier the existing immediate folding
code is able to work.
This also avoids the need for the shader input processing code
to manually split vector types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338416
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Matt Davis [Tue, 31 Jul 2018 18:59:46 +0000 (18:59 +0000)]
[llvm-mca][docs] Replace "temporary" with "physical registers". NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338415
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Simon Pilgrim [Tue, 31 Jul 2018 18:24:24 +0000 (18:24 +0000)]
[X86] WriteBSWAP sched classes are reg-reg only.
Don't declare them as X86SchedWritePair when the folded class will never be used.
Note: MOVBE (load/store endian conversion) instructions tend to have a very different behaviour to BSWAP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338412
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Andrea Di Biagio [Tue, 31 Jul 2018 18:19:15 +0000 (18:19 +0000)]
[llvm-mca][docs] Improve the "How LLVM-MCA works" section.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338410
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Vlad Tsyrklevich [Tue, 31 Jul 2018 18:10:37 +0000 (18:10 +0000)]
Revert "[DebugInfo] Generate DWARF debug information for labels."
This reverts commits r338390 and r338398, they were causing LSan
failures on the ASan bot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338408
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Simon Pilgrim [Tue, 31 Jul 2018 18:05:56 +0000 (18:05 +0000)]
[X86][SSE] Use ISD::MULHU for constant/non-zero ISD::SRL lowering (PR38151)
As was done for vector rotations, we can efficiently use ISD::MULHU for vXi8/vXi16 ISD::SRL lowering.
Shift-by-zero cases are still problematic (mainly on v32i8 due to extra AND/ANDN/OR or VPBLENDVB blend masks but v8i16/v16i16 aren't great either if PBLENDW fails) so I've limited this first patch to known non-zero cases if we can't easily use PBLENDW.
Differential Revision: https://reviews.llvm.org/D49562
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338407
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Rui Ueyama [Tue, 31 Jul 2018 18:04:58 +0000 (18:04 +0000)]
Make ICF log output order deterministic.
This patch does the same thing as r338153 for COFF.
Note that this patch affects only the order of log messages.
The output file is already deterministic.
Differential Revision: https://reviews.llvm.org/D50023
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338406
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Simon Pilgrim [Tue, 31 Jul 2018 17:33:08 +0000 (17:33 +0000)]
[llvm-mca][x86] Add 32-bit instruction resource tests
These aren't exhaustive, but cover some instructions that are only available in 32-bit mode (where would we be without good BCD math performance?).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338404
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Zachary Turner [Tue, 31 Jul 2018 17:16:44 +0000 (17:16 +0000)]
Resubmit r338340 "[MS Demangler] Better demangling of template arguments."
This broke the build with GCC, but has since been fixed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338403
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Craig Topper [Tue, 31 Jul 2018 17:12:08 +0000 (17:12 +0000)]
[X86] Add pattern matching for PMADDUBSW
Summary:
Similar to D49636, but for PMADDUBSW. This instruction has the additional complexity that the addition of the two products saturates to 16-bits rather than wrapping around. And one operand is treated as signed and the other as unsigned.
A C example that triggers this pattern
```
static const int N = 128;
int8_t A[2*N];
uint8_t B[2*N];
int16_t C[N];
void foo() {
for (int i = 0; i != N; ++i)
C[i] = MIN(MAX((int16_t)A[2*i]*(int16_t)B[2*i] + (int16_t)A[2*i+1]*(int16_t)B[2*i+1], -32768), 32767);
}
```
Reviewers: RKSimon, spatel, zvi
Reviewed By: RKSimon, zvi
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D49829
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338402
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Craig Topper [Tue, 31 Jul 2018 17:12:06 +0000 (17:12 +0000)]
[X86] Add test cases that could use PMADDUBSW.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338401
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Francis Visoiu Mistrih [Tue, 31 Jul 2018 16:41:12 +0000 (16:41 +0000)]
[X86] Preserve more liveness information in emitStackProbeInline
This commit fixes two issues with the liveness information after the
call:
1) The code always spills RCX and RDX if InProlog == true, which results
in an use of undefined phys reg.
2) FinalReg, JoinReg, RoundedReg, SizeReg are not added as live-ins to
the basic blocks that use them, therefore they are seen undefined.
https://llvm.org/PR38376
Differential Revision: https://reviews.llvm.org/D50020
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338400
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Hsiangkai Wang [Tue, 31 Jul 2018 16:22:09 +0000 (16:22 +0000)]
[DebugInfo] Fix build failed in 'clang-cmake-armv8-full'.
Builder clang-cmake-armv8-full failed due to the assembly 'comment'
notation is not '#' in the target. So, I use CHECK-SAME to avoid to
check the comment notation in the same line in the test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338398
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Jakub Kuderski [Tue, 31 Jul 2018 15:53:10 +0000 (15:53 +0000)]
[Dominators] Make slow walks shorter
Summary:
When DFS numbers are not yet calculated for a dominator tree, we have to walk it up to say whether one node dominates some other.
This patch makes the slow walks shorter by only walking until the level of the node we check against is reached. This is because a node cannot possibly dominate something higher in its tree.
When running opt with -O3, the patch results in:
* 25% fewer loop iterations for `opt` (fullLTO)
* 30% fewer loop iterations for sqlite
Reviewers: brzycki, asbirlea, chandlerc, NutshellySima, grosser
Reviewed By: NutshellySima
Subscribers: mehdi_amini, dexonsmith, llvm-commits
Differential Revision: https://reviews.llvm.org/D49955
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338396
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Ewan Crawford [Tue, 31 Jul 2018 15:53:03 +0000 (15:53 +0000)]
Fix InstCombine address space assert
Workaround bug where the InstCombine pass was asserting on the IR added in lit
test, where we have a bitcast instruction after a GEP from an addrspace cast.
The second bitcast in the test was getting combined into
`bitcast <16 x i32>* %0 to <16 x i32> addrspace(3)*`, which looks like it should
be an addrspace cast instruction instead. Otherwise if control flow is allowed
to continue as it is now we create a GEP instruction
`<badref> = getelementptr inbounds <16 x i32>, <16 x i32>* %0, i32 0`. However
because the type of this instruction doesn't match the address space we hit an
assert when replacing the bitcast with that GEP.
```
void llvm::Value::doRAUW(llvm::Value*, bool): Assertion `New->getType() == getType() && "replaceAllUses of value with new value of different type!"' failed.
```
Differential Revision: https://reviews.llvm.org/D50058
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338395
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Andrea Di Biagio [Tue, 31 Jul 2018 15:29:10 +0000 (15:29 +0000)]
[llvm-mca][docs] Always use `llvm-mca` in place of `MCA`.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338394
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Sanjay Patel [Tue, 31 Jul 2018 15:07:32 +0000 (15:07 +0000)]
[InstCombine] regenerate checks and add tests for D50035; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338392
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Anastasis Grammenos [Tue, 31 Jul 2018 14:54:52 +0000 (14:54 +0000)]
[DebugInfo][LCSSA] Preserve debug location in lcssa phis
Summary:
When inserting lcssa Phi Nodes in the exit block
mak sure to preserve the original instructions DL.
Reviewers: vsk
Subscribers: JDevlieghere, llvm-commits
Differential Revision: https://reviews.llvm.org/D50009
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338391
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Hsiangkai Wang [Tue, 31 Jul 2018 14:48:32 +0000 (14:48 +0000)]
[DebugInfo] Generate DWARF debug information for labels.
There are two forms for label debug information in DWARF format.
1. Labels in a non-inlined function:
DW_TAG_label
DW_AT_name
DW_AT_decl_file
DW_AT_decl_line
DW_AT_low_pc
2. Labels in an inlined function:
DW_TAG_label
DW_AT_abstract_origin
DW_AT_low_pc
We will collect label information from DBG_LABEL. Before every DBG_LABEL,
we will generate a temporary symbol to denote the location of the label.
The symbol could be used to get DW_AT_low_pc afterwards. So, we create a
mapping between 'inlined label' and DBG_LABEL MachineInstr in DebugHandlerBase.
The DBG_LABEL in the mapping is used to query the symbol before it.
The AbstractLabels in DwarfCompileUnit is used to process labels in inlined
functions.
We also keep a mapping between scope and labels in DwarfFile to help to
generate correct tree structure of DIEs.
It also generates label debug information under global isel.
Differential Revision: https://reviews.llvm.org/D45556
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338390
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David Bolvansky [Tue, 31 Jul 2018 14:47:22 +0000 (14:47 +0000)]
Revert Enrich inline messages
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338389
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Sanjay Patel [Tue, 31 Jul 2018 14:27:30 +0000 (14:27 +0000)]
[InstCombine] auto-generate checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338388
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David Bolvansky [Tue, 31 Jul 2018 14:25:24 +0000 (14:25 +0000)]
Enrich inline messages
Summary:
This patch improves Inliner to provide causes/reasons for negative inline decisions.
1. It adds one new message field to InlineCost to report causes for Always and Never instances. All Never and Always instantiations must provide a simple message.
2. Several functions that used to return the inlining results as boolean are changed to return InlineResult which carries the cause for negative decision.
3. Changed remark priniting and debug output messages to provide the additional messages and related inline cost.
4. Adjusted tests for changed printing.
Patch by: yrouban (Yevgeny Rouban)
Reviewers: craig.topper, sammccall, sgraenitz, NutshellySima, shchenz, chandlerc, apilipenko, javed.absar, tejohnson, dblaikie, sanjoy, eraman, xbolva00
Reviewed By: tejohnson, xbolva00
Subscribers: xbolva00, llvm-commits, arsenm, mehdi_amini, eraman, haicheng, steven_wu, dexonsmith
Differential Revision: https://reviews.llvm.org/D49412
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338387
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Andrea Di Biagio [Tue, 31 Jul 2018 14:23:49 +0000 (14:23 +0000)]
[llvm-mca] Remove README.txt
A detailed description of the tool has been recently added by Matt to
CommandGuide/llvm-mca.rst. File README.txt is now redundant and can be removed;
all the relevant user-guide information has been improved and then moved to
llvm-mca.rst.
In future, we should add another .rst for the "llvm-mca developer manual" to
provide infromation about:
- llvm-mca internals.
- How to add custom stages to the simulated pipeline.
- How to provide extra processor info in the scheduling model to improve the
analysis performed by llvm-mca.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338386
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John Brawn [Tue, 31 Jul 2018 14:19:29 +0000 (14:19 +0000)]
[MemDep] Use PhiValuesAnalysis to improve alias analysis results
This is being done in order to make GVN able to better optimize certain inputs.
MemDep doesn't use PhiValues directly, but does need to notifiy it when things
get invalidated.
Differential Revision: https://reviews.llvm.org/D48489
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338384
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David Bolvansky [Tue, 31 Jul 2018 14:17:15 +0000 (14:17 +0000)]
[InstSimplify] Fold another Select with And/Or pattern
Summary: Proof: https://rise4fun.com/Alive/L5J
Reviewers: lebedev.ri, spatel
Reviewed By: spatel
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D49975
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338383
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Matt Arsenault [Tue, 31 Jul 2018 14:15:22 +0000 (14:15 +0000)]
DAG: Fix PromoteFloatResult for fcanonicalize
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338382
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Matt Arsenault [Tue, 31 Jul 2018 14:15:16 +0000 (14:15 +0000)]
AMDGPU: Don't handle FP16_TO_FP in isCanonicalized
This needs more special handling to do correctly.
Fixes test in subsequent commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338381
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Alexey Bataev [Tue, 31 Jul 2018 14:02:43 +0000 (14:02 +0000)]
[SLP] Fix PR38339: Instruction does not dominate all uses!
Summary:
If the ExtractElement instructions can be optimized out during the
vectorization and we need to reshuffle the parent vector, this
ShuffleInstruction may be inserted in the wrong place causing compiler
to produce incorrect code.
Reviewers: spatel, RKSimon, mkuper, hfinkel, javed.absar
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D49928
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338380
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Matt Arsenault [Tue, 31 Jul 2018 13:34:31 +0000 (13:34 +0000)]
AMDGPU: Fold undef fcanonicalize to qNaN
We could choose a free 0 for this, but this
matches the behavior for fmul undef, 1.0. Also,
the NaN use is more useful for folding use operations
although if it's not eliminated it is more expensive
in terms of code size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338376
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Matt Arsenault [Tue, 31 Jul 2018 13:25:23 +0000 (13:25 +0000)]
AMDGPU: Fix test check line bugs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338374
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Peter Smith [Tue, 31 Jul 2018 13:24:49 +0000 (13:24 +0000)]
[ARM] Complete enumeration values for Tag_ABI_VFP_args
The LLD implementation of Tag_ABI_VFP_args needs to check the rarely seen
values of 3 (toolchain specific) and 4 compatible with both Base and VFP.
Add the missing enumeration values so that LLD can refer to them without
having to use the raw numbers.
Differential Revision: https://reviews.llvm.org/D50049
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338373
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Andrea Di Biagio [Tue, 31 Jul 2018 13:21:43 +0000 (13:21 +0000)]
[llvm-mca][BtVer2] Teach how to identify dependency-breaking idioms.
This patch teaches llvm-mca how to identify dependency breaking instructions on
btver2.
An example of dependency breaking instructions is the zero-idiom XOR (example:
`XOR %eax, %eax`), which always generates zero regardless of the actual value of
the input register operands.
Dependency breaking instructions don't have to wait on their input register
operands before executing. This is because the computation is not dependent on
the inputs.
Not all dependency breaking idioms are also zero-latency instructions. For
example, `CMPEQ %xmm1, %xmm1` is independent on
the value of XMM1, and it generates a vector of all-ones.
That instruction is not eliminated at register renaming stage, and its opcode is
issued to a pipeline for execution. So, the latency is not zero.
This patch adds a new method named isDependencyBreaking() to the MCInstrAnalysis
interface. That method takes as input an instruction (i.e. MCInst) and a
MCSubtargetInfo.
The default implementation of isDependencyBreaking() conservatively returns
false for all instructions. Targets may override the default behavior for
specific CPUs, and return a value which better matches the subtarget behavior.
In future, we should teach to Tablegen how to automatically generate the body of
isDependencyBreaking from scheduling predicate definitions. This would allow us
to expose the knowledge about dependency breaking instructions to the machine
schedulers (and, potentially, other codegen passes).
Differential Revision: https://reviews.llvm.org/D49310
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338372
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Peter Smith [Tue, 31 Jul 2018 13:03:54 +0000 (13:03 +0000)]
[ELF][ARM] Add Arm ABI names for float ABI ELF Header flags
The ELF for the Arm architecture document defines, for EF_ARM_EABI_VER5 and
above, the flags EF_ARM_ABI_FLOAT_HARD and EF_ARM_ABI_FLOAT_SOFT. These
have been defined to be compatible with the existing EF_ARM_VFP_FLOAT and
EF_ARM_SOFT_FLOAT used by gcc for EF_ARM_EABI_UNKNOWN.
This patch adds the flags in addition to the existing ones so that any code
depending on the old names will still work.
Differential Revision: https://reviews.llvm.org/D49992
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338370
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Simon Pilgrim [Tue, 31 Jul 2018 13:00:51 +0000 (13:00 +0000)]
Revert r338365: [X86] Improved sched models for X86 BT*rr instructions.
https://reviews.llvm.org/D49243
Contains WIP code that should not have been included.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338369
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Jonas Paulsson [Tue, 31 Jul 2018 13:00:42 +0000 (13:00 +0000)]
[SystemZ] Improve decoding in case of instructions with four register operands.
Since z13, the max group size will be 2 if any μop has more than 3 register
sources.
This has been ignored sofar in the SystemZHazardRecognizer, but is now
handled by recognizing those instructions and adjusting the tracking of
decoding and the cost heuristic for grouping.
Review: Ulrich Weigand
https://reviews.llvm.org/D49847
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338368
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Sanjay Patel [Tue, 31 Jul 2018 13:00:03 +0000 (13:00 +0000)]
[InstCombine] simplify code for A & (A ^ B) --> A & ~B
This fold was written in an odd way and tried to avoid
an endless loop by bailing out on all constants instead
of the supposedly problematic case of -1. But (X & -1)
should always be simplified before we reach here, so I'm
not sure how that is a problem.
There were no tests for the commuted patterns, so I added
those at rL338364.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338367
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Andrew V. Tischenko [Tue, 31 Jul 2018 12:33:48 +0000 (12:33 +0000)]
[X86] Improved sched models for X86 BT*rr instructions.
https://reviews.llvm.org/D49243
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338365
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Sanjay Patel [Tue, 31 Jul 2018 12:31:00 +0000 (12:31 +0000)]
[InstCombine] move/add tests for xor+add fold; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338364
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Andrew V. Tischenko [Tue, 31 Jul 2018 10:14:43 +0000 (10:14 +0000)]
[X86] Improved sched models for X86 SHLD/SHRD* instructions.
Differential Revision: https://reviews.llvm.org/D9611
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338359
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Simon Pilgrim [Tue, 31 Jul 2018 10:13:17 +0000 (10:13 +0000)]
[X86][SSE] isFNEG - Use getTargetConstantBitsFromNode to handle all constant cases
isFNEG was duplicating much of what was done by getTargetConstantBitsFromNode in its own calls to getTargetConstantFromNode.
Noticed while reviewing D48467.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338358
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Martin Storsjo [Tue, 31 Jul 2018 09:27:07 +0000 (09:27 +0000)]
[ARM] Allow automatically deducing the thumb instruction size for .inst
This matches GAS, that allows unsuffixed .inst for thumb.
Differential Revision: https://reviews.llvm.org/D49937
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338357
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Martin Storsjo [Tue, 31 Jul 2018 09:27:01 +0000 (09:27 +0000)]
[ARM] Support the .inst directive for MachO and COFF targets
Contrary to ELF, we don't add any markers that distinguish data generated
with .short/.long from normal instructions, so the .inst directive only
adds compatibility with assembly that uses it.
Differential Revision: https://reviews.llvm.org/D49936
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338356
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Martin Storsjo [Tue, 31 Jul 2018 09:26:52 +0000 (09:26 +0000)]
[AArch64] Support the .inst directive for MachO and COFF targets
Contrary to ELF, we don't add any markers that distinguish data generated
with .long from normal instructions, so the .inst directive only adds
compatibility with assembly that uses it.
Differential Revision: https://reviews.llvm.org/D49935
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338355
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Sam Parker [Tue, 31 Jul 2018 09:04:14 +0000 (09:04 +0000)]
[ARM] Revert r337821
Re-enabling ARMCodeGenPrepare by default after failing to reproduce
the bootstrap issues that I was concerned it was causing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338354
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Hsiangkai Wang [Tue, 31 Jul 2018 06:09:29 +0000 (06:09 +0000)]
Test commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338352
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Hiroshi Inoue [Tue, 31 Jul 2018 05:29:20 +0000 (05:29 +0000)]
[InstSimplify] tests for D48828, D49981: fold extraction from std::pair
Minor touch up in the previous comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338351
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Hiroshi Inoue [Tue, 31 Jul 2018 05:10:36 +0000 (05:10 +0000)]
[InstSimplify] tests for D48828, D49981: fold extraction from std::pair
Updated unit tests for D48828 and D49981.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338350
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Max Kazantsev [Tue, 31 Jul 2018 04:37:11 +0000 (04:37 +0000)]
[NFC] Collect statistics in GuardWidening
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338348
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Diego Caballero [Tue, 31 Jul 2018 01:57:29 +0000 (01:57 +0000)]
[VPlan] Introduce VPLoopInfo analysis.
The patch introduces loop analysis (VPLoopInfo/VPLoop) for VPBlockBases.
This analysis will be necessary to perform some H-CFG transformations and
detect and introduce regions representing a loop in the H-CFG.
Reviewers: fhahn, rengolin, mkuper, hfinkel, mssimpso
Reviewed By: fhahn
Differential Revision: https://reviews.llvm.org/D48816
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338346
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Reid Kleckner [Tue, 31 Jul 2018 01:08:42 +0000 (01:08 +0000)]
Revert r338340 "[MS Demangler] Better demangling of template arguments."
Breaks the build with GCC, apparently.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338344
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Craig Topper [Tue, 31 Jul 2018 00:43:54 +0000 (00:43 +0000)]
[X86] Stop accidentally running the Bonnell LEA fixup path on Goldmont.
In one place we checked X86Subtarget.slowLEA() to decide if the pass should run. But to decide what the pass should we only check isSLM. This resulted in Goldmont going down the Bonnell path.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338342
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Ana Pazos [Tue, 31 Jul 2018 00:36:28 +0000 (00:36 +0000)]
[RISCV] Fixed test case failure due to r338047
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338341
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Zachary Turner [Tue, 31 Jul 2018 00:26:52 +0000 (00:26 +0000)]
[MS Demangler] Better demangling of template arguments.
This patch fixes demangling of template aliases as template-template
arguments, and also fixes function pointers and references as
not type template parameters. All of these can be properly
demangled now, so I've ported over the test
clang/test/CodeGenCXX/ms-template-callbacks.cpp. All of these
tests pass
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338340
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Amara Emerson [Tue, 31 Jul 2018 00:09:02 +0000 (00:09 +0000)]
[AArch64][GlobalISel] Add isel support for G_BLOCK_ADDR.
Also refactors some existing code to materialize addresses for the large code
model so it can be shared between G_GLOBAL_VALUE and G_BLOCK_ADDR.
This implements PR36390.
Differential Revision: https://reviews.llvm.org/D49903
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338337
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Amara Emerson [Tue, 31 Jul 2018 00:08:56 +0000 (00:08 +0000)]
[AArch64][GlobalISel] Make G_BLOCK_ADDR legal.
Differential Revision: https://reviews.llvm.org/D49902
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338336
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Amara Emerson [Tue, 31 Jul 2018 00:08:50 +0000 (00:08 +0000)]
[GlobalISel] Add a G_BLOCK_ADDR opcode to handle IR blockaddress constants.
Differential Revision: https://reviews.llvm.org/D49900
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338335
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Zachary Turner [Mon, 30 Jul 2018 23:22:39 +0000 (23:22 +0000)]
[MS Demangler] Add ms-return-qualifiers.test.
This is a copy of the tests from
clang/CodeGenCXX/ms-return-qualifiers.cpp converted to demangling
tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338330
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Craig Topper [Mon, 30 Jul 2018 23:22:00 +0000 (23:22 +0000)]
[DAGCombiner][TargetLowering] Pass a SmallVector instead of a std::vector to BuildSDIV/BuildUDIV/etc.
The vector contains the SDNodes that these functions create. The number of nodes is always a small number so we should use SmallVector to avoid a heap allocation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338329
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Zachary Turner [Mon, 30 Jul 2018 23:02:10 +0000 (23:02 +0000)]
[MS Demangler] Add rudimentary C++11 Support
This patch adds support for demangling r-value references, new
operators such as the ""_foo operator, lambdas, alias types,
nullptr_t, and various other C++11'isms.
There is 1 failing test remaining in this file, which appears to
be related to back-referencing. This type of problem has the
potential to get ugly so I'd rather fix it in a separate patch.
Differential Revision: https://reviews.llvm.org/D50013
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338324
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Matt Davis [Mon, 30 Jul 2018 22:30:14 +0000 (22:30 +0000)]
[llvm-mca][docs] Add instruction flow documentation. NFC.
Summary:
This patch mostly copies the existing Instruction Flow, and stage descriptions
from the mca README. I made a few text tweaks, but no semantic changes,
and made reference to the "default pipeline." I also removed the internals
references (e.g., reference to class names and header files). I did leave the
LSUnit name around, but only as an abbreviated word for the load-store unit.
Reviewers: andreadb, courbet, RKSimon, gbedwell, filcab
Reviewed By: andreadb
Subscribers: tschuett, jfb, llvm-commits
Differential Revision: https://reviews.llvm.org/D49692
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338319
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Sanjay Patel [Mon, 30 Jul 2018 22:21:37 +0000 (22:21 +0000)]
[DAGCombiner] transform sub-of-shifted-signbit to add
This is exchanging a sub-of-1 with add-of-minus-1:
https://rise4fun.com/Alive/plKAH
This is another step towards improving select-of-constants codegen (see D48970).
x86 is the motivating target, and those diffs all appear to be wins. PPC and AArch64 look neutral.
I've limited this to early combining (!LegalOperations) in case a target wants to reverse it, but
I think canonicalizing to 'add' is more likely to produce further transforms because we have more
folds for 'add'.
Differential Revision: https://reviews.llvm.org/D49924
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338317
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Diego Caballero [Mon, 30 Jul 2018 21:33:31 +0000 (21:33 +0000)]
[VPlan] Introduce VPlan-based dominator analysis.
The patch introduces dominator analysis for VPBlockBases and extend
VPlan's GraphTraits specialization with the required interfaces. Dominator
analysis will be necessary to perform some H-CFG transformations and
to introduce VPLoopInfo (LoopInfo analysis on top of the VPlan representation).
Reviewers: fhahn, rengolin, mkuper, hfinkel, mssimpso
Reviewed By: fhahn
Differential Revision: https://reviews.llvm.org/D48815
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338310
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Alexandre Ganea [Mon, 30 Jul 2018 21:14:25 +0000 (21:14 +0000)]
This fixes a crash when a second pass is required for the Codeview Type merging *and* the index points outside of the table (which should lead to an error being printed).
This occurs currently until MS precompiled headers .obj is added (see D45213)
Differential Revision: https://reviews.llvm.org/D50006
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338308
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Lang Hames [Mon, 30 Jul 2018 21:08:06 +0000 (21:08 +0000)]
[ORC] Add SerializationTraits for std::set and std::map.
Also, make SerializationTraits for pairs forward the actual pair
template type arguments to the underlying serializer. This allows, for example,
std::pair<StringRef, bool> to be passed as an argument to an RPC call expecting
a std::pair<std::string, bool>, since there is an underlying serializer from
StringRef to std::string that can be used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338305
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Craig Topper [Mon, 30 Jul 2018 21:04:38 +0000 (21:04 +0000)]
[TargetLowering] In BuildSDIV, add the MULHS/SMUL_LOHI to the Created vector.
BuildUDIV was already correct.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338304
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Craig Topper [Mon, 30 Jul 2018 21:04:34 +0000 (21:04 +0000)]
[DAGCombiner][PowerPC][AArch64] Pass Created vector by reference to BuildSDIVPow2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338303
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David Bolvansky [Mon, 30 Jul 2018 20:38:53 +0000 (20:38 +0000)]
[InstCombine] Fold Select with binary op
Summary:
Fold
%A = icmp eq i8 %x, 0
%B = xor i8 %x, %z
%C = select i1 %A, i8 %B, i8 %y
To
%C = select i1 %A, i8 %z, i8 %y
Fixes https://bugs.llvm.org/show_bug.cgi?id=38345
Proof: https://rise4fun.com/Alive/43J
Reviewers: lebedev.ri, spatel
Reviewed By: spatel
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D49954
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338300
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Craig Topper [Mon, 30 Jul 2018 20:27:10 +0000 (20:27 +0000)]
Revert r338222 "[DAGCombiner] Remove unnecessary calls to AddToWorklist."
Thinking about it more it might be possible for the later nodes to be folded in getNode in such a way that the other created nodes are left dead. This can cause use counts to be incorrect on nodes that aren't dead.
So its probably safer to leave this alone.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338298
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Vlad Tsyrklevich [Mon, 30 Jul 2018 20:07:33 +0000 (20:07 +0000)]
Revert "[GVNHoist] Re-enable GVNHoist by default"
This reverts commit r338240 because it was causing OOMs on the UBSan
buildbot when building clang/lib/Sema/SemaChecking.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338297
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Fangrui Song [Mon, 30 Jul 2018 19:41:25 +0000 (19:41 +0000)]
Remove trailing space
sed -Ei 's/[[:space:]]+$//' include/**/*.{def,h,td} lib/**/*.{cpp,h}
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338293
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Manoj Gupta [Mon, 30 Jul 2018 19:33:53 +0000 (19:33 +0000)]
[Inline] Copy "null-pointer-is-valid" attribute in caller.
Summary:
Normally, inling does not happen if caller does not have
"null-pointer-is-valid"="true" attibute but callee has it.
However, alwaysinline may force callee to be inlined.
In this case, if the caller has the "null-pointer-is-valid"="true"
attribute, copy the attribute to caller.
Reviewers: efriedma, a.elovikov, lebedev.ri, jyknight
Reviewed By: efriedma
Subscribers: eraman, llvm-commits
Differential Revision: https://reviews.llvm.org/D50000
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338292
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David Bolvansky [Mon, 30 Jul 2018 18:22:18 +0000 (18:22 +0000)]
[InstSimplify] [NFC] Tests for Select with AND/OR fold
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338285
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Jessica Paquette [Mon, 30 Jul 2018 17:45:28 +0000 (17:45 +0000)]
[MachineOutliner][AArch64] Add support for saving LR to a register
This teaches the outliner to save LR to a register rather than the stack when
possible. This allows us to avoid bumping the stack in outlined functions in
some cases. By doing this, in a later patch, we can teach the outliner to do
something like this:
f1:
...
bl OUTLINED_FUNCTION
...
f2:
...
move LR's contents to a register
bl OUTLINED_FUNCTION
move the register's contents back
instead of falling back to saving LR in both cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338278
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Craig Topper [Mon, 30 Jul 2018 17:34:31 +0000 (17:34 +0000)]
[X86] Fix typo in comment. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338274
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Craig Topper [Mon, 30 Jul 2018 17:29:57 +0000 (17:29 +0000)]
Recommit r338204 "[X86] Correct the immediate cost for 'add/sub i64 %x, 0x80000000'."
This checks in a more direct way without triggering a UBSAN error.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338273
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Jessica Paquette [Mon, 30 Jul 2018 17:13:25 +0000 (17:13 +0000)]
Add machine verifier to arm64-opt-remarks-lazy-bfi
Previously, I thought this was a Windows failure. Then I realized it failed on
every bot that used the verifier. This makes it use the verifier always, and
adds that pass to the pipeline checks so that it's consistent across all bots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338272
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David Bolvansky [Mon, 30 Jul 2018 16:50:00 +0000 (16:50 +0000)]
[DAGCombiner] Bug 31275- Extract a shift from a constant mul or udiv if a rotate can be formed
Summary:
Attempt to extract a shrl from a udiv or a shl from a mul if this allows a rotate to be formed. This targets cases where the input to a rotate pattern was a mul or udiv by a constant and InstCombine merged one of the shifts with the op.
Patch by: sameconrad (Sam Conrad)
Reviewers: RKSimon, craig.topper, spatel, lebedev.ri, javed.absar
Reviewed By: lebedev.ri
Subscribers: efriedma, kparzysz, llvm-commits
Differential Revision: https://reviews.llvm.org/D47681
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338270
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Thomas Preud'homme [Mon, 30 Jul 2018 16:48:39 +0000 (16:48 +0000)]
Reapply "Fix crash on inline asm with 64bit matching input in 32bit GPR"
This reapplies commit r338206 reverted by r338214 since the bug that
r338206 uncovered has been fixed in r338268.
Add support for inline assembly with matching input operand that do not
naturally go in the register class it is constrained to (eg. double in a
32-bit GPR). Note that regular input is already handled by existing
code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338269
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Thomas Preud'homme [Mon, 30 Jul 2018 16:45:40 +0000 (16:45 +0000)]
Fix uninitialized read in ARM's PrintAsmOperand
Summary:
Fix read of uninitialized RC variable in ARM's PrintAsmOperand when
hasRegClassConstraint returns false. This was causing
inline-asm-operand-implicit-cast test to fail in r338206.
Reviewers: t.p.northover, weimingz, javed.absar, chill
Reviewed By: chill
Subscribers: chill, eraman, kristof.beyls, chrib, llvm-commits
Differential Revision: https://reviews.llvm.org/D49984
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338268
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Jessica Paquette [Mon, 30 Jul 2018 16:36:22 +0000 (16:36 +0000)]
Attempt to fix Windows test failure caused by r338133
It seems like the pass pipeline on Windows is slightly different than on Linux
and macOS. As a result, the arm64-opt-remarks-lazy-bfi test has been failing.
This switches a CHECK-NEXT to a CHECK-DAG to try and get this running properly
again.
It'd be nice to switch it back to a CHECK-NEXT if possible, but the CHECK-NEXT
lines following the line we care about (the optimization remark emitter)
do a pretty good job of enforcing the ordering we want.
Hopefully this works, since I don't have a Windows machine. ;)
Example failure: http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win/builds/11295
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338267
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Evandro Menezes [Mon, 30 Jul 2018 16:20:04 +0000 (16:20 +0000)]
[SLC] Refactor the simplication of pow() (NFC)
Use more meaningful variable names. Mostly NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338266
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Simon Pilgrim [Mon, 30 Jul 2018 16:18:38 +0000 (16:18 +0000)]
[X86] Regenerate NOBMI/BMI combine-select tests.
Test cleanup for D38128
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338265
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Simon Pilgrim [Mon, 30 Jul 2018 16:15:18 +0000 (16:15 +0000)]
[X86] Regenerate PKU test to merge 32/64-bit rdpkru checks
Test cleanup for D38128
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338264
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Simon Pilgrim [Mon, 30 Jul 2018 16:13:40 +0000 (16:13 +0000)]
[X86] Regenerate fast-isel tests.
Test cleanup for D38128
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338262
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Sander de Smalen [Mon, 30 Jul 2018 16:05:45 +0000 (16:05 +0000)]
[AArch64][SVE] Asm: Enable instructions to be prefixed.
This patch enables instructions that are destructive on their
destination- and first source operand, to be prefixed with a
MOVPRFX instruction.
This patch also adds a variety of tests:
- positive tests for all instructions and forms that accept a
movprfx for either or both predicated and unpredicated forms.
- negative tests for all instructions and forms that do not accept
an unpredicated or predicated movprfx.
- negative tests for the diagnostics that get emitted when a MOVPRFX
instruction is used incorrectly.
This is patch [2/2] in a series to add MOVPRFX instructions:
- Patch [1/2]: https://reviews.llvm.org/D49592
- Patch [2/2]: https://reviews.llvm.org/D49593
Reviewers: rengolin, SjoerdMeijer, samparker, fhahn, javed.absar
Reviewed By: SjoerdMeijer
Differential Revision: https://reviews.llvm.org/D49593
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338261
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Sander de Smalen [Mon, 30 Jul 2018 15:42:46 +0000 (15:42 +0000)]
[AArch64][SVE] Asm: Add MOVPRFX instructions.
This patch adds predicated and unpredicated MOVPRFX instructions, which
can be prepended to SVE instructions that are destructive on their first
source operand, to make them a constructive operation, e.g.
add z1.s, p0/m, z1.s, z2.s <=> z1 = z1 + z2
can be made constructive:
movprfx z0, z1
add z0.s, p0/m, z0.s, z2.s <=> z0 = z1 + z2
The predicated MOVPRFX instruction can additionally be used to zero
inactive elements, e.g.
movprfx z0.s, p0/z, z1.s
add z0.s, p0/m, z0.s, z2.s
Not all instructions can be prefixed with the MOVPRFX instruction
which is why this patch also adds a mechanism to validate prefixed
instructions. The exact rules when a MOVPRFX applies is detailed in
the SVE supplement of the Architectural Reference Manual.
This is patch [1/2] in a series to add MOVPRFX instructions:
- Patch [1/2]: https://reviews.llvm.org/D49592
- Patch [2/2]: https://reviews.llvm.org/D49593
Reviewers: rengolin, SjoerdMeijer, samparker, fhahn, javed.absar
Reviewed By: SjoerdMeijer
Differential Revision: https://reviews.llvm.org/D49592
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338258
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David Bolvansky [Mon, 30 Jul 2018 15:38:42 +0000 (15:38 +0000)]
[InstCombine] [NFC] Added tests for Select with binop fold
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338257
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Joel Galenson [Mon, 30 Jul 2018 15:14:24 +0000 (15:14 +0000)]
[doc] Fix Getting Started typo.
This makes it easier for someone to copy-paste this line, change the path, and run the command.
Differential Revision: https://reviews.llvm.org/D49201
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338254
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Krzysztof Parzyszek [Mon, 30 Jul 2018 14:28:02 +0000 (14:28 +0000)]
[Hexagon] Simplify A4_rcmp[n]eqi R, 0
Consider cases when register R is known to be zero/non-zero, or when it
is defined by a C2_muxii instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338251
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John Brawn [Mon, 30 Jul 2018 14:26:24 +0000 (14:26 +0000)]
Adjust opt pass pipeline tests to cope with combination of r338240 and r338242
The combination of r338240 and r338242 causes the opt pass pipeline tests to
fail because of how r338242 makes BasicAA be invalidated more often. Adjust the
tests to reflect this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338250
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Matt Arsenault [Mon, 30 Jul 2018 12:16:58 +0000 (12:16 +0000)]
AMDGPU: Reduce code size with fcanonicalize (fneg x)
When fcanonicalize is lowered to a mul, we can
use -1.0 for free and avoid the cost of the bigger
encoding for source modifers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338244
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Matt Arsenault [Mon, 30 Jul 2018 12:16:47 +0000 (12:16 +0000)]
AMDGPU: Make fneg combine handle fcanonicalize
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338243
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John Brawn [Mon, 30 Jul 2018 11:52:08 +0000 (11:52 +0000)]
[BasicAA] Use PhiValuesAnalysis if available when handling phi alias
By using PhiValuesAnalysis we can get all the values reachable from a phi, so
we can be more precise instead of giving up when a phi has phi operands. We
can't make BaseicAA directly use PhiValuesAnalysis though, as the user of
BasicAA may modify the function in ways that PhiValuesAnalysis can't cope with.
For this optional usage to work correctly BasicAAWrapperPass now needs to be not
marked as CFG-only (i.e. it is now invalidated even when CFG is preserved) due
to how the legacy pass manager handles dependent passes being invalidated,
namely the depending pass still has a pointer to the now-dead dependent pass.
Differential Revision: https://reviews.llvm.org/D44564
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338242
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Alexandros Lamprineas [Mon, 30 Jul 2018 10:50:18 +0000 (10:50 +0000)]
[GVNHoist] Re-enable GVNHoist by default
My initial motivation for this came from https://reviews.llvm.org/D48122,
where it was pointed out that my change didn't fit well in SimplifyCFG and
therefore using GVNHoist was a better way to go. GVNHoist has been disabled
for a while as there was a list of bugs related to it.
I have fixed the following bugs:
https://bugs.llvm.org/show_bug.cgi?id=37808 -> https://reviews.llvm.org/D48372 (rL337149)
https://bugs.llvm.org/show_bug.cgi?id=36787 -> https://reviews.llvm.org/D49555 (rL337674)
https://bugs.llvm.org/show_bug.cgi?id=37445 -> https://reviews.llvm.org/D49425 (rL337680)
The next two bugs no longer occur, and it's unclear which commit fixed them:
https://bugs.llvm.org/show_bug.cgi?id=36635
https://bugs.llvm.org/show_bug.cgi?id=37791
I investigated this one and proved to be unrelated to GVNHoist, but a genuine bug in NewGvn:
https://bugs.llvm.org/show_bug.cgi?id=37660
To convince myself GVNHoist is in a good state I made a successful bootstrap build of LLVM.
Merging this change now in order to make it to the LLVM 7.0.0 branch.
Differential Revision: https://reviews.llvm.org/D49858
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338240
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Francis Visoiu Mistrih [Mon, 30 Jul 2018 09:59:33 +0000 (09:59 +0000)]
[MachineOutliner][X86] Use TAILJMPd64 instead of JMP_1 for TailCall construction
The machine verifier asserts with:
Assertion failed: (isMBB() && "Wrong MachineOperand accessor"), function getMBB, file ../include/llvm/CodeGen/MachineOperand.h, line 542.
It calls analyzeBranch which tries to call getMBB if the opcode is
JMP_1, but in this case we do:
JMP_1 @OUTLINED_FUNCTION
I believe we have to use TAILJMPd64 instead of JMP_1 since JMP_1 is used
with brtarget8.
Differential Revision: https://reviews.llvm.org/D49299
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338237
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Dean Michael Berris [Mon, 30 Jul 2018 09:45:09 +0000 (09:45 +0000)]
Revert "[X86] Correct the immediate cost for 'add/sub i64 %x, 0x80000000'."
This reverts commit r338204.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338236
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Nicolai Haehnle [Mon, 30 Jul 2018 09:23:59 +0000 (09:23 +0000)]
AMDGPU: Force skip over s_sendmsg and exp instructions
Summary:
These instructions interact with hardware blocks outside the shader core,
and they can have "scalar" side effects even when EXEC = 0. We don't
want these scalar side effects to occur when all lanes want to skip
these instructions, so always add the execz skip branch instruction
for basic blocks that contain them.
Also ensure that we skip scalar stores / atomics, though we don't
code-gen those yet.
Reviewers: arsenm, rampitec
Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D48431
Change-Id: Ieaeb58352e2789ffd64745603c14970c60819d44
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338235
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Petr Pavlu [Mon, 30 Jul 2018 08:49:30 +0000 (08:49 +0000)]
[ARM] Fix over-alignment in arguments that are HA of 128-bit vectors
Code in `CC_ARM_AAPCS_Custom_Aggregate()` is responsible for handling
homogeneous aggregates for `CC_ARM_AAPCS_VFP`. When an aggregate ends up
fully on stack, the function tries to pack all resulting items of the
aggregate as tightly as possible according to AAPCS.
Once the first item was laid out, the alignment used for consecutive
items was the size of one item. This logic went wrong for 128-bit
vectors because their alignment is normally only 64 bits, and so could
result in inserting unexpected padding between the first and second
element.
The patch fixes the problem by updating the alignment with the item size
only if this results in reducing it.
Differential Revision: https://reviews.llvm.org/D49720
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338233
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