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Matthias Braun [Thu, 28 Apr 2016 03:07:11 +0000 (03:07 +0000)]
TableGen: Produce CoveredBySubRegs summary for register classes
This will be used in the upcoming "DetectDeadLanes" pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267850
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Matthias Braun [Thu, 28 Apr 2016 03:07:07 +0000 (03:07 +0000)]
TargetRegisterInfo: Introduce reverseComposeSubRegIndexLaneMask()
This function performs the reverse computation of
composeSubRegIndexLaneMask().
It will be used in the upcoming "DetectDeadLanes" pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267849
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Matthias Braun [Thu, 28 Apr 2016 03:07:04 +0000 (03:07 +0000)]
TableGen: Support lanemasks for classes without subregisters
Previously using lanemasks on registers without any subregisters was not
well defined. This commit extends TargetRegisterInfo/tablegen to:
- Report a lanemask of 1 for regclasses without subregisters
- Do the right thing when mapping a 0/1 lanemask from a class without
subregisters into a class with subregisters in
TargetRegisterInfo::composeSubRegIndexLaneMasks().
This will be used in the upcoming "DetectDeadLanes" patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267848
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Matthias Braun [Thu, 28 Apr 2016 02:11:49 +0000 (02:11 +0000)]
LiveIntervalAnalysis: Fix handleMove() using wrong value numbers
handleMove() was incorrectly swapping two value numbers. This was missed
before because the problem only occured when moving subregister definitions
and needed -verify-machineinstrs to be detected.
I cannot add a testcase as long as I cannot reapply r260905/r260806.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267840
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Craig Topper [Thu, 28 Apr 2016 01:58:21 +0000 (01:58 +0000)]
[AArch64] Expand CTTZ for all vector types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267837
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Richard Smith [Thu, 28 Apr 2016 00:57:14 +0000 (00:57 +0000)]
Fix bogus documentation for StringRef::slice in the End < Start case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267831
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Chaoren Lin [Thu, 28 Apr 2016 00:49:37 +0000 (00:49 +0000)]
Use llvm:Twine instead of std::to_string.
std::to_string is not available from the Android NDK.
Reviewers: lhames, ovyalov, chandlerc
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D19638
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267829
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Sanjay Patel [Thu, 28 Apr 2016 00:29:27 +0000 (00:29 +0000)]
Update test to use FileCheck
Also, add some metadata to show what that currently looks like.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267827
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Bryan Chan [Thu, 28 Apr 2016 00:17:23 +0000 (00:17 +0000)]
[SystemZ] Support Swift Calling Convention
Summary:
Port rL265480, rL264754, rL265997 and rL266252 to SystemZ, in order to enable the Swift port on the architecture. SwiftSelf and SwiftError are assigned to R10 and R9, respectively, which are normally callee-saved registers. For more information, see:
RFC: Implementing the Swift calling convention in LLVM and Clang
https://groups.google.com/forum/#!topic/llvm-dev/epDd2w93kZ0
Reviewers: kbarton, manmanren, rjmccall, uweigand
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D19414
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267823
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Peter Collingbourne [Wed, 27 Apr 2016 23:48:11 +0000 (23:48 +0000)]
LTO: Don't bother trying to mangle unnamed globals, as they can't be preserved with MustPreserveSymbols.
Summary: Should fix sanitizer-windows bot.
Reviewers: joker.eph
Subscribers: llvm-commits, joker.eph
Differential Revision: http://reviews.llvm.org/D19635
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267820
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Kevin Enderby [Wed, 27 Apr 2016 23:43:00 +0000 (23:43 +0000)]
Fix bugs in llvm-objdump printing the last word for -section in non i386 and x86 files.
Two problems, 1) for the last 4 bytes it would print them as separate bytes not a word
and 2) it would print the same last byte for those bytes less than a word.
rdar://
25938224
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267819
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Zachary Turner [Wed, 27 Apr 2016 23:41:42 +0000 (23:41 +0000)]
Parse module information from DBI stream.
This gets more data out of the DBI strema of the PDB. In
particular it extracts the metadata for the list of modules
(compilands) that this PDB contains info about, and adds support
for dumping these fields to llvm-pdbdump.
Differential Revision: http://reviews.llvm.org/D19570
Reviewed By: ruiu
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267818
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Quentin Colombet [Wed, 27 Apr 2016 23:26:40 +0000 (23:26 +0000)]
[ImplicitNullChecks] Properly update the live-in of the block of the memory operation.
We basically replace:
HoistBB:
cond_br NullBB, NotNullBB
NullBB:
...
NotNullBB:
<reg> = load
into
HoistBB
<reg> = load_faulting_op NullBB
uncond_br NotNullBB
NullBB:
...
NotNullBB: ## <reg> is now live-in of NotNullBB
...
This partially fixes the machine verifier error for
test/CodeGen/X86/implicit-null-check.ll, but it still fails because
of the implicit CFG structure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267817
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Rong Xu [Wed, 27 Apr 2016 23:23:53 +0000 (23:23 +0000)]
more buildbot failure fix to r267792
__llvm_prf_nm length is embedded in llvm_used. Relax llvm_used check.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267816
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Rong Xu [Wed, 27 Apr 2016 23:20:27 +0000 (23:20 +0000)]
[PGO] Promote indirect calls to conditional direct calls with value-profile
This patch implements the transformation that promotes indirect calls to
conditional direct calls when the indirect-call value profile meta-data is
available.
Differential Revision: http://reviews.llvm.org/D17864
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267815
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Sanjay Patel [Wed, 27 Apr 2016 23:14:12 +0000 (23:14 +0000)]
[SimplifyCFG] propagate branch metadata when creating select
There's no existing test for this path, and I don't know how to expose
it in a regression test, but I'm assuming there's some reason this
path exists.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267813
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Lang Hames [Wed, 27 Apr 2016 22:54:03 +0000 (22:54 +0000)]
[RuntimeDyld] Propagate another dropped error in RuntimeDyldELF.
This should fix the PPC64 bots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267810
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Mitch Bodart [Wed, 27 Apr 2016 22:52:35 +0000 (22:52 +0000)]
[X86] Enable the post-RA-scheduler for clang's default 32-bit cpu.
For compilations with no explicit cpu specified, this exhibits
nice gains on Silvermont, with neutral performance on big cores.
Differential Revision: http://reviews.llvm.org/D19138
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267809
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Kevin Enderby [Wed, 27 Apr 2016 22:36:18 +0000 (22:36 +0000)]
Fix a bug in llvm-objdump printing of 32-bit addresses for -section in non i386 and x86 files.
rdar://
25896202
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267807
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Quentin Colombet [Wed, 27 Apr 2016 22:33:42 +0000 (22:33 +0000)]
[X86][FastISel] Make sure we use the right register class when we select stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267806
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Rong Xu [Wed, 27 Apr 2016 22:06:35 +0000 (22:06 +0000)]
Fix buildbot failure due to r267792
Relax the test check as some targets do not have name compression.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267803
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Colin LeMahieu [Wed, 27 Apr 2016 21:37:44 +0000 (21:37 +0000)]
[Hexagon] Merging nops in to previous packet rather than always creating a new one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267798
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Quentin Colombet [Wed, 27 Apr 2016 21:37:37 +0000 (21:37 +0000)]
[X86] Fix the lowering of TLS calls.
The callseq_end node must be glued with the TLS calls, otherwise,
the generic code will miss the uses of the returned value and will
mark it dead.
Moreover, TLSCall 64-bit pseudo must not set an implicit-use on RDI,
the pseudo uses the symbol address at this point not RDI and the
lowering will do the right thing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267797
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Colin LeMahieu [Wed, 27 Apr 2016 21:26:13 +0000 (21:26 +0000)]
[MCAssembler] Allow backend to finalize layout post-relaxation.
Differential revision: http://reviews.llvm.org/D19429
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267796
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Rong Xu [Wed, 27 Apr 2016 21:17:30 +0000 (21:17 +0000)]
[PGO] Prohibit address recording if the function is both internal and COMDAT
Differential Revision: http://reviews.llvm.org/D19515
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267792
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Matt Arsenault [Wed, 27 Apr 2016 21:05:08 +0000 (21:05 +0000)]
AMDGPU: Account for globals in AMDGPUPromoteAlloca pass
Patch by Bas Nieuwenhuizen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267791
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Lang Hames [Wed, 27 Apr 2016 20:54:49 +0000 (20:54 +0000)]
[RuntimeDyld] Add missing include - <string> is requried for std::to_string.
This should fix the compile error that showed up in build:
http://lab.llvm.org:8011/builders/lldb-x86_64-ubuntu-14.04-buildserver/builds/6754/
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267790
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Lang Hames [Wed, 27 Apr 2016 20:51:58 +0000 (20:51 +0000)]
[RuntimeDyld] Propagate Errors from findPPC64TOCSection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267789
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Kevin Enderby [Wed, 27 Apr 2016 20:37:06 +0000 (20:37 +0000)]
Add a test case for the crash fixed with r267037. David Blaikie said it would be nice to have!
This was crashing llvm-objdump with -macho -objc-meta-data when trying dump a non-existent section.
So the test binary is simply created from an empty .s file compiled with: clang -arch armv7 empty.s -c
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267782
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Ahmed Bougacha [Wed, 27 Apr 2016 20:33:07 +0000 (20:33 +0000)]
[ARM] Set AddPristinesAndCSRs to expandCMP_SWAP LivePhysRegs.
We run after PEI.
Found via inspection; no obvious testcase.
Follow-up to r266679.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267781
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Ahmed Bougacha [Wed, 27 Apr 2016 20:33:05 +0000 (20:33 +0000)]
[AArch64] Set AddPristinesAndCSRs to expandCMP_SWAP LivePhysRegs.
We run after PEI.
Found via inspection; no obvious testcase.
Follow-up to r266339.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267780
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Ahmed Bougacha [Wed, 27 Apr 2016 20:33:02 +0000 (20:33 +0000)]
[AArch64] Set correct successors in CMPXCHG pseudo expansion.
transferSuccessors() would LoadCmpBB a successor of DoneBB,
whereas it should be a successor of the original MBB.
Follow-up to r266339.
Unfortunately, it's tricky to catch this in the verifier.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267779
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Ahmed Bougacha [Wed, 27 Apr 2016 20:32:54 +0000 (20:32 +0000)]
[ARM] Set correct successors in CMPXCHG pseudo expansion.
transferSuccessors() would LoadCmpBB a successor of DoneBB, whereas
it should be a successor of the original MBB.
The testcase changes are caused by Thumb2SizeReduction, which
was previously confused by the broken CFG.
Follow-up to r266679.
Unfortunately, it's tricky to catch this in the verifier.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267778
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Simon Pilgrim [Wed, 27 Apr 2016 20:25:34 +0000 (20:25 +0000)]
[InstCombine][AVX2] Add AVX2 per-element vector shift tests
At the moment we don't simplify PSRAV/PSRLV/PSLLV intrinsics to generic IR for constant shift amounts, but we could.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267777
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Lang Hames [Wed, 27 Apr 2016 20:24:48 +0000 (20:24 +0000)]
[RuntimeDyld] Plumb Error/Expected through the internals of RuntimeDyld.
Also replaces a number of calls to report_fatal_error with Error returns.
The plumbing will make it easier to return errors originating in libObject.
Replacing report_fatal_errors with Error returns will give JIT clients the
opportunity to recover gracefully when the JIT is unable to produce/relocate
code, as well as providing meaningful error messages that can be used to file
bug reports.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267776
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Than McIntosh [Wed, 27 Apr 2016 20:07:02 +0000 (20:07 +0000)]
Fix build failure under NDEBUG.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267774
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Kevin B. Smith [Wed, 27 Apr 2016 19:58:03 +0000 (19:58 +0000)]
[X86]: Quit promoting 16 bit loads to 32 bit.
Differential Revision: http://reviews.llvm.org/D19592
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267773
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Kostya Serebryany [Wed, 27 Apr 2016 19:52:56 +0000 (19:52 +0000)]
[libFuzzer] disable leak detection if we have tried it for 1000 times w/o finding a leak [part 2]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267771
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Kostya Serebryany [Wed, 27 Apr 2016 19:52:34 +0000 (19:52 +0000)]
[libFuzzer] disable leak detection if we have tried it for 1000 times w/o finding a leak
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267770
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Andrew Kaylor [Wed, 27 Apr 2016 19:39:32 +0000 (19:39 +0000)]
Add optimization bisect opt-in calls for PowerPC passes
Differential Revision: http://reviews.llvm.org/D19554
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267769
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David Majnemer [Wed, 27 Apr 2016 19:36:38 +0000 (19:36 +0000)]
[CodeGenPrepare] Don't sink a cast past its user
The sink cast machinery is supposed to sink casts as close to their user
as possible. However, an EH pad is the first instruction in it's basic
block. Don't sink if the user is an EH pad.
This fixes PR27536.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267767
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Than McIntosh [Wed, 27 Apr 2016 19:26:25 +0000 (19:26 +0000)]
Refactor debugging code, NFC.
Summary:
Refactor debugging routines to reduce code duplication. Remove a couple
of #include's that were not needed. Don't require MachineDominator as a
prereq for this pass (not needed).
These changes split off from http://reviews.llvm.org/D18827.
Reviewers: wmi, gbiv, qcolombet
Subscribers: llvm-commits, davidxl, jevinskie
Differential Revision: http://reviews.llvm.org/D18992
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267766
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Justin Lebar [Wed, 27 Apr 2016 19:13:37 +0000 (19:13 +0000)]
[NVPTX] Run NVVMReflect at the beginning of IR passes.
Summary:
Currently the NVVMReflect pass is run at the beginning of our backend
passes. But really, it should be run as early as possible, as it's
simply resolving an "if" statement in code. So copy it into
TargetMachine::addEarlyAsPossiblePasses.
We still run it at the beginning of the backend passes, since it's
needed for correctness when lowering to nvptx.
(Specifically, NVVMReflect changes each call to the __nvvm_reflect
function or llvm.nvvm.reflect intrinsic into an integer constant, based
on the pass's configuration. Clearly we miss many optimization
opportunities if we perform this transformation at the beginning of
codegen.)
Reviewers: rnk
Subscribers: tra, llvm-commits, jholewinski
Differential Revision: http://reviews.llvm.org/D18616
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267765
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Justin Lebar [Wed, 27 Apr 2016 19:08:24 +0000 (19:08 +0000)]
Add TargetMachine::addEarlyAsPossiblePasses, and call it from opt.
Summary:
This is a hook to allow TargetMachine to install passes at the
EP_EarlyAsPossible PassManagerBuilder extension point.
Reviewers: chandlerc
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D18614
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267763
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Ahmed Bougacha [Wed, 27 Apr 2016 19:04:50 +0000 (19:04 +0000)]
[LIR] Set attributes on memset_pattern16.
"inferattrs" will deduce the attribute, but it will be too late for
many optimizations. Set it ourselves when creating the call.
Differential Revision: http://reviews.llvm.org/D17598
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267762
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Ahmed Bougacha [Wed, 27 Apr 2016 19:04:46 +0000 (19:04 +0000)]
[LIR] Reuse variable. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267761
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Ahmed Bougacha [Wed, 27 Apr 2016 19:04:43 +0000 (19:04 +0000)]
[InferAttrs] Mark memset_pattern16 params nocapture.
Differential Revision: http://reviews.llvm.org/D19471
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267760
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Ahmed Bougacha [Wed, 27 Apr 2016 19:04:40 +0000 (19:04 +0000)]
[TLI] Unify LibFunc attribute inference. NFCI.
Now the pass is just a tiny wrapper around the util. This lets us reuse
the logic elsewhere (done here for BuildLibCalls) instead of duplicating
it.
The next step is to have something like getOrInsertLibFunc that also
sets the attributes.
Differential Revision: http://reviews.llvm.org/D19470
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267759
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Ahmed Bougacha [Wed, 27 Apr 2016 19:04:35 +0000 (19:04 +0000)]
[TLI] Unify LibFunc signature checking. NFCI.
I tried to be as close as possible to the strongest check that
existed before; cleaning these up properly is left for future work.
Differential Revision: http://reviews.llvm.org/D19469
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267758
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Ahmed Bougacha [Wed, 27 Apr 2016 19:04:29 +0000 (19:04 +0000)]
[TLI] Fix indentation. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267757
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Sjoerd Meijer [Wed, 27 Apr 2016 18:35:02 +0000 (18:35 +0000)]
Clean up to avoid compiler warnings for casting away const qualifiers.
Differential Revision: http://reviews.llvm.org/D19598
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267753
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Chad Rosier [Wed, 27 Apr 2016 18:29:11 +0000 (18:29 +0000)]
Revert "[AMDGPU][llvm-mc] Add support of TTMP quads. Rework M0 exclusion for SMRD."
This reverts commit r267733 due to a -Werror,-Wunused-function error.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267752
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Matthew Simpson [Wed, 27 Apr 2016 18:21:36 +0000 (18:21 +0000)]
[LV] Reallow positive-stride interleaved load groups with gaps
We previously disallowed interleaved load groups that may cause us to
speculatively access memory out-of-bounds (r261331). We did this by ensuring
each load group had an access corresponding to the first and last member.
Instead of bailing out for these interleaved groups, this patch enables us to
peel off the last vector iteration, ensuring that we execute at least one
iteration of the scalar remainder loop. This solution was proposed in the
review of the previous patch.
Differential Revision: http://reviews.llvm.org/D19487
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267751
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Arch D. Robison [Wed, 27 Apr 2016 17:46:25 +0000 (17:46 +0000)]
[SLPVectorizer] Refactor where MinVecRegSize and MaxVecRegSize live.
This is the first of two commits for extending SLP Vectorizer to deal with aggregates.
This commit merely refactors existing logic.
http://reviews.llvm.org/D14185
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267748
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Gerolf Hoflehner [Wed, 27 Apr 2016 17:27:16 +0000 (17:27 +0000)]
[DAGCombiner] Follow coding convention for function name (NFC)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267745
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Marcin Koscielnicki [Wed, 27 Apr 2016 17:21:49 +0000 (17:21 +0000)]
[Mips] Add support for llvm.thread.pointer intrinsic.
This will be used to implement __builtin_thread_pointer in clang.
Differential Revision: http://reviews.llvm.org/D19569
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267743
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Gerolf Hoflehner [Wed, 27 Apr 2016 17:19:54 +0000 (17:19 +0000)]
[InstCombine] Sharpended test case in pr21210.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267742
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Reid Kleckner [Wed, 27 Apr 2016 16:46:33 +0000 (16:46 +0000)]
Silence a -Wdangling-else
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267737
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Matthew Simpson [Wed, 27 Apr 2016 16:25:04 +0000 (16:25 +0000)]
Add parentheses to silence buildbot warning
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267734
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Artem Tamazov [Wed, 27 Apr 2016 16:20:23 +0000 (16:20 +0000)]
[AMDGPU][llvm-mc] Add support of TTMP quads. Rework M0 exclusion for SMRD.
Added support of TTMP quads.
Reworked M0 exclusion machinery for SMRD and similar instructions
to enable usage of TTMP registers in those instructions as destinations.
Tests added.
Differential Revision: http://reviews.llvm.org/D19342
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267733
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Reid Kleckner [Wed, 27 Apr 2016 16:10:29 +0000 (16:10 +0000)]
[PDB] Fix function names for private symbols in PDBs
Summary:
llvm-symbolizer wants to get linkage names of functions for historical
reasons. Linkage names are only recorded in the PDB for public symbols,
and the linkage name is apparently stored separately in some "public
symbol" record. We had a workaround in PDBContext which would look for
such symbols when the user requested linkage names.
However, when given an address that was truly in a private function and
public funciton, we would accidentally find nearby public symbols and
return those function names. The fix is to look for both function
symbols and public symbols and only prefer the public symbol name if the
addresses of the symbols agree.
Fixes PR27492
Reviewers: zturner
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D19571
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267732
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Nicolai Haehnle [Wed, 27 Apr 2016 15:46:01 +0000 (15:46 +0000)]
AMDGPU/SI: Add llvm.amdgcn.s.waitcnt.all intrinsic
Summary:
So it appears that to guarantee some of the ordering requirements of a GLSL
memoryBarrier() executed in the shader, we need to emit an s_waitcnt.
(We can't use an s_barrier, because memoryBarrier() may appear anywhere in
the shader, in particular it may appear in non-uniform control flow.)
Reviewers: arsenm, mareko, tstellarAMD
Subscribers: arsenm, llvm-commits
Differential Revision: http://reviews.llvm.org/D19203
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267729
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Matthew Simpson [Wed, 27 Apr 2016 15:20:21 +0000 (15:20 +0000)]
[TTI] Add hook for vector extract with extension
This change adds a new hook for estimating the cost of vector extracts followed
by zero- and sign-extensions. The motivating example for this change is the
SMOV and UMOV instructions on AArch64. These instructions move data from vector
to general purpose registers while performing the corresponding extension
(sign-extend for SMOV and zero-extend for UMOV) at the same time. For these
operations, TargetTransformInfo can assume the extensions are free and only
report the cost of the vector extract. The SLP vectorizer has been updated to
make use of the new hook.
Differential Revision: http://reviews.llvm.org/D18523
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267725
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Artem Tamazov [Wed, 27 Apr 2016 15:17:03 +0000 (15:17 +0000)]
[AMDGPU][llvm-mc] s_getreg/setreg* - Support symbolic names of hardware registers.
Possibility to specify code of hardware register kept.
Disassemble to symbolic name, if name is known.
Tests updated/added.
Differential Revision: http://reviews.llvm.org/D19335
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267724
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Nico Weber [Wed, 27 Apr 2016 15:16:54 +0000 (15:16 +0000)]
Revert r267649, it caused PR27539.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267723
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Kristof Beyls [Wed, 27 Apr 2016 15:03:09 +0000 (15:03 +0000)]
Remove size 1 from check as that isn't part of what the test is meant to be testing.
This test also runs on e.g. ARM-native builds when the X86 backend is also
built. This test produces code for the default instruction set, even though it
is in a "X86" sub-directory. Given that this test doesn't seem to be testing
anything architecture-specific, it seems it's best to adapt the check to not
check for an architecture-dependent value (the size of the function), rather
than hard-code the test to target x86.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267722
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Teresa Johnson [Wed, 27 Apr 2016 14:19:38 +0000 (14:19 +0000)]
[ThinLTO] Refine fix to avoid renaming of uses in inline assembly.
Summary:
Refine the workaround from r266877 that attempts to prevent
renaming of locals in inline assembly, so that in addition to looking
for a llvm.used local value, that there is at least one inline assembly
call in the module. Otherwise, debug functions added to the llvm.used
can block importing/exporting unnecessarily.
Reviewers: joker.eph
Subscribers: llvm-commits, joker.eph
Differential Revision: http://reviews.llvm.org/D19573
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267717
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Teresa Johnson [Wed, 27 Apr 2016 13:28:35 +0000 (13:28 +0000)]
[ThinLTO] Use valueid instead of bitcode offsets in combined index file
Summary:
With the removal of support for lazy parsing of combined index summary
records (e.g. r267344), we no longer need to include the summary record
bitcode offset in the VST entries for definitions. Change the combined
index format to be similar to the per-module index format in using value
ids to cross-reference from the summary record to the VST entry (rather
than the summary record bitcode offset to cross-reference in the other
direction).
The visible changes are:
1) Add the value id to the combined summary records
2) Remove the summary offset from the combined VST records, which has
the following effects:
- No longer need the VST_CODE_COMBINED_GVDEFENTRY record, as all
combined index VST entries now only contain the value id and
corresponding GUID.
- No longer have duplicate VST entries in the case where there are
multiple definitions of a symbol (e.g. weak/linkonce), as they all
have the same value id and GUID.
An implication of #2 above is that in order to hook up an alias to the
correct aliasee based on the value id of the aliasee recorded in the
combined index alias record, we need to scan the entries in the index
for that GUID to find the one from the same module (i.e. the case where
there are multiple entries for the aliasee). But the reader no longer
has to maintain a special map to hook up the alias/aliasee.
Reviewers: joker.eph
Subscribers: joker.eph, llvm-commits
Differential Revision: http://reviews.llvm.org/D19481
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267712
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Artur Pilipenko [Wed, 27 Apr 2016 12:51:01 +0000 (12:51 +0000)]
NFC. Introduce Value::getPointerDerferecnceableBytes
Extract a part of isDereferenceableAndAlignedPointer functionality to Value::getPointerDerferecnceableBytes. Currently it's a NFC, but in future I'm going to accumulate all the logic about value dereferenceability in this function similarly to Value::getPointerAlignment function (D16144).
Reviewed By: reames
Differential Revision: http://reviews.llvm.org/D17572
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267708
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Simon Pilgrim [Wed, 27 Apr 2016 12:04:44 +0000 (12:04 +0000)]
[InstCombine][SSE] Regenerated vector shift tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267699
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Zlatko Buljan [Wed, 27 Apr 2016 11:31:44 +0000 (11:31 +0000)]
[mips][microMIPS] Add CodeGen support for SUBU16, SUB, SUBU, DSUB and DSUBU instructions
Differential Revision: http://reviews.llvm.org/D16676
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267694
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Zlatko Buljan [Wed, 27 Apr 2016 11:02:23 +0000 (11:02 +0000)]
[mips][microMIPS] Add CodeGen support for SLL16, SRL16, SLL, SLLV, SRA, SRAV, SRL and SRLV instructions
Differential Revision: http://reviews.llvm.org/D17989
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267693
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Artur Pilipenko [Wed, 27 Apr 2016 11:00:48 +0000 (11:00 +0000)]
isSafeToLoadUnconditionally support queries without a context
This is required to use this function from isSafeToSpeculativelyExecute
Reviewed By: hfinkel
Differential Revision: http://reviews.llvm.org/D16231
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267692
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Artur Pilipenko [Wed, 27 Apr 2016 10:42:29 +0000 (10:42 +0000)]
Use DL preferred alignment for alloca in Value::getPointerAlignment
Teach Value::getPointerAlignment that allocas with no explicit alignment are aligned to preferred alignment of the allocated type.
Reviewed By: hfinkel
Differential Revision: http://reviews.llvm.org/D17569
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267689
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Simon Pilgrim [Wed, 27 Apr 2016 09:53:09 +0000 (09:53 +0000)]
[InstCombine][SSE] Added DemandedBits tests for MOVMSK instructions
MOVMSK zeros the upper bits of the gpr - we should be able to use this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267686
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Adam Nemet [Wed, 27 Apr 2016 05:59:51 +0000 (05:59 +0000)]
Fixed sphinx warning from r267672
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267675
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Adam Nemet [Wed, 27 Apr 2016 05:28:18 +0000 (05:28 +0000)]
[LoopDist] Add llvm.loop.distribute.enable loop metadata
Summary:
D19403 adds a new pragma for loop distribution. This change adds
support for the corresponding metadata that the pragma is translated to
by the FE.
As part of this I had to rethink the flag -enable-loop-distribute. My
goal was to be backward compatible with the existing behavior:
A1. pass is off by default from the optimization pipeline
unless -enable-loop-distribute is specified
A2. pass is on when invoked directly from opt (e.g. for unit-testing)
The new pragma/metadata overrides these defaults so the new behavior is:
B1. A1 + enable distribution for individual loop with the pragma/metadata
B2. A2 + disable distribution for individual loop with the pragma/metadata
The default value whether the pass is on or off comes from the initiator
of the pass. From the PassManagerBuilder the default is off, from opt
it's on.
I moved -enable-loop-distribute under the pass. If the flag is
specified it overrides the default from above.
Then the pragma/metadata can further modifies this per loop.
As a side-effect, we can now also use -enable-loop-distribute=0 from opt
to emulate the default from the optimization pipeline. So to be precise
this is the new behavior:
C1. pass is off by default from the optimization pipeline
unless -enable-loop-distribute or the pragma/metadata enables it
C2. pass is on when invoked directly from opt
unless -enable-loop-distribute=0 or the pragma/metadata disables it
Reviewers: hfinkel
Subscribers: joker.eph, mzolotukhin, llvm-commits
Differential Revision: http://reviews.llvm.org/D19431
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267672
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Vaivaswatha Nagaraj [Wed, 27 Apr 2016 05:25:09 +0000 (05:25 +0000)]
[Cloning] cloneLoopWithPreheader(): add assert to ensure no sub-loops
Summary:
cloneLoopWithPreheader() does not update LoopInfo for sub-loop of
the original loop being cloned. Add assert to ensure no sub-loops for loop being cloned.
Reviewers: anemet, ashutosh.nema, hfinkel
Subscribers: mzolotukhin, llvm-commits
Differential Revision: http://reviews.llvm.org/D15922
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267671
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Craig Topper [Wed, 27 Apr 2016 05:17:00 +0000 (05:17 +0000)]
[Support][X86] Add a few more Intel model numbers to getHostCPUName for airmont and knl.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267670
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Craig Topper [Wed, 27 Apr 2016 05:16:58 +0000 (05:16 +0000)]
[Support][X86] Change the case values in the Intel family 6 code to hex so its easier to compare with Intel's docs. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267669
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Mehdi Amini [Wed, 27 Apr 2016 05:11:44 +0000 (05:11 +0000)]
Revert "Support "preserving" the summary information when using setModule() API in LTOCodeGenerator"
This reverts commit r267665.
ASAN shows that there is a use of undefined value.
From: Mehdi Amini <mehdi.amini@apple.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267668
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Craig Topper [Wed, 27 Apr 2016 04:40:03 +0000 (04:40 +0000)]
[Support][X86] Add a couple more Broadwell CPU models numbers to getHostCPUName.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267666
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Mehdi Amini [Wed, 27 Apr 2016 04:24:10 +0000 (04:24 +0000)]
Support "preserving" the summary information when using setModule() API in LTOCodeGenerator
Another attempt at r267655...
From: Mehdi Amini <mehdi.amini@apple.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267665
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Mehdi Amini [Wed, 27 Apr 2016 03:34:28 +0000 (03:34 +0000)]
Revert "Support "preserving" the summary information when using setModule() API in LTOCodeGenerator"
This reverts commit r267657, r267656, and r267655.
The test does not pass on multiple bots, I'm unsure why yet but let's unbreak them.
From: Mehdi Amini <mehdi.amini@apple.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267664
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Evgeny Stupachenko [Wed, 27 Apr 2016 03:04:54 +0000 (03:04 +0000)]
The patch fixes PR27392.
Summary:
It is incorrect to compare TripCount (which is BECount + 1)
with extraiters (or Count) to check if we should enter unrolled
loop or not, because TripCount can potentially overflow
(when BECount is max unsigned integer).
While comparing BECount with (Count - 1) is overflow safe and
therefore correct.
Reviewer: hfinkel
Differential Revision: http://reviews.llvm.org/D19256
From: Evgeny Stupachenko <evstupac@gmail.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267662
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Philip Reames [Wed, 27 Apr 2016 03:03:15 +0000 (03:03 +0000)]
[LVI] Delete stale and misleading comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267661
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Chuang-Yu Cheng [Wed, 27 Apr 2016 02:59:28 +0000 (02:59 +0000)]
[ppc64] fix bug in prologue that mfocrf's cr operand should be explict state instead of implicit
This fixes PR27414
Reviewers: kbarton mgrang tjablin
http://reviews.llvm.org/D19255
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267660
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Ahmed Bougacha [Wed, 27 Apr 2016 01:51:38 +0000 (01:51 +0000)]
[X86] Set AddPristinesAndCSRs to FixupBW LivePhysRegs. NFC.
We run after PEI, so we need to AddPristinesAndCSRs.
In practice, that makes no difference here, because we only ask about
liveness of super-registers of defined GR8/GR16 registers, so they
can't be pristine. Still, it's the correct thing to do.
Thanks to Quentin for noticing!
Follow-up to r267495.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267658
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Mehdi Amini [Wed, 27 Apr 2016 01:49:11 +0000 (01:49 +0000)]
Fix the test from r267656: Support "preserving" the summary information when using setModule() API in LTOCodeGenerator
From: Mehdi Amini <mehdi.amini@apple.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267657
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Mehdi Amini [Wed, 27 Apr 2016 01:47:46 +0000 (01:47 +0000)]
Add a test for r267655: Support "preserving" the summary information when using setModule() API in LTOCodeGenerator
From: Mehdi Amini <mehdi.amini@apple.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267656
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Mehdi Amini [Wed, 27 Apr 2016 01:46:48 +0000 (01:46 +0000)]
Support "preserving" the summary information when using setModule() API in LTOCodeGenerator
From: Mehdi Amini <mehdi.amini@apple.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267655
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Sanjoy Das [Wed, 27 Apr 2016 01:44:31 +0000 (01:44 +0000)]
Fix typo in comment; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267653
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Ahmed Bougacha [Wed, 27 Apr 2016 01:35:29 +0000 (01:35 +0000)]
[X86] Don't assume that MMX extractelts are from index 0.
It's probably the case for all 3 MMX users out there, but with
hand-crafted IR, you can trigger selection failures. Fix that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267652
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Ahmed Bougacha [Wed, 27 Apr 2016 01:35:25 +0000 (01:35 +0000)]
[X86] Re-enable MMX i32 extractelt combine.
This effectively adds back the extractelt combine removed by r262358:
the direct case can still occur (because x86_mmx is special, see
r262446), but it's the indirect case that's now superseded by the
generic combine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267651
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Cong Hou [Wed, 27 Apr 2016 01:29:18 +0000 (01:29 +0000)]
Detects the SAD pattern on X86 so that much better code will be emitted once the pattern is matched.
Differential revision: http://reviews.llvm.org/D14840
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267649
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Philip Reames [Wed, 27 Apr 2016 01:02:25 +0000 (01:02 +0000)]
[LVI] Add a comment explaining a subtle piece of code
Or at least, I didn't understand the implications the first several times I read it it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267648
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Adam Nemet [Wed, 27 Apr 2016 00:52:48 +0000 (00:52 +0000)]
[Docs] Try to clarify the concept of domains for noalias scope
Summary:
This tries to anchor down the concept of domains a bit better. I had
trouble initially relating this to anything. Also talking to David
Majnemer on IRC suggested that I wasn't the only one.
Reviewers: hfinkel
Subscribers: llvm-commits, majnemer
Differential Revision: http://reviews.llvm.org/D18799
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267647
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Mehdi Amini [Wed, 27 Apr 2016 00:32:13 +0000 (00:32 +0000)]
ThinLTO: do not promote GlobalVariable that have a specific section.
Differential Revision: http://reviews.llvm.org/D18298
From: Mehdi Amini <mehdi.amini@apple.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267646
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Matt Arsenault [Wed, 27 Apr 2016 00:32:09 +0000 (00:32 +0000)]
SLSR: Use UnknownAddressSpace instead of 0 for pure arithmetic.
In the case where isLegalAddressingMode is used for cases
not related to addressing modes, such as pure adds and muls,
it should not be using address space 0. LSR already passes -1
as the address space in these cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267645
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Mehdi Amini [Wed, 27 Apr 2016 00:32:02 +0000 (00:32 +0000)]
LTOCodeGenerator: turns linkonce(_odr) into weak_(odr) when present "MustPreserve" set
Summary:
If the linker requested to preserve a linkonce function, we should
honor this even if we drop all uses.
Reviewers: dexonsmith
Subscribers: llvm-commits, joker.eph
Differential Revision: http://reviews.llvm.org/D19527
From: Mehdi Amini <mehdi.amini@apple.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267644
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