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Peter Maydell [Fri, 7 Mar 2014 16:36:37 +0000 (16:36 +0000)]
Merge remote-tracking branch 'remotes/agraf/tags/signed-ppc-for-upstream' into staging
Patch queue for ppc - 2014-03-05
This pull request includes:
- VSX emulation support
- book3s pr/hv selection
- some bug fixes
- qdev stable numbering
- eTSEC emulation
# gpg: Signature made Wed 05 Mar 2014 02:14:19 GMT using RSA key ID
03FEDC60
# gpg: Can't check signature: public key not found
* remotes/agraf/tags/signed-ppc-for-upstream: (130 commits)
target-ppc: spapr: e500: fix to use cpu_dt_id
target-ppc: add PowerPCCPU::cpu_dt_id
target-ppc: Introduce hypervisor call H_GET_TCE
target-ppc: Update ppc_hash64_store_hpte to support updating in-kernel htab
target-ppc: Change the hpte store API
target-ppc: Fix page table lookup with kvm enabled
target-ppc: Fix htab_mask calculation
target-ppc: Use Additional Temporary in stqcx Case
target-ppc: Fix Compiler Warnings Due to 64-Bit Constants Declared as UL
PPC: sPAPR: Only use getpagesize() when we run with kvm
target-ppc/translate.c: Use ULL suffix for 64 bit constants
spapr-vlan: flush queue whenever can_receive can go from false to true
target-ppc: Altivec 2.07: Vector Permute and Exclusive OR
target-ppc: Altivec 2.07: Vector SHA Sigma Instructions
target-ppc: Altivec 2.07: AES Instructions
target-ppc: Altivec 2.07: Binary Coded Decimal Instructions
target-ppc: Altivec 2.07: Vector Polynomial Multiply Sum
target-ppc: Altivec 2.07: Vector Gather Bits by Bytes
target-ppc: Altivec 2.07: Doubleword Compares
target-ppc: Altivec 2.07: vbpermq Instruction
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Maydell [Fri, 7 Mar 2014 15:58:27 +0000 (15:58 +0000)]
Merge remote-tracking branch 'remotes/cohuck/tags/virtio-ccw-
20140305' into staging
One patch introducing support for adapter interrupts in virtio-ccw.
This improves performance for those guests that issue the new
CCW_CMD_SET_IND_ADAPTER channel command.
# gpg: Signature made Wed 05 Mar 2014 08:48:18 GMT using RSA key ID
C6F02FAF
# gpg: Can't check signature: public key not found
* remotes/cohuck/tags/virtio-ccw-
20140305:
s390x/virtio-ccw: Adapter interrupt support.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Maydell [Wed, 26 Feb 2014 21:53:30 +0000 (21:53 +0000)]
configure: Always build with -fno-common
MacOSX doesn't pull .o files from .a archives if the symbol that it
requires is one which the .o file defines as a common symbol.
(Common symbols are those declared without "extern"; the linker
will merge together common symbols with the same name, so
redeclaring the same variable in two compilation units results in
them referring to the same symbol rather than a compilation error).
This MacOSX difference from traditional linker behaviour means that
"make check" produces link errors:
Undefined symbols for architecture x86_64:
"_cur_mon", referenced from:
_error_vprintf in libqemuutil.a(qemu-error.o)
_error_printf in libqemuutil.a(qemu-error.o)
_error_printf_unless_qmp in libqemuutil.a(qemu-error.o)
_error_print_loc in libqemuutil.a(qemu-error.o)
_error_report in libqemuutil.a(qemu-error.o)
ld: symbol(s) not found for architecture x86_64
in this case because "cur_mon" is a common symbol in
libqemustub.a(mon-set-error.o).
In QEMU we don't make any use at all of the common symbol
functionality, so we can avoid this problem entirely simply
by compiling with -fno-common. Enable this option for all
builds, not just MacOSX, so that if we ever inadvertently
introduce multiple definitions of some variable that will
be immediately spotted as a build error rather than only
breaking the MacOSX build.
Suggested-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Message-id:
1393451610-24617-1-git-send-email-peter.maydell@linaro.org
Peter Maydell [Tue, 25 Feb 2014 18:27:49 +0000 (18:27 +0000)]
configure: Make C++ test work with --enable-werror
gcc's C++ compiler complains about being passed some -W options
which make sense for C but not for C++. This means we mustn't try
a C++ compile with QEMU_CFLAGS, but only with a filtered version
that removes the offending options. This filtering was already being
done for uses of C++ in the build itself, but was omitted for the
"does C++ work?" configure test. This only showed up when doing
builds which explicitly enabled -Werror with --enable-werror,
because the "do the compilers work" tests were mistakenly placed
above the "default werror based on whether compiling from git" code.
Another error in this category is that clang warns if you ask it to
compile C++ code from a file named "foo.c". Further, because we
were running do_cc in a subshell in the condition part of an "if",
the error_exit inside do_compiler wouldn't terminate configure and
we would plunge on regardless. Fix this complex of errors:
1. Move the default-werror code up so that there are no invocations
of compile_object and friends between it and the point where we
set $werror explicitly based on the --enable-werror command line
option.
2. Provide a mechanism for filtering QEMU_CFLAGS to create
QEMU_CXXFLAGS, and use it for the test we run here.
3. Provide a do_cxx function to run a test with the C++ compiler
rather than doing cute tricks with subshells and do_cc.
4. Use a new temporary file TMPCXX for the C++ program fragment.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id:
1393352869-22257-1-git-send-email-peter.maydell@linaro.org
Tested-by: Andreas Färber <afaerber@suse.de>
Cornelia Huck [Wed, 6 Feb 2013 09:31:37 +0000 (10:31 +0100)]
s390x/virtio-ccw: Adapter interrupt support.
Handle the new CCW_CMD_SET_IND_ADAPTER command enabling adapter interrupts
on guest request. When active, host->guest notifications will be handled
via global_indicator -> queue indicators instead of queue indicators +
subchannel I/O interrupt. Indicators for virtqueues may be present at an
offset.
Acked-by: Christian Borntraeger <borntraeger@de.ibm.com>
Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
Alexey Kardashevskiy [Sat, 1 Feb 2014 14:45:52 +0000 (01:45 +1100)]
target-ppc: spapr: e500: fix to use cpu_dt_id
This makes use of @cpu_dt_id and related API in:
1. emulated XICS hypercall handlers as they receive fixed CPU indexes;
2. XICS-KVM to enable in-kernel XICS on right CPU;
3. device-tree renderer.
This removes @cpu_index fixup as @cpu_dt_id is used instead so QEMU monitor
can accept command-line CPU indexes again.
This changes kvm_arch_vcpu_id() to use ppc_get_vcpu_dt_id() as at the moment
KVM CPU id and device tree ID are calculated using the same algorithm.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Acked-by: Mike Day <ncmike@ncultra.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexey Kardashevskiy [Sat, 1 Feb 2014 14:45:51 +0000 (01:45 +1100)]
target-ppc: add PowerPCCPU::cpu_dt_id
Normally CPUState::cpu_index is used to pick the right CPU for various
operations. However default consecutive numbering does not always work
for POWERPC.
These indexes are reflected in /proc/device-tree/cpus/PowerPC,POWER7@XX
and used to call KVM VCPU's ioctls. In order to achieve this,
kvmppc_fixup_cpu() was introduced. Roughly speaking, it multiplies
cpu_index by the number of threads per core.
This approach has disadvantages such as:
1. NUMA configuration stays broken after the fixup;
2. CPU-targeted commands from the QEMU Monitor do not work properly as
CPU indexes have been fixed and there is no clear way for the user to
know what the new CPU indexes are.
This introduces a @cpu_dt_id field in the CPUPPCState struct which
is initialized from @cpu_index by default and can be fixed later
to meet the device tree requirements.
This adds an API to handle @cpu_dt_id.
This removes kvmppc_fixup_cpu() as it is not more needed, @cpu_dt_id
is calculated in ppc_cpu_realize().
This will be used later in machine code.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Acked-by: Mike Day <ncmike@ncultra.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
Laurent Dufour [Fri, 21 Feb 2014 09:29:06 +0000 (10:29 +0100)]
target-ppc: Introduce hypervisor call H_GET_TCE
This patch introduces the hypervisor call H_GET_TCE which is basically the
reverse of H_PUT_TCE, as defined in the Power Architecture Platform
Requirements (PAPR).
The hcall H_GET_TCE is required by the kdump kernel which is calling it to
retrieve the TCE set up by the panicing kernel.
Signed-off-by: Laurent Dufour <ldufour@linux.vnet.ibm.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Aneesh Kumar K.V [Thu, 20 Feb 2014 17:52:38 +0000 (18:52 +0100)]
target-ppc: Update ppc_hash64_store_hpte to support updating in-kernel htab
This support updating htab managed by the hypervisor. Currently we don't have
any user for this feature. This actually bring the store_hpte interface
in-line with the load_hpte one. We may want to use this when we want to
emulate henter hcall in qemu for HV kvm.
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
[ folded fix for the "warn_unused_result" build break in
kvmppc_hash64_write_pte(), Greg Kurz <gkurz@linux.vnet.ibm.com> ]
Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Aneesh Kumar K.V [Thu, 20 Feb 2014 17:52:31 +0000 (18:52 +0100)]
target-ppc: Change the hpte store API
For updating in kernel htab we need to provide both pte0 and pte1, hence update
the interface to take pte0 and pte1 together
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
[ ldq_phys() API change, Greg Kurz <gkurz@linux.vnet.ibm.com> ]
Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Aneesh Kumar K.V [Thu, 20 Feb 2014 17:52:24 +0000 (18:52 +0100)]
target-ppc: Fix page table lookup with kvm enabled
With kvm enabled, we store the hash page table information in the hypervisor.
Use ioctl to read the htab contents. Without this we get the below error when
trying to read the guest address
(gdb) x/10 do_fork
0xc000000000098660 <do_fork>: Cannot access memory at address 0xc000000000098660
(gdb)
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
[ fixes for 32 bit build (casts!), ldq_phys() API change,
Greg Kurz <gkurz@linux.vnet.ibm.com ]
Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Aneesh Kumar K.V [Thu, 20 Feb 2014 17:52:17 +0000 (18:52 +0100)]
target-ppc: Fix htab_mask calculation
Correctly update the htab_mask using the return value of
KVM_PPC_ALLOCATE_HTAB ioctl. Also we don't update sdr1
on GET_SREGS for HV. We check for external htab and if
found true, we don't need to update sdr1
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
[ fixed pte group offset computation in ppc_hash64_htab_lookup() that
caused TCG to fail, Greg Kurz <gkurz@linux.vnet.ibm.com> ]
Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Tom Musta [Mon, 24 Feb 2014 14:16:16 +0000 (08:16 -0600)]
target-ppc: Use Additional Temporary in stqcx Case
Per Alex Graf's suggestion, the recently added case to gen_conditional_store
for stqcx should use an additional temporary when accessing the second
doubleword. This avoids the mutation of the EA argument to the function,
which is counter intuitive.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Tom Musta [Mon, 24 Feb 2014 14:12:13 +0000 (08:12 -0600)]
target-ppc: Fix Compiler Warnings Due to 64-Bit Constants Declared as UL
This patch fixes 64 bit constants that were erroneously declared as "ul" instead of
"ull". The preferred form "ULL" is used.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Fri, 21 Feb 2014 09:38:51 +0000 (10:38 +0100)]
PPC: sPAPR: Only use getpagesize() when we run with kvm
We currently size the msi window trap page according to the host's page
size so that we poke a working hole into a memory slot in case we overlap.
However, this is only ever necessary with KVM active. Without KVM, we should
rather try to be host platform agnostic and use a constant size: 4k.
This fixes a build breakage on win32 hosts.
Signed-off-by: Alexander Graf <agraf@suse.de>
Peter Maydell [Thu, 20 Feb 2014 19:47:27 +0000 (19:47 +0000)]
target-ppc/translate.c: Use ULL suffix for 64 bit constants
64 bit constants need the "ULL" suffix, not just "UL", because
on 32 bit platforms 'long' is not large enough and this will
cause a compiler warning.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Stefan Weil <sw@weilnetz.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexey Kardashevskiy [Fri, 14 Feb 2014 01:27:04 +0000 (12:27 +1100)]
spapr-vlan: flush queue whenever can_receive can go from false to true
When the guests adds buffers to receive queue, the network device
should flush its queue of pending packets. This is done with
qemu_flush_queued_packets.
This adds a call to qemu_flush_queued_packets() which wakes up the main
loop and let QEMU update the network device status which now is "can
receive". The patch basically does the same thing as
e8b4c68 does.
Suggested-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Signed-off-by: Alexander Graf <agraf@suse.de>
Tom Musta [Wed, 12 Feb 2014 21:23:19 +0000 (15:23 -0600)]
target-ppc: Altivec 2.07: Vector Permute and Exclusive OR
This patch adds the Vector Permuate and Exclusive OR (vpermxor)
instruction introduced in Power ISA Version 2.07.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Tom Musta [Wed, 12 Feb 2014 21:23:18 +0000 (15:23 -0600)]
target-ppc: Altivec 2.07: Vector SHA Sigma Instructions
This patch adds the Vector SHA Sigma instructions introduced in Power
ISA Version 2.07:
- Vector SHA-512 Sigma Doubleword (vshasigmad)
- Vector SHA-256 Sigma Word (vshasigmaw)
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Tom Musta [Wed, 12 Feb 2014 21:23:17 +0000 (15:23 -0600)]
target-ppc: Altivec 2.07: AES Instructions
This patch adds the Vector AES instructions introduced in Power ISA
Version 2.07:
- Vector AES Cipher (vcipher)
- Vector AES Cipher Last (vcipherlast)
- Vector AES Inverse Cipher (vncipher)
- Vector AES Inverse Cipher Last (vncipherlast)
- Vector AES SubBytes (vsbox)
Note that the implementation of vncipher deviates from the RTL in
ISA V2.07. However it does match the verbal description in the
third paragraph. The RTL will be fixed in ISA V2.07B. The
implementation here has been tested against actual P8 hardware.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Tom Musta [Wed, 12 Feb 2014 21:23:16 +0000 (15:23 -0600)]
target-ppc: Altivec 2.07: Binary Coded Decimal Instructions
This patch add the Binary Coded Decimal instructions bcdadd. and
bcdsub.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Tom Musta [Wed, 12 Feb 2014 21:23:15 +0000 (15:23 -0600)]
target-ppc: Altivec 2.07: Vector Polynomial Multiply Sum
This patch adds the Vectory Polynomial Multiply Sum instructions
introduced in Power ISA Version 2.07:
- Vectory Polynomial Multiply Sum Byte (vpmsumb)
- Vectory Polynomial Multiply Sum Halfword (vpmsumh)
- Vectory Polynomial Multiply Sum Word (vpmsumw)
- Vectory Polynomial Multiply Sum Doubleword (vpmsumd)
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Tom Musta [Wed, 12 Feb 2014 21:23:14 +0000 (15:23 -0600)]
target-ppc: Altivec 2.07: Vector Gather Bits by Bytes
This patch adds the Vector Gather Bits by Bytes Doubleword (vgbbd)
instruction which is introduced in Power ISA Version 2.07.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Tom Musta [Wed, 12 Feb 2014 21:23:13 +0000 (15:23 -0600)]
target-ppc: Altivec 2.07: Doubleword Compares
This patch adds the Vector Compare Doubleword instructions introduced
by Power ISA Version 2.07:
- Vector Compare Equal to Unsigned Doubleword (vcmpequd)
- Vector Compare Greater Than Signed Doubleword (vcmpgtsd)
- Vector Compare Greater Than Unsigned Doubleword (vcmpgtud)
These instructions are encoded with bit 31 set to 1 and so are duals with
vcmpeqfp, vcmpgtfp and vcmpbfp respectively.
The helper macro for integer compares is enhanced to account for 64-bit
operands.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Tom Musta [Wed, 12 Feb 2014 21:23:12 +0000 (15:23 -0600)]
target-ppc: Altivec 2.07: vbpermq Instruction
This patch adds the Vector Bit Permute Quadword (vbpermq) instruction
introduced in Power ISA Version 2.07.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Tom Musta [Wed, 12 Feb 2014 21:23:11 +0000 (15:23 -0600)]
target-ppc: Altivec 2.07: Quadword Addition and Subtracation
This patch adds the Vector Quadword Addition and Subtraction instructions
introduced in Power ISA Version 2.07:
- Vector Add Unsigned Quadword Modulo (vadduqm)
- Vector Add & Write Carry Unsigned Quadword (vaddcuq)
- Vector Add Extended Unsigned Quadword (vaddeuqm)
- Vector Add Extended & Write Carry Unsigned Quadword (vaddecuq)
- Vector Subtract Unsigned Quadword Modulo (vsubuqm)
- Vector Subtract & Write Carry Unsigned Quadword (vsubcuq)
- Vector Subtract Extended Unsigned Quadword (vsubeuqm)
- Vector Subtract Extended & Write Carry Unsigned Quadword (vsubecuq)
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Tom Musta [Wed, 12 Feb 2014 21:23:10 +0000 (15:23 -0600)]
target-ppc: Altivec 2.07: Vector Doubleword Rotate and Shift Instructions
This patch adds the vector doublword rotate and shift instructions
introduced in Power ISA Version 2.07:
- Vector Rotate Left Doubleword instruction (vrld)
- Vector Shift Left Doubleword (vsld)
- Vector Shift Right Doubleword (vsrd)
- Vector Shift Right Algegbraic Doubleword (vsrad)
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Tom Musta [Wed, 12 Feb 2014 21:23:09 +0000 (15:23 -0600)]
target-ppc: Altivec 2.07: Change Bit Masks to Support 64-bit Rotates and Shifts
Existing code in the VROTATE, VSL and VSR macros for the Altivec rotate and shift
helpers uses a formula to compute a bit mask used to extract the rotate/shift
amount from the VRB register. What is desired is:
mask = (1 << (3 + log2(sizeof(element)))) - 1
but what is implemented is:
mask = (1 << (3 + (sizeof(element)/2))) - 1
This produces correct answers when "element" is uint8_t, uint16_t or uint_32t. But
it breaks down when element is uint64_t.
This patch corrects the situation. Since the mask is known at compile time, the
macros are changed to simply accept the mask as an argument.
Subsequent patches in this series will add double-word variants of rotates and
shifts and thus take advantage of this fix.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Tom Musta [Wed, 12 Feb 2014 21:23:08 +0000 (15:23 -0600)]
target-ppc: Altivec 2.07: Vector Merge Instructions
This patch adds the Vector Merge Even Word (vmrgew) and Vector
Merge Odd Word (vmrgow) instructions introduced in Power ISA
Version 2.07.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Tom Musta [Wed, 12 Feb 2014 21:23:07 +0000 (15:23 -0600)]
target-ppc: Altivec 2.07: Unpack Signed Word Instructions
This patch adds the Unpack Signed Word instructions introduced in
Power ISA Version 2.07:
- Vector Unpack High Signed Word (vupkusw)
- Vector Unpack Low Signed Word (vupklsw)
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Tom Musta [Wed, 12 Feb 2014 21:23:06 +0000 (15:23 -0600)]
target-ppc: Altivec 2.07: Pack Doubleword Instructions
This patch adds the Vector Pack Doubleword instructions introduced in
Power ISA Version 2.07:
- Vector Pack Signed Doubleword Signed Saturate (vpksdss)
- Vector Pack Signed Doubleword Unsigned Saturate (vpksdus)
- Vector Pack Unsigned Doubleword Unsigned Modulo (vpkudum)
- Vector Pack Unsigned Doubleword Unsigned Saturate (vpkudus)
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Tom Musta [Wed, 12 Feb 2014 21:23:05 +0000 (15:23 -0600)]
target-ppc: Altivec 2.07: Vector Min/Max Doubleword Instructions
This patch adds the Vector Minimum and Maximum Doubleword instructions
that are introduced in Power ISA Version 2.07.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Tom Musta [Wed, 12 Feb 2014 21:23:04 +0000 (15:23 -0600)]
target-ppc: Altivec 2.07: Vector Population Count Instructions
This patch adds the Vector Population Count instructions introduced in Power
ISA Version 2.07: vpopcntb, vpopcnth, vpopcntw and vpopcntd.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Tom Musta [Wed, 12 Feb 2014 21:23:03 +0000 (15:23 -0600)]
target-ppc: Altivec 2.07: Add Vector Count Leading Zeroes
This patch adds the Vector Count Leading Zeroes instructions introduced
in Power ISA Version 2.07 - vclzb, vclzh, vclzw and vclzd.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Tom Musta [Wed, 12 Feb 2014 21:23:02 +0000 (15:23 -0600)]
target-ppc: Altivec 2.07: vmuluw Instruction
This patch adds the Vector Multiply Unsigned Word Modulo (vmuluwm)
instruction.
The existing VARITH_DO macro is re-used to (trivially) instantiate
the helper code.
Since bits 21-31 of any vmuluwm instruction is 137, the instruction
is coded as a dual to vmulouw (bits 21-31 = 136).
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Tom Musta [Wed, 12 Feb 2014 21:23:01 +0000 (15:23 -0600)]
target-ppc: Altivec 2.07: Multiply Even/Odd Word Instructions
This patch adds the Multilpy Even/Odd Word instructions that are introduced
in Power ISA Version 2.07:
- Vector Multiply Even Unsigned Word (vmuleuw)
- Vector Multiply Even Signed Word (vmulesw)
- Vector Multiply Odd Unsigned Word (vmulouw)
- Vector Multiply Odd Signed Word (vmulosw)
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Tom Musta [Wed, 12 Feb 2014 21:23:00 +0000 (15:23 -0600)]
target-ppc: Altivec 2.07: Change VMUL_DO to Support 64-bit Integers
This VMUL_DO macro provides support for the various vmule* and vmulo*
instructions. These instructions multiply vector elements, producing
products that are one size larger; e.g. vmuleub multiplies unsigned 8-bit
elements and produces a 16 bit unsigned element.
The existing macro works correctly for the existing instructions (8-bit,
and 16-bit source elements) but does not work correctly for 32-bit
source elements.
This patch adds an explicit cast to the multiplicands, forcing them to be
of the target element type. This is required for the forthcoming patches
that add the vmul[eo][us]w instructions.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Tom Musta [Wed, 12 Feb 2014 21:22:59 +0000 (15:22 -0600)]
target-ppc: Altivec 2.07: Add/Subtract Unsigned Doubleword Modulo
This patch adds two Altivec unsigned doublword modulo instructions that
are introduced in Power ISA Version V2.07:
- vaddudm : Vector Add Unsigned Doubleword Modulo
- vsubudm : Vector Subtrace Unsigned Doubleword Modulo
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Tom Musta [Wed, 12 Feb 2014 21:22:58 +0000 (15:22 -0600)]
target-ppc: Altivec 2.07: Vector Logical Instructions
This patch adds the Vector Logical Instructions that are introduced
in Power ISA Version 2.07: veqv, vnand and vorc.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Tom Musta [Wed, 12 Feb 2014 21:22:57 +0000 (15:22 -0600)]
target-ppc: Altivec 2.07: Add Support for R-Form Dual Instructions
Some Alitvec instructions introduced in Power ISA Version 2.07 use bit 31
(aka the "Rc" bit) as an opcode but also use bit 21 as an actual Rc
bit. QEMU for PowerPC typically uses bits 0-5 and 21-30 for opcodes.
This patch introduces a generator macro that injects an auxiliary handler
which decodes both bits 21 and 31 and invokes one of four standard
handlers. Since the instructions are not, in general, from the same version
of the ISA, two sets of PPC_*/PPC2_* flags are supported.
This patch also introduces a macro to insert two entries into the opcode
table -- one for bit 21 equal to 0 and one for bit 21 equal to 1.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Tom Musta [Wed, 12 Feb 2014 21:22:56 +0000 (15:22 -0600)]
target-ppc: Altivec 2.07: Add Opcode Macro for VX Form Instructions
This patch adds a macro to insert an entry into the opcode table for Altivec
Power ISA Version 2.07 instructions. The macro is similar to the GEN_VXFORM macro
except that it tags the entry with the PPC2_ALTIVEC_207 flag rather than
PPC_ALTIVEC.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Tom Musta [Wed, 12 Feb 2014 21:22:55 +0000 (15:22 -0600)]
target-ppc: Altivec 2.07: Add Support for Dual Altivec Instructions
Some Alitvec instructions introduced in Power ISA Version 2.07 use bit 31
(aka the "Rc" bit) as an opcode bit. However, QEMU for PowerPC uses
bits 0-5 and 21-30 for opcodes and not bit 31.
This patch introduces macros that will handle this situation by injecting
an auxiliary handler which decodes bit 31 in invokes one of two standard
handlers. Since the instructions are not, in general, from the same version
of the ISA, two sets of PPC_*/PPC2_* instruction tags are supported.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Tom Musta [Wed, 12 Feb 2014 21:22:54 +0000 (15:22 -0600)]
target-ppc: Altivec 2.07: Add GEN_VXFORM3
This patch adds generator macro for Altivec instructions that have 3
source AVR operands. The macro is similar to the 2 operand form.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Tom Musta [Wed, 12 Feb 2014 21:22:53 +0000 (15:22 -0600)]
target-ppc: Altivec 2.07: Update AVR Structure
This patch updates the ppc_avr_t data structure to include elements for
signed 64-bit integers and (conditionally) unsigned 128 bit integers.
These elements will be in instructions models later on in this patch series.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Tom Musta [Wed, 12 Feb 2014 21:22:52 +0000 (15:22 -0600)]
target-ppc: Altivec 2.07: Add Instruction Flag
This patch adds a flag that will be used to tag the Altivec instructions
introduced in Power ISA Version 2.07.
The flag is added to Power8 model since P8 supports these instructions.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Tom Musta [Mon, 10 Feb 2014 17:27:01 +0000 (11:27 -0600)]
target-ppc: Add Store Quadword Conditional
This patch adds the Store Quadword Conditionl (stqcx.) instruction
which is introduced in Power ISA 2.07.
Signed-off-by: Tom Musta <tommusta@gmail.com>
[agraf: fix compile error when !TARGET_PPC64]
Signed-off-by: Alexander Graf <agraf@suse.de>
Tom Musta [Mon, 10 Feb 2014 17:27:00 +0000 (11:27 -0600)]
target-ppc: Add Load Quadword and Reserve
This patch adds the Load Quadword and Reserve (lqarx) instruction,
which is new in Power ISA 2.07.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Tom Musta [Mon, 10 Feb 2014 17:26:59 +0000 (11:26 -0600)]
target-ppc: Store Quadword
This patch adds support for the Store Quadword instruction in user mode. Prior
to Power ISA 2.07, stq was legal only in privileged mode. Support for Little
Endian mode is also new in ISA 2.07.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Tom Musta [Mon, 10 Feb 2014 17:26:58 +0000 (11:26 -0600)]
target-ppc: Load Quadword
This patch adds the Book I (user space) Load Quadword (lq) instruction.
This instruction was introduced into Book I in Power ISA V2.07. Previous
versions of the architecture supported this as a privileged instruction.
Previous versions of the architecture also did not support Little Endian
mode.
Note that this patch also adds the PPC_64BX flag to the Power8 model,
which enables the lq instruction.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Tom Musta [Mon, 10 Feb 2014 17:26:57 +0000 (11:26 -0600)]
target-ppc: Add is_user_mode Utility Routine
This patch adds a boolean function is_user_mode that can be re-used
in translation code that is sensitive to the MSR[PR] (user-mode)
state.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Tom Musta [Mon, 10 Feb 2014 17:26:56 +0000 (11:26 -0600)]
target-ppc: Add Flag for ISA 2.07 Load/Store Quadword Instructions
This patch adds a flag to identify the load/store quadword instructions
that are introduced with Power ISA 2.07.
The flag is added to the Power8 model since P8 supports these
instructions.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Tom Musta [Mon, 10 Feb 2014 17:26:55 +0000 (11:26 -0600)]
target-ppc: Add bctar Instruction
This patch adds the Branch Conditional to Address Register (bctar)
instruction.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Tom Musta [Mon, 10 Feb 2014 17:26:54 +0000 (11:26 -0600)]
target-ppc: Add Target Address SPR (TAR) to Power8
This patch adds support for the Target Address Register (TAR) to the Power8
model.
Because supported SPRs are typically identified in an init_proc_*()
function and because the Power8 model is currently just using the
init_proc_POWER7() function, a new init_proc_POWER8() function
is added and plugged into the P8 model.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Tom Musta [Mon, 10 Feb 2014 17:26:53 +0000 (11:26 -0600)]
target-ppc: Add Flag for bctar
This patch adds a flag for the bctar instruction. This instruction
is being introduced via Power ISA 2.07.
Also, the flag is added to the Power8 machine model since the P8
processor supports this instruction.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Tom Musta [Mon, 10 Feb 2014 17:25:09 +0000 (11:25 -0600)]
target-ppc: Fix xxpermdi When T==A or T==B
The existing implementation of xxpermdi is defective if the target
VSR is also a source VSR. This patch fixes the defect in this case
but also preserves the simpler, two TCG operation implementation
when the target is not once of the two sources.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
CĂ©dric Le Goater [Thu, 20 Feb 2014 13:20:35 +0000 (14:20 +0100)]
target-ppc: add extended opcodes for dcbt/dcbtst
The latest glibc provides a memrchr routine using an extended opcode
of the 'dcbt' instruction :
00000000000a7cc0 <memrchr>:
a7cc0: 11 00 4c 3c addis r2,r12,17
a7cc4: b8 f8 42 38 addi r2,r2,-1864
a7cc8: 14 2a e3 7c add r7,r3,r5
a7ccc: d0 00 07 7c neg r0,r7
a7cd0: ff ff e7 38 addi r7,r7,-1
a7cd4: 78 1b 6a 7c mr r10,r3
a7cd8: 24 06 e6 78 rldicr r6,r7,0,56
a7cdc: 60 00 20 39 li r9,96
a7ce0: 2c 32 09 7e dcbtt r9,r6
....
which breaks grep, and other commands, in TCG mode :
invalid bits:
02000000 for opcode: 1f - 16 - 08 (
7e09322c)
00003fff799feca0
This patch adds the extended opcodes for dcbt/dcbtst as no-ops just
like the 'dcbt' instruction.
Signed-off-by: CĂ©dric Le Goater <clg@fr.ibm.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexander Graf [Thu, 6 Feb 2014 15:08:15 +0000 (16:08 +0100)]
qdev: Keep global allocation counter per bus
When we have 2 separate qdev devices that both create a qbus of the
same type without specifying a bus name or device name, we end up
with two buses of the same name, such as ide.0 on the Mac machines:
dev: macio-ide, id ""
bus: ide.0
type IDE
dev: macio-ide, id ""
bus: ide.0
type IDE
If we now spawn a device that connects to a ide.0 the last created
bus gets the device, with the first created bus inaccessible to the
command line.
After some discussion on IRC we concluded that the best quick fix way
forward for this is to make automated bus-class type based allocation
count a global counter. That's what this patch implements. With this
we instead get
dev: macio-ide, id ""
bus: ide.1
type IDE
dev: macio-ide, id ""
bus: ide.0
type IDE
on the example mentioned above.
This also means that if you did -device ...,bus=ide.0 you got a device
on the first bus (the last created one) before this patch and get that
device on the second one (the first created one) now. Breaks
migration unless you change bus=ide.0 to bus=ide.1 on the destination.
This is intended and makes the bus enumeration work as expected.
As per review request follows a list of otherwise affected boards and
the reasoning for the conclusion that they are ok:
target machine bus id times
------ ------- ------ -----
aarch64 n800 i2c-bus.0 2
aarch64 n810 i2c-bus.0 2
arm n800 i2c-bus.0 2
arm n810 i2c-bus.0 2
-> Devices are only created explicitly on one of the two buses, using
s->mpu->i2c[0], so no change to the guest.
aarch64 vexpress-a15 virtio-mmio-bus.0 4
aarch64 vexpress-a9 virtio-mmio-bus.0 4
aarch64 virt virtio-mmio-bus.0 32
arm vexpress-a15 virtio-mmio-bus.0 4
arm vexpress-a9 virtio-mmio-bus.0 4
arm virt virtio-mmio-bus.0 32
-> Makes -device bus= work for all virtio-mmio buses. Breaks
migration. Workaround for migration from old to new: specify
virtio-mmio-bus.4 or .32 respectively rather than .0 on the
destination.
aarch64 xilinx-zynq-a9 usb-bus.0 2
arm xilinx-zynq-a9 usb-bus.0 2
mips64el fulong2e usb-bus.0 2
-> Normal USB operation not affected. Migration driver needs command
line to use the other bus.
i386 isapc ide.0 2
x86_64 isapc ide.0 2
mips mips ide.0 2
mips64 mips ide.0 2
mips64el mips ide.0 2
mipsel mips ide.0 2
ppc g3beige ide.0 2
ppc mac99 ide.0 2
ppc prep ide.0 2
ppc64 g3beige ide.0 2
ppc64 mac99 ide.0 2
ppc64 prep ide.0 2
-> Makes -device bus= work for all IDE buses. Breaks migration.
Workaround for migration from old to new: specify ide.1 rather than
ide.0 on the destination.
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Andreas Faerber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
Aneesh Kumar K.V [Tue, 28 Jan 2014 07:59:59 +0000 (13:29 +0530)]
target-ppc: Update external_htab even when HTAB is managed by kernel
We will use this in later patches to make sure we use the right load
functions when copying hpte entries.
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexey Kardashevskiy [Tue, 4 Feb 2014 04:04:19 +0000 (15:04 +1100)]
spapr: print more detailed error message on failed load_elf()
This makes use of new error codes which load_elf() can return and
prints more informative error message.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexey Kardashevskiy [Tue, 4 Feb 2014 04:04:18 +0000 (15:04 +1100)]
elf-loader: add more return codes
The existing load_elf() just returns -1 if it fails to load ELF. However
it could be smarter than this and tell more about the failure such as
wrong endianness or incompatible platform.
This adds additional return codes for wrong architecture, wrong
endianness and if the image is not ELF at all.
This adds a load_elf_strerror() helper to convert return codes into
string messages.
This fixes handling of what load_elf() returns for s390x, other
callers just check the return value for <0 and this remains unchanged.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexey Kardashevskiy [Tue, 4 Feb 2014 04:04:17 +0000 (15:04 +1100)]
moxie: fix load_elf() usage
At the moment in the case of error, load_elf() returns -1 so load_kernel()
will not signal error at all.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexey Kardashevskiy [Tue, 4 Feb 2014 04:04:16 +0000 (15:04 +1100)]
spapr: support only ELF kernel images
Currently everybody uses ELF kernel images with "-kernel" option on
pseries machine but QEMU still tries to boot from an image even it
fails to recognize it is ELF. This produces undefined behaviour if
the user tries a kernel image compiled for another architecture.
This removes support of raw kernel images.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Signed-off-by: Alexander Graf <agraf@suse.de>
Fabien Chouteau [Wed, 5 Feb 2014 13:59:28 +0000 (14:59 +0100)]
Add Enhanced Three-Speed Ethernet Controller (eTSEC)
This implementation doesn't include ring priority, TCP/IP Off-Load, QoS.
Signed-off-by: Fabien Chouteau <chouteau@adacore.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexey Kardashevskiy [Tue, 4 Feb 2014 04:12:34 +0000 (15:12 +1100)]
PPC: KVM: suppress warnings about not supported SPRs
PR KVM lacks support of many SPRs in set/get one register API but it does
really break PR KVM. So convert them to switchable traces for now.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Signed-off-by: Alexander Graf <agraf@suse.de>
Edgar E. Iglesias [Mon, 3 Feb 2014 15:20:20 +0000 (15:20 +0000)]
virtex_ml507: Add support for loading initrd images
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
[agraf: fix up stray quotes and newlines in strings]
Signed-off-by: Alexander Graf <agraf@suse.de>
Alexey Kardashevskiy [Fri, 31 Jan 2014 02:24:00 +0000 (13:24 +1100)]
PPC: KVM: store SLB slot number
When ppc_store_slb() is called from kvm_arch_get_registers(), it stores
a SLB in CPUPPCState::slb[slot]. However it drops the slot number from
ESID so when kvm_arch_put_registers() puts SLBs back to KVM, they do not
have correct "index" field anymore. This broke migration with LPCR_AIR
enabled as now the guest is handling interrupts in virtual mode and unable
to reconstruct correct SLBs anymore.
This adds "index" field for valid SLBs when putting them to KVM.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Reviewed-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Cc: qemu-stable@nongnu.org
Signed-off-by: Alexander Graf <agraf@suse.de>
Tom Musta [Tue, 7 Jan 2014 16:06:10 +0000 (10:06 -0600)]
target-ppc: Add ISA2.06 lfiwzx Instruction
This patch adds the Load Floating Point as Integer Word and
Zero Indexed (lfiwzx) instruction which was introduced in
Power ISA 2.06.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
Tom Musta [Tue, 7 Jan 2014 16:06:09 +0000 (10:06 -0600)]
target-ppc: Enable frsqrtes on Power7 and Power8
The frsqrtes instruction was introduced prior to ISA 2.06 and is
support on both the Power7 and Power8 processors. However, this
instruction is handled as illegal in the current QEMU emulation
machines. This patch enables the existing implemention of frsqrtes
in the P7 and P8 machines.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
Tom Musta [Tue, 7 Jan 2014 16:06:08 +0000 (10:06 -0600)]
target-ppc: Add ISA 2.06 ftsqrt
This patch adds the Floating Point Test for Square Root instruction
which was introduced in Power ISA 2.06.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
Tom Musta [Tue, 7 Jan 2014 16:06:07 +0000 (10:06 -0600)]
target-ppc: Add ISA 2.06 ftdiv Instruction
This patch adds the Floating Point Test for Divide instruction which
was introduced in Power ISA 2.06B.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
Tom Musta [Tue, 7 Jan 2014 16:06:06 +0000 (10:06 -0600)]
target-ppc: Add Flag for Power ISA V2.06 Floating Point Test Instructions
This patch adds a flag for Floating Point Test instructions that were
introduced in Power ISA V2.06B.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
Tom Musta [Tue, 7 Jan 2014 16:06:05 +0000 (10:06 -0600)]
target-ppc: Fix and enable fri[mnpz]
The fri* series of instructions was introduced prior to ISA 2.06 and
is supported on Power7 and Power8 hardware. However, the instruction
is still considered illegal in the P7 and P8 QEMU emulation models.
This patch enables these instructions for the P7 and P8 machines.
Also, the existing helper is modified to correctly handle some of
the boundary cases (NaNs and the inexact flag).
Signed-off-by: Tom Musta <tommusta@gmail.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
Tom Musta [Tue, 7 Jan 2014 16:06:00 +0000 (10:06 -0600)]
target-ppc: Add ISA 2.06 fcfid[u][s] Instructions
This patch adds the fcfids, fcfidu and fcfidus instructions which
were introduced in Power ISA 2.06B. A common macro is provided to
eliminate repetitious code, and the existing fcfid instruction is
refactored to use this macro.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
Tom Musta [Tue, 7 Jan 2014 16:05:59 +0000 (10:05 -0600)]
target-ppc: Add ISA2.06 Float to Integer Instructions
This patch adds the four floating point to integer conversion instructions
introduced by Power ISA V2.06:
- Floating Convert to Integer Word Unsigned (fctiwu)
- Floating Convert to Integer Word Unsigned with Round Toward
Zero (fctiwuz)
- Floating Convert to Integer Doubleword Unsigned (fctidu)
- Floating Convert to Integer Doubleword Unsigned with Round
Toward Zero (fctiduz)
A common macro is developed to eliminate repetitious code. Existing instructions
are also refactoried to use this macro (fctiw, fctiwz, fctid, fctidz).
Signed-off-by: Tom Musta <tommusta@gmail.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
Tom Musta [Tue, 7 Jan 2014 16:05:58 +0000 (10:05 -0600)]
target-ppc: Add Flag for ISA V2.06 Floating Point Conversion
This patch adds a flag for the floating point conversion instructions
introduced in Power ISA 2.06B.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
Tom Musta [Tue, 7 Jan 2014 16:05:57 +0000 (10:05 -0600)]
target-ppc: Add ISA 2.06 stbcx. and sthcx. Instructions
This patch adds the byte and halfword variants of the Store Conditional
instructions. A common macro is introduced and the existing implementations
of stwcx. and stdcx. are refactored to use this macro.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
Tom Musta [Tue, 7 Jan 2014 16:05:56 +0000 (10:05 -0600)]
target-ppc: Add ISA2.06 lbarx, lharx Instructions
This patch adds the byte and halfword variants of the Load and
Reserve instructions. Since there is much commonality among
all forms of Load and Reserve, a macro is provided and the existing
implementations of lwarx and ldarx are refactoried to use this
macro.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
Tom Musta [Tue, 7 Jan 2014 16:05:55 +0000 (10:05 -0600)]
target-ppc: Add Flag for ISA2.06 Atomic Instructions
This patch adds a flag for the atomic instructions introduced
in Power ISA V2.06B.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
Tom Musta [Tue, 7 Jan 2014 16:05:54 +0000 (10:05 -0600)]
target-ppc: Add ISA 2.06 divwe[o] Instructions
This patch addes the signed Divide Word Extended instructions
which were introduced in Power ISA 2.06B.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
Tom Musta [Tue, 7 Jan 2014 16:05:53 +0000 (10:05 -0600)]
target-ppc: Add ISA 2.06 divweu[o] Instructions
This patch addes the Unsigned Divide Word Extended instructions
which were introduced in Power ISA 2.06B.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
Tom Musta [Tue, 7 Jan 2014 16:05:52 +0000 (10:05 -0600)]
target-ppc: Add ISA2.06 divde[o] Instructions
This patch adds the Divide Doubleword Extended instructions.
The implementation builds on the unsigned helper provided in
the previous patch.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
Tom Musta [Tue, 7 Jan 2014 16:05:51 +0000 (10:05 -0600)]
target-ppc: Add ISA2.06 divdeu[o] Instructions
This patch adds the Divide Doubleword Extended Unsigned
instructions. This instruction requires dividing a 128-bit
value by a 64 bit value. Since 128 bit integer division is
not supported in TCG, a helper is used. An architecture
independent 128-bit division routine is added to host-utils.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
[agraf: use ||]
Signed-off-by: Alexander Graf <agraf@suse.de>
Tom Musta [Tue, 7 Jan 2014 16:05:50 +0000 (10:05 -0600)]
target-ppc: Add Flag for ISA2.06 Divide Extended Instructions
This patch adds a flag for the Divide Extended instructions that
were introduced in Power ISA V2.06B. The flag is added to the
Power7 and Power8 models.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
Tom Musta [Tue, 7 Jan 2014 16:05:49 +0000 (10:05 -0600)]
target-ppc: Add ISA2.06 bpermd Instruction
This patch adds the Bit Permute Doubleword (bpermd) instruction,
which was introduced in Power ISA 2.06 as part of the base 64-bit
architecture.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
Tom Musta [Wed, 15 Jan 2014 14:10:45 +0000 (08:10 -0600)]
target-ppc: Scalar Non-Signalling Conversions
This patch adds the non-signalling scalar conversion instructions:
- VSX Scalar Convert Single Precision to Double Precision
Non-Signalling (xscvspdpn)
- VSX Scalar Convert Double Precision to Single Precision
Non-Signalling (xscvdpspn)
Signed-off-by: Tom Musta <tommusta@gmail.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
Tom Musta [Wed, 15 Jan 2014 14:10:44 +0000 (08:10 -0600)]
target-ppc: Scalar Round to Single Precision
This patch adds the VSX Scalar Round to Single Precision (xsrsp)
instruction.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
Tom Musta [Wed, 15 Jan 2014 14:10:43 +0000 (08:10 -0600)]
target-ppc: Floating Merge Word Instructions
This patch adds the Floating Merge Even Word (fmrgew) and Floating
Merge Odd Word (fmrgow) instructions.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
Tom Musta [Wed, 15 Jan 2014 14:10:42 +0000 (08:10 -0600)]
target-ppc: Move To/From VSR Instructions
This patch adds the Move To VSR instructions (mfvsrd, mfvsrwz)
and Move From VSR instructions (mtvsrd, mtvsrwa, mtvsrwz). These
instructions are unusual in that they are considered a floating
point instruction if the indexed VSR is in the first half of the
array (0-31) but they are considered vector instructions if the
indexed VSR is in the second half of the array (32-63).
Signed-off-by: Tom Musta <tommusta@gmail.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
Tom Musta [Wed, 15 Jan 2014 14:10:41 +0000 (08:10 -0600)]
target-ppc: VSX Stage 4: Add xxleqv, xxlnand and xxlorc
This patchs adds the VSX Logical instructions that are new with
ISA V2.07:
- VSX Logical Equivalence (xxleqv)
- VSX Logical NAND (xxlnand)
- VSX Logical ORC (xxlorc)
Signed-off-by: Tom Musta <tommusta@gmail.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
Tom Musta [Wed, 15 Jan 2014 14:10:40 +0000 (08:10 -0600)]
target-ppc: VSX Stage 4: Add xscvsxdsp and xscvuxdsp
This patch adds the VSX Scalar Convert Unsigned Integer Doubleword
to Floating Point Format and Round to Single Precision (xscvuxdsp)
and VSX Scalar Convert Signed Integer Douglbeword to Floating Point
Format and Round to Single Precision (xscvsxdsp) instructions.
The existing integer to floating point conversion macro (VSX_CVT_INT_TO_FP)
is modified to support the rounding of the intermediate floating point
result to single precision.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
Tom Musta [Wed, 15 Jan 2014 14:10:39 +0000 (08:10 -0600)]
target-ppc: VSX Stage 4: Add Scalar SP Fused Multiply-Adds
This patch adds the Single Precision VSX Scalar Fused Multiply-Add
instructions: xsmaddasp, xsmaddmsp, xssubasp, xssubmsp, xsnmaddasp,
xsnmaddmsp, xsnmsubasp, xsnmsubmsp.
The existing VSX_MADD() macro is modified to support rounding of the
intermediate double precision result to single precision.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
Tom Musta [Wed, 15 Jan 2014 14:10:38 +0000 (08:10 -0600)]
target-ppc: VSX Stage 4: add xsrsqrtesp
This patch adds the VSX Scalar Reciprocal Square Root Estimate
Single Precision (xsrsqrtesp) instruction.
The existing VSX_RSQRTE() macro is modified to support rounding
of the intermediate double-precision result to single precision.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
Tom Musta [Wed, 15 Jan 2014 14:10:37 +0000 (08:10 -0600)]
target-ppc: VSX Stage 4: Add xssqrtsp
This patch adds the VSX Scalar Square Root Single Precision (xssqrtsp)
instruction.
The existing VSX_SQRT() macro is modified to support rounding of the
intermediate double-precision result to single-precision.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
Tom Musta [Wed, 15 Jan 2014 14:10:36 +0000 (08:10 -0600)]
target-ppc: VSX Stage 4: Add xsresp
This patch adds the VSX Scalar Reciprocal Estimate Single Precision
(xsresp) instruction.
The existing VSX_RE macro is modified to support rounding of the
intermediate double precision result to single precision.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
Tom Musta [Wed, 15 Jan 2014 14:10:35 +0000 (08:10 -0600)]
target-ppc: VSX Stage 4: Add xsdivsp
This patch adds the VSX Scalar Divide Single Precision (xsdivsp)
instruction.
The existing VSX_DIV macro is modified to support rounding of the
intermediate double precision result to single precision.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
Tom Musta [Wed, 15 Jan 2014 14:10:34 +0000 (08:10 -0600)]
target-ppc: VSX Stage 4: Add xsmulsp
This patch adds the VSX Scalar Multiply Single-Precision (xsmulsp)
instruction.
The existing VSX_MUL macro is modified to support rounding of the
intermediate result to single precision.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
Tom Musta [Wed, 15 Jan 2014 14:10:33 +0000 (08:10 -0600)]
target-ppc: VSX Stage 4: Add xsaddsp and xssubsp
This patch adds the VSX Scalar Add Single-Precision (xsaddsp) and
VSX Scalar Subtract Single-Precision (xssubsp) instructions.
The existing VSX_ADD_SUB macro is modified to support the rounding
of the (intermediate) result to single-precision.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
Tom Musta [Wed, 15 Jan 2014 14:10:32 +0000 (08:10 -0600)]
target-ppc: VSX Stage 4: Add stxsiwx and stxsspx
This patch adds two store scalar instructions:
- Store VSX Scalar as Integer Word Indexed (stxsiwx)
- Store VSX Scalar Single-Precision Indexed (stxsspx)
Signed-off-by: Tom Musta <tommusta@gmail.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
Tom Musta [Wed, 15 Jan 2014 14:10:31 +0000 (08:10 -0600)]
target-ppc: VSX Stage 4: Refactor stxsdx
This patch refactors the stxsdx instruction. Reusable code is
extracted into a macro which will be used in subsequent patches
in this series.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
Tom Musta [Wed, 15 Jan 2014 14:10:30 +0000 (08:10 -0600)]
target-ppc: VSX Stage 4: Add lxsiwax, lxsiwzx and lxsspx
This patch adds the scalar load instructions introduced in ISA
V2.07:
- Load VSX Scalar as Integer Word Algebraic Indexd (lxsiwax)
- Load VSX Scalar as Integer Word and Zero Indexed (lxsiwzx)
- Load VSX Scalar Single-Precision Indexed (lxsspx)
Signed-off-by: Tom Musta <tommusta@gmail.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Alexander Graf <agraf@suse.de>