OSDN Git Service
Craig Topper [Tue, 21 Nov 2017 23:36:42 +0000 (23:36 +0000)]
[X86] Move the information about the feature bits used by compiler-rt and shared by Host.cpp to a .def file and TargetParser.h so clang can make use of it.
Since we keep Host.cpp and compiler-rt relatively in sync, clang can use this information as a proxy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318814
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Krzysztof Parzyszek [Tue, 21 Nov 2017 22:13:16 +0000 (22:13 +0000)]
[Hexagon] Add HexagonSubtarget::getVectorLength()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318807
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Peter Collingbourne [Tue, 21 Nov 2017 22:06:20 +0000 (22:06 +0000)]
Object: Improve COFF irsymtab comdat representation.
Change the representation of COFF comdats so that a COFF linker
is able to accurately resolve comdats between IR and native object
files. Specifically, apply name mangling to comdat names consistently
with native object files, and do not export comdats with an internal
leader because they do not affect symbol resolution.
Differential Revision: https://reviews.llvm.org/D40278
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318805
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Evandro Menezes [Tue, 21 Nov 2017 21:33:52 +0000 (21:33 +0000)]
[TableGen] Improve error reporting
When searching for a resource unit, use the reference location instead of
the definition location in case of an error.
Differential revision: https://reviews.llvm.org/D40263
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318803
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Krzysztof Parzyszek [Tue, 21 Nov 2017 21:05:51 +0000 (21:05 +0000)]
[Hexagon] Make sure that RDF does not remove EH_LABELs
Since EH_LABELs (and other labels) no longer have "side-effects", they
should be checked for separately.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318801
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Craig Topper [Tue, 21 Nov 2017 21:05:21 +0000 (21:05 +0000)]
[X86] Allow vpclmulqdq instructions to be commuted during isel to allow load folding.
The commuting patterns for the AVX version actually still had priority over the new patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318800
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Craig Topper [Tue, 21 Nov 2017 21:05:18 +0000 (21:05 +0000)]
[X86] Add BITALG, VAES, VBMI2, VNNI, VPCLMULQDQ, and VPOPCNTDQ instructions to icelake CPU.
This is based on table 1-1 of the October 2017 revision of Intel® Architecture Instruction Set Extensions and Future Features Programming Reference
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318799
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Nirav Dave [Tue, 21 Nov 2017 19:28:13 +0000 (19:28 +0000)]
Avoid unecessary opsize byte in segment move to memory
Segment moves to memory are always 16-bit. Remove invalid 32 and 64
bit variants.
Recommiting with missing clang inline assembly test change.
Fixes PR34478.
Reviewers: rnk, craig.topper
Subscribers: llvm-commits, hiraditya
Differential Revision: https://reviews.llvm.org/D39847
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318797
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Craig Topper [Tue, 21 Nov 2017 18:50:41 +0000 (18:50 +0000)]
[X86] Sort bits in getHostCPUFeatures again.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318792
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Chad Rosier [Tue, 21 Nov 2017 18:08:34 +0000 (18:08 +0000)]
[AArch64] Mark mrs of TPIDR_EL0 (thread pointer) as *having* side effects.
This partially reverts r298851. The the underlying issue is that we don't
currently model the dependency between mrs (read system register) and
msr (write system register) instructions.
Something like the below should never be reordered:
msr TPIDR_EL0, x0 ;; set thread pointer
mrs x8, TPIDR_EL0 ;; read thread pointer
but was being reordered after r298851. The functional part of the patch
that wasn't reverted needed to remain in place in order to not break
r299462.
PR35317
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318788
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Hans Wennborg [Tue, 21 Nov 2017 18:00:01 +0000 (18:00 +0000)]
Fix r318786
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318787
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Nuno Lopes [Tue, 21 Nov 2017 17:53:19 +0000 (17:53 +0000)]
removed unused private method decl. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318786
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Hans Wennborg [Tue, 21 Nov 2017 17:22:19 +0000 (17:22 +0000)]
Rename test/Transforms/CountingFunctionInserter -> EntryExitInstrumenter
The pass was renamed in r318195.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318784
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Hans Wennborg [Tue, 21 Nov 2017 17:22:19 +0000 (17:22 +0000)]
EntryExitInstrumenter: support __cyg_profile_func_enter_bare
It works just like __cyg_profile_func_enter but takes no arguments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318783
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Oliver Stannard [Tue, 21 Nov 2017 16:20:25 +0000 (16:20 +0000)]
[ARM] Remove pre-UAL FLDM/FSTM aliases
These are pre-UAL syntax, and we don't support any other pre-UAL instructions,
with the exception of FLDMX/FSTMX, which don't have a UAL equivalent. Therefore
there's no reason to keep them or their AsmParser hacks around.
With the AsmParser hacks removed, the FLDMX and FSTMX instructions get the same
operand diagnostics as the UAL instructions.
Differential revision: https://reviews.llvm.org/D39196
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318777
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Alina Sbirlea [Tue, 21 Nov 2017 15:45:46 +0000 (15:45 +0000)]
Add MemorySSA as loop dependency, disabled by default [NFC].
Summary:
First step in adding MemorySSA as dependency for loop pass manager.
Adding the dependency under a flag.
New pass manager: MSSA pointer in LoopStandardAnalysisResults can be null.
Legacy and new pass manager: Use cl::opt EnableMSSALoopDependency. Disabled by default.
Reviewers: sanjoy, davide, gberry
Subscribers: mehdi_amini, Prazek, llvm-commits
Differential Revision: https://reviews.llvm.org/D40274
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318772
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Oliver Stannard [Tue, 21 Nov 2017 15:34:15 +0000 (15:34 +0000)]
[ARM] Don't omit non-default predication code
This was causing the (invalid) predicated versions of the NEON VRINTX and
VRINTZ instructions to be accepted, with the condition code being ignored.
Also, there is no NEON VRINTR instruction, so that part of the check was not
necessary.
Differential revision: https://reviews.llvm.org/D39193
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318771
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Oliver Stannard [Tue, 21 Nov 2017 15:16:50 +0000 (15:16 +0000)]
[Asm] Improve "too few operands" errors
- We can still emit this error if the actual instruction has two or more
operands missing compared to the expected one.
- We should only emit this error once per instruction.
Differential revision: https://reviews.llvm.org/D36746
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318770
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Oliver Stannard [Tue, 21 Nov 2017 15:12:05 +0000 (15:12 +0000)]
[Asm] Finish matching once end of formal and actual lists reached (NFC)
This is NFC, as the matcher would continue looping up to the maximum
number of operands with no effect, but this should improve performance a
bit, and makes the debug trace clearer.
Differential revision: https://reviews.llvm.org/D36744
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318769
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Sander de Smalen [Tue, 21 Nov 2017 15:07:43 +0000 (15:07 +0000)]
Revert r318759 due to make check-all failure on Windows
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318768
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Oliver Stannard [Tue, 21 Nov 2017 15:06:01 +0000 (15:06 +0000)]
[ARM] Add diagnostics for SPR/DPR lists
Differential revision: https://reviews.llvm.org/D39195
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318766
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Alexey Bataev [Tue, 21 Nov 2017 14:49:13 +0000 (14:49 +0000)]
[InstCombine] Test for PR35354: unable to vectorize loop with std::max
on floats, NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318764
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Sam Kolton [Tue, 21 Nov 2017 14:11:59 +0000 (14:11 +0000)]
[AMDGPU] SDWA: remove omod src operand for VOP2b instructions
Summary: VOP2b instructions (v_subbrev_u32, v_add_i32 ...) shouldn't support OMod operand in SDWA encoding
Reviewers: rampitec, dp
Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye
Differential Revision: https://reviews.llvm.org/D40172
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318761
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Alex Bradbury [Tue, 21 Nov 2017 12:41:41 +0000 (12:41 +0000)]
[RISCV][NFC] Remove unnecessary {} around single statement if block
Almost too trivial to worry about, but it seems worth having consistency with
upcoming commits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318760
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Sander de Smalen [Tue, 21 Nov 2017 12:26:06 +0000 (12:26 +0000)]
[TableGen] AsmMatcher: Fix bug with reported diagnostic for operand.
Summary:
The generated diagnostic by the AsmMatcher isn't always applicable to the AsmOperand.
This is because the code will only update the diagnostic if it is more specific than the previous diagnostic. However, when having validated operands and 'moved on' to a next operand (for some instruction/alias for which all previous operands are valid), if the diagnostic is InvalidOperand, than that should be set as the diagnostic, not the more specific message about a previous operand for some other instruction/alias candidate.
Reviewers: craig.topper, olista01, rengolin, stoklund
Reviewed By: olista01
Subscribers: javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D40011
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318759
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Simon Pilgrim [Tue, 21 Nov 2017 12:02:18 +0000 (12:02 +0000)]
[X86][XOP] Add missing scheduler classes to XOP instructions
All match equivalent basic classes (WritePHAdd, WriteFAdd etc.) according to both the AMD 15h SOG and Agner's tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318758
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Alex Bradbury [Tue, 21 Nov 2017 12:00:19 +0000 (12:00 +0000)]
[RISCV][NFC] Clean up RISCVDAGToDAGISel::Select
As pointed out in post-commit review of r318738, `return ReplaceNode(..)` when
both ReplaceNode and the current function return void is confusing. This patch
moves to using a more obvious early return, and moves to just using an if to
catch the one case we currently care about. A future patch that adds further
custom instruction selection can introduce a switch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318757
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Martell Malone [Tue, 21 Nov 2017 11:30:20 +0000 (11:30 +0000)]
[ARM] Use SEH exceptions on thumbv7-windows
Reviewers: mstorsjo
Differential Revision: https://reviews.llvm.org/D40286
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318756
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Simon Pilgrim [Tue, 21 Nov 2017 11:17:11 +0000 (11:17 +0000)]
[X86][LWP] Add missing LWP itinerary class to lwpins instructions
It's on all other LWP instruction but I missed it from lwpins, despite similar scheduling behaviour.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318751
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Eugene Leviant [Tue, 21 Nov 2017 11:01:28 +0000 (11:01 +0000)]
[MI scheduler] Fix VADD and VSUB in cortex-a57 model
This patch fixes instregex for interger vector add/sub instructions
Differential revision: https://reviews.llvm.org/D40254
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318749
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Coby Tayree [Tue, 21 Nov 2017 10:32:42 +0000 (10:32 +0000)]
[x86][icelake]BITALG
vpopcnt{b,w}
Differential Revision: https://reviews.llvm.org/D40213
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318748
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Diana Picus [Tue, 21 Nov 2017 10:17:02 +0000 (10:17 +0000)]
[ARM GlobalISel] Add comment for r318398. NFC.
Mention the purpose of the BICri tests added by r318398, as requested in
post-commit review.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318747
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Coby Tayree [Tue, 21 Nov 2017 10:04:28 +0000 (10:04 +0000)]
[x86][icelake]VNNI
Introducing Vector Neural Network Instructions, consisting of:
vpdpbusd{s}
vpdpwssd{s}
Differential Revision: https://reviews.llvm.org/D40208
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318746
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Coby Tayree [Tue, 21 Nov 2017 09:48:44 +0000 (09:48 +0000)]
[x86][icelake]vbmi2
introducing vbmi2, consisting of
vpcompress{b,w}
vpexpand{b,w}
vpsh{l,r}d{w,d,q}
vpsh{l,r}dv{w,d,q}
Differential Revision: https://reviews.llvm.org/D40206
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318745
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NAKAMURA Takumi [Tue, 21 Nov 2017 09:41:01 +0000 (09:41 +0000)]
SLPVectorizer.cpp: Avoid std::stable_sort(properlyDominates()).
properlyDominates() shouldn't be used as sort key. It causes different output between stdlibc++ and libc++.
Instead, I introduced RPOT. In most cases, it works for CSE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318743
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Coby Tayree [Tue, 21 Nov 2017 09:30:33 +0000 (09:30 +0000)]
[x86][icelake]vpclmulqdq introduction
an icelake promotion of pclmulqdq
Differential Revision: https://reviews.llvm.org/D40101
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318741
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Coby Tayree [Tue, 21 Nov 2017 09:11:41 +0000 (09:11 +0000)]
[x86][icelake]VAES introduction
an icelake promotion of AES
Differential Revision: https://reviews.llvm.org/D40078
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318740
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Alex Bradbury [Tue, 21 Nov 2017 08:23:08 +0000 (08:23 +0000)]
[RISCV] Use register X0 (ZERO) for constant 0
The obvious approach of defining a pattern like the one below actually doesn't
work:
`def : Pat<(i32 0), (i32 X0)>;`
As was noted when Lanai made this change (https://reviews.llvm.org/rL288215),
attempting to handle the constant 0 in tablegen leads to assertions due to a
physical register being used where a virtual register is expected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318738
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Alex Bradbury [Tue, 21 Nov 2017 08:11:03 +0000 (08:11 +0000)]
[RISCV] Support and tests for a variety of additional LLVM IR constructs
Previous patches primarily ensured that codegen was possible for the standard
RISC-V instructions. However, there are a number of IR inputs that wouldn't be
appropriately lowered. This patch both adds test cases and supports lowering
for a number of these cases:
* Improved sext/zext/trunc support
* Support for setcc variants that don't map directly to RISC-V instructions
* Lowering mul, and hence support for external symbols
* addc, adde, subc, sube
* mulhs, srem, mulhu, urem, udiv, sdiv
* {srl,sra,shl}_parts
* brind
* br_jt
* bswap, ctlz, cttz, ctpop
* rotl, rotr
* BlockAddress operands
Differential Revision: https://reviews.llvm.org/D29938
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318737
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Alex Bradbury [Tue, 21 Nov 2017 07:51:32 +0000 (07:51 +0000)]
[RISCV] Implement lowering of ISD::SELECT
Although ISD::SELECT_CC is a more natural match for RISCVISD::SELECT_CC (and
ultimately the integer RISC-V conditional branch instructions), we choose to
expand ISD::SELECT_CC and lower ISD::SELECT. The appropriate compare+branch
will be created in the case where an ISD::SELECT condition value is created by
an ISD::SETCC node, which operates on XLen types. Other datatypes such as
floating point don't have conditional branch instructions, and lowering
ISD::SELECT allows more flexibility for handling these cases.
Differential Revision: https://reviews.llvm.org/D29937
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318735
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Dean Michael Berris [Tue, 21 Nov 2017 07:16:57 +0000 (07:16 +0000)]
[XRay] Use optimistic logging model for FDR mode
Summary:
Before this change, the FDR mode implementation relied on at thread-exit
handling to return buffers back to the (global) buffer queue. This
introduces issues with the initialisation of the thread_local objects
which, even through the use of pthread_setspecific(...) may eventually
call into an allocation function. Similar to previous changes in this
line, we're finding that there is a huge potential for deadlocks when
initialising these thread-locals when the memory allocation
implementation is also xray-instrumented.
In this change, we limit the call to pthread_setspecific(...) to provide
a non-null value to associate to the key created with
pthread_key_create(...). While this doesn't completely eliminate the
potential for the deadlock(s), it does allow us to still clean up at
thread exit when we need to. The change is that we don't need to do more
work when starting and ending a thread's lifetime. We also have a test
to make sure that we actually can safely recycle the buffers in case we
end up re-using the buffer(s) available from the queue on multiple
thread entry/exits.
This change cuts across both LLVM and compiler-rt to allow us to update
both the XRay runtime implementation as well as the library support for
loading these new versions of the FDR mode logging. Version 2 of the FDR
logging implementation makes the following changes:
* Introduction of a new 'BufferExtents' metadata record that's outside
of the buffer's contents but are written before the actual buffer.
This data is associated to the Buffer handed out by the BufferQueue
rather than a record that occupies bytes in the actual buffer.
* Removal of the "end of buffer" records. This is in-line with the
changes we described above, to allow for optimistic logging without
explicit record writing at thread exit.
The optimistic logging model operates under the following assumptions:
* Threads writing to the buffers will potentially race with the thread
attempting to flush the log. To avoid this situation from occuring,
we make sure that when we've finalized the logging implementation,
that threads will see this finalization state on the next write, and
either choose to not write records the thread would have written or
write the record(s) in two phases -- first write the record(s), then
update the extents metadata.
* We change the buffer queue implementation so that once it's handed
out a buffer to a thread, that we assume that buffer is marked
"used" to be able to capture partial writes. None of this will be
safe to handle if threads are racing to write the extents records
and the reader thread is attempting to flush the log. The optimism
comes from the finalization routine being required to complete
before we attempt to flush the log.
This is a fairly significant semantics change for the FDR
implementation. This is why we've decided to update the version number
for FDR mode logs. The tools, however, still need to be able to support
older versions of the log until we finally deprecate those earlier
versions.
Reviewers: dblaikie, pelikan, kpw
Subscribers: llvm-commits, hiraditya
Differential Revision: https://reviews.llvm.org/D39526
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318733
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Craig Topper [Tue, 21 Nov 2017 06:28:15 +0000 (06:28 +0000)]
[X86] Simplify type constraints for AVX2 masked gather.
We don't need separate 32 and 64 node types. We can use SDTCisInt and SDTCisSameSizeAs to ensure the mask size the result type and is integer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318732
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Serguei Katkov [Tue, 21 Nov 2017 06:03:43 +0000 (06:03 +0000)]
Revert "[CGP] Enable complex addr mode (2nd attempt)"
Revert the patch rl318728 causing buildbot hangs-ups.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318731
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Craig Topper [Tue, 21 Nov 2017 06:01:20 +0000 (06:01 +0000)]
[X86] Simplify the predicates for avx2 masked gather patterns.
We don't need a dyn_cast and we only need to check the type of the index. The base ptr is guaranteed to be scalar.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318730
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Rafael Espindola [Tue, 21 Nov 2017 05:35:45 +0000 (05:35 +0000)]
move static function. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318729
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Serguei Katkov [Tue, 21 Nov 2017 05:31:47 +0000 (05:31 +0000)]
[CGP] Enable complex addr mode (2nd attempt)
2nd attempt to enable complex addr modes after
fix of the crash by rL318638.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318728
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Yaxun Liu [Tue, 21 Nov 2017 02:29:54 +0000 (02:29 +0000)]
[AMDGPU] Fix DAGTypeLegalizer::SplitInteger for shift amount type
DAGTypeLegalizer::SplitInteger uses default pointer size as shift amount constant type,
which causes less performant ISA in amdgcn---amdgiz target since the default pointer
type is i64 whereas the desired shift amount type is i32.
This patch fixes that by using TLI.getScalarShiftAmountTy in DAGTypeLegalizer::SplitInteger.
The X86 change is necessary since splitting i512 requires shifting amount of 256, which
cannot be held by i8.
Differential Revision: https://reviews.llvm.org/D40148
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318727
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Rafael Espindola [Tue, 21 Nov 2017 01:52:44 +0000 (01:52 +0000)]
Split a rename_handle out of rename on windows.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318725
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Richard Trieu [Tue, 21 Nov 2017 01:45:17 +0000 (01:45 +0000)]
Add default values for member functions.
Initialize IsVis2 and IsVis3 in SparcSubtarget::initializeSubtargetDependencies.
MSan detected uninitialized read of IsVis3 after r318704. Initializing the
variables to false will prevent undefined behavior.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318724
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Zachary Turner [Tue, 21 Nov 2017 01:20:28 +0000 (01:20 +0000)]
Re-revert "Refactor debuginfo-tests."
This is still breaking greendragon.
At this point I give up until someone can fix the greendragon
bots, and I will probably abandon this effort in favor of using
a private github repository.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318722
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David Blaikie [Tue, 21 Nov 2017 00:33:17 +0000 (00:33 +0000)]
xray-record-yaml.h: Remove unused file
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318715
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David Blaikie [Tue, 21 Nov 2017 00:23:19 +0000 (00:23 +0000)]
llvm-rc/ResourceScriptTokenList.h: Turns this into a .def file to imply that it's non-modular
Also undef the macros at the end of the file to make it easier to use.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318714
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David Blaikie [Tue, 21 Nov 2017 00:23:19 +0000 (00:23 +0000)]
XRayRecord.h: Add missing #include
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318713
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David Blaikie [Tue, 21 Nov 2017 00:23:17 +0000 (00:23 +0000)]
YAML/XRay/std::vector: Fix ODR violation by removing local specialization
There's a generic partial specialization for all std::vector<T> that
does what's desired, so no need for this full specialization that's
causing an ODR violation anyway.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318712
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Davide Italiano [Tue, 21 Nov 2017 00:21:52 +0000 (00:21 +0000)]
[SCCP] If we replace with a constant, we can't replace with a range.
This microoptimization is NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318711
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Richard Trieu [Tue, 21 Nov 2017 00:12:18 +0000 (00:12 +0000)]
Revert r318678 to fix Clang test
r318678 caused the Clang test CodeGen/ms-inline-asm.c to start failing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318710
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Vitaly Buka [Mon, 20 Nov 2017 23:37:56 +0000 (23:37 +0000)]
[msan] Don't sanitize "nosanitize" instructions
Reviewers: eugenis
Subscribers: hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D40205
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318708
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Craig Topper [Mon, 20 Nov 2017 23:08:50 +0000 (23:08 +0000)]
[SelectionDAG] When promoting the result of a VSELECT, make sure we promote the condition to the SetCC type for the final result type not the original type.
Normally this would be cleaned up by promoting the condition operand next. But in the attached case we promoted the result from v2i48 to v2i64 and the condition from v2i1 to v2i48. Then we tried to "promote" the v2i48 condition back to v2i1 because that's what the SetCC result type for v2i64 is on X86 with VLX. But promote is either a NOP or SIGN_EXTEND and this would need a truncation.
With the change here we now get the SetCC type of v2i1 when we're handling the result promotion and the operand no longer needs to be promoted itself.
Fixes PR35272.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318706
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Fedor Sergeev [Mon, 20 Nov 2017 22:33:58 +0000 (22:33 +0000)]
[Sparc] efficient pattern for UINT_TO_FP conversion
Summary:
while investigating performance degradation of imagick benchmark
there were found inefficient pattern for UINT_TO_FP conversion.
That pattern causes RAW hazard in assembly code. Specifically,
uitofp IR operator results in poor assembler :
st %i0, [%fp - 952]
ldd [%fp - 952], %f0
it stores 32-bit integer register into memory location and then
loads 64-bit floating point data from that location.
That is exactly RAW hazard case. To optimize that case it is
possible to use SPISD::ITOF and SPISD::XTOF for conversion from
integer to floating point data type and to use ISD::BITCAST to
copy from integer register into floating point register.
The fix is to write custom UINT_TO_FP pattern using SPISD::ITOF,
SPISD::XTOF, ISD::BITCAST.
Patch by Alexey Lapshin
Reviewers: fedor.sergeev, jyknight, dcederman, lero_chris
Reviewed By: jyknight
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D36875
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318704
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David Blaikie [Mon, 20 Nov 2017 22:12:55 +0000 (22:12 +0000)]
Add ADL support to range based <algorithm> extensions
This adds support for ADL in the range based <algorithm> extensions
(llvm::for_each etc.).
Also adds the helper functions llvm::adl::begin and llvm::adl::end which wrap
std::begin and std::end with ADL support.
Saw this was missing from a recent llvm weekly post about adding llvm::for_each
and thought I might add it.
Patch by Stephen Dollberg!
Differential Revision: https://reviews.llvm.org/D40006
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318703
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Zachary Turner [Mon, 20 Nov 2017 21:41:36 +0000 (21:41 +0000)]
Resubmit "Refactor debuginfo-tests" again.
This was reverted due to the tests being run twice on some
build bots. Each run had a slightly different configuration
due to the way in which it was being invoked. This fixes
the problem (albeit in a somewhat hacky way). Hopefully in
the future we can get rid of the workflow of running
debuginfo-tests as part of clang, and then this hack can
go away.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318697
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Hiroshi Yamauchi [Mon, 20 Nov 2017 21:38:43 +0000 (21:38 +0000)]
Fix a lld-x86_64-darwin13 build error.
Summary:
Fix this build error
http://lab.llvm.org:8011/builders/lld-x86_64-darwin13/builds/15112/steps/build_Lld/logs/stdio
after https://reviews.llvm.org/rL318693
Reviewers: davidxl
Reviewed By: davidxl
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D40266
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318696
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Yonghong Song [Mon, 20 Nov 2017 21:37:58 +0000 (21:37 +0000)]
bpf: add a test case for trunc-op optimization
Commit
b5cbc7760ab8 ("[bpf] allow direct and indirect calls")
allowed more than one function in the bpf program, and
commit
114353884415 ("bpf: fix a bug in trunc-op optimization")
fixed a bug in trunc-op optimization which only showed up
with more than one function in the bpf program.
This patch added a test case for trunc-op optimization
for bpf programs with two functions. Reverting commit
"bpf: fix a bug in trunc-op optimization" will cause
failure for this test case.
Signed-off-by: Yonghong Song <yhs@fb.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318695
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Hiroshi Yamauchi [Mon, 20 Nov 2017 21:03:38 +0000 (21:03 +0000)]
Add heuristics for irreducible loop metadata under PGO
Summary:
Add the following heuristics for irreducible loop metadata:
- When an irreducible loop header is missing the loop header weight metadata,
give it the minimum weight seen among other headers.
- Annotate indirectbr targets with the loop header weight metadata (as they are
likely to become irreducible loop headers after indirectbr tail duplication.)
These greatly improve the accuracy of the block frequency info of the Python
interpreter loop (eg. from ~3-16x off down to ~40-55% off) and the Python
performance (eg. unpack_sequence from ~50% slower to ~8% faster than GCC) due to
better register allocation under PGO.
Reviewers: davidxl
Reviewed By: davidxl
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D39980
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318693
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Simon Pilgrim [Mon, 20 Nov 2017 19:18:33 +0000 (19:18 +0000)]
Fix spelling in comment. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318687
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Mandeep Singh Grang [Mon, 20 Nov 2017 19:17:11 +0000 (19:17 +0000)]
Revert "[SelectionDAG] Make sorting predicate stronger to remove non-deterministic ordering"
This broke the bots. Reverting this until I can fix the failures.
This reverts commit
5a3db2856d12a3c4b400f487d39f8f05989e79f0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318686
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Evandro Menezes [Mon, 20 Nov 2017 19:11:56 +0000 (19:11 +0000)]
[AArch64] Adjust the cost model for Exynos M1 and M2
Fix the modeling of test and branch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318685
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Paul Robinson [Mon, 20 Nov 2017 19:07:52 +0000 (19:07 +0000)]
Revert "Fix out-of-order stepping behavior in programs with sunk instructions."
This reverts commit
30419e150cd940893a13b345e85f96053850208f.
aka r318679. It caused "sanitizer-windows" bot to fail.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318684
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Mandeep Singh Grang [Mon, 20 Nov 2017 18:46:11 +0000 (18:46 +0000)]
[SelectionDAG] Make sorting predicate stronger to remove non-deterministic ordering
Summary:
This fixes failures in the following tests uncovered by D39245:
LLVM :: CodeGen/ARM/ifcvt3.ll
LLVM :: CodeGen/ARM/switch-minsize.ll
LLVM :: CodeGen/X86/switch.ll
Reviewers: hans, efriedma
Reviewed By: hans
Subscribers: fhahn, aemerson, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D39995
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318680
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Paul Robinson [Mon, 20 Nov 2017 18:42:17 +0000 (18:42 +0000)]
Fix out-of-order stepping behavior in programs with sunk instructions.
MachineSink attempts to place instructions near the basic blocks where
they are needed. Once an instruction has been sunk, its location
relative to other instructions is no longer consistent with the
original source code. In order to ensure correct single-stepping and
profiling, the debug location for sunk instructions is either merged
with the insertion point or erased if the target successor block is
empty.
Patch by Matthew Voss!
Differential Revision: https://reviews.llvm.org/D39933
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318679
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Nirav Dave [Mon, 20 Nov 2017 18:38:55 +0000 (18:38 +0000)]
[X86] Avoid unecessary opsize byte in segment move to memory
Summary:
Segment moves to memory are always 16-bit. Remove invalid 32 and 64
bit variants.
Fixes PR34478.
Reviewers: rnk, craig.topper
Subscribers: llvm-commits, hiraditya
Differential Revision: https://reviews.llvm.org/D39847
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318678
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Teresa Johnson [Mon, 20 Nov 2017 18:33:38 +0000 (18:33 +0000)]
[SROA] Correctly invalidate analyses when dead instructions deleted
Summary:
SROA can fail in rewriting alloca but still rewrite a phi resulting
in dead instruction elimination. The Changed flag was not being set
correctly, resulting in downstream passes using stale analyses.
The included test case will assert during the second BDCE pass as a
result.
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D39921
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318677
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Dmitry Preobrazhensky [Mon, 20 Nov 2017 18:24:21 +0000 (18:24 +0000)]
[AMDGPU][MC][GFX8][GFX9] Corrected names of integer v_{add/addc/sub/subrev/subb/subbrev}
See bug 34765: https://bugs.llvm.org//show_bug.cgi?id=34765
Reviewers: tamazov, SamWot, arsenm, vpykhtin
Differential Revision: https://reviews.llvm.org/D40088
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318675
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Evgeniy Stepanov [Mon, 20 Nov 2017 17:41:57 +0000 (17:41 +0000)]
[asan] Use dynamic shadow on 32-bit Android, try 2.
Summary:
This change reverts r318575 and changes FindDynamicShadowStart() to
keep the memory range it found mapped PROT_NONE to make sure it is
not reused. We also skip MemoryRangeIsAvailable() check, because it
is (a) unnecessary, and (b) would fail anyway.
Reviewers: pcc, vitalybuka, kcc
Subscribers: srhines, kubamracek, mgorny, llvm-commits, hiraditya
Differential Revision: https://reviews.llvm.org/D40203
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318666
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Tony Jiang [Mon, 20 Nov 2017 16:55:07 +0000 (16:55 +0000)]
[MachineCSE] Add new callback for is caller preserved or constant physregs
The instructions addis,addi, bl are used to calculate the address of TLS thread
local variables. These TLS access code sequences are generated repeatedly every
time the thread local variable is accessed. By communicating to Machine CSE that
X2 is guaranteed to have the same value within the same function call (so called
Caller Preserved Physical Register), the redundant TLS access code sequences are
cleaned up.
Differential Revision: https://reviews.llvm.org/D39173
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318661
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Yaxun Liu [Mon, 20 Nov 2017 16:53:13 +0000 (16:53 +0000)]
[AMDGPU] Update test r600.amdgpu-alias-analysis.ll
Manually update test r600.amdgpu-alias-analysis.ll for amdgiz environment
since it cannot be done by script.
The two pointers are swapped in the output because PrintResults in
AliasAnalysisEvaluator.cpp sorts the strings obtained from printAsOperand
before printing them.
Differential Revision: https://reviews.llvm.org/D40131
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318660
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Simon Dardis [Mon, 20 Nov 2017 15:59:18 +0000 (15:59 +0000)]
[mips] Reorder target specific passes
Move the hazard scheduling pass to after the long branch pass, as the
long branch pass can create forbiddden slot hazards. Rather than complicating
the implementation of the long branch pass to handle forbidden slot hazards,
just reorder the passes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318657
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Jonas Paulsson [Mon, 20 Nov 2017 14:54:03 +0000 (14:54 +0000)]
[SystemZ] Bugfix for handling of subregisters in getRegAllocationHints().
The 32 bit subreg indices of GR128 registers must also be checked for in
getRC32().
Review: Ulrich Weigand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318652
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Tony Jiang [Mon, 20 Nov 2017 14:38:30 +0000 (14:38 +0000)]
[PPC] Heuristic to choose between a X-Form VSX ld/st vs a X-Form FP ld/st.
The VSX versions have the advantage of a full 64-register target whereas the FP
ones have the advantage of lower latency and higher throughput. So what we’re
after is using the faster instructions in low register pressure situations and
using the larger register file in high register pressure situations.
The heuristic chooses between the following 7 pairs of instructions.
PPC::LXSSPX vs PPC::LFSX
PPC::LXSDX vs PPC::LFDX
PPC::STXSSPX vs PPC::STFSX
PPC::STXSDX vs PPC::STFDX
PPC::LXSIWAX vs PPC::LFIWAX
PPC::LXSIWZX vs PPC::LFIWZX
PPC::STXSIWX vs PPC::STFIWX
Differential Revision: https://reviews.llvm.org/D38486
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318651
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Sander de Smalen [Mon, 20 Nov 2017 14:36:40 +0000 (14:36 +0000)]
[AArch64][TableGen] Skip tied result operands for InstAlias
Summary:
This patch fixes an issue so that the right alias is printed when the instruction has tied operands. It checks the number of operands in the resulting instruction as opposed to the alias, and then skips over tied operands that should not be printed in the alias.
This allows to generate the preferred assembly syntax for the AArch64 'ins' instruction, which should always be displayed as 'mov' according to the ARM Architecture Reference Manual. Several unit tests have changed as a result, but only to reflect the preferred disassembly. Some other InstAlias patterns (movk/bic/orr) needed a slight adjustment to stop them becoming the default and breaking other unit tests.
Please note that the patch is mostly the same as https://reviews.llvm.org/D29219 which was reverted because of an issue found when running TableGen with the Address Sanitizer. That issue has been addressed in this iteration of the patch.
Reviewers: rengolin, stoklund, huntergr, SjoerdMeijer, rovka
Reviewed By: rengolin, SjoerdMeijer
Subscribers: fhahn, aemerson, javed.absar, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D40030
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318650
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Valery Pykhtin [Mon, 20 Nov 2017 14:35:53 +0000 (14:35 +0000)]
AMDGPU: Partial ILP scheduler port from SelectionDAG to SchedulingDAG (experimental)
Differential revision: https://reviews.llvm.org/D39897
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318649
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Gil Rapaport [Mon, 20 Nov 2017 12:01:47 +0000 (12:01 +0000)]
[LV] Model masking in VPlan, introducing VPInstructions
This patch adds a new abstraction layer to VPlan and leverages it to model the planned
instructions that manipulate masks (AND, OR, NOT), introduced during predication.
The new VPValue and VPUser classes model how data flows into, through and out
of a VPlan, forming the vertices of a planned Def-Use graph. The new
VPInstruction class is a generic single-instruction Recipe that models a
planned instruction along with its opcode, operands and users. See
VectorizationPlan.rst for more details.
Differential Revision: https://reviews.llvm.org/D38676
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318645
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Diana Picus [Mon, 20 Nov 2017 11:05:31 +0000 (11:05 +0000)]
[ARM GlobalISel] Add test for RSBri. NFC
Add instruction selector test for RSBri, which is derived from
AsI1_rbin_irs, and make sure it doesn't get mistaken for SUBri, which is
derived from the very similar AsI1_bin_irs pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318643
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Diana Picus [Mon, 20 Nov 2017 10:35:35 +0000 (10:35 +0000)]
[ARM GlobalISel] Clean up binary operator tests. NFC
Remove some of the instruction selector tests for binary operators (and,
or, xor). These are all derived from the same kind of TableGen pattern,
AsI1_bin_irs, so there's no point in testing all of them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318642
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Mohammed Agabaria [Mon, 20 Nov 2017 08:18:12 +0000 (08:18 +0000)]
[LV][X86] Support of AVX2 Gathers code generation and update the LV with this
This patch depends on: https://reviews.llvm.org/D35348
Support of pattern selection of masked gathers of AVX2 (X86\AVX2 code gen)
Update LoopVectorize to generate gathers for AVX2 processors.
Reviewers: delena, zvi, RKSimon, craig.topper, aaboud, igorb
Reviewed By: delena, RKSimon
Differential Revision: https://reviews.llvm.org/D35772
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318641
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Craig Topper [Mon, 20 Nov 2017 08:15:04 +0000 (08:15 +0000)]
[X86] Regenerate a test with broadcast comments. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318640
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Max Kazantsev [Mon, 20 Nov 2017 06:07:57 +0000 (06:07 +0000)]
[IRCE] Smart range intersection
In rL316552, we ban intersection of unsigned latch range with signed range check and vice
versa, unless the entire range check iteration space is known positive. It was a correct
functional fix that saved us from dealing with ambiguous values, but it also appeared
to be a very restrictive limitation. In particular, in the following case:
loop:
%iv = phi i32 [ 0, %preheader ], [ %iv.next, %latch]
%iv.offset = add i32 %iv, 10
%rc = icmp slt i32 %iv.offset, %len
br i1 %rc, label %latch, label %deopt
latch:
%iv.next = add i32 %iv, 11
%cond = icmp i32 ult %iv.next, 100
br it %cond, label %loop, label %exit
Here, the unsigned iteration range is `[0, 100)`, and the safe range for range
check is `[-10, %len - 10)`. For unsigned iteration spaces, we use unsigned
min/max functions for range intersection. Given this, we wanted to avoid dealing
with `-10` because it is interpreted as a very big unsigned value. Semantically, range
check's safe range goes through unsigned border, so in fact it is two disjoint
ranges in IV's iteration space. Intersection of such ranges is not trivial, so we prohibited
this case saying that we are not allowed to intersect such ranges.
What semantics of this safe range actually means is that we can start from `-10` and go
up increasing the `%iv` by one until we reach `%len - 10` (for simplicity let's assume that
`%len - 10` is a reasonably big positive value).
In particular, this safe iteration space includes `0, 1, 2, ..., %len - 11`. So if we were able to return
safe iteration space `[0, %len - 10)`, we could safely intersect it with IV's iteration space. All
values in this range are non-negative, so using signed/unsigned min/max for them is unambiguous.
In this patch, we alter the algorithm of safe range calculation so that it returnes a subset of the
original safe space which is represented by one continuous range that does not go through wrap.
In order to reach this, we use modified SCEV substraction function. It can be imagined as a function
that substracts by `1` (or `-1`) as long as the further substraction does not cause a wrap in IV iteration
space. This allows us to perform IRCE in many situations when we deal with IV space and range check
of different types (in terms of signed/unsigned).
We apply this approach for both matching and not matching types of IV iteration space and the
range check. One implication of this is that now IRCE became smarter in detection of empty safe
ranges. For example, in this case:
loop:
%iv = phi i32 [ %begin, %preheader ], [ %iv.next, %latch]
%iv.offset = sub i32 %iv, 10
%rc = icmp ult i32 %iv.offset, %len
br i1 %rc, label %latch, label %deopt
latch:
%iv.next = add i32 %iv, 11
%cond = icmp i32 ult %iv.next, 100
br it %cond, label %loop, label %exit
If `%len` was less than 10 but SCEV failed to trivially prove that `%begin - 10 >u %len- 10`,
we could end up executing entire loop in safe preloop while the main loop was still generated,
but never executed. Now, cutting the ranges so that if both `begin - 10` and `%len - 10` overflow,
we have a trivially empty range of `[0, 0)`. This in some cases prevents us from meaningless optimization.
Differential Revision: https://reviews.llvm.org/D39954
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318639
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Serguei Katkov [Mon, 20 Nov 2017 05:42:36 +0000 (05:42 +0000)]
[CGP] Fix the crash caused by enable of complex addr mode
We must collect all AddModes even if they are the same.
This is due to Original value is different but we need all original
values collected as they are used as anchors in common phi finding.
Reviewers: john.brawn, reames
Reviewed By: john.brawn
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D40166
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318638
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Craig Topper [Sun, 19 Nov 2017 23:49:19 +0000 (23:49 +0000)]
[X86] clzero check in getHostCPUFeatures should use getX86CpuIDAndInfo not getX86CpuIDAndInfoEx.
This leaf doesn't take an additional argument.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318634
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Craig Topper [Sun, 19 Nov 2017 23:30:22 +0000 (23:30 +0000)]
[X86] Reorder and reformat the feature bit checks in getHostCPUFeatues to keep the bits in order per register and encourage future additions to be in order too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318633
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Sanjay Patel [Sun, 19 Nov 2017 17:31:37 +0000 (17:31 +0000)]
[x86] add sqrt tests for partially-inline-libcalls (PR31455)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318630
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Sanjay Patel [Sun, 19 Nov 2017 16:42:27 +0000 (16:42 +0000)]
[LibCallSimplifier] allow splat vectors for pow(x, 0.5) -> sqrt() transforms
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318629
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Sanjay Patel [Sun, 19 Nov 2017 16:13:14 +0000 (16:13 +0000)]
[LibCallSimplifier] partly fix pow(x, 0.5) -> sqrt() transforms
As the first test shows, we could transform an llvm intrinsic which never sets errno
into a libcall which could set errno (even though it's marked readnone?), so that's
not ideal.
It's possible that we can also transform a libcall which could set errno to an
intrinsic given the fast-math-flags constraint, but that's deferred to determine
exactly which set of FMF are needed.
Differential Revision: https://reviews.llvm.org/D40150
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318628
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Sanjay Patel [Sun, 19 Nov 2017 15:34:27 +0000 (15:34 +0000)]
[InstSimplify] fold and/or of fcmp ord/uno when operand is known nnan
The 'ord' and 'uno' predicates have a logic operation for NAN built into their definitions:
FCMP_ORD = 7, ///< 0 1 1 1 True if ordered (no nans)
FCMP_UNO = 8, ///< 1 0 0 0 True if unordered: isnan(X) | isnan(Y)
So we can simplify patterns like this:
(fcmp ord (known NNAN), X) && (fcmp ord X, Y) --> fcmp ord X, Y
(fcmp uno (known NNAN), X) || (fcmp uno X, Y) --> fcmp uno X, Y
It might be better to split this into (X uno 0) | (Y uno 0) as a canonicalization, but that
would be another patch.
Differential Revision: https://reviews.llvm.org/D40130
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318627
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Craig Topper [Sun, 19 Nov 2017 06:24:26 +0000 (06:24 +0000)]
[X86] Add test cases for rndscaless/sd intrinsics.
Also fix the memop in the ins for these instructions. Not sure what effect this has.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318624
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Craig Topper [Sun, 19 Nov 2017 05:42:54 +0000 (05:42 +0000)]
[X86] Improve load folding of scalar rcp28 and rsqrt28 instructions using sse_load_f32/f64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318623
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Alexei Starovoitov [Sun, 19 Nov 2017 02:41:53 +0000 (02:41 +0000)]
[bpf] remove unused variable
Signed-off-by: Alexei Starovoitov <ast@kernel.org>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318615
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Alexei Starovoitov [Sun, 19 Nov 2017 01:35:00 +0000 (01:35 +0000)]
[bpf] allow direct and indirect calls
kernel verifier is becoming smarter and soon will support
direct and indirect function calls.
Remove obsolete error from BPF backend.
Make call to use PCRel_4 fixup.
'bpf to bpf' calls are distinguished from 'bpf to kernel' calls
by insn->src_reg == BPF_PSEUDO_CALL == 1 which is used as relocation
indicator similar to ld_imm64->src_reg == BPF_PSEUDO_MAP_FD == 1
The actual 'call' instruction remains the same for both
'bpf to kernel' and 'bpf to bpf' calls.
Signed-off-by: Alexei Starovoitov <ast@kernel.org>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318614
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Craig Topper [Sun, 19 Nov 2017 01:25:30 +0000 (01:25 +0000)]
[X86] Switch cannonlake to use the SkylakeServer scheduling model instead of Haswell.
Cannonlake comes after skylake and supports avx512 so this is probably a closer model for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318613
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Craig Topper [Sun, 19 Nov 2017 01:12:00 +0000 (01:12 +0000)]
[X86] Add skeleton support for icelake CPU.
There are several patches out for review right now to implement Icelake features. This adds a CPU to collect them under.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318612
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