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Stefan Hajnoczi [Thu, 13 Oct 2022 17:55:03 +0000 (13:55 -0400)]
Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
* scsi-disk: support setting CD-ROM block size via device options
* target/i386: Implement MSR_CORE_THREAD_COUNT MSR
* target/i386: notify VM exit support
* target/i386: PC-relative translation block support
* target/i386: support for XSAVE state in signal frames (linux-user)
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# gpg: Signature made Tue 11 Oct 2022 04:27:42 EDT
# gpg: using RSA key
F13338574B662389866C7682BFFBD25F78C7AE83
# gpg: issuer "pbonzini@redhat.com"
# gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full]
# gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full]
# Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1
# Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83
* tag 'for-upstream' of https://gitlab.com/bonzini/qemu: (37 commits)
linux-user: i386/signal: support XSAVE/XRSTOR for signal frame fpstate
linux-user: i386/signal: support FXSAVE fpstate on 32-bit emulation
linux-user: i386/signal: move fpstate at the end of the 32-bit frames
KVM: x86: Implement MSR_CORE_THREAD_COUNT MSR
i386: kvm: Add support for MSR filtering
x86: Implement MSR_CORE_THREAD_COUNT MSR
target/i386: Enable TARGET_TB_PCREL
target/i386: Inline gen_jmp_im
target/i386: Add cpu_eip
target/i386: Create eip_cur_tl
target/i386: Merge gen_jmp_tb and gen_goto_tb into gen_jmp_rel
target/i386: Remove MemOp argument to gen_op_j*_ecx
target/i386: Use gen_jmp_rel for DISAS_TOO_MANY
target/i386: Use gen_jmp_rel for gen_jcc
target/i386: Use gen_jmp_rel for loop, repz, jecxz insns
target/i386: Create gen_jmp_rel
target/i386: Use DISAS_TOO_MANY to exit after gen_io_start
target/i386: Create eip_next_*
target/i386: Truncate values for lcall_real to i32
target/i386: Introduce DISAS_JUMP
...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Stefan Hajnoczi [Wed, 12 Oct 2022 20:00:15 +0000 (16:00 -0400)]
Merge tag 'for_upstream' of https://git./virt/kvm/mst/qemu into staging
pc,virtio: features, tests, fixes, cleanups
virtio introspection
new serial number opton for cxl
vhost user blk dynamic config size
virtio-gpio vhost user backend
Tests fixes cleanups all over the place
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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# -----END PGP SIGNATURE-----
# gpg: Signature made Mon 10 Oct 2022 13:27:06 EDT
# gpg: using RSA key
5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469
# gpg: issuer "mst@redhat.com"
# gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [full]
# gpg: aka "Michael S. Tsirkin <mst@redhat.com>" [full]
# Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67
# Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469
* tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu: (55 commits)
x86: pci: acpi: consolidate PCI slots creation
tests: acpi: update expected blobs
x86: pci: acpi: reorder Device's _DSM method
tests: acpi: whitelist pc/q35 DSDT before moving _ADR field
tests: acpi: update expected blobs
x86: pci: acpi: reorder Device's _ADR and _SUN fields
tests: acpi: whitelist pc/q35 DSDT before moving _ADR field
tests: acpi: update expected blobs
x86: acpi: cleanup PCI device _DSM duplication
tests: acpi: whitelist pc/q35 DSDT before switching _DSM to use ASUN
tests: acpi: update expected blobs
x86: acpi: _DSM: use Package to pass parameters
acpi: x86: refactor PDSM method to reduce nesting
tests: acpi: whitelist pc/q35 DSDT due to HPET AML move
tests: acpi: update expected blobs after HPET move
acpi: x86: deduplicate HPET AML building
tests: acpi: whitelist pc/q35 DSDT due to HPET AML move
hw/smbios: support for type 8 (port connector)
pci: Sanity check mask argument to pci_set_*_by_mask()
pci: Remove unused pci_get_*_by_mask() functions
...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Stefan Hajnoczi [Wed, 12 Oct 2022 19:59:10 +0000 (15:59 -0400)]
Merge tag 'pull-target-arm-
20221010' of https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue:
* Retry KVM_CREATE_VM call if it fails EINTR
* allow setting SCR_EL3.EnTP2 when FEAT_SME is implemented
* docs/nuvoton: Update URL for images
* refactoring of page table walk code
* hw/arm/boot: set CPTR_EL3.ESM and SCR_EL3.EnTP2 when booting Linux with EL3
* Don't allow guest to use unimplemented granule sizes
* Report FEAT_GTG support
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# -----END PGP SIGNATURE-----
# gpg: Signature made Mon 10 Oct 2022 10:26:38 EDT
# gpg: using RSA key
E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full]
# gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* tag 'pull-target-arm-
20221010' of https://git.linaro.org/people/pmaydell/qemu-arm: (28 commits)
docs/system/arm/emulation.rst: Report FEAT_GTG support
target/arm: Use ARMGranuleSize in ARMVAParameters
target/arm: Don't allow guest to use unimplemented granule sizes
hw/arm/boot: set CPTR_EL3.ESM and SCR_EL3.EnTP2 when booting Linux with EL3
target/arm: Use tlb_set_page_full
target/arm: Fix cacheattr in get_phys_addr_disabled
target/arm: Split out get_phys_addr_disabled
target/arm: Fix ATS12NSO* from S PL1
target/arm: Pass HCR to attribute subroutines.
target/arm: Remove env argument from combined_attrs_fwb
target/arm: Hoist read of *is_secure in S1_ptw_translate
target/arm: Introduce arm_hcr_el2_eff_secstate
target/arm: Drop secure check for HCR.TGE vs SCTLR_EL1.M
target/arm: Reorg regime_translation_disabled
target/arm: Fold secure and non-secure a-profile mmu indexes
target/arm: Add is_secure parameter to do_ats_write
target/arm: Merge regime_is_secure into get_phys_addr
target/arm: Add TBFLAG_M32.SECURE
target/arm: Add is_secure parameter to v7m_read_half_insn
target/arm: Split out get_phys_addr_with_secure
...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Stefan Hajnoczi [Wed, 12 Oct 2022 19:57:56 +0000 (15:57 -0400)]
Merge tag 'for-upstream' of git://repo.or.cz/qemu/kevin into staging
Block layer patches
- job: replace AioContext lock with job_mutex
- Fixes to make coroutine_fn annotations more accurate
- QAPI schema: Fix incorrect example
- Code cleanup
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# -----END PGP SIGNATURE-----
# gpg: Signature made Fri 07 Oct 2022 06:45:19 EDT
# gpg: using RSA key
DC3DEB159A9AF95D3D7456FE7F09B272C88F2FD6
# gpg: issuer "kwolf@redhat.com"
# gpg: Good signature from "Kevin Wolf <kwolf@redhat.com>" [full]
# Primary key fingerprint: DC3D EB15 9A9A F95D 3D74 56FE 7F09 B272 C88F 2FD6
* tag 'for-upstream' of git://repo.or.cz/qemu/kevin: (50 commits)
file-posix: Remove unused s->discard_zeroes
job: remove unused functions
blockjob: remove unused functions
block_job_query: remove atomic read
job.c: enable job lock/unlock and remove Aiocontext locks
job.h: categorize JobDriver callbacks that need the AioContext lock
blockjob: protect iostatus field in BlockJob struct
blockjob: rename notifier callbacks as _locked
blockjob.h: categorize fields in struct BlockJob
jobs: protect job.aio_context with BQL and job_mutex
job: detect change of aiocontext within job coroutine
jobs: group together API calls under the same job lock
block/mirror.c: use of job helpers in drivers
jobs: use job locks also in the unit tests
jobs: add job lock in find_* functions
blockjob: introduce block_job _locked() APIs
job: move and update comments from blockjob.c
job.c: add job_lock/unlock while keeping job.h intact
aio-wait.h: introduce AIO_WAIT_WHILE_UNLOCKED
job.c: API functions not used outside should be static
...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Stefan Hajnoczi [Tue, 11 Oct 2022 19:31:27 +0000 (15:31 -0400)]
Merge tag 'pull-testing-gdbstub-plugins-gitdm-111022-1' of https://github.com/stsquad/qemu into staging
testing:
- revert patch to stop always building pc-bios roms
# -----BEGIN PGP SIGNATURE-----
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# gpg: Signature made Tue 11 Oct 2022 15:28:06 EDT
# gpg: using RSA key
6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44
# gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 6685 AE99 E751 67BC AFC8 DF35 FBD0 DB09 5A9E 2A44
* tag 'pull-testing-gdbstub-plugins-gitdm-111022-1' of https://github.com/stsquad/qemu:
Revert "configure: build ROMs with container-based cross compilers"
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Alex Bennée [Tue, 11 Oct 2022 11:34:16 +0000 (12:34 +0100)]
Revert "configure: build ROMs with container-based cross compilers"
This reverts commit
730fe750fba63023e294ff0acf0f874369f1946f.
Unconditionally building all the bios for all arches was a little too
far too fast.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Tested-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <
20221011113417.794841-4-alex.bennee@linaro.org>
Stefan Hajnoczi [Tue, 11 Oct 2022 13:31:19 +0000 (09:31 -0400)]
Merge tag 'dump-pull-request' of https://gitlab.com/marcandre.lureau/qemu into staging
dump patches
Hi
Includes:
- the first patches from "[PATCH v5 00/18] dump: Add arch section and s390x PV dump"
- "[PATCH v2 0/2] Fix dumping in kdump format with non-aligned memory"
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# gpg: Signature made Thu 06 Oct 2022 11:33:30 EDT
# gpg: using RSA key
87A9BD933F87C606D276F62DDAE8E10975969CE5
# gpg: issuer "marcandre.lureau@redhat.com"
# gpg: Good signature from "Marc-André Lureau <marcandre.lureau@redhat.com>" [full]
# gpg: aka "Marc-André Lureau <marcandre.lureau@gmail.com>" [full]
# Primary key fingerprint: 87A9 BD93 3F87 C606 D276 F62D DAE8 E109 7596 9CE5
* tag 'dump-pull-request' of https://gitlab.com/marcandre.lureau/qemu:
dump: fix kdump to work over non-aligned blocks
dump: simplify a bit kdump get_next_page()
dump: Rename write_elf*_phdr_note to prepare_elf*_phdr_note
dump: Split elf header functions into prepare and write
dump: Rework dump_calculate_size function
dump: Rework filter area variables
dump: Rework get_start_block
dump: Refactor dump_iterate and introduce dump_filter_memblock_*()
dump: Rename write_elf_loads to write_elf_phdr_loads
dump: Replace opaque DumpState pointer with a typed one
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Paolo Bonzini [Mon, 10 Oct 2022 13:28:54 +0000 (15:28 +0200)]
linux-user: i386/signal: support XSAVE/XRSTOR for signal frame fpstate
Add support for saving/restoring extended save states when signals
are delivered. This allows using AVX, MPX or PKRU registers in
signal handlers.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Paolo Bonzini [Thu, 6 Oct 2022 11:31:06 +0000 (13:31 +0200)]
linux-user: i386/signal: support FXSAVE fpstate on 32-bit emulation
Linux can use FXSAVE to save/restore XMM registers even on 32-bit
systems. This requires some care in order to keep the FXSAVE area
aligned to 16 bytes; for this reason, get_sigframe is changed to
pass the offset into the FXSAVE area rather than the full frame
size.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Paolo Bonzini [Fri, 7 Oct 2022 13:47:35 +0000 (15:47 +0200)]
linux-user: i386/signal: move fpstate at the end of the 32-bit frames
Recent versions of Linux moved the 32-bit fpstate towards the end of the
frame, so that the variable-sized xsave data does not overwrite the
(ABI-defined) extramask[] field. Follow suit in QEMU.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Alexander Graf [Tue, 4 Oct 2022 22:56:43 +0000 (00:56 +0200)]
KVM: x86: Implement MSR_CORE_THREAD_COUNT MSR
The MSR_CORE_THREAD_COUNT MSR describes CPU package topology, such as number
of threads and cores for a given package. This is information that QEMU has
readily available and can provide through the new user space MSR deflection
interface.
This patch propagates the existing hvf logic from patch
027ac0cb516
("target/i386/hvf: add rdmsr 35H MSR_CORE_THREAD_COUNT") to KVM.
Signed-off-by: Alexander Graf <agraf@csgraf.de>
Message-Id: <
20221004225643.65036-4-agraf@csgraf.de>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Alexander Graf [Tue, 4 Oct 2022 22:56:42 +0000 (00:56 +0200)]
i386: kvm: Add support for MSR filtering
KVM has grown support to deflect arbitrary MSRs to user space since
Linux 5.10. For now we don't expect to make a lot of use of this
feature, so let's expose it the easiest way possible: With up to 16
individually maskable MSRs.
This patch adds a kvm_filter_msr() function that other code can call
to install a hook on KVM MSR reads or writes.
Signed-off-by: Alexander Graf <agraf@csgraf.de>
Message-Id: <
20221004225643.65036-3-agraf@csgraf.de>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Alexander Graf [Tue, 4 Oct 2022 22:56:41 +0000 (00:56 +0200)]
x86: Implement MSR_CORE_THREAD_COUNT MSR
Intel CPUs starting with Haswell-E implement a new MSR called
MSR_CORE_THREAD_COUNT which exposes the number of threads and cores
inside of a package.
This MSR is used by XNU to populate internal data structures and not
implementing it prevents virtual machines with more than 1 vCPU from
booting if the emulated CPU generation is at least Haswell-E.
This patch propagates the existing hvf logic from patch
027ac0cb516
("target/i386/hvf: add rdmsr 35H MSR_CORE_THREAD_COUNT") to TCG.
Signed-off-by: Alexander Graf <agraf@csgraf.de>
Message-Id: <
20221004225643.65036-2-agraf@csgraf.de>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Richard Henderson [Sat, 1 Oct 2022 14:09:35 +0000 (07:09 -0700)]
target/i386: Enable TARGET_TB_PCREL
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <
20221001140935.465607-27-richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Richard Henderson [Sat, 1 Oct 2022 14:09:34 +0000 (07:09 -0700)]
target/i386: Inline gen_jmp_im
Expand this function at each of its callers.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <
20221001140935.465607-26-richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Richard Henderson [Sat, 1 Oct 2022 14:09:33 +0000 (07:09 -0700)]
target/i386: Add cpu_eip
Create a tcg global temp for this, and use it instead of explicit stores.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <
20221001140935.465607-25-richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Richard Henderson [Sat, 1 Oct 2022 14:09:32 +0000 (07:09 -0700)]
target/i386: Create eip_cur_tl
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <
20221001140935.465607-24-richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Richard Henderson [Sat, 1 Oct 2022 14:09:31 +0000 (07:09 -0700)]
target/i386: Merge gen_jmp_tb and gen_goto_tb into gen_jmp_rel
These functions have only one caller, and the logic is more
obvious this way.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <
20221001140935.465607-23-richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Richard Henderson [Sat, 1 Oct 2022 14:09:30 +0000 (07:09 -0700)]
target/i386: Remove MemOp argument to gen_op_j*_ecx
These functions are always passed aflag, so we might as well
read it from DisasContext directly. While we're at it, use
a common subroutine for these two functions.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <
20221001140935.465607-22-richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Richard Henderson [Sat, 1 Oct 2022 14:09:29 +0000 (07:09 -0700)]
target/i386: Use gen_jmp_rel for DISAS_TOO_MANY
With gen_jmp_rel, we may chain between two translation blocks
which may only be separated because of TB size limits.
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20221001140935.465607-21-richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Richard Henderson [Sat, 1 Oct 2022 14:09:28 +0000 (07:09 -0700)]
target/i386: Use gen_jmp_rel for gen_jcc
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <
20221001140935.465607-20-richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Richard Henderson [Sat, 1 Oct 2022 14:09:27 +0000 (07:09 -0700)]
target/i386: Use gen_jmp_rel for loop, repz, jecxz insns
With gen_jmp_rel, we may chain to the next tb instead of merely
writing to eip and exiting. For repz, subtract cur_insn_len to
restart the current insn.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <
20221001140935.465607-19-richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Richard Henderson [Sat, 1 Oct 2022 14:09:26 +0000 (07:09 -0700)]
target/i386: Create gen_jmp_rel
Create a common helper for pc-relative branches. The jmp jb insn
was missing a mask for CODE32. In all cases the CODE64 check was
incorrectly placed, allowing PREFIX_DATA to truncate %rip to 16 bits.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <
20221001140935.465607-18-richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Richard Henderson [Sat, 1 Oct 2022 14:09:25 +0000 (07:09 -0700)]
target/i386: Use DISAS_TOO_MANY to exit after gen_io_start
We can set is_jmp early, using only one if, and let that
be overwritten by gen_rep*'s calls to gen_jmp_tb.
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20221001140935.465607-17-richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Richard Henderson [Sat, 1 Oct 2022 14:09:24 +0000 (07:09 -0700)]
target/i386: Create eip_next_*
Create helpers for loading the address of the next insn.
Use tcg_constant_* in adjacent code where convenient.
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20221001140935.465607-16-richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Richard Henderson [Sat, 1 Oct 2022 14:09:23 +0000 (07:09 -0700)]
target/i386: Truncate values for lcall_real to i32
Use i32 not int or tl for eip and cs arguments.
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20221001140935.465607-15-richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Richard Henderson [Sat, 1 Oct 2022 14:09:22 +0000 (07:09 -0700)]
target/i386: Introduce DISAS_JUMP
Drop the unused dest argument to gen_jr().
Remove most of the calls to gen_jr, and use DISAS_JUMP.
Remove some unused loads of eip for lcall and ljmp.
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20221001140935.465607-14-richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Richard Henderson [Sat, 1 Oct 2022 14:09:21 +0000 (07:09 -0700)]
target/i386: Remove cur_eip, next_eip arguments to gen_repz*
All callers pass s->base.pc_next and s->pc, which we can just
as well compute within the functions. Pull out common helpers
and reduce the amount of code under macros.
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20221001140935.465607-13-richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Richard Henderson [Sat, 1 Oct 2022 14:09:20 +0000 (07:09 -0700)]
target/i386: Create cur_insn_len, cur_insn_len_i32
Create common routines for computing the length of the insn.
Use tcg_constant_i32 in the new function, while we're at it.
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20221001140935.465607-12-richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Richard Henderson [Sat, 1 Oct 2022 14:09:19 +0000 (07:09 -0700)]
target/i386: USe DISAS_EOB_ONLY
Replace lone calls to gen_eob() with the new enumerator.
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20221001140935.465607-11-richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Richard Henderson [Sat, 1 Oct 2022 14:09:18 +0000 (07:09 -0700)]
target/i386: Use DISAS_EOB_NEXT
Replace sequences of gen_update_cc_op, gen_update_eip_next,
and gen_eob with the new is_jmp enumerator.
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20221001140935.465607-10-richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Richard Henderson [Sat, 1 Oct 2022 14:09:17 +0000 (07:09 -0700)]
target/i386: Use DISAS_EOB* in gen_movl_seg_T0
Set is_jmp properly in gen_movl_seg_T0, so that the callers
need to nothing special.
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20221001140935.465607-9-richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Richard Henderson [Sat, 1 Oct 2022 14:09:16 +0000 (07:09 -0700)]
target/i386: Introduce DISAS_EOB*
Add a few DISAS_TARGET_* aliases to reduce the number of
calls to gen_eob() and gen_eob_inhibit_irq(). So far,
only update i386_tr_translate_insn for exiting the block
because of single-step or previous inhibit irq.
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20221001140935.465607-8-richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Richard Henderson [Sat, 1 Oct 2022 14:09:15 +0000 (07:09 -0700)]
target/i386: Create gen_update_eip_next
Sync EIP before exiting a translation block.
Replace all gen_jmp_im that use s->pc.
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20221001140935.465607-7-richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Richard Henderson [Sat, 1 Oct 2022 14:09:14 +0000 (07:09 -0700)]
target/i386: Create gen_update_eip_cur
Like gen_update_cc_op, sync EIP before doing something
that could raise an exception. Replace all gen_jmp_im
that use s->base.pc_next.
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20221001140935.465607-6-richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Richard Henderson [Sat, 1 Oct 2022 14:09:13 +0000 (07:09 -0700)]
target/i386: Remove cur_eip, next_eip arguments to gen_interrupt
All callers pass s->base.pc_next and s->pc, which we can just as
well compute within the function. Adjust to use tcg_constant_i32
while we're at it.
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20221001140935.465607-5-richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Richard Henderson [Sat, 1 Oct 2022 14:09:12 +0000 (07:09 -0700)]
target/i386: Remove cur_eip argument to gen_exception
All callers pass s->base.pc_next - s->cs_base, which we can just
as well compute within the function. Note the special case of
EXCP_VSYSCALL in which s->cs_base wasn't subtracted, but cs_base
is always zero in 64-bit mode, when vsyscall is used.
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20221001140935.465607-4-richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Richard Henderson [Sat, 1 Oct 2022 14:09:11 +0000 (07:09 -0700)]
target/i386: Return bool from disas_insn
Instead of returning the new pc, which is present in
DisasContext, return true if an insn was translated.
This is false when we detect a page crossing and must
undo the insn under translation.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <
20221001140935.465607-3-richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Richard Henderson [Sat, 1 Oct 2022 14:09:10 +0000 (07:09 -0700)]
target/i386: Remove pc_start
The DisasContext member and the disas_insn local variable of
the same name are identical to DisasContextBase.pc_next.
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20221001140935.465607-2-richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Chenyi Qiang [Thu, 29 Sep 2022 07:20:14 +0000 (15:20 +0800)]
i386: add notify VM exit support
There are cases that malicious virtual machine can cause CPU stuck (due
to event windows don't open up), e.g., infinite loop in microcode when
nested #AC (CVE-2015-5307). No event window means no event (NMI, SMI and
IRQ) can be delivered. It leads the CPU to be unavailable to host or
other VMs. Notify VM exit is introduced to mitigate such kind of
attacks, which will generate a VM exit if no event window occurs in VM
non-root mode for a specified amount of time (notify window).
A new KVM capability KVM_CAP_X86_NOTIFY_VMEXIT is exposed to user space
so that the user can query the capability and set the expected notify
window when creating VMs. The format of the argument when enabling this
capability is as follows:
Bit 63:32 - notify window specified in qemu command
Bit 31:0 - some flags (e.g. KVM_X86_NOTIFY_VMEXIT_ENABLED is set to
enable the feature.)
Users can configure the feature by a new (x86 only) accel property:
qemu -accel kvm,notify-vmexit=run|internal-error|disable,notify-window=n
The default option of notify-vmexit is run, which will enable the
capability and do nothing if the exit happens. The internal-error option
raises a KVM internal error if it happens. The disable option does not
enable the capability. The default value of notify-window is 0. It is valid
only when notify-vmexit is not disabled. The valid range of notify-window
is non-negative. It is even safe to set it to zero since there's an
internal hardware threshold to be added to ensure no false positive.
Because a notify VM exit may happen with VM_CONTEXT_INVALID set in exit
qualification (no cases are anticipated that would set this bit), which
means VM context is corrupted. It would be reflected in the flags of
KVM_EXIT_NOTIFY exit. If KVM_NOTIFY_CONTEXT_INVALID bit is set, raise a KVM
internal error unconditionally.
Acked-by: Peter Xu <peterx@redhat.com>
Signed-off-by: Chenyi Qiang <chenyi.qiang@intel.com>
Message-Id: <
20220929072014.20705-5-chenyi.qiang@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Chenyi Qiang [Thu, 29 Sep 2022 07:20:13 +0000 (15:20 +0800)]
kvm: expose struct KVMState
Expose struct KVMState out of kvm-all.c so that the field of struct
KVMState can be accessed when defining target-specific accelerator
properties.
Signed-off-by: Chenyi Qiang <chenyi.qiang@intel.com>
Message-Id: <
20220929072014.20705-4-chenyi.qiang@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Peter Maydell [Mon, 3 Oct 2022 16:23:15 +0000 (17:23 +0100)]
docs/system/arm/emulation.rst: Report FEAT_GTG support
FEAT_GTG is a change tho the ID register ID_AA64MMFR0_EL1 so that it
can report a different set of supported granule (page) sizes for
stage 1 and stage 2 translation tables. As of commit
c20281b2a5048
we already report the granule sizes that way for '-cpu max', and now
we also correctly make attempts to use unimplemented granule sizes
fail, so we can report the support of the feature in the
documentation.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id:
20221003162315.
2833797-4-peter.maydell@linaro.org
Peter Maydell [Mon, 3 Oct 2022 16:23:14 +0000 (17:23 +0100)]
target/arm: Use ARMGranuleSize in ARMVAParameters
Now we have an enum for the granule size, use it in the
ARMVAParameters struct instead of the using16k/using64k bools.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20221003162315.
2833797-3-peter.maydell@linaro.org
Peter Maydell [Mon, 3 Oct 2022 16:23:13 +0000 (17:23 +0100)]
target/arm: Don't allow guest to use unimplemented granule sizes
Arm CPUs support some subset of the granule (page) sizes 4K, 16K and
64K. The guest selects the one it wants using bits in the TCR_ELx
registers. If it tries to program these registers with a value that
is either reserved or which requests a size that the CPU does not
implement, the architecture requires that the CPU behaves as if the
field was programmed to some size that has been implemented.
Currently we don't implement this, and instead let the guest use any
granule size, even if the CPU ID register fields say it isn't
present.
Make aa64_va_parameters() check against the supported granule size
and force use of a different one if it is not implemented.
(A subsequent commit will make ARMVAParameters use the new enum
rather than the current pair of using16k/using64k bools.)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id:
20221003162315.
2833797-2-peter.maydell@linaro.org
Jerome Forissier [Mon, 3 Oct 2022 14:56:41 +0000 (16:56 +0200)]
hw/arm/boot: set CPTR_EL3.ESM and SCR_EL3.EnTP2 when booting Linux with EL3
According to the Linux kernel booting.rst [1], CPTR_EL3.ESM and
SCR_EL3.EnTP2 must be initialized to 1 when EL3 is present and FEAT_SME
is advertised. This has to be taken care of when QEMU boots directly
into the kernel (i.e., "-M virt,secure=on -cpu max -kernel Image").
Cc: qemu-stable@nongnu.org
Fixes:
78cb9776662a ("target/arm: Enable SME for -cpu max")
Link: [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/arm64/booting.rst?h=v6.0#n321
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Message-id:
20221003145641.
1921467-1-jerome.forissier@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Sat, 1 Oct 2022 16:22:56 +0000 (09:22 -0700)]
target/arm: Use tlb_set_page_full
Adjust GetPhysAddrResult to fill in CPUTLBEntryFull,
so that it may be passed directly to tlb_set_page_full.
The change is large, but mostly mechanical. The major
non-mechanical change is page_size -> lg_page_size.
Most of the time this is obvious, and is related to
TARGET_PAGE_BITS.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id:
20221001162318.153420-21-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Sat, 1 Oct 2022 16:22:55 +0000 (09:22 -0700)]
target/arm: Fix cacheattr in get_phys_addr_disabled
Do not apply memattr or shareability for Stage2 translations.
Make sure to apply HCR_{DC,DCT} only to Regime_EL10, per the
pseudocode in AArch64.S1DisabledOutput.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id:
20221001162318.153420-20-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Sat, 1 Oct 2022 16:22:54 +0000 (09:22 -0700)]
target/arm: Split out get_phys_addr_disabled
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20221001162318.153420-19-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Sat, 1 Oct 2022 16:22:53 +0000 (09:22 -0700)]
target/arm: Fix ATS12NSO* from S PL1
Use arm_hcr_el2_eff_secstate instead of arm_hcr_el2_eff, so
that we use is_secure instead of the current security state.
These AT* operations have been broken since arm_hcr_el2_eff
gained a check for "el2 enabled" for Secure EL2.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20221001162318.153420-18-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Sat, 1 Oct 2022 16:22:52 +0000 (09:22 -0700)]
target/arm: Pass HCR to attribute subroutines.
These subroutines did not need ENV for anything except
retrieving the effective value of HCR anyway.
We have computed the effective value of HCR in the callers,
and this will be especially important for interpreting HCR
in a non-current security state.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20221001162318.153420-17-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Sat, 1 Oct 2022 16:22:51 +0000 (09:22 -0700)]
target/arm: Remove env argument from combined_attrs_fwb
This value is unused.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id:
20221001162318.153420-16-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Sat, 1 Oct 2022 16:22:50 +0000 (09:22 -0700)]
target/arm: Hoist read of *is_secure in S1_ptw_translate
Rename the argument to is_secure_ptr, and introduce a
local variable is_secure with the value. We only write
back to the pointer toward the end of the function.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20221001162318.153420-15-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Sat, 1 Oct 2022 16:22:49 +0000 (09:22 -0700)]
target/arm: Introduce arm_hcr_el2_eff_secstate
For page walking, we may require HCR for a security state
that is not "current".
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20221001162318.153420-14-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Sat, 1 Oct 2022 16:22:48 +0000 (09:22 -0700)]
target/arm: Drop secure check for HCR.TGE vs SCTLR_EL1.M
The effect of TGE does not only apply to non-secure state,
now that Secure EL2 exists.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20221001162318.153420-13-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Sat, 1 Oct 2022 16:22:47 +0000 (09:22 -0700)]
target/arm: Reorg regime_translation_disabled
Use a switch on mmu_idx for the a-profile indexes, instead of
three different if's vs regime_el and arm_mmu_idx_is_stage1_of_2.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20221001162318.153420-12-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Sat, 1 Oct 2022 16:22:46 +0000 (09:22 -0700)]
target/arm: Fold secure and non-secure a-profile mmu indexes
For a-profile aarch64, which does not bank system registers, it takes
quite a lot of code to switch between security states. In the process,
registers such as TCR_EL{1,2} must be swapped, which in itself requires
the flushing of softmmu tlbs. Therefore it doesn't buy us anything to
separate tlbs by security state.
Retain the distinction between Stage2 and Stage2_S.
This will be important as we implement FEAT_RME, and do not wish to
add a third set of mmu indexes for Realm state.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20221001162318.153420-11-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Sat, 1 Oct 2022 16:22:45 +0000 (09:22 -0700)]
target/arm: Add is_secure parameter to do_ats_write
Use get_phys_addr_with_secure directly. For a-profile, this is the
one place where the value of is_secure may not equal arm_is_secure(env).
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20221001162318.153420-10-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Sat, 1 Oct 2022 16:22:44 +0000 (09:22 -0700)]
target/arm: Merge regime_is_secure into get_phys_addr
This is the last use of regime_is_secure; remove it
entirely before changing the layout of ARMMMUIdx.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20221001162318.153420-9-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Sat, 1 Oct 2022 16:22:43 +0000 (09:22 -0700)]
target/arm: Add TBFLAG_M32.SECURE
Remove the use of regime_is_secure from arm_tr_init_disas_context.
Instead, provide the value of v8m_secure directly from tb_flags.
Rather than use regime_is_secure, use the env->v7m.secure directly,
as per arm_mmu_idx_el.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20221001162318.153420-8-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Sat, 1 Oct 2022 16:22:42 +0000 (09:22 -0700)]
target/arm: Add is_secure parameter to v7m_read_half_insn
Remove the use of regime_is_secure from v7m_read_half_insn, using
the new parameter instead.
As it happens, both callers pass true, propagated from the argument
to arm_v7m_mmu_idx_for_secstate which created the mmu_idx argument,
but that is a detail of v7m_handle_execute_nsc we need not expose
to the callee.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20221001162318.153420-7-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Sat, 1 Oct 2022 16:22:41 +0000 (09:22 -0700)]
target/arm: Split out get_phys_addr_with_secure
Retain the existing get_phys_addr interface using the security
state derived from mmu_idx. Move the kerneldoc comments to the
header file where they belong.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20221001162318.153420-6-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Sat, 1 Oct 2022 16:22:40 +0000 (09:22 -0700)]
target/arm: Add is_secure parameter to regime_translation_disabled
Remove the use of regime_is_secure from regime_translation_disabled,
using the new parameter instead.
This fixes a bug in S1_ptw_translate and get_phys_addr where we had
passed ARMMMUIdx_Stage2 and not ARMMMUIdx_Stage2_S to determine if
Stage2 is disabled, affecting FEAT_SEL2.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20221001162318.153420-5-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Sat, 1 Oct 2022 16:22:39 +0000 (09:22 -0700)]
target/arm: Fix S2 disabled check in S1_ptw_translate
Pass the correct stage2 mmu_idx to regime_translation_disabled,
which we computed afterward.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id:
20221001162318.153420-4-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Sat, 1 Oct 2022 16:22:38 +0000 (09:22 -0700)]
target/arm: Add is_secure parameter to get_phys_addr_lpae
Remove the use of regime_is_secure from get_phys_addr_lpae,
using the new parameter instead.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20221001162318.153420-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Fri, 7 Oct 2022 15:21:59 +0000 (08:21 -0700)]
target/arm: Make the final stage1+2 write to secure be unconditional
While the stage2 call to get_phys_addr_lpae should never set
attrs.secure when given a non-secure input, it's just as easy
to make the final update to attrs.secure be unconditional and
false in the case of non-secure input.
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20221007152159.
1414065-1-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Sat, 1 Oct 2022 16:22:37 +0000 (09:22 -0700)]
target/arm: Split s2walk_secure from ipa_secure in get_phys_addr
The starting security state comes with the translation regime,
not the current state of arm_is_secure_below_el3().
Create a new local variable, s2walk_secure, which does not need
to be written back to result->attrs.secure -- we compute that
value later, after the S2 walk is complete.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id:
20221001162318.153420-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Joel Stanley [Tue, 4 Oct 2022 05:00:42 +0000 (15:30 +1030)]
docs/nuvoton: Update URL for images
openpower.xyz was retired some time ago. The OpenBMC Jenkins is where
images can be found these days.
Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Hao Wu <wuhaotsh@google.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id:
20221004050042.22681-1-joel@jms.id.au
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Jerome Forissier [Tue, 4 Oct 2022 07:23:54 +0000 (09:23 +0200)]
target/arm: allow setting SCR_EL3.EnTP2 when FEAT_SME is implemented
Updates write_scr() to allow setting SCR_EL3.EnTP2 when FEAT_SME is
implemented. SCR_EL3 being a 64-bit register, valid_mask is changed
to uint64_t and the SCR_* constants in target/arm/cpu.h are extended
to 64-bit so that masking and bitwise not (~) behave as expected.
This enables booting Linux with Trusted Firmware-A at EL3 with
"-M virt,secure=on -cpu max".
Cc: qemu-stable@nongnu.org
Fixes:
78cb9776662a ("target/arm: Enable SME for -cpu max")
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20221004072354.27037-1-jerome.forissier@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Maydell [Fri, 30 Sep 2022 11:38:24 +0000 (12:38 +0100)]
target/arm/kvm: Retry KVM_CREATE_VM call if it fails EINTR
Occasionally the KVM_CREATE_VM ioctl can return EINTR, even though
there is no pending signal to be taken. In commit
94ccff13382055
we added a retry-on-EINTR loop to the KVM_CREATE_VM call in the
generic KVM code. Adopt the same approach for the use of the
ioctl in the Arm-specific KVM code (where we use it to create a
scratch VM for probing for various things).
For more information, see the mailing list thread:
https://lore.kernel.org/qemu-devel/8735e0s1zw.wl-maz@kernel.org/
Reported-by: Vitaly Chikunov <vt@altlinux.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Vitaly Chikunov <vt@altlinux.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Acked-by: Marc Zyngier <maz@kernel.org>
Message-id:
20220930113824.
1933293-1-peter.maydell@linaro.org
Paolo Bonzini [Thu, 29 Sep 2022 07:20:12 +0000 (15:20 +0800)]
kvm: allow target-specific accelerator properties
Several hypervisor capabilities in KVM are target-specific. When exposed
to QEMU users as accelerator properties (i.e. -accel kvm,prop=value), they
should not be available for all targets.
Add a hook for targets to add their own properties to -accel kvm, for
now no such property is defined.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <
20220929072014.20705-3-chenyi.qiang@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Chenyi Qiang [Thu, 29 Sep 2022 07:20:11 +0000 (15:20 +0800)]
i386: kvm: extend kvm_{get, put}_vcpu_events to support pending triple fault
For the direct triple faults, i.e. hardware detected and KVM morphed
to VM-Exit, KVM will never lose them. But for triple faults sythesized
by KVM, e.g. the RSM path, if KVM exits to userspace before the request
is serviced, userspace could migrate the VM and lose the triple fault.
A new flag KVM_VCPUEVENT_VALID_TRIPLE_FAULT is defined to signal that
the event.triple_fault_pending field contains a valid state if the
KVM_CAP_X86_TRIPLE_FAULT_EVENT capability is enabled.
Acked-by: Peter Xu <peterx@redhat.com>
Signed-off-by: Chenyi Qiang <chenyi.qiang@intel.com>
Message-Id: <
20220929072014.20705-2-chenyi.qiang@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
John Millikin [Thu, 4 Aug 2022 12:29:51 +0000 (21:29 +0900)]
scsi-disk: support setting CD-ROM block size via device options
SunOS expects CD-ROM devices to have a block size of 512, and will
fail to mount or install using QEMU's default block size of 2048.
When initializing the SCSI device, allow the `physical_block_size'
block device option to override the default block size.
Signed-off-by: John Millikin <john@john-millikin.com>
Message-Id: <
20220804122950.
1577012-1-john@john-millikin.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Igor Mammedov [Fri, 1 Jul 2022 13:35:15 +0000 (09:35 -0400)]
x86: pci: acpi: consolidate PCI slots creation
No functional changes nor AML bytecode changes.
Consolidate code that generates empty and populated slot
descriptors. Besides eliminating duplication,
it helps consolidate conditions for generating
parts of Device{} desriptor in one place, which makes
code more compact and easier to read.
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <
20220701133515.137890-18-imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Igor Mammedov [Fri, 1 Jul 2022 13:35:14 +0000 (09:35 -0400)]
tests: acpi: update expected blobs
Expected change:
+ Device (SE8)
+ {
+ Name (_ADR, 0x001D0000) // _ADR: Address
+ Name (ASUN, 0x1D)
Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method
{
Local0 = Package (0x02)
{
BSEL,
ASUN
}
Return (PDSM (Arg0, Arg1, Arg2, Arg3, Local0))
}
- }
- Device (SE8)
- {
- Name (_ADR, 0x001D0000) // _ADR: Address
- Name (ASUN, 0x1D)
Name (_SUN, 0x1D) // _SUN: Slot User Number
Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device
{
PCEJ (BSEL, _SUN)
}
+ }
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <
20220701133515.137890-17-imammedo@redhat.com>
Igor Mammedov [Fri, 1 Jul 2022 13:35:13 +0000 (09:35 -0400)]
x86: pci: acpi: reorder Device's _DSM method
align _DSM method in empty slot descriptor with
a populated slot position.
Expected change:
+ Device (SE8)
+ {
+ Name (_ADR, 0x001D0000) // _ADR: Address
+ Name (ASUN, 0x1D)
Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method
{
Local0 = Package (0x02)
{
BSEL,
ASUN
}
Return (PDSM (Arg0, Arg1, Arg2, Arg3, Local0))
}
- }
- Device (SE8)
- {
- Name (_ADR, 0x001D0000) // _ADR: Address
- Name (ASUN, 0x1D)
Name (_SUN, 0x1D) // _SUN: Slot User Number
Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device
{
PCEJ (BSEL, _SUN)
}
+ }
i.e. put _DSM right after ASUN, with _SUN/_EJ0 following it.
that will eliminate contextual changes (causing test failures)
when follow up patches merge code generating populated and empty
slots descriptors.
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <
20220701133515.137890-16-imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Igor Mammedov [Fri, 1 Jul 2022 13:35:12 +0000 (09:35 -0400)]
tests: acpi: whitelist pc/q35 DSDT before moving _ADR field
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <
20220701133515.137890-15-imammedo@redhat.com>
Igor Mammedov [Fri, 1 Jul 2022 13:35:11 +0000 (09:35 -0400)]
tests: acpi: update expected blobs
Expected change:
- Name (_SUN, 0x0X) // _SUN: Slot User Number
Name (_ADR, 0xY) // _ADR: Address
...
+ Name (_SUN, 0xX) // _SUN: Slot User Number
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <
20220701133515.137890-14-imammedo@redhat.com>
Igor Mammedov [Fri, 1 Jul 2022 13:35:10 +0000 (09:35 -0400)]
x86: pci: acpi: reorder Device's _ADR and _SUN fields
no functional change, align order of fields in empty slot
descriptor with a populated slot ordering.
Expected diff:
- Name (_SUN, 0x0X) // _SUN: Slot User Number
Name (_ADR, 0xY) // _ADR: Address
...
+ Name (_SUN, 0xX) // _SUN: Slot User Number
that will eliminate contextual changes (causing test failures)
when follow up patches merge code generating populated and empty
slots descriptors.
Put mandatory _ADR as the 1st field, then ASUN as it can be
present for both pupulated and empty slots and only then _SUN
which is present only when slot is hotpluggable.
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <
20220701133515.137890-13-imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Igor Mammedov [Fri, 1 Jul 2022 13:35:09 +0000 (09:35 -0400)]
tests: acpi: whitelist pc/q35 DSDT before moving _ADR field
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <
20220701133515.137890-12-imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Igor Mammedov [Fri, 1 Jul 2022 13:35:08 +0000 (09:35 -0400)]
tests: acpi: update expected blobs
It's expected that hotpluggable slots will, get ASUN variable
and use that instead of _SUN with its _DSM method.
For example:
@@ -979,8 +979,9 @@ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001)
Device (S18)
{
- Name (_SUN, 0x03) // _SUN: Slot User Number
+ Name (ASUN, 0x03)
Name (_ADR, 0x00030000) // _ADR: Address
+ Name (_SUN, 0x03) // _SUN: Slot User Number
Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device
{
PCEJ (BSEL, _SUN)
@@ -991,7 +992,7 @@ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001)
Local0 = Package (0x02)
{
BSEL,
- _SUN
+ ASUN
}
Return (PDSM (Arg0, Arg1, Arg2, Arg3, Local0))
}
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <
20220701133515.137890-11-imammedo@redhat.com>
Igor Mammedov [Fri, 1 Jul 2022 13:35:07 +0000 (09:35 -0400)]
x86: acpi: cleanup PCI device _DSM duplication
add ASUN variable to hotpluggable slots and use it
instead of _SUN which has the same value to reuse
_DMS code on both branches (hot- and non-hotpluggable).
No functional change.
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <
20220701133515.137890-10-imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Igor Mammedov [Fri, 1 Jul 2022 13:35:06 +0000 (09:35 -0400)]
tests: acpi: whitelist pc/q35 DSDT before switching _DSM to use ASUN
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <
20220701133515.137890-9-imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Igor Mammedov [Fri, 1 Jul 2022 13:35:05 +0000 (09:35 -0400)]
tests: acpi: update expected blobs
An intermediate blobs update to keep changes (last 2 patches)
reviewable.
Includes refactored PDSM that uses Package argument for custom
parameters.
===== PDSM taking package as arguments
Return (Local0)
}
- Method (PDSM, 6, Serialized)
+ Method (PDSM, 5, Serialized)
{
- If ((Arg0 == ToUUID ("
e5c937d0-3553-4d7a-9117-
ea4d19c3434d") /* Device Labeling Interface */))
+ If ((Arg2 == Zero))
{
- Local0 = AIDX (Arg4, Arg5)
- If ((Arg2 == Zero))
- {
- If ((Arg1 == 0x02))
+ Local0 = Buffer (One)
{
- If (!((Local0 == Zero) | (Local0 == 0xFFFFFFFF)))
- {
- Return (Buffer (One)
- {
- 0x81 // .
- })
- }
+ 0x00 // .
}
+ Local1 = Zero
+ If ((Arg0 != ToUUID ("
e5c937d0-3553-4d7a-9117-
ea4d19c3434d") /* Device Labeling Interface */))
+ {
+ Return (Local0)
+ }
- Return (Buffer (One)
- {
- 0x00 // .
- })
+ If ((Arg1 < 0x02))
+ {
+ Return (Local0)
}
- ElseIf ((Arg2 == 0x07))
+
+ Local2 = AIDX (DerefOf (Arg4 [Zero]), DerefOf (Arg4 [One]
+ ))
+ If (!((Local2 == Zero) | (Local2 == 0xFFFFFFFF)))
{
- Local1 = Package (0x02)
- {
- Zero,
- ""
- }
- Local1 [Zero] = Local0
- Return (Local1)
+ Local1 |= One
+ Local1 |= (One << 0x07)
}
+
+ Local0 [Zero] = Local1
+ Return (Local0)
+ }
+
+ If ((Arg2 == 0x07))
+ {
+ Local0 = Package (0x02)
+ {
+ Zero,
+ ""
+ }
+ Local2 = AIDX (DerefOf (Arg4 [Zero]), DerefOf (Arg4 [One]
+ ))
+ Local0 [Zero] = Local2
+ Return (Local0)
}
}
}
===== PCI slot using Package to pass arguments to _DSM
Name (ASUN, Zero)
Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method
{
- Return (PDSM (Arg0, Arg1, Arg2, Arg3, BSEL, ASUN))
+ Local0 = Package (0x02)
+ {
+ BSEL,
+ ASUN
+ }
+ Return (PDSM (Arg0, Arg1, Arg2, Arg3, Local0))
}
}
===== hotpluggable PCI slot using Package to pass arguments to _DSM
Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method
{
- Return (PDSM (Arg0, Arg1, Arg2, Arg3, BSEL, _SUN))
+ Local0 = Package (0x02)
+ {
+ BSEL,
+ _SUN
+ }
+ Return (PDSM (Arg0, Arg1, Arg2, Arg3, Local0))
}
}
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <
20220701133515.137890-8-imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Igor Mammedov [Fri, 1 Jul 2022 13:35:04 +0000 (09:35 -0400)]
x86: acpi: _DSM: use Package to pass parameters
Numer of possible arguments to pass to a method is limited
in ACPI. The following patches will need to pass over more
parameters to PDSM method, will hit that limit.
Prepare for this by passing structure (Package) to method,
which let us workaround arguments limitation.
Pass to PDSM all standard arguments of _DSM as is, and
pack custom parameters into Package that is passed as
the last argument to PDSM.
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <
20220701133515.137890-7-imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Igor Mammedov [Fri, 1 Jul 2022 13:35:03 +0000 (09:35 -0400)]
acpi: x86: refactor PDSM method to reduce nesting
.., it will help with code readability and make easier
to extend method in followup patches
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <
20220701133515.137890-6-imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Igor Mammedov [Fri, 1 Jul 2022 13:35:02 +0000 (09:35 -0400)]
tests: acpi: whitelist pc/q35 DSDT due to HPET AML move
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <
20220701133515.137890-5-imammedo@redhat.com>
Igor Mammedov [Fri, 1 Jul 2022 13:35:01 +0000 (09:35 -0400)]
tests: acpi: update expected blobs after HPET move
HPET AML moved after PCI host bridge description (no functional change)
diff example for PC machine:
@@ -54,47 +54,6 @@ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001)
}
}
- Scope (_SB)
- {
- Device (HPET)
- {
- Name (_HID, EisaId ("PNP0103") /* HPET System Timer */) // _HID: Hardware ID
- Name (_UID, Zero) // _UID: Unique ID
- OperationRegion (HPTM, SystemMemory, 0xFED00000, 0x0400)
- Field (HPTM, DWordAcc, Lock, Preserve)
- {
- VEND, 32,
- PRD, 32
- }
-
- Method (_STA, 0, NotSerialized) // _STA: Status
- {
- Local0 = VEND /* \_SB_.HPET.VEND */
- Local1 = PRD /* \_SB_.HPET.PRD_ */
- Local0 >>= 0x10
- If (((Local0 == Zero) || (Local0 == 0xFFFF)))
- {
- Return (Zero)
- }
-
- If (((Local1 == Zero) || (Local1 > 0x05F5E100)))
- {
- Return (Zero)
- }
-
- Return (0x0F)
- }
-
- Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
- {
- Memory32Fixed (ReadOnly,
- 0xFED00000, // Address Base
- 0x00000400, // Address Length
- )
- })
- }
- }
-
Scope (_SB.PCI0)
{
Device (ISA)
@@ -529,6 +488,47 @@ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001)
}
}
+ Scope (_SB)
+ {
+ Device (HPET)
+ {
+ Name (_HID, EisaId ("PNP0103") /* HPET System Timer */) // _HID: Hardware ID
+ Name (_UID, Zero) // _UID: Unique ID
+ OperationRegion (HPTM, SystemMemory, 0xFED00000, 0x0400)
+ Field (HPTM, DWordAcc, Lock, Preserve)
+ {
+ VEND, 32,
+ PRD, 32
+ }
+
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Local0 = VEND /* \_SB_.HPET.VEND */
+ Local1 = PRD /* \_SB_.HPET.PRD_ */
+ Local0 >>= 0x10
+ If (((Local0 == Zero) || (Local0 == 0xFFFF)))
+ {
+ Return (Zero)
+ }
+
+ If (((Local1 == Zero) || (Local1 > 0x05F5E100)))
+ {
+ Return (Zero)
+ }
+
+ Return (0x0F)
+ }
+
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadOnly,
+ 0xFED00000, // Address Base
+ 0x00000400, // Address Length
+ )
+ })
+ }
+ }
+
Scope (_SB)
{
Device (\_SB.PCI0.PRES)
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <
20220701133515.137890-4-imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Igor Mammedov [Fri, 1 Jul 2022 13:35:00 +0000 (09:35 -0400)]
acpi: x86: deduplicate HPET AML building
HPET AML doesn't depend on piix4 nor q35, move code buiding it
to common scope to avoid duplication.
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <
20220701133515.137890-3-imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Igor Mammedov [Fri, 1 Jul 2022 13:34:59 +0000 (09:34 -0400)]
tests: acpi: whitelist pc/q35 DSDT due to HPET AML move
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <
20220701133515.137890-2-imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Hal Martin [Fri, 12 Aug 2022 13:51:53 +0000 (15:51 +0200)]
hw/smbios: support for type 8 (port connector)
PATCH v1: add support for SMBIOS type 8 to qemu
PATCH v2: incorporate patch v1 feedback and add smbios type=8 to qemu-options
internal_reference: internal reference designator
external_reference: external reference designator
connector_type: hex value for port connector type (see SMBIOS 7.9.2)
port_type: hex value for port type (see SMBIOS 7.9.3)
After studying various vendor implementationsi (Dell, Lenovo, MSI),
the value of internal connector type was hard-coded to 0x0 (None).
Example usage:
-smbios type=8,internal_reference=JUSB1,external_reference=USB1,connector_type=0x12,port_type=0x10 \
-smbios type=8,internal_reference=JAUD1,external_reference="Audio Jack",connector_type=0x1f,port_type=0x1d \
-smbios type=8,internal_reference=LAN,external_reference=Ethernet,connector_type=0x0b,port_type=0x1f \
-smbios type=8,internal_reference=PS2,external_reference=Mouse,connector_type=0x0f,port_type=0x0e \
-smbios type=8,internal_reference=PS2,external_reference=Keyboard,connector_type=0x0f,port_type=0x0d
Signed-off-by: Hal Martin <hal.martin@gmail.com>
Message-Id: <
20220812135153.17859-1-hal.martin@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Peter Maydell [Thu, 18 Aug 2022 13:54:21 +0000 (14:54 +0100)]
pci: Sanity check mask argument to pci_set_*_by_mask()
Coverity complains that in functions like pci_set_word_by_mask()
we might end up shifting by more than 31 bits. This is true,
but only if the caller passes in a zero mask. Help Coverity out
by asserting that the mask argument is valid.
Fixes: CID
1487168
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <
20220818135421.
2515257-3-peter.maydell@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Peter Maydell [Thu, 18 Aug 2022 13:54:20 +0000 (14:54 +0100)]
pci: Remove unused pci_get_*_by_mask() functions
The helper functions pci_get_{byte,word,long,quad}_by_mask()
were added in 2012 in commit
c9f50cea70a1596. In the decade
since we have never added a single use of them.
The helpers clearly aren't that helpful, so drop them
rather than carrying around dead code.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <
20220818135421.
2515257-2-peter.maydell@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Laurent Vivier [Thu, 11 Aug 2022 12:24:44 +0000 (08:24 -0400)]
hmp: add virtio commands
This patch implements the HMP versions of the virtio QMP commands.
[Jonah: Adjusted hmp monitor output format for features / statuses
with their descriptions.]
Signed-off-by: Laurent Vivier <lvivier@redhat.com>
Signed-off-by: Jonah Palmer <jonah.palmer@oracle.com>
Message-Id: <
1660220684-24909-7-git-send-email-jonah.palmer@oracle.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Laurent Vivier [Thu, 11 Aug 2022 12:24:43 +0000 (08:24 -0400)]
qmp: add QMP command x-query-virtio-queue-element
This new command shows the information of a VirtQueue element.
[Note: Up until v10 of this patch series, virtio.json had many (15+)
enums defined (e.g. decoded device features, statuses, etc.). In v10
most of these enums were removed and replaced with string literals.
By doing this we get (1) simpler schema, (2) smaller generated code,
and (3) less maintenance burden for when new things are added (e.g.
devices, device features, etc.).]
Signed-off-by: Laurent Vivier <lvivier@redhat.com>
Signed-off-by: Jonah Palmer <jonah.palmer@oracle.com>
Message-Id: <
1660220684-24909-6-git-send-email-jonah.palmer@oracle.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Laurent Vivier [Thu, 11 Aug 2022 12:24:42 +0000 (08:24 -0400)]
qmp: add QMP commands for virtio/vhost queue-status
These new commands show the internal status of a VirtIODevice's
VirtQueue and a vhost device's vhost_virtqueue (if active).
Signed-off-by: Laurent Vivier <lvivier@redhat.com>
Signed-off-by: Jonah Palmer <jonah.palmer@oracle.com>
Message-Id: <
1660220684-24909-5-git-send-email-jonah.palmer@oracle.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Laurent Vivier [Thu, 11 Aug 2022 12:24:41 +0000 (08:24 -0400)]
qmp: decode feature & status bits in virtio-status
Display feature names instead of bitmaps for host, guest, and
backend for VirtIODevices.
Display status names instead of bitmaps for VirtIODevices.
Display feature names instead of bitmaps for backend, protocol,
acked, and features (hdev->features) for vhost devices.
Decode features according to device ID. Decode statuses
according to configuration status bitmap (config_status_map).
Decode vhost user protocol features according to vhost user
protocol bitmap (vhost_user_protocol_map).
Transport features are on the first line. Undecoded bits (if
any) are stored in a separate field.
[Jonah: Several changes made to this patch from prev. version (v14):
- Moved all device features mappings to hw/virtio/virtio.c
- Renamed device features mappings (less generic)
- Generalized @FEATURE_ENTRY macro for all device mappings
- Virtio device feature map definitions include descriptions of
feature bits
- Moved @VHOST_USER_F_PROTOCOL_FEATURES feature bit from transport
feature map to vhost-user-supported device feature mappings
(blk, fs, i2c, rng, net, gpu, input, scsi, vsock)
- New feature bit added for virtio-vsock: @VIRTIO_VSOCK_F_SEQPACKET
- New feature bit added for virtio-iommu: @VIRTIO_IOMMU_F_BYPASS_CONFIG
- New feature bit added for virtio-mem: @VIRTIO_MEM_F_UNPLUGGED_INACCESSIBLE
- New virtio transport feature bit added: @VIRTIO_F_IN_ORDER
- Added device feature map definition for virtio-rng
]
Signed-off-by: Laurent Vivier <lvivier@redhat.com>
Signed-off-by: Jonah Palmer <jonah.palmer@oracle.com>
Message-Id: <
1660220684-24909-4-git-send-email-jonah.palmer@oracle.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Laurent Vivier [Thu, 11 Aug 2022 12:24:40 +0000 (08:24 -0400)]
qmp: add QMP command x-query-virtio-status
This new command shows the status of a VirtIODevice, including
its corresponding vhost device's status (if active).
Next patch will improve output by decoding feature bits, including
vhost device's feature bits (backend, protocol, acked, and features).
Also will decode status bits of a VirtIODevice.
[Jonah: From patch v12; added a check to @virtio_device_find to ensure
synchronicity between @virtio_list and the devices in the QOM
composition tree.]
Signed-off-by: Laurent Vivier <lvivier@redhat.com>
Signed-off-by: Jonah Palmer <jonah.palmer@oracle.com>
Message-Id: <
1660220684-24909-3-git-send-email-jonah.palmer@oracle.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Laurent Vivier [Thu, 11 Aug 2022 12:24:39 +0000 (08:24 -0400)]
qmp: add QMP command x-query-virtio
This new command lists all the instances of VirtIODevices with
their canonical QOM path and name.
[Jonah: @virtio_list duplicates information that already exists in
the QOM composition tree. However, extracting necessary information
from this tree seems to be a bit convoluted.
Instead, we still create our own list of realized virtio devices
but use @qmp_qom_get with the device's canonical QOM path to confirm
that the device exists and is realized. If the device exists but
is actually not realized, then we remove it from our list (for
synchronicity to the QOM composition tree).
Also, the QMP command @x-query-virtio is redundant as @qom-list
and @qom-get are sufficient to search '/machine/' for realized
virtio devices. However, @x-query-virtio is much more convenient
in listing realized virtio devices.]
Signed-off-by: Laurent Vivier <lvivier@redhat.com>
Signed-off-by: Jonah Palmer <jonah.palmer@oracle.com>
Message-Id: <
1660220684-24909-2-git-send-email-jonah.palmer@oracle.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Peter Xu [Mon, 26 Sep 2022 15:32:06 +0000 (11:32 -0400)]
Revert "intel_iommu: Fix irqchip / X2APIC configuration checks"
It's true that when vcpus<=255 we don't require the length of 32bit APIC
IDs. However here since we already have EIM=ON it means the hypervisor
will declare the VM as x2apic supported (e.g. VT-d ECAP register will have
EIM bit 4 set), so the guest should assume the APIC IDs are 32bits width
even if vcpus<=255. In short, commit
77250171bdc breaks any simple cmdline
that wants to boot a VM with >=9 but <=255 vcpus with:
-device intel-iommu,intremap=on
For anyone who does not want to enable x2apic, we can use eim=off in the
intel-iommu parameters to skip enabling KVM x2apic.
This partly reverts commit
77250171bdc02aee106083fd2a068147befa1a38, while
keeping the valid bit on checking split irqchip, but revert the other change.
One thing to mention is that this patch may break migration compatibility
of such VM, however that's probably the best thing we can do, because the
old behavior was simply wrong and not working for >8 vcpus. For <=8 vcpus,
there could be a light guest ABI change (by enabling KVM x2apic after this
patch), but logically it shouldn't affect the migration from working.
Also, this is not the 1st commit to change x2apic behavior. Igor provided
a full history of how this evolved for the past few years:
https://lore.kernel.org/qemu-devel/
20220922154617.
57d1a1fb@redhat.com/
Relevant commits for reference:
fb506e701e ("intel_iommu: reject broken EIM", 2016-10-17)
c1bb5418e3 ("target/i386: Support up to 32768 CPUs without IRQ remapping", 2020-12-10)
77250171bd ("intel_iommu: Fix irqchip / X2APIC configuration checks", 2022-05-16)
dc89f32d92 ("target/i386: Fix sanity check on max APIC ID / X2APIC enablement", 2022-05-16)
We may want to have this for stable too (mostly for 7.1.0 only). Adding a
fixes tag.
Cc: David Woodhouse <dwmw2@infradead.org>
Cc: Claudio Fontana <cfontana@suse.de>
Cc: Igor Mammedov <imammedo@redhat.com>
Fixes:
77250171bd ("intel_iommu: Fix irqchip / X2APIC configuration checks")
Signed-off-by: Peter Xu <peterx@redhat.com>
Message-Id: <
20220926153206.10881-1-peterx@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Jonathan Cameron [Fri, 23 Sep 2022 16:18:35 +0000 (17:18 +0100)]
mem/cxl-type3: Add sn option to provide serial number for PCI ecap
The Device Serial Number Extended Capability PCI r6.0 sec 7.9.3
provides a standard way to provide a device serial number as
an IEEE defined 64-bit extended unique identifier EUI-64.
CXL 2.0 section 8.1.12.2 Memory Device PCIe Capabilities and
Extended Capabilities requires this to be used to uniquely
identify CXL memory devices.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <
20220923161835.9805-1-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Ben Widawsky <bwidawsk@kernel.org>