OSDN Git Service
Nemanja Ivanovic [Wed, 26 Jun 2019 02:01:11 +0000 (02:01 +0000)]
[PowerPC][NFC] Add a TOC save test case prior to posting a related patch
An upcoming patch will modify the behaviour with respect to saving the TOC
in functions with indirect calls.
Adding a test case so the patch will show the difference in codegen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364375
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Peter Collingbourne [Wed, 26 Jun 2019 01:52:22 +0000 (01:52 +0000)]
gn build: Merge r364288.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364374
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Nemanja Ivanovic [Wed, 26 Jun 2019 01:48:57 +0000 (01:48 +0000)]
[PowerPC] Mark FCOPYSIGN legal for FP vectors
This was just an omission in the back end. We have had the instructions for both
single and double precision for a few HW generations, but never got around to
legalizing these.
Differential revision: https://reviews.llvm.org/D63634
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364373
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Kai Luo [Wed, 26 Jun 2019 01:34:37 +0000 (01:34 +0000)]
[PowerPC][NFC] Move peephole optimization of RLDICR into a method.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364372
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Saleem Abdulrasool [Wed, 26 Jun 2019 01:09:52 +0000 (01:09 +0000)]
MC: correct the emission of weak aliases in COFF
The weak alias should have the characteristics set to
`IMAGE_EXTERN_WEAK_SEARCH_ALIAS` to indicate that the weak external here
is a symbol alias and that the symbol is aliased to a locally defined
symbol. We were previously setting the characteristics to
`IMAGE_EXTERN_WEAK_SEARCH_LIBRARY` which indicates that the symbol
should be looked for in the libraries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364370
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Keno Fischer [Wed, 26 Jun 2019 00:52:42 +0000 (00:52 +0000)]
[WebAssembly] Fix list of relocations with addends in lld
Summary:
The list of relocations with addend in lld was missing `R_WASM_MEMORY_ADDR_REL_SLEB`,
causing `wasm-ld` to generate corrupted output. This fixes that problem and while
we're at it pulls the list of such relocations into the Wasm.h header, to avoid
duplicating it in multiple places.
Reviewers: sbc100
Differential Revision: https://reviews.llvm.org/D63696
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364367
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Erich Keane [Wed, 26 Jun 2019 00:08:22 +0000 (00:08 +0000)]
Teach TableGen Intrin Emitter to handle LLVMPointerType<llvm_any_ty>
r363233 rewrote a bunch of the Intrin Emitter code, however the new
function to update the arg codes did not properly consider a pointer to
an any. This patch adds that logic.
Differential Revision: https://reviews.llvm.org/D63507
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364364
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Heejin Ahn [Tue, 25 Jun 2019 23:04:12 +0000 (23:04 +0000)]
[WebAssembly] Remove catch_all from AsmParser
Summary:
`catch_all` is from the first version of EH proposal and now has been
removed. There were no tests covering this, and thus no tests to remove
or fix.
Reviewers: aardappel
Subscribers: dschuff, sbc100, jgravelle-google, sunfish, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63737
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364360
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Reid Kleckner [Tue, 25 Jun 2019 22:33:32 +0000 (22:33 +0000)]
Dump what value failed byval attribute verification
This verifier check is failing for us while doing ThinLTO on Chrome for
x86, see https://crbug.com/978218, and this helps to debug the problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364357
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Jinsong Ji [Tue, 25 Jun 2019 21:50:56 +0000 (21:50 +0000)]
[MachinePipeliner] Fix risky iterator usage R++, --R
When we calculate MII, we use two loops, one with iterator R++ to
check whether we can reserve the resource, then --R to move back
the iterator to do reservation.
This is risky, as R++, --R may not point to the same element at all.
The can cause wrong MII.
Differential Revision: https://reviews.llvm.org/D63536
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364353
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Jinsong Ji [Tue, 25 Jun 2019 20:56:17 +0000 (20:56 +0000)]
[PowerPC][NFC]Add a test for MachinePipeliner bug
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364350
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Matt Arsenault [Tue, 25 Jun 2019 20:53:35 +0000 (20:53 +0000)]
Don't look for the TargetFrameLowering in the implementation
The same oddity was apparently copy-pasted between multiple targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364349
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Huihui Zhang [Tue, 25 Jun 2019 20:44:52 +0000 (20:44 +0000)]
[InstCombine] Simplify icmp ult/uge (shl %x, C2), C1 iff C1 is power of two -> icmp eq/ne (and %x, (lshr -C1, C2)), 0.
Simplify 'shl' inequality test into 'and' equality test.
This pattern happens in the middle-end while simplifying bitfield access,
Exposed in https://reviews.llvm.org/D63505
https://rise4fun.com/Alive/6uz
Reviewers: lebedev.ri, efriedma
Reviewed By: lebedev.ri
Subscribers: spatel, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63675
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364348
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Philip Reames [Tue, 25 Jun 2019 20:14:08 +0000 (20:14 +0000)]
[LFTR] Adjust debug output to include extensions (if any)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364346
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Pirama Arumuga Nainar [Tue, 25 Jun 2019 19:34:52 +0000 (19:34 +0000)]
[llvm-shlib] Do not use version script when building with MinGW
Summary:
The MinGW driver for lld does not support the --version-script option.
For GNU ld, it's a no-op since LLVM.dll exports all symbols.
Reviewers: srhines, mstorsjo
Subscribers: mgorny, fedor.sergeev, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63743
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364343
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Diego Novillo [Tue, 25 Jun 2019 18:55:16 +0000 (18:55 +0000)]
Update phis in AMDGPUUnifyDivergentExitNodes
Original patch https://reviews.llvm.org/D63659 from
Steven Perron <stevenperron@google.com>
The pass AMDGPUUnifyDivergentExitNodes does not update the phi nodes in
the successors of blocks that is splits. This is fixed by calling
BasicBlock::splitBasicBlock to split the block instead of doing it
manually. This does extra work because a new conditional branch is
created in BB which is immediately replaced, but I think the simplicity
is worth it. It also helps make the code more future proof in case other
things need to be updated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364342
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Sanjay Patel [Tue, 25 Jun 2019 18:51:44 +0000 (18:51 +0000)]
[InstCombine] reduce checks for power-of-2-or-zero using ctpop
This follows up the transform from rL363956 to use the ctpop intrinsic when checking for power-of-2-or-zero.
This is matching the isPowerOf2() patterns used in PR42314:
https://bugs.llvm.org/show_bug.cgi?id=42314
But there's at least 1 instcombine follow-up needed to match the alternate form:
(v & (v - 1)) == 0;
We should have all of the backend expansions handled with:
rL364319
(x86-specific changes still needed for optimal code based on subtarget)
And the larger patterns to exclude zero as a power-of-2 are joining with this change after:
rL364153 ( D63660 )
rL364246
Differential Revision: https://reviews.llvm.org/D63777
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364341
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Stanislav Mekhanoshin [Tue, 25 Jun 2019 18:33:53 +0000 (18:33 +0000)]
[AMDGPU] Removed dead SIMachineFunctionInfo::getWorkItemIDVGPR()
Differential Revision: https://reviews.llvm.org/D63780
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364339
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Craig Topper [Tue, 25 Jun 2019 17:31:52 +0000 (17:31 +0000)]
[X86] Remove isel patterns that look for (vzext_movl (scalar_to_vector (load)))
I believe these all get canonicalized to vzext_movl. The only case where that wasn't true was when the load was loadi32 and the load was an extload aligned to 32 bits. But that was fixed in r364207.
Differential Revision: https://reviews.llvm.org/D63701
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364337
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Philip Reames [Tue, 25 Jun 2019 17:29:18 +0000 (17:29 +0000)]
[Peephole] Allow folding loads into instructions w/multiple uses (such as test64rr)
Peephole opt has a one use limitation which appears to be accidental. The function being used was incorrectly documented as returning whether the def had one *user*, but instead returned true only when there was one *use*. Add a corresponding hasOneNonDbgUser helper, and adjust peephole-opt to use the appropriate one.
All of the actual folding code handles multiple uses within a single instruction. That codepath is well exercised through instruction selection.
Differential Revision: https://reviews.llvm.org/D63656
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364336
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Craig Topper [Tue, 25 Jun 2019 17:08:26 +0000 (17:08 +0000)]
[X86] Add a DAG combine to turn vzmovl+load into vzload if the load isn't volatile. Remove isel patterns for vzmovl+load
We currently have some isel patterns for treating vzmovl+load the same as vzload, but that shrinks the load which we shouldn't do if the load is volatile.
Rather than adding isel checks for volatile. This patch removes the patterns and teachs DAG combine to merge them into vzload when its legal to do so.
Differential Revision: https://reviews.llvm.org/D63665
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364333
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Simon Tatham [Tue, 25 Jun 2019 16:49:32 +0000 (16:49 +0000)]
[ARM] Support inline assembler constraints for MVE.
"To" selects an odd-numbered GPR, and "Te" an even one. There are some
8.1-M instructions that have one too few bits in their register fields
and require registers of particular parity, without necessarily using
a consecutive even/odd pair.
Also, the constraint letter "t" should select an MVE q-register, when
MVE is present. This didn't need any source changes, but some extra
tests have been added.
Reviewers: dmgreen, samparker, SjoerdMeijer
Subscribers: javed.absar, eraman, kristof.beyls, hiraditya, cfe-commits, llvm-commits
Tags: #clang, #llvm
Differential Revision: https://reviews.llvm.org/D60709
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364331
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Ayke van Laethem [Tue, 25 Jun 2019 16:49:22 +0000 (16:49 +0000)]
[AVR] Adjust to Register class change
A refactor in r364191 changed register types from an unsigned int to the
llvm:Register class. Adjust the AVR backend to this change.
This fixes build errors when building with the experimental AVR backend
enabled.
Differential Revision: https://reviews.llvm.org/D63776
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364330
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Simon Tatham [Tue, 25 Jun 2019 16:48:46 +0000 (16:48 +0000)]
[ARM] Code-generation infrastructure for MVE.
This provides the low-level support to start using MVE vector types in
LLVM IR, loading and storing them, passing them to __asm__ statements
containing hand-written MVE vector instructions, and *if* you have the
hard-float ABI turned on, using them as function parameters.
(In the soft-float ABI, vector types are passed in integer registers,
and combining all those 32-bit integers into a q-reg requires support
for selection DAG nodes like insert_vector_elt and build_vector which
aren't implemented yet for MVE. In fact I've also had to add
`arm_aapcs_vfpcc` to a couple of existing tests to avoid that
problem.)
Specifically, this commit adds support for:
* spills, reloads and register moves for MVE vector registers
* ditto for the VPT predication mask that lives in VPR.P0
* make all the MVE vector types legal in ISel, and provide selection
DAG patterns for BITCAST, LOAD and STORE
* make loads and stores of scalar FP types conditional on
`hasFPRegs()` rather than `hasVFP2Base()`. As a result a few
existing tests needed their llc command lines updating to use
`-mattr=-fpregs` as their method of turning off all hardware FP
support.
Reviewers: dmgreen, samparker, SjoerdMeijer
Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D60708
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364329
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Kevin P. Neal [Tue, 25 Jun 2019 16:09:39 +0000 (16:09 +0000)]
[FPEnv] A missing crucial step was undocumented.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364328
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Simon Pilgrim [Tue, 25 Jun 2019 16:00:16 +0000 (16:00 +0000)]
[DAGCombine] combineRepeatedFPDivisors - recognize -1.0 / X as a reciprocal
Fixes issue identified by @nemanjai (Nemanja Ivanovic) in D62963 / rL363040 - infinite loop due to GetNegatedExpression fighting combineRepeatedFPDivisors resulting in fneg(fdiv(x,splat)) -> fneg(fmul(x,1.0/splat)) -> fmul(x,-1.0/splat) -> fmul(x,(-1.0 * 1.0)/splat) ......
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364326
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Fangrui Song [Tue, 25 Jun 2019 15:56:32 +0000 (15:56 +0000)]
[PPC32] Support PLT calls for -msecure-plt -fpic
Summary:
In Secure PLT ABI, -fpic is similar to -fPIC. The differences are that:
* -fpic stores the address of _GLOBAL_OFFSET_TABLE_ in r30, while -fPIC stores .got2+0x8000.
* -fpic uses an addend of 0 for R_PPC_PLTREL24, while -fPIC uses 0x8000.
Reviewers: hfinkel, jhibbits, joerg, nemanjai, spetrovic
Reviewed By: jhibbits
Subscribers: adalava, kbarton, jsji, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63563
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364324
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Sam Parker [Tue, 25 Jun 2019 15:11:17 +0000 (15:11 +0000)]
[ARM] Fix for DLS/LE CodeGen
The expensive buildbots highlighted the mir tests were broken, which
I've now updated and added --verify-machineinstrs to them. This also
uncovered a couple of bugs in the backend pass, so these have also
been fixed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364323
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Xing Xue [Tue, 25 Jun 2019 15:08:28 +0000 (15:08 +0000)]
Improve zero-size allocation with safe_malloc, etc.
Summary:
The current implementations of the memory allocation functions mistake a nullptr returned from std::malloc, std::calloc, or std::realloc as a failure. The behaviour for each of std::malloc, std::calloc, and std::realloc when the size is 0 is implementation defined (ISO/IEC 9899:2018 7.22.3), and may return a nullptr.
This patch checks if space requested is zero when a nullptr is returned, retry requesting non-zero if it is.
Authored By: andusy
Reviewers: hubert.reinterpretcast, xingxue, jasonliu
Reviewed By: hubert.reinterpretcast, xingxue, abrachet
Subscribers: abrachet, jsji, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63668
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364322
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Simon Pilgrim [Tue, 25 Jun 2019 14:58:20 +0000 (14:58 +0000)]
[SLPVectorizer] Precommit of supernode.ll test for D63661
This is a pre-commit of the tests introduced by the SuperNode SLP patch D63661.
Committed on behalf of @vporpo (Vasileios Porpodas)
Differential Revision: https://reviews.llvm.org/D63664
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364320
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Sanjay Patel [Tue, 25 Jun 2019 14:46:52 +0000 (14:46 +0000)]
[SDAG] expand ctpop != 1
Change the generic ctpop expansion to more efficiently handle a
check for not-a-power-of-two value:
(ctpop x) != 1 --> (x == 0) || ((x & x-1) != 0)
This is the inverted predicate sibling pattern that was added with:
D63004
This should have been done before I changed IR canonicalization to
favor this form with:
rL364246
...so if this requires revert/changing, the earlier commit may also
need to modified.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364319
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Michael Liao [Tue, 25 Jun 2019 14:06:34 +0000 (14:06 +0000)]
[AMDGPU] Null checking on TS to avoid crashing in clang tests.
- `test/Misc/backend-resource-limit-diagnostics.cl` crashes as null
streamer is used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364318
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Matt Arsenault [Tue, 25 Jun 2019 13:57:53 +0000 (13:57 +0000)]
AMDGPU/GlobalISel: Fix broken test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364316
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Sanjay Patel [Tue, 25 Jun 2019 13:37:16 +0000 (13:37 +0000)]
[AArch64][x86] add tests for ctpop != 1; NFC
This is the inverted predicate pattern for D63004.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364314
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Simon Pilgrim [Tue, 25 Jun 2019 13:36:53 +0000 (13:36 +0000)]
[X86] lowerShuffleAsSpecificZeroOrAnyExtend - add ANY_EXTEND TODO.
lowerShuffleAsSpecificZeroOrAnyExtend should be able to lower to ANY_EXTEND_VECTOR_INREG as well as ZER_EXTEND_VECTOR_INREG.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364313
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Fangrui Song [Tue, 25 Jun 2019 13:28:44 +0000 (13:28 +0000)]
[ARM] Fix -Wunused-variable in -DLLVM_ENABLE_ASSERTIONS=off builds after D60692
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364312
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Simon Pilgrim [Tue, 25 Jun 2019 13:25:57 +0000 (13:25 +0000)]
[TargetLowering] SimplifyDemandedBits - add ANY_EXTEND_VECTOR_INREG support
Add 'lowest' demanded elt -> bitcast fold to all *_EXTEND_VECTOR_INREG cases.
Reapplies rL363856.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364311
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Whitney Tsang [Tue, 25 Jun 2019 13:23:13 +0000 (13:23 +0000)]
Expand cloneLoopWithPreheader() to support cloning loop nest
Summary: cloneLoopWithPreheader() currently only support innermost loop,
and assert otherwise.
Reviewers: Meinersbur, fhahn, kbarton
Reviewed By: Meinersbur
Subscribers: hiraditya, jsji, llvm-commits
Tag: LLVM
Differential Revision: https://reviews.llvm.org/D63446
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364310
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Matt Arsenault [Tue, 25 Jun 2019 13:23:08 +0000 (13:23 +0000)]
AMDGPU/GlobalISel: Fix duplicated test
Somehow ended up with copies of the same tests in AMDGPU and
AMDGPU/GlobalISel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364309
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Matt Arsenault [Tue, 25 Jun 2019 13:18:11 +0000 (13:18 +0000)]
AMDGPU: Select G_SEXT/G_ZEXT/G_ANYEXT
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364308
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James Henderson [Tue, 25 Jun 2019 13:14:18 +0000 (13:14 +0000)]
[llvm-objcopy][llvm-strip] Fix help text typo for --allow-broken-links
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364307
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James Henderson [Tue, 25 Jun 2019 13:12:38 +0000 (13:12 +0000)]
[docs][llvm-readobj] Improve llvm-readobj documentation
There were a number of issues with the llvm-readobj documentation. The
following points were raised in https://bugs.llvm.org/show_bug.cgi?id=42255,
and have been fixed in this patch:
1. The description section claimed "The tool and its output is
primarily designed for use in FileCheck-based tests" which is not
really the case any more.
2. The documentation used single-dash long options for option names,
but references in the help text to other options exclusively used
double-dashes. Fixed by standardising on double-dashes for all
long-form options.
3. The majority of options available and in the help text were not
present in the documentation. This patch adds them.
4. Several aliases, both long and short, were missing, e.g. --relocs.
Additionally, this patch improves the documentation by:
1. Splitting the options into categories based on the file format they
are specific to.
2. Updating the Exit Status section to correctly mention that errors
lead to a non-zero exit code.
3. Adding a See Also section referencing other similar LLVM tools.
4. Improving/correcting some of the descriptions of options that did
not quite match up with what llvm-readobj does.
Reviewed by: peter.smith, MaskRay, mtrent
Differential Revision: https://reviews.llvm.org/D63719
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364306
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Simon Tatham [Tue, 25 Jun 2019 13:10:29 +0000 (13:10 +0000)]
[ARM] Re-enable misspelled RUN: lines in fullfp16.s.
rL364293 committed a couple of lines that just said "// RUN llvm-mc ..."
without the all-important ':' after RUN, so those test lines weren't
actually running anything.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364305
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Matt Arsenault [Tue, 25 Jun 2019 13:03:06 +0000 (13:03 +0000)]
AMDGPU: Make amdgcn.s.get.waveid.in.workgroup inaccessiblememonly
This should probably be readnone, even though the instruction looks
like a load.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364304
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Simon Pilgrim [Tue, 25 Jun 2019 12:57:43 +0000 (12:57 +0000)]
[TargetLowering] SimplifyDemandedBits ZERO_EXTEND_VECTOR_INREG -> ANY_EXTEND_VECTOR_INREG
Simplify ZERO_EXTEND_VECTOR_INREG if the extended bits are not required.
Matches what we already do for ZERO_EXTEND.
Reapplies rL363850 but now with legality checks added at rL364290
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364303
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Sanjay Patel [Tue, 25 Jun 2019 12:49:35 +0000 (12:49 +0000)]
[SDAG] improve expansion of ctpop+setcc
This should not cause any visible change in output, but it's
more efficient because we were producing non-canonical 'sub x, 1'
and 'setcc ugt x, 0'. As mentioned in the TODO, we should also
be handling the inverse predicate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364302
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Simon Pilgrim [Tue, 25 Jun 2019 12:35:38 +0000 (12:35 +0000)]
Fix frame.s test dir-separator checks
Handle / and \ separators
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364301
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Simon Tatham [Tue, 25 Jun 2019 12:23:46 +0000 (12:23 +0000)]
[ARM] Fix buildbot failure due to -Werror.
Including both 'case ARM_AM::uxtw' and 'default' in the getShiftOp
switch caused a buildbot to fail with
error: default label in switch which covers all enumeration values [-Werror,-Wcovered-switch-default]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364300
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Simon Pilgrim [Tue, 25 Jun 2019 12:19:12 +0000 (12:19 +0000)]
[TargetLowering] SimplifyDemandedBits SIGN_EXTEND_VECTOR_INREG -> ANY/ZERO_EXTEND_VECTOR_INREG
Simplify SIGN_EXTEND_VECTOR_INREG if the extended bits are not required/known zero.
Matches what we already do for SIGN_EXTEND.
Reapplies rL363802 but now with legality checks added at rL364290
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364299
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Sjoerd Meijer [Tue, 25 Jun 2019 12:04:31 +0000 (12:04 +0000)]
[ARM] MVE VPT Blocks
A minor iteration on the MVE VPT Block pass to enable more efficient VPT Block
code generation: consecutive VPT predicated statements, predicated on the same
condition, will be placed within the same VPT Block. This essentially is also
an exercise to write some more tests for the next step, which should be more
generic also merging instructions when they are not consecutive.
Differential Revision: https://reviews.llvm.org/D63711
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364298
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Nicolai Haehnle [Tue, 25 Jun 2019 11:52:30 +0000 (11:52 +0000)]
AMDGPU: Write LDS objects out as global symbols in code generation
Summary:
The symbols use the processor-specific SHN_AMDGPU_LDS section index
introduced with a previous change. The linker is then expected to resolve
relocations, which are also emitted.
Initially disabled for HSA and PAL environments until they have caught up
in terms of linker and runtime loader.
Some notes:
- The llvm.amdgcn.groupstaticsize intrinsics can no longer be lowered
to a constant at compile times, which means some tests can no longer
be applied.
The current "solution" is a terrible hack, but the intrinsic isn't
used by Mesa, so we can keep it for now.
- We no longer know the full LDS size per kernel at compile time, which
means that we can no longer generate a relevant error message at
compile time. It would be possible to add a check for the size of
individual variables, but ultimately the linker will have to perform
the final check.
Change-Id: If66dbf33fccfbf3609aefefa2558ac0850d42275
Reviewers: arsenm, rampitec, t-tye, b-sumner, jsjodin
Subscribers: qcolombet, kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D61494
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364297
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Nicolai Haehnle [Tue, 25 Jun 2019 11:51:35 +0000 (11:51 +0000)]
AMDGPU/MC: Add .amdgpu_lds directive
Summary:
The directive defines a symbol as an group/local memory (LDS) symbol.
LDS symbols behave similar to common symbols for the purposes of ELF,
using the processor-specific SHN_AMDGPU_LDS as section index.
It is the linker and/or runtime loader's job to "instantiate" LDS symbols
and resolve relocations that reference them.
It is not possible to initialize LDS memory (not even zero-initialize
as for .bss).
We want to be able to link together objects -- starting with relocatable
objects, but possible expanding to shared objects in the future -- that
access LDS memory in a flexible way.
LDS memory is in an address space that is entirely separate from the
address space that contains the program image (code and normal data),
so having program segments for it doesn't really make sense.
Furthermore, we want to be able to compile multiple kernels in a
compilation unit which have disjoint use of LDS memory. In that case,
we may want to place LDS symbols differently for different kernels
to save memory (LDS memory is very limited and physically private to
each kernel invocation), so we can't simply place LDS symbols in a
.lds section.
Hence this solution where LDS symbols always stay undefined.
Change-Id: I08cbc37a7c0c32f53f7b6123aa0afc91dbc1748f
Reviewers: arsenm, rampitec, t-tye, b-sumner, jsjodin
Subscribers: kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, rupprecht, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D61493
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364296
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Simon Pilgrim [Tue, 25 Jun 2019 11:31:37 +0000 (11:31 +0000)]
[VectorLegalizer] ExpandANY_EXTEND_VECTOR_INREG/ExpandZERO_EXTEND_VECTOR_INREG - widen source vector
The *_EXTEND_VECTOR_INREG opcodes were relaxed back around rL346784 to support source vector widths that are smaller than the output - it looks like the legalizers were never updated to account for this.
This patch inserts the smaller source vector into an undef vector of the same width of the result before performing the shuffle+bitcast to correctly handle this.
Part of the yak shaving to solve the crashes from rL364264 and rL364272
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364295
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Simon Tatham [Tue, 25 Jun 2019 11:24:50 +0000 (11:24 +0000)]
[ARM] Explicit lowering of half <-> double conversions.
If an FP_EXTEND or FP_ROUND isel dag node converts directly between
f16 and f32 when the target CPU has no instruction to do it in one go,
it has to be done in two steps instead, going via f32.
Previously, this was done implicitly, because all such CPUs had the
storage-only implementation of f16 (i.e. the only thing you can do
with one at all is to convert it to/from f32). So isel would legalize
the f16 into an f32 as soon as it saw it, by inserting an fp16_to_fp
node (or vice versa), and then the fp_extend would already be f32->f64
rather than f16->f64.
But that technique can't support a target CPU which has full f16
support but _not_ f64, such as some variants of Arm v8.1-M. So now we
provide custom lowering for FP_EXTEND and FP_ROUND, which checks
support for f16 and f64 and decides on the best thing to do given the
combination of flags it gets back.
Reviewers: dmgreen, samparker, SjoerdMeijer
Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D60692
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364294
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Simon Tatham [Tue, 25 Jun 2019 11:24:42 +0000 (11:24 +0000)]
[ARM] Extra MVE-related testing.
This adds some extra RUN lines to existing test files, to check that
things that worked in previous architecture versions haven't
accidentally stopped working in 8.1-M. Also we add some new tests: a
test of scalar floating point instructions that could be easily
confused with the similar-looking vector ones at assembly time, a test
of basic load/store/move access to the FP registers (which has to work
even in integer-only MVE); and one final check of the really obvious
case where turning off MVE should make sure MVE instructions really
are rejected.
Reviewers: dmgreen, samparker, SjoerdMeijer, t.p.northover
Subscribers: javed.absar, kristof.beyls, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62682
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364293
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Simon Tatham [Tue, 25 Jun 2019 11:24:33 +0000 (11:24 +0000)]
[ARM] Add remaining miscellaneous MVE instructions.
This final batch includes the tail-predicated versions of the
low-overhead loop instructions (LETP); the VPSEL instruction to select
between two vector registers based on the predicate mask without
having to open a VPT block; and VPNOT which complements the predicate
mask in place.
Reviewers: dmgreen, samparker, SjoerdMeijer, t.p.northover
Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62681
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364292
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Simon Tatham [Tue, 25 Jun 2019 11:24:18 +0000 (11:24 +0000)]
[ARM] Add MVE vector load/store instructions.
This adds the rest of the vector memory access instructions. It
includes contiguous loads/stores, with an ordinary addressing mode
such as [r0,#offset] (plus writeback variants); gather loads and
scatter stores with a scalar base address register and a vector of
offsets from it (written [r0,q1] or similar); and gather/scatters with
a vector of base addresses (written [q0,#offset], again with
writeback). Additionally, some of the loads can widen each loaded
value into a larger vector lane, and the corresponding stores narrow
them again.
To implement these, we also have to add the addressing modes they
need. Also, in AsmParser, the `isMem` query function now has
subqueries `isGPRMem` and `isMVEMem`, according to which kind of base
register is used by a given memory access operand.
I've also had to add an extra check in `checkTargetMatchPredicate` in
the AsmParser, without which our last-minute check of `rGPR` register
operands against SP and PC was failing an assertion because Tablegen
had inserted an immediate 0 in place of one of a pair of tied register
operands. (This matches the way the corresponding check for `MCK_rGPR`
in `validateTargetOperandClass` is guarded.) Apparently the MVE load
instructions were the first to have ever triggered this assertion, but
I think only because they were the first to have a combination of the
usual Arm pre/post writeback system and the `rGPR` class in particular.
Reviewers: dmgreen, samparker, SjoerdMeijer, t.p.northover
Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62680
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364291
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Simon Pilgrim [Tue, 25 Jun 2019 10:51:15 +0000 (10:51 +0000)]
[TargetLowering] SimplifyDemandedBits - legal checks for SIGN/ZERO_EXTEND -> ZERO/ANY_EXTEND
As part of the fix for rL364264 + rL364272 - limit the *_EXTEND conversion to !TLO.LegalOperations || isOperationLegal cases.
We'll improve X86 legality in future commits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364290
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Nemanja Ivanovic [Tue, 25 Jun 2019 10:46:13 +0000 (10:46 +0000)]
[PowerPC] Emit XXSEL for vec_sel and code that has the same pattern
As pointed out in https://bugs.llvm.org/show_bug.cgi?id=41777
we do not emit a vector select even when the pretty much asks for one.
This patch changes that.
Differential revision: https://reviews.llvm.org/D61658
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364289
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Sam Parker [Tue, 25 Jun 2019 10:45:51 +0000 (10:45 +0000)]
[ARM] DLS/LE low-overhead loop code generation
Introduce three pseudo instructions to be used during DAG ISel to
represent v8.1-m low-overhead loops. One maps to set_loop_iterations
while loop_decrement_reg is lowered to two, so that we can separate
the decrement and branching operations. The pseudo instructions are
expanded pre-emission, where we can still decide whether we actually
want to generate a low-overhead loop, in a new pass:
ARMLowOverheadLoops. The pass currently bails, reverting to an sub,
icmp and br, in the cases where a call or stack spill/restore happens
between the decrement and branching instructions, or if the loop is
too large.
Differential Revision: https://reviews.llvm.org/D63476
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364288
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James Henderson [Tue, 25 Jun 2019 10:36:15 +0000 (10:36 +0000)]
[docs][llvm-cxxfilt] Write llvm-cxxfilt documentation
There was a stub for llvm-cxxfilt, but it didn't describe the options.
Additionally, it was in markdown, which was causing issues, so as
discussed in https://reviews.llvm.org/D63211, this change replaces the
existing stub with an RST file.
Reviewed by: MaskRay, mattd
Differential Revision: https://reviews.llvm.org/D63722
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364287
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Roman Lebedev [Tue, 25 Jun 2019 10:01:42 +0000 (10:01 +0000)]
[Codegen] TargetLowering::SimplifySetCC(): omit urem when possible
Summary:
This addresses the regression that is being exposed by D50222 in `test/CodeGen/X86/jump_sign.ll`
The missing fold, at least partially, looks trivial:
https://rise4fun.com/Alive/Zsln
i.e. if we are comparing with zero, and comparing the `urem`-by-non-power-of-two,
and the `urem` is of something that may at most have a single bit set (or no bits set at all),
the `urem` is not needed.
Reviewers: RKSimon, craig.topper, xbolva00, spatel
Reviewed By: xbolva00, spatel
Subscribers: xbolva00, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63390
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364286
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George Rimar [Tue, 25 Jun 2019 08:22:57 +0000 (08:22 +0000)]
[yaml2obj/obj2yaml] - Allow having the symbols and sections with duplicated names.
The patch teaches yaml2obj/obj2yaml to support parsing/dumping
the sections and symbols with the same name.
A special suffix is added to a name to make it unique.
Differential revision: https://reviews.llvm.org/D63596
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364282
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Clement Courbet [Tue, 25 Jun 2019 08:04:13 +0000 (08:04 +0000)]
[ExpandMemCmp] Move all options to TargetTransformInfo.
Split off from D60318.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364281
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Hiroshi Inoue [Tue, 25 Jun 2019 07:24:27 +0000 (07:24 +0000)]
[NFC] fix trivial typos in documents
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364278
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Hans Wennborg [Tue, 25 Jun 2019 07:15:41 +0000 (07:15 +0000)]
Add llvm-symbolizer to LLVM_TOOLCHAIN_TOOLS (PR40152)
So that it gets installed in LLVM_INSTALL_TOOLCHAIN_ONLY builds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364277
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Hans Wennborg [Tue, 25 Jun 2019 07:05:00 +0000 (07:05 +0000)]
[LLVM-C] Add LLVM-C.dll to Windows installer package
This is a follow up to D56781, D56774 and D35077 to makes the LLVM-C.dll
file and LLVM-C.lib be installed on Windows, just like LTO.dll and
LTO.lib are.
Patch by Jakob Bornecrantz!
Differential revision: https://reviews.llvm.org/D63717
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364275
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Craig Topper [Tue, 25 Jun 2019 06:40:28 +0000 (06:40 +0000)]
[X86] Add test case that led to the revert of r363802, r363850, and r363856 in r364264
I've been trying to fix this, but hit some roadblocks. So I'm
committing the test case for now so we'll at least avoid
recreating that failure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364272
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Craig Topper [Tue, 25 Jun 2019 01:32:42 +0000 (01:32 +0000)]
Revert r363802, r363850, and r363856 "[TargetLowering] SimplifyDemandedBits..."
This reverts the following patches.
"[TargetLowering] SimplifyDemandedBits SIGN_EXTEND_VECTOR_INREG -> ANY/ZERO_EXTEND_VECTOR_INREG"
"[TargetLowering] SimplifyDemandedBits ZERO_EXTEND_VECTOR_INREG -> ANY_EXTEND_VECTOR_INREG"
"[TargetLowering] SimplifyDemandedBits - add ANY_EXTEND_VECTOR_INREG support"
We can end up with an any_extend_vector_inreg with a 256 bit result type
and a 128 bit result type. This is allowed by the ISD opcode, but the
generic operation legalizer is only able to expand cases where the
total vector width is the same.
The X86 backend creates these mismatched cases for zext_vec_inreg/sext_vec_inreg.
The SimplifyDemandedBits changes are allowing those nodes to become
aext_vec_inreg. For the zext/sext cases, the X86 backend has Custom
handling and never lets them get to the generic legalizer. We need to do the same
for aext_vec_inreg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364264
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Seiya Nuta [Tue, 25 Jun 2019 01:08:21 +0000 (01:08 +0000)]
[llvm-objcopy][NFCI] Fix build failure with GCC
Here is unreachable since the switch statement above is exhaustive.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364263
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Matt Arsenault [Tue, 25 Jun 2019 01:07:22 +0000 (01:07 +0000)]
AMDGPU/GlobalISel: Fix regbankselect for amdgcn.class
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364262
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Huihui Zhang [Tue, 25 Jun 2019 00:14:02 +0000 (00:14 +0000)]
[InstCombine][NFC] Add test to show missing fold for icmp ult/uge (shl %x, C2), C1.
Summary:
'shl' inequality test
```
icmp ult/uge (shl %x, C2), C1 iff C1 is power of two
```
can be simplified as 'and' equality test
```
icmp eq/ne (and %x, (lshr -C1, C2)), 0.
```
Reviewers: lebedev.ri, efriedma
Reviewed By: lebedev.ri
Subscribers: llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63670
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364256
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Huihui Zhang [Tue, 25 Jun 2019 00:09:10 +0000 (00:09 +0000)]
[InstCombine] Fold icmp eq/ne (and %x, C), 0 iff (-C) is power of two -> %x u</u>= (-C) earlier.
Summary:
To generate simplified IR, make sure fold
(X & ~C) ==/!= 0 --> X u</u>= C+1
is scheduled before fold
((X << Y) & C) == 0 -> (X & (C >> Y)) == 0.
https://rise4fun.com/Alive/7ZN
Reviewers: lebedev.ri, efriedma, spatel, craig.topper
Reviewed By: lebedev.ri
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63505
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364255
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Seiya Nuta [Tue, 25 Jun 2019 00:02:04 +0000 (00:02 +0000)]
[llvm-objcopy][NFC] Refactor output target parsing
Summary:
Use an enum instead of string to hold the output file format in Config.InputFormat and Config.OutputFormat. It's essential to support other output file formats other than ELF.
Reviewers: espindola, alexshap, rupprecht, jhenderson
Reviewed By: rupprecht, jhenderson
Subscribers: jyknight, compnerd, emaste, arichardson, fedor.sergeev, jakehehrlich, MaskRay, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63239
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364254
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David Blaikie [Mon, 24 Jun 2019 23:45:18 +0000 (23:45 +0000)]
DataExtractor: use decodeSLEB128 to implement getSLEB128
Should've been NFC, but turns out DataExtractor had better test coverage
for decoding SLEB128 than the decodeSLEB128 did - revealing a couple of
bugs (one in the error handling, another in sign extension). So fixed
those to get the DataExtractor tests passing again.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364253
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Seiya Nuta [Mon, 24 Jun 2019 23:39:01 +0000 (23:39 +0000)]
[llvm-objcopy][MachO] Fix strict-aliasing warning. NFCI
Summary:
Use MachOObjectFile::isRelocationScattered instead of reinterpret_cast.
Fixes https://bugs.llvm.org/show_bug.cgi?id=42360
Reviewers: alexshap, rupprecht, jhenderson
Reviewed By: alexshap
Subscribers: dendibakh, bjope, uabelho, jakehehrlich, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D63699
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364252
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Tim Shen [Mon, 24 Jun 2019 23:29:20 +0000 (23:29 +0000)]
Revert "[NVPTX][NFC] Fix documentation for shfl instructions." The
original documentation is correct as it matches the C++ builtins.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364250
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Douglas Yung [Mon, 24 Jun 2019 23:16:32 +0000 (23:16 +0000)]
[NFC] Fix tests added in r364225 which failed on Windows due to incorrect path separators.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364249
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Tim Shen [Mon, 24 Jun 2019 23:16:32 +0000 (23:16 +0000)]
[NVPTX][NFC] Fix documentation for shfl instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364248
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Vitaly Buka [Mon, 24 Jun 2019 22:42:53 +0000 (22:42 +0000)]
[NFC] Add missing consts into memoryaccess_def_iterator
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364247
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Sanjay Patel [Mon, 24 Jun 2019 22:35:26 +0000 (22:35 +0000)]
[InstCombine] squash is-not-power-of-2 using ctpop
This is the Demorgan'd 'not' of the pattern handled in:
D63660 / rL364153
This is another intermediate IR step towards solving PR42314:
https://bugs.llvm.org/show_bug.cgi?id=42314
We can test if a value is not a power-of-2 using ctpop(X) > 1,
so combining that with an is-zero check of the input is the
same as testing if not exactly 1 bit is set:
(X == 0) || (ctpop(X) u> 1) --> ctpop(X) != 1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364246
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Matt Arsenault [Mon, 24 Jun 2019 22:21:02 +0000 (22:21 +0000)]
AMDGPU/GlobalISel: Add tests for regbankselect of v2s16 and/or/xor
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364244
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Vasileios Porpodas [Mon, 24 Jun 2019 21:40:48 +0000 (21:40 +0000)]
[SLP] NFC: Fixed typo in comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364237
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Matt Arsenault [Mon, 24 Jun 2019 21:37:03 +0000 (21:37 +0000)]
InstCombine: Preserve nuw when reassociating nuw ops [3/3]
Alive says this is OK.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364235
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Matt Arsenault [Mon, 24 Jun 2019 21:37:02 +0000 (21:37 +0000)]
InstCombine: Preserve nuw when reassociating nuw ops [2/3]
Alive says this is OK.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364234
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Matt Arsenault [Mon, 24 Jun 2019 21:36:59 +0000 (21:36 +0000)]
InstCombine: Preserve nuw when reassociating nuw ops [1/3]
Alive says this is OK.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364233
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Cameron McInally [Mon, 24 Jun 2019 21:36:09 +0000 (21:36 +0000)]
[NFC][Reassociate] Add unary FNeg tests to fast-ReassociateVector.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364232
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David Blaikie [Mon, 24 Jun 2019 20:43:36 +0000 (20:43 +0000)]
NFC: DataExtractor: use decodeULEB128 to implement getULEB128
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364230
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Nikita Popov [Mon, 24 Jun 2019 20:13:13 +0000 (20:13 +0000)]
[CVP] Reenable nowrap flag inference
Inference of nowrap flags in CVP has been disabled, because it
triggered a bug in LFTR (https://bugs.llvm.org/show_bug.cgi?id=31181).
This issue has been fixed in D60935, so we should be able to reenable
nowrap flag inference now.
Differential Revision: https://reviews.llvm.org/D62776
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364228
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Sanjay Patel [Mon, 24 Jun 2019 20:11:40 +0000 (20:11 +0000)]
[InstCombine] add tests for more variants of isPowerOf2; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364227
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Peter Collingbourne [Mon, 24 Jun 2019 20:03:23 +0000 (20:03 +0000)]
llvm-symbolizer: Add a FRAME command.
This command prints a description of the referenced function's stack frame.
For each formal parameter and local variable, the tool prints:
- function name
- variable name
- file/line of declaration
- FP-relative variable location (if available)
- size in bytes
- HWASAN tag offset
This information will be used by the HWASAN runtime to identify local
variables in UAR reports.
Differential Revision: https://reviews.llvm.org/D63468
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364225
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Huihui Zhang [Mon, 24 Jun 2019 19:49:42 +0000 (19:49 +0000)]
[InstCombine] Regenerate test pr17827. NFCI.
Prep work for upcoming patch D63505.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364224
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Roland Froese [Mon, 24 Jun 2019 19:27:07 +0000 (19:27 +0000)]
[CodeGen] Add missing vector type legalization for ctlz_zero_undef
Widen vector result type for ctlz_zero_undef and cttz_zero_undef the same as
ctlz and cttz.
Differential Revision: https://reviews.llvm.org/D63463
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364221
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Philip Reames [Mon, 24 Jun 2019 19:26:17 +0000 (19:26 +0000)]
[Tests] Add cases where we're failing to discharge provably loop exits (tests for D63733)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364220
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Cameron McInally [Mon, 24 Jun 2019 19:24:23 +0000 (19:24 +0000)]
[SLP] Support unary FNeg vectorization
Differential Revision: https://reviews.llvm.org/D63609
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364219
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Nico Weber [Mon, 24 Jun 2019 18:47:53 +0000 (18:47 +0000)]
Remove flag for no longer supported MSVC version
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364218
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Matt Arsenault [Mon, 24 Jun 2019 18:02:18 +0000 (18:02 +0000)]
AMDGPU/GlobalISel: Select G_TRUNC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364215
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Matt Arsenault [Mon, 24 Jun 2019 18:00:47 +0000 (18:00 +0000)]
AMDGPU/GlobalISel: RegBankSelect for amdgcn.class
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364214
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Jinsong Ji [Mon, 24 Jun 2019 18:00:34 +0000 (18:00 +0000)]
[PowerPC][UpdateTestChecks] powerpc- triple support
There are quite some old testcases with powerpc- triple,
we should add this triple support so that we can update them with script.
Differential Revision: https://reviews.llvm.org/D63723
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364213
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Matt Arsenault [Mon, 24 Jun 2019 17:54:12 +0000 (17:54 +0000)]
AMDGPU/GlobalISel: Split VALU s64 G_ZEXT/G_SEXT in RegBankSelect
Scalar extends to s64 can use S_BFE_{I64|U64}, but vector extends need
to extend to the 32-bit half, and then to 64.
I'm not sure what the line should be between what RegBankSelect
handles, and what instruction select does, but for now I'm erring on
the side of RegBankSelect for future post-RBS combines.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364212
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