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Dave Airlie [Thu, 8 Dec 2016 00:54:24 +0000 (00:54 +0000)]
radv/ac: no need to pass nir to the post outputs handling
We don't use the nir shader in here at all.
Reviewed by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Thu, 8 Dec 2016 00:12:08 +0000 (00:12 +0000)]
radv: fix warnings in ubo load code.
Reviewed by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Thu, 8 Dec 2016 00:11:33 +0000 (00:11 +0000)]
radv/ac: pass a mask of array params not a number.
This makes it easier to add new params before the array ones.
Reviewed by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Thu, 8 Dec 2016 00:03:38 +0000 (00:03 +0000)]
radv: split out a chunk of variant filling code.
This code will have use for copy shaders etc.
Reviewed by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Wed, 7 Dec 2016 23:58:08 +0000 (23:58 +0000)]
radv/meta: don't pass rect into blit2d src function.
Reviewed by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Wed, 30 Nov 2016 02:08:15 +0000 (02:08 +0000)]
radv/meta: cleanup image info setup.
This just passes the subresource info in and uses it.
Reviewed by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Wed, 30 Nov 2016 02:03:33 +0000 (02:03 +0000)]
radv/meta: split copyimage api into api and meta function
This make it easier to add multiple queues later.
Reviewed by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Wed, 30 Nov 2016 01:56:11 +0000 (01:56 +0000)]
radv/meta: clean up buffer->image code.
Removes some unnecessary functions and pull
some stuff out of the loop.
Reviewed by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Wed, 7 Dec 2016 23:45:36 +0000 (23:45 +0000)]
radv/ac: don't pass nir to create_function
This isn't needed for later things like geom shader copy shaders,
we won't have NIR.
Reviewed by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Wed, 30 Nov 2016 01:51:19 +0000 (01:51 +0000)]
radv: add missing license file to radv_meta_bufimage.
Just noticed this file was missing license and any
explaination of what is in it.
(stable just for license header reasons)
Reviewed by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Cc: "13.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Wed, 7 Dec 2016 23:39:49 +0000 (23:39 +0000)]
radv/ac: use build_gep0 instead of opencoding it.
Reviewed by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Marek Olšák [Wed, 7 Dec 2016 22:01:56 +0000 (23:01 +0100)]
radeonsi: disable the constant engine (CE) on Carrizo and Stoney
It must be disabled until the kernel bug is fixed, and then we'll enable CE
based on the DRM version.
Cc: 12.0 13.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Michel Dänzer [Thu, 8 Dec 2016 01:51:03 +0000 (10:51 +0900)]
radeonsi: Fix typo: "llvm.fs.interp" => "llvm.SI.fs.interp"
Fixes lots of pixel shaders failing to compile with LLVM 3.9 or older.
Trivial.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99013#c4
Dave Airlie [Mon, 28 Nov 2016 03:15:30 +0000 (03:15 +0000)]
radv: make push constants optional
We don't set the push constants slot up unless
something will cause us to need it.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 28 Nov 2016 02:43:27 +0000 (02:43 +0000)]
radv: only emit descriptor sgprs when needed
This only emits enough descriptor sgprs for the number
of sets in the layout, and only emits the descriptors
necessary for the current stage.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 28 Nov 2016 01:11:34 +0000 (01:11 +0000)]
radv: move userdata sgpr ownership to compiler side.
This isn't fully what we want yet, but is a good step on the way.
This allows the compiler to create the information structures
for the state setting side, however the state setting still expects
things to be pretty much in 2 sgpr wide register sets, and can't
handle the indirect setting yet.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 28 Nov 2016 00:57:30 +0000 (00:57 +0000)]
radv: refactor out the constant setting user sgpr code.
This just refactors out some common code to make future changes
easier to understand.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 28 Nov 2016 00:56:37 +0000 (00:56 +0000)]
radv: refactor out the descriptor user sgpr setting.
This just splits some common code into a utility function.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 28 Nov 2016 00:46:00 +0000 (00:46 +0000)]
radv: only bind descriptor sets to stages that need them
This copies the push constant code and only binds descriptor
sets to the stages that need them. It also now has to dirty
descriptors on pipeline binds.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 28 Nov 2016 00:42:56 +0000 (00:42 +0000)]
radv: move descriptor set userdata emission to draw flush time.
This is another step towards having the compiler decide the
user sgpr layout.
This still emits the descriptors sets for all shader types, but
we will fix this later.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 28 Nov 2016 00:37:25 +0000 (00:37 +0000)]
radv: refactor descriptor set userdata emission out.
This just moves this into a separate function.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 28 Nov 2016 00:33:39 +0000 (00:33 +0000)]
radv: pass pipeline to constant flush function
I'll need this later rather than just the layout.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 28 Nov 2016 00:32:22 +0000 (00:32 +0000)]
radv: consolidate compute pipeline flushing (v1.1)
This just moves some common code into a utility function
to avoid having to change multiple places later.
v1.1: rename function to better reflect what it does. (Bas)
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Marek Olšák [Fri, 2 Dec 2016 18:40:40 +0000 (19:40 +0100)]
radeonsi: wait for outstanding LDS instructions in memory barriers if needed
Cc: 13.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Fri, 2 Dec 2016 18:17:52 +0000 (19:17 +0100)]
tgsi: fix the src type of TGSI_OPCODE_MEMBAR
It's a literal integer. The next commit will need this.
Cc: 13.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Fri, 2 Dec 2016 18:10:11 +0000 (19:10 +0100)]
radeonsi: wait for outstanding memory instructions in TCS barriers
Cc: 13.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Fri, 2 Dec 2016 17:56:21 +0000 (18:56 +0100)]
radeonsi: allow specifying simm16 of emit_waitcnt at call sites
The next commit will use this.
Cc: 13.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Fri, 2 Dec 2016 01:23:16 +0000 (02:23 +0100)]
radeonsi: write shader descriptors into hang reports
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Fri, 2 Dec 2016 02:34:07 +0000 (03:34 +0100)]
radeonsi: check for sampler state CSO corruption
It really happens.
v2: declare "magic" in debug builds only
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> (v1)
Marek Olšák [Fri, 2 Dec 2016 02:39:04 +0000 (03:39 +0100)]
radeonsi: properly declare context sampler states
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Fri, 2 Dec 2016 01:57:30 +0000 (02:57 +0100)]
radeonsi: fix incorrect FMASK checking in bind_sampler_states
Cc: 12.0 13.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Fri, 2 Dec 2016 01:18:25 +0000 (02:18 +0100)]
radeonsi: always restore sampler states when unbinding sampler views
Cc: 12.0 13.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 1 Dec 2016 02:23:27 +0000 (03:23 +0100)]
radeonsi: take LDS into account for compute shader occupancy stats
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Fri, 2 Dec 2016 15:37:22 +0000 (16:37 +0100)]
st/mesa: round lod_bias to a multiple of 1/256
This reduces the number of sampler states 3.6x in Batman Arkham: Origins.
(from ~7200 to ~2000)
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Fri, 2 Dec 2016 15:26:43 +0000 (16:26 +0100)]
gallium: decrease the size of pipe_sampler_state fields
We've had unused bits.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Marek Olšák [Fri, 2 Dec 2016 14:39:25 +0000 (15:39 +0100)]
cso: don't release sampler states that are bound
This fixes random radeonsi GPU hangs in Batman Arkham: Origins (Wine) and
probably many other games too.
cso_cache deletes sampler states when the cache size is too big and doesn't
check which sampler states are bound, causing use-after-free in drivers.
Because of that, radeonsi uploaded garbage sampler states and the hardware
went bananas. Other drivers may have experienced similar issues.
Cc: 12.0 13.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Jordan Justen [Thu, 3 Nov 2016 19:20:19 +0000 (12:20 -0700)]
i965: Increase max texture to 16k for gen7+
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98297
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Jordan Justen [Wed, 23 Nov 2016 01:20:42 +0000 (17:20 -0800)]
intel/blorp_blit: Add split_blorp_blit_debug switch
Enabling this debug switch causes surface shrinking to happen by
default, and lowers the surface size limit which causes blorp blits to
be split.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Jordan Justen [Mon, 7 Nov 2016 22:07:07 +0000 (14:07 -0800)]
intel/blorp_blit: Enable splitting large blorp blits
Detect when the surface sizes are too large for a blorp blit. When it
is too large, the blorp blit will be split into a smaller operation
and attempted again.
For gen7, this fixes the cts test:
ES3-CTS.gtf.GL3Tests.framebuffer_blit.framebuffer_blit_functionality_multisampled_to_singlesampled_blit
It will also enable us to increase our renderable size from 8k x 8k to
16k x 16k.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Jordan Justen [Wed, 30 Nov 2016 23:53:48 +0000 (15:53 -0800)]
intel/blorp_blit: Move RGB=>R conversion to follow blit splitting
In blorp_copy, when RGB surfaces are copied, we convert the
destination surface to a Red only surface, but 3 times as wide. This
introduces an implicit restriction of "mod 3" for the destination
width.
It is easier to handle the blorp split buffer offsetting with the
original RGB surface, and do the RGB=>R after this.
Suggested-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Jordan Justen [Mon, 7 Nov 2016 22:08:22 +0000 (14:08 -0800)]
intel/blorp_blit: Adjust blorp surface parameters for split blits
If try_blorp_blit() previously returned that a blit was too large,
shrink_surface_params() will be used to update the surface parameters
for the smaller blit so the blit operation can proceed.
v2:
* Use double instead of float. (Jason)
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Jordan Justen [Mon, 7 Nov 2016 22:06:56 +0000 (14:06 -0800)]
intel/blorp_blit: Split blorp blits if they are too large
We rename do_blorp_blit() to try_blorp_blit(), and add a return error
if the surface size for the blit is too large. Now, do_blorp_blit() is
rewritten to try to split the blit into smaller operations if
try_blorp_blit() fails.
Note: In this commit, try_blorp_blit() will always attempt to blit and
never return an error, which matches the previous behavior. We will
enable the size checking and splitting in a future commit.
The motivation for this splitting is that in some cases when we
flatten an image, it's dimensions grow, and this can then exceed the
programmable hardware limits. An example is w-tiled+MSAA blits.
v2:
* Use double instead of float. (Jason)
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Jordan Justen [Mon, 7 Nov 2016 22:06:49 +0000 (14:06 -0800)]
intel/blorp_blit: Create structure for src & dst coordinates
This will be useful for splitting blits into smaller sizes.
We also make the coordinates of type double rather than float. Since
we will be splitting and scaling the coordinates, we might require
extra precision in the calculations.
v2:
* Use double instead of float. (Jason)
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Edward O'Callaghan [Tue, 6 Dec 2016 23:30:48 +0000 (10:30 +1100)]
vulkan: use STATIC_ASSERT instead of static_assert
Following the spirit of commit
23d1799f, fixes compilation
warnings on Android build due to lack of C11 features.
Signed-off-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Lionel Landwerlin [Fri, 25 Nov 2016 14:23:01 +0000 (14:23 +0000)]
i965: enable INTEL_conservative_rasterization on Gen9+
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Chris Forbes <chrisforbes@google.com>
Lionel Landwerlin [Wed, 30 Nov 2016 14:47:41 +0000 (14:47 +0000)]
mesa: add support for GL_INTEL_conservative_rasterization
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Chris Forbes <chrisforbes@google.com>
Plamena Manolova [Tue, 6 Dec 2016 19:37:01 +0000 (21:37 +0200)]
i965: Add i965 plumbing for ARB_post_depth_coverage for i965 (gen9+).
This extension allows the fragment shader to control whether values in
gl_SampleMaskIn[] reflect the coverage after application of the early
depth and stencil tests.
Signed-off-by: Plamena Manolova <plamena.manolova@intel.com>
Reviewed-by: Chris Forbes <chrisforbes@google.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Plamena Manolova [Tue, 6 Dec 2016 19:32:36 +0000 (21:32 +0200)]
mesa: Add GL and GLSL plumbing for ARB_post_depth_coverage for i965 (gen9+).
This extension allows the fragment shader to control whether values in
gl_SampleMaskIn[] reflect the coverage after application of the early
depth and stencil tests.
Signed-off-by: Plamena Manolova <plamena.manolova@intel.com>
Reviewed-by: Chris Forbes <chrisforbes@google.com>
Nicolai Hähnle [Mon, 5 Dec 2016 13:39:50 +0000 (14:39 +0100)]
radeonsi: fix isolines tess factor writes to control ring
Fixes piglit arb_tessellation_shader/execution/isoline{_no_tcs}.shader_test.
Cc: mesa-stable@lists.freedesktop.org
Kenneth Graunke [Tue, 6 Dec 2016 10:50:21 +0000 (02:50 -0800)]
i965: Drop redundant key->outputs_written initialization.
This was already set to the same value earlier.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Kenneth Graunke [Tue, 6 Dec 2016 10:43:07 +0000 (02:43 -0800)]
i965: Initialize "separate" flag in VUE maps.
This was uninitialized, which resulted in weird looking printouts where
it appeared that the TCS output and TES input patch URB entries differed
in SSO/non-SSO layout. There is no "separable" layout for both, as
they're tied together.
It should have no other actual effect.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Ian Romanick [Wed, 7 Sep 2016 21:35:20 +0000 (14:35 -0700)]
nir: In split_var_copies_block, uint, int, and bool types cannot be matrices
Noticed while adding support for 64-bit integer types.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tom Stellard [Tue, 15 Nov 2016 23:50:38 +0000 (23:50 +0000)]
radeonsi: Use amdgcn intrinsics for fs interpolation
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Rob Clark [Tue, 6 Dec 2016 20:52:28 +0000 (15:52 -0500)]
freedreno/a5xx: fix draw packet size with index buffer
gpuaddr of idx buffer is now two dwords (64b).
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Tue, 6 Dec 2016 19:21:22 +0000 (14:21 -0500)]
freedreno/a5xx: gmem bypass mode
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Tue, 6 Dec 2016 17:57:24 +0000 (12:57 -0500)]
freedreno/a5xx: fix emit_string_marker()
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Sat, 3 Dec 2016 17:34:10 +0000 (12:34 -0500)]
freedreno: pitch alignment should match gmem alignment
Deal w/ differing gmem tile size alignment between generations, and make
sure texture pitch matches.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Thu, 1 Dec 2016 21:40:36 +0000 (16:40 -0500)]
freedreno/a5xx: more formats
Bunch of stuff we can at least turn on for vbo formats.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Thu, 1 Dec 2016 20:02:14 +0000 (15:02 -0500)]
freedreno/a5xx: fix fragface
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Thu, 1 Dec 2016 18:57:22 +0000 (13:57 -0500)]
freedreno/a5xx: fix fragcoord
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Thu, 1 Dec 2016 18:55:03 +0000 (13:55 -0500)]
freedreno: update generated headers
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Tue, 6 Dec 2016 22:07:16 +0000 (17:07 -0500)]
freedreno/a5xx: fix alpha test
GRAS_SU_DEPTH_PLANE_CNTL doesn't in fact seem to be anything to do with
alpha test. This fixes xonotic and (other than some iommu faults) gets
gnome-shell working.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Thu, 1 Dec 2016 18:31:57 +0000 (13:31 -0500)]
freedreno/a5xx: fix VPC_VAR[n].DISABLE bits
We don't need varying interpolators enabled for pos/psize out of the VS
(despite the fact that they show up in VS_OUT map), so emit these before
we append pos/psize to the linkage.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Nanley Chery [Mon, 5 Dec 2016 21:40:59 +0000 (13:40 -0800)]
anv/TODO: Document sampling from HiZ
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Kenneth Graunke [Mon, 5 Dec 2016 06:35:42 +0000 (22:35 -0800)]
i965: Don't force SSO layout for VS->TCS.
This was a hack which worked around the VS and TCS disagreeing on their
shared interface due to the lack of varying packing. In particular, it
was needed by Piglit's tcs-input-read-array-interface test.
However, that was just one case where things could go awry, so the
previous commit forcibly made interfaces match. This hack is no longer
necessary.
It also seems to be broken, though I'm not sure why. It fixes Piglit
regressions in spec/arb_shader_image_load_store/semantics from commit
ec1f159ac81ed964415d102eed4a0a29be8e7937.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98893
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Kenneth Graunke [Mon, 5 Dec 2016 07:54:48 +0000 (23:54 -0800)]
i965: Unify shader interfaces explicitly.
A while ago, I made i965 start compiling shaders independently. The VUE
map layouts were based entirely on each shader's input/output bitfields.
Assuming the interfaces match, this works out well - both sides will
compute the same layout, and outputs are correctly routed to inputs.
At the time, I had assumed that the linker would guarantee that the
interfaces match. While it usually succeeds, it unfortunately seems
to fail in some cases.
For example, Piglit's tcs-input-read-array-interface test has a VS
output array with two elements, but the TCS only reads one. The linker
isn't able to eliminate the unused element from the VS, which makes the
interfaces not match.
Another case is where a shader other than the last writes clip/cull
distances. These should be demoted to ordinary varyings, but they
currently aren't - so we think they still have some special meaning,
and prevent them from being eliminated.
Fixing the linker to guarantee this in all cases is complicated. It
needs to be able to optimize out dead code. It's tied into varying
packing and other messiness. While we can certainly improve it---and
should---I'd rather not rely on it being correct in all cases.
This patch ORs adjacent stages' input/output bitfields together,
ensuring that their interface (and hence VUE map layout) will be
compatible. This should safeguard us against linker insufficiencies.
Fixes line rendering in Dolphin, and the Piglit test based on it:
spec/glsl-1.50/execution/geometry/clip-distance-vs-gs-out.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97232
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Jason Ekstrand [Tue, 6 Dec 2016 06:09:35 +0000 (22:09 -0800)]
genxml/gen9: Change the default of MI_SEMAPHORE_WAIT::RegisterPoleMode
We would really like it to be false as that's what you get on hardware that
doesn't have RegisterPoleMode (Sky Lake for example). While we're at it,
we change it to a boolean. This fixes dEQP-VK.synchronization.smoke.events
on Broxton.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "13.0" <mesa-stable@lists.freedesktop.org>
Roland Scheidegger [Tue, 6 Dec 2016 18:59:51 +0000 (19:59 +0100)]
gallivm: optimize 16bit->32bit gather path a bit
LLVM can't really optimize anything which crosses scalar/vector boundaries,
so help a bit with some particular gather operations when the width is
expanded (only do it for 16->32bit expansion for now), by doing expansion
after fetch. That is probably a better solution anyway even if llvm would
recognize it, makes for cleaner IR...
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Roland Scheidegger [Sat, 3 Dec 2016 16:10:46 +0000 (17:10 +0100)]
gallivm: handle 16bit float fetches in lp_build_fetch_rgba_soa
Note that we really want to _never_ reach the bottom of the function, which
resorts to AoS fetch.
Half floats can be handled just like other formats which fit into 32bit
vectors (so, only 1x16 and 2x16 formats, albeit with more channels things
are not THAT bad), with minimal plumbing. I've seen code size go down nearly
by a factor of 3 for a complete texture sampling function (including bilinear
filtering) using R16F.
(What we should do for everything not special cased is to do AoS gather,
shuffle/shift things into SoA vectors, and then do the conversion there.
Otherwise it's particularly bad with 1 or 2 channel formats - that r16f
format with either 4 or 8-wide vectors was still doing one element at a
time, essentially doing exactly the same work as for rgba16f. Also replacing
the channels with SWIZZLE0/1 (particularly the latter) adds even more
work, as it has to be done per aos vector, and not just straightforward
at the end with the SoA vector.)
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Roland Scheidegger [Sat, 3 Dec 2016 16:10:09 +0000 (17:10 +0100)]
util: (trivial) ETC1 meets the criteria for fitting into unorm8
Just like other similar compressed formats.
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Matt Turner [Sun, 4 Dec 2016 04:14:55 +0000 (20:14 -0800)]
i965: Emit proper NOPs.
The PRMs for HSW and newer say that other than the opcode and DebugCtrl
bits of the instruction word, the rest must be zero.
By zeroing the instruction word manually, we avoid using any of the
state inherited through brw_codegen.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96959
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Roland Scheidegger [Tue, 6 Dec 2016 16:44:21 +0000 (17:44 +0100)]
glsl: (trivial) fix type typo
Accidentally changed the type of a constant in
df33f11b39abf313a0db7b9fefaf739b88133161 causing assertion failures.
Kenneth Graunke [Sat, 15 Oct 2016 00:59:36 +0000 (17:59 -0700)]
i965: Allocate at least some URB space even when max_vertices = 0.
Allocating zero URB space is a really bad idea. The hardware has to
give threads a handle to their URB space, and threads have to use that
to terminate the thread. Having it be an empty region just breaks a
lot of assumptions. Hence, why we asserted that it isn't possible.
Unfortunately, it /is/ possible prior to Gen8, if max_vertices = 0.
In theory a geometry shader could do SSBO/image access and maybe
still accomplish something. In reality, this is tripped up by
conformance tests.
Gen8+ already avoids this problem by placing the vertex count DWord
in the URB entry header. This fixes things on earlier generations.
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Tested-by: Ian Romanick <ian.d.romanick@intel.com>
Roland Scheidegger [Mon, 5 Dec 2016 12:39:16 +0000 (13:39 +0100)]
main: allow NEAREST_MIPMAP_NEAREST for stencil texturing
As per GL 4.5 rules, which fixed a spec mistake in GL_ARB_stencil_texturing.
The extension spec wasn't updated, but just allow it with older GL versions
as well, hoping there aren't any crazy tests which want to see an error
there... (Compile tested only.)
Reported by Józef Kucia <joseph.kucia@gmail.com>
Acked-by: Józef Kucia <joseph.kucia@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Roland Scheidegger [Sat, 3 Dec 2016 16:08:05 +0000 (17:08 +0100)]
glsl: fix ldexp lowering if bitfield insert lowering is also requested
Trivial, this just resurrects the code which was there once upon a time
(the code can't lower instructions generated in the lowering pass there,
and even if it could it would probably be suboptimal).
This fixes piglit mesa_shader_integer_functions fs-ldexp.shader_test and
vs-ldexp.shader_test with llvmpipe.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Nayan Deshmukh [Sun, 4 Dec 2016 17:45:38 +0000 (23:15 +0530)]
radv: fix resource leak in radv_amdgpu_ctx_create
CovID:
1396387
V2. Fixup bad whitespace.
Signed-off-by: Nayan Deshmukh <nayan26deshmukh@gmail.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folkore1984.net>
Andy Furniss [Mon, 5 Dec 2016 23:53:40 +0000 (23:53 +0000)]
st/omx/enc Raise default encode level
Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=91281
Signed-off-by: Andy Furniss <adf.lists@gmail.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Andy Furniss [Tue, 6 Dec 2016 00:02:21 +0000 (00:02 +0000)]
radeon/vce Handle H.264 level 5.2
Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=91281
v2: explicitly add case 52
Signed-off-by: Andy Furniss <adf.lists@gmail.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Jason Ekstrand [Sat, 16 Jul 2016 15:21:50 +0000 (08:21 -0700)]
nir: Remove some unused fields from nir_variable
All of these are happily set from glsl_to_nir or spirv_to_nir but their
values are never used for anything.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Jason Ekstrand [Sat, 16 Jul 2016 00:17:40 +0000 (17:17 -0700)]
nir: Delete most of the constant_initializer support
Constant initializers have been a constant (ha!) pain for quite some time.
While they're useful from a language perspective, people writing passes or
backends really don't want deal with them most of the time. This commit
removes most of the constant initializer support from NIR. It is expected
that you call nir_lower_constant_initializers VERY EARLY to ensure that
they're gone before you do anything interesting.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Jason Ekstrand [Sat, 16 Jul 2016 00:15:21 +0000 (17:15 -0700)]
nir: Simplify nir_lower_gs_intrinsics
It's only ever called on single-function shaders. At this point, there are
a lot of helpers that can make it all much simpler.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Jason Ekstrand [Wed, 20 Jul 2016 17:37:43 +0000 (10:37 -0700)]
nir/lower_returns: Stop using constant initializers
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Jason Ekstrand [Fri, 15 Jul 2016 23:57:06 +0000 (16:57 -0700)]
glsl/nir: Call nir_lower_constant_initializers
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Jason Ekstrand [Fri, 15 Jul 2016 23:55:14 +0000 (16:55 -0700)]
anv/pipeline: Call nir_lower_constant_initializers
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Jason Ekstrand [Fri, 15 Jul 2016 23:44:53 +0000 (16:44 -0700)]
nir: Add a pass for lowering away constant initializers
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Jason Ekstrand [Mon, 5 Dec 2016 23:20:52 +0000 (15:20 -0800)]
Revert "i965: use nir_lower_indirect_derefs() for GLSL"
This reverts commit
9404439a754e5640ccd98df40fa694835c0d8759. I didn't
intend to push it and it breaks clip and cull distance.
Jason Ekstrand [Tue, 29 Nov 2016 20:36:14 +0000 (12:36 -0800)]
i965: Delete the meta-base CopyImageSubData implementation
When I originally implemented the ARB_copy_image extension, the fast-path
was written in meta using texture views. This path only worked if both
images were uncompressed color images. All of the other cases fell back to
the blitter or, in the worst case, mapping and memcpy on the CPU. Now that
we have the blorp path, it handles all copies ever and the old meta,
blitter, and CPU paths are only used on gen5 and below. The primary reason
why we needed the meta path (apart from having a slow blitter on later
hardware) was to handle multisampling which gen5 and earlier don't support
anyway. Since the blitter is reasonably fast on gen5, we can just delete
the meta path and get rid of all that terrible code.
If we decide that we're ok with just disabling ARB_copy_image on gen5 and
earlier (I personally am), then we could get rid of another 300 lines or so
of semi-hairy code.
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Jason Ekstrand [Thu, 1 Dec 2016 03:08:51 +0000 (19:08 -0800)]
i965/copy_image: Re-implement the blitter path with emit_miptree_blit
By using emit_miptree_blit which does chunking, this fixes the blitter path
for the case where the image is too tall to blit normally. We also pull it
into intel_blit as intel_miptree_copy. This matches the naming of the
blorp blit and copy functions brw_blorp_blit and brw_blorp_copy.
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Cc: "13.0" <mesa-dev@lists.freedesktop.org>
Jason Ekstrand [Thu, 1 Dec 2016 02:14:27 +0000 (18:14 -0800)]
i965/blit: Break the guts of intel_miptree_blit into a helper
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Cc: "13.0" <mesa-dev@lists.freedesktop.org>
Timothy Arceri [Mon, 15 Aug 2016 00:09:25 +0000 (10:09 +1000)]
i965: use nir_lower_indirect_derefs() for GLSL
This moves the nir_lower_indirect_derefs() call into
brw_preprocess_nir() so thats is called by both OpenGL and Vulkan
and removes that call to the old GLSL IR pass
lower_variable_index_to_cond_assign()
We want to do this pass in nir to be able to move loop unrolling
to nir.
There is a increase of 1-3 instructions in a small number of shaders,
and 2 Kerbal Space program shaders that increase by 32 instructions.
Shader-db results BDW:
total instructions in shared programs:
8705873 ->
8706194 (0.00%)
instructions in affected programs: 32515 -> 32836 (0.99%)
helped: 3
HURT: 79
total cycles in shared programs:
74618120 ->
74583476 (-0.05%)
cycles in affected programs: 528104 -> 493460 (-6.56%)
helped: 47
HURT: 37
LOST: 2
GAINED: 0
Tim Rowley [Mon, 5 Dec 2016 17:35:57 +0000 (11:35 -0600)]
swr: mark PIPE_CAP_NATIVE_FENCE_FD unsupported
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Tim Rowley [Mon, 5 Dec 2016 17:32:19 +0000 (11:32 -0600)]
swr: include llvm version and vector width in renderer string
Uses llvmpipe's string formating.
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Tim Rowley [Mon, 31 Oct 2016 15:29:07 +0000 (10:29 -0500)]
gallivm: use getHostCPUFeatures on x86/llvm-4.0+.
Use llvm provided API based on cpuid rather than our own
manually mantained list of mattr enabling/disabling.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Juan A. Suarez Romero [Fri, 2 Dec 2016 16:26:51 +0000 (16:26 +0000)]
st/va: declare vlVaBuffer before vlVaContext
And declare coded_buf in vlVaContext as "vlVaBuffer *" instead of
"struct vlVaBuffer *".
This fixes several warnings later about assignment from incompatible
pointer type.
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Juan A. Suarez Romero [Fri, 2 Dec 2016 16:26:50 +0000 (16:26 +0000)]
st/va: remove unused variable pbuff
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Elie Tournier <tournier.elie@gmail.com>
Emil Velikov [Fri, 2 Dec 2016 16:26:49 +0000 (16:26 +0000)]
st/va: automake: cleanup C{PP,}FLAGS
Remove some transitional left overs from the gallium pipe-loader rework
and kill off unneeded AM_CPPFLAGS.
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Rob Clark [Thu, 16 Aug 2012 22:28:19 +0000 (17:28 -0500)]
add EGL_TEXTURE_EXTERNAL_WL to WL_bind_wayland_display spec
Signed-off-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Emil Velikov [Mon, 5 Dec 2016 15:42:58 +0000 (15:42 +0000)]
docs: add news item and link release notes for 12.0.5
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Emil Velikov [Mon, 5 Dec 2016 15:38:13 +0000 (15:38 +0000)]
docs: add sha256 checksums for 12.0.5
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit
6b1c3c3aa0a2b643dbb9964b7001097eed3c4888)
Emil Velikov [Mon, 5 Dec 2016 15:31:47 +0000 (15:31 +0000)]
docs: add release notes for 12.0.5
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit
01579a9d007830f2f905646c9d1f9bd0a03caa89)