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Craig Topper [Wed, 3 Oct 2018 19:48:26 +0000 (19:48 +0000)]
[X86] Add CMOV pseudos for VR128X and VR256X register classes. Use them when AVX512VL is enabled.
This allows the phi nodes to be generated with the correct register class when expanded.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343710
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Craig Topper [Wed, 3 Oct 2018 19:48:23 +0000 (19:48 +0000)]
[X86] Don't break CMOV pseudo instructions down by type. Just by register class.
The register class is all that's important for the pseudo instructions. We can use patterns to handle the different types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343709
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Simon Pilgrim [Wed, 3 Oct 2018 19:02:38 +0000 (19:02 +0000)]
[X86] PUSH/POP 'mem-mem' instructions are not RMW - these are 2 different addresses
This patch adds a 'WriteCopy' [WriteLoad, WriteStore] schedule sequence instead to better model the behaviour
Found by @andreadb during llvm-mca testing on btver2 which was crashing on "zero uop" WriteRMW only instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343708
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Matthew Voss [Wed, 3 Oct 2018 18:44:53 +0000 (18:44 +0000)]
Emit template type and value parameter DIEs for template variables.
Summary:
Ensure the TemplateParam attribute of the DIGlobalVariable node is translated into the proper DIEs.
Resolves https://bugs.llvm.org/show_bug.cgi?id=22119
Reviewers: dblaikie, probinson, aprantl, JDevlieghere, clayborg, whitequark, deadalnix
Reviewed By: dblaikie
Subscribers: llvm-commits
Tags: #debug-info
Differential Revision: https://reviews.llvm.org/D52057
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343706
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Simon Pilgrim [Wed, 3 Oct 2018 18:38:28 +0000 (18:38 +0000)]
[X86] Move Atomic binops to use WriteALURMW schedule class
These were being tagged as <WriteALULd, WriteRMW> instead of properly using the RMW sequence
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343705
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Simon Pilgrim [Wed, 3 Oct 2018 18:18:50 +0000 (18:18 +0000)]
[X86][Btver2] Fix MMX PSHUFB schedule
Match AMD Fam16h SOG + llvm-exegesis tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343701
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Simon Pilgrim [Wed, 3 Oct 2018 18:05:01 +0000 (18:05 +0000)]
[X86] Move Atomic CMPXCHG to WriteCMPXCHGRMW schedule class
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343700
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Simon Pilgrim [Wed, 3 Oct 2018 16:45:26 +0000 (16:45 +0000)]
[X86] Add SkylakeClient uops counter - same as the other Intel models.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343697
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Daniel Sanders [Wed, 3 Oct 2018 16:29:24 +0000 (16:29 +0000)]
Correct implementation of -verify-machineinstrs such that it's still overridable for EXPENSIVE_CHECKS
-verify-machineinstrs was implemented as a simple bool. As a result, the
'VerifyMachineCode == cl::BOU_UNSET' used by EXPENSIVE_CHECKS to make it on by
default but possible to disable didn't work as intended. Changed
-verify-machineinstrs to a boolOrDefault to correct this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343696
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Sanjay Patel [Wed, 3 Oct 2018 15:46:03 +0000 (15:46 +0000)]
[InstCombine] clean up foldVectorBinop(); NFC
1. Fix include ordering.
2. Improve variable name (width is bitwidth not number-of-elements).
3. Add local Opcode variable to reduce code duplication.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343694
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Daniel Sanders [Wed, 3 Oct 2018 15:43:39 +0000 (15:43 +0000)]
[globalisel][combines] Don't sink G_TRUNC down to use if that use is a G_PHI
This fixes a problem where the register allocator fails to eliminate a PHI
because there's a non-PHI in the middle of the PHI instructions at the start
of a BB.
This G_TRUNC can be better placed but this at least fixes the correctness issue
quickly. I'll follow up with a patch to the verifier to catch this kind of bug
in future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343693
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Sanjay Patel [Wed, 3 Oct 2018 15:20:58 +0000 (15:20 +0000)]
[InstCombine] name change: foldShuffledBinop -> foldVectorBinop; NFC
This function will deal with more than shuffles with D50992, and I
have another potential per-element fold that could live here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343692
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Andrea Di Biagio [Wed, 3 Oct 2018 15:02:44 +0000 (15:02 +0000)]
[llvm-mca] Add support for move elimination in class RegisterFile.
This patch teaches class RegisterFile how to analyze register writes from
instructions that are move elimination candidates.
In particular, it teaches it how to check if a move can be effectively eliminated
by the underlying PRF, and (if necessary) how to perform move elimination.
The long term goal is to allow processor models to describe instructions that
are valid move elimination candidates.
The idea is to let register file definitions in tablegen declare if/when moves
can be eliminated.
This patch is a non functional change.
The logic that performs move elimination is currently disabled. A future patch
will add support for move elimination in the processor models, and enable this
new code path.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343691
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Simon Pilgrim [Wed, 3 Oct 2018 14:51:09 +0000 (14:51 +0000)]
[llvm-exegesis] Avoid yaml parser from calling sscanf for obvious non-matches (PR39102)
deserializeMCOperand - ensure that we at least match the first character of the sscanf pattern before calling
This reduces llvm-exegesis uops analysis of the instructions supported from btver2 from 5m13s to 2m1s on debug builds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343690
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Nirav Dave [Wed, 3 Oct 2018 14:13:30 +0000 (14:13 +0000)]
[X86] Correctly use SSE registers if no-x87 is selected.
Fix use of SSE1 registers for f32 ops in no-x87 mode.
Notably, allow use of SSE instructions for f32 operations in 64-bit
mode (but not 32-bit which is disallowed by callign convention).
Also avoid translating memset/memcopy/memmove into SSE registers
without X87 for 32-bit mode.
This fixes PR38738.
Reviewers: nickdesaulniers, craig.topper
Subscribers: hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D52555
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343689
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Alex Bradbury [Wed, 3 Oct 2018 13:13:13 +0000 (13:13 +0000)]
[RISCV][NFC] Refactor RISCVDAGToDAGISel::Select
Introduce and use a switch on the opcode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343688
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James Henderson [Wed, 3 Oct 2018 13:00:20 +0000 (13:00 +0000)]
[ThinLTO]Expose cache entry expiration time option in llvm-lto and fix a test
Two cases in a ThinLTO test were passing for the wrong reasons, since
rL340374. The tests were supposed to be testing that files were being
pruned due to the cache size, but they were in fact being pruned because
they were older than the default expiration period of 1 week.
This change fixes the tests by explicitly setting the expiration time to
the maximum value. This required the option to be exposed in llvm-lto.
By assigning all files in the cache a similar time, it is possible to see
that the newest files are still being kept, and that we aren't passing
for the wrong reason again. In the event that the entry expiration were
to expire for them, then the test would start failing, because these
files would be removed too.
Reviewed by: rnk, inglorion
Differential Revision: https://reviews.llvm.org/D51992
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343687
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Jonas Paulsson [Wed, 3 Oct 2018 12:51:19 +0000 (12:51 +0000)]
[RA CopyHints] Fix compile-time regression
This patch makes sure that a register is only hinted once to RA. In extreme
cases the same register can otherwise be hinted numerous times and cause a
compile time slowdown.
Review: Simon Pilgrim
https://reviews.llvm.org/D52826
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343686
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Clement Courbet [Wed, 3 Oct 2018 12:48:50 +0000 (12:48 +0000)]
[llvm-exegesis][NFC] Revert rL343682 "Fix unused variable warning".
That was not the proper fix: the variable is used in debug mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343685
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Clement Courbet [Wed, 3 Oct 2018 12:35:35 +0000 (12:35 +0000)]
[llvm-exegesis] Fix rL343680 in release mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343684
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Clement Courbet [Wed, 3 Oct 2018 12:27:43 +0000 (12:27 +0000)]
[llvm-exegesis][NFC] Fix unused variable warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343682
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Clement Courbet [Wed, 3 Oct 2018 11:50:25 +0000 (11:50 +0000)]
[llvm-exegesis] Resolve variant classes in analysis.
Summary: See PR38884.
Reviewers: gchatelet
Subscribers: tschuett, RKSimon, llvm-commits
Differential Revision: https://reviews.llvm.org/D52825
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343680
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Alex Bradbury [Wed, 3 Oct 2018 11:35:22 +0000 (11:35 +0000)]
[RISCV] Gate float<->int and double<->int conversion patterns on IsRV32
The patterns as defined are correct only when XLen==32.
This is another preparatory patch for a set of patches that flesh out RV64
codegen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343679
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Alex Bradbury [Wed, 3 Oct 2018 11:14:26 +0000 (11:14 +0000)]
[RISCV] Remove XLenVT==i32 assumptions from RISCVInstrInfo td
1. brcond operates on an condition.
2. atomic_fence and the pseudo AMO instructions should all take xlen immediates
This allows the same definitions and patterns to work for RV64 (XLenVT==i64).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343678
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Alex Bradbury [Wed, 3 Oct 2018 11:04:59 +0000 (11:04 +0000)]
[RISCV] Gate simm32 materialisation pattern and SW pattern on IsRV32
These patterns are not correct for RV64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343677
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Florian Hahn [Wed, 3 Oct 2018 11:01:23 +0000 (11:01 +0000)]
[LoopInterchange] Remove unused variable PreserveLCSSA (NFC).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343676
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Alex Bradbury [Wed, 3 Oct 2018 10:59:42 +0000 (10:59 +0000)]
[RISCV] Remove RV64 test lines from umulo-128-legalisation-lowering.ll
The generated code is incorrect anyway, and this test adds noise to the
upcoming set of patches that flesh out RV64 support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343675
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Jonas Toth [Wed, 3 Oct 2018 10:59:19 +0000 (10:59 +0000)]
[CodeGen] NFC fix pedantic warning from extra semicolon
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343674
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Tim Renouf [Wed, 3 Oct 2018 10:29:43 +0000 (10:29 +0000)]
[AMDGPU] Fix for negative offsets in buffer/tbuffer intrinsics
Summary:
The new buffer/tbuffer intrinsics handle an out-of-range immediate
offset by moving/adding offset&-4096 to a vgpr, leaving an in-range
immediate offset, with a chance of the move/add being CSEd for similar
loads/stores.
However it turns out that a negative offset in a vgpr is illegal, even
if adding the immediate offset makes it legal again.
Therefore, this commit disables the offset&-4096 thing if the offset is
negative.
Differential Revision: https://reviews.llvm.org/D52683
Change-Id: Ie02f0a74f240a138dc2a29d17cfbd9e350e4ed13
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343672
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Simon Pilgrim [Wed, 3 Oct 2018 10:28:43 +0000 (10:28 +0000)]
[X86][Btver2] Most RMW instructions don't require an additional uop
Remove uop on WriteRMW and move it into the few instructions that need it.
Match AMD Fam16h SOG + llvm-exegesis tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343671
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Simon Pilgrim [Wed, 3 Oct 2018 10:01:13 +0000 (10:01 +0000)]
[X86] ALU/ADC RMW instructions should use the WriteRMW sequence class
I was expecting this to be a nfc but Silvermont seems to be setup a little differently:
// A folded store needs a cycle on MEC_RSV for the store data, but it does not need an extra port cycle to recompute the address.
def : WriteRes<WriteRMW, [SLM_MEC_RSV]>;
So moving from WriteStore to WriteRMW reduces predicted port pressure, confirmed by @craig.topper that this is correct.
Differential Revision: https://reviews.llvm.org/D52740
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343670
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Aditya Kumar [Wed, 3 Oct 2018 06:21:05 +0000 (06:21 +0000)]
Improve static analysis of cold basic blocks
Differential Revision: https://reviews.llvm.org/D52704
Reviewers: sebpop, tejohnson, brzycki, SirishP
Reviewed By: sebpop
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343663
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Aditya Kumar [Wed, 3 Oct 2018 05:55:20 +0000 (05:55 +0000)]
Add support for new pass manager
Modified the testcases to use both pass managers
Use single commandline flag for both pass managers.
Differential Revision: https://reviews.llvm.org/D52708
Reviewers: sebpop, tejohnson, brzycki, SirishP
Reviewed By: tejohnson, brzycki
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343662
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Fangrui Song [Wed, 3 Oct 2018 03:38:22 +0000 (03:38 +0000)]
[AMDGPU] Rename pass "isel" to "amdgpu-isel"
Summary: The AMDGPU target specific pass "isel" is a misleading name.
Reviewers: tstellar, echristo, javed.absar, arsenm
Reviewed By: arsenm
Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D52759
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343659
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Daniel Sanders [Wed, 3 Oct 2018 02:52:54 +0000 (02:52 +0000)]
[globalisel] Fix one more missing Verifier pass from gisel-commandline-option.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343658
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Matt Arsenault [Wed, 3 Oct 2018 02:47:25 +0000 (02:47 +0000)]
AMDGPU: Always run AMDGPUAlwaysInline
Even if calls are enabled, it still needs to be run
for forcing inline of functions that use LDS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343657
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Matt Arsenault [Wed, 3 Oct 2018 02:37:15 +0000 (02:37 +0000)]
Add atomicrmw operation to error messages
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343656
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Daniel Sanders [Wed, 3 Oct 2018 02:21:30 +0000 (02:21 +0000)]
Add the missing new files from r343654
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343655
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Daniel Sanders [Wed, 3 Oct 2018 02:12:17 +0000 (02:12 +0000)]
Re-commit: [globalisel] Add a combiner helpers for extending loads and use them in a pre-legalize combiner for AArch64
Summary: Depends on D45541
Reviewers: ab, aditya_nandakumar, bogner, rtereshin, volkan, rovka, javed.absar, aemerson
Subscribers: aemerson, rengolin, mgorny, javed.absar, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D45543
The previous commit failed portions of the test-suite on GreenDragon due to
duplicate COPY instructions and iterator invalidation. Both issues have now
been fixed. To assist with this, a helper (cloneVirtualRegister) has been added
to MachineRegisterInfo that can be used to get another register that has the same
type and class/bank as an existing one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343654
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Thomas Lively [Wed, 3 Oct 2018 00:19:39 +0000 (00:19 +0000)]
[WebAssembly] any_true and all_true intrinsics and instructions
Reviewers: aheejin, dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D52755
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343649
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Stanislav Mekhanoshin [Wed, 3 Oct 2018 00:00:41 +0000 (00:00 +0000)]
[AMDGPU] Assert in getOpSize() there are no sub-dword subregs
Differential Revision: https://reviews.llvm.org/D52769
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343648
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Matt Arsenault [Tue, 2 Oct 2018 23:44:11 +0000 (23:44 +0000)]
IR: Move AtomicRMW string names into class
This will be used to improve error messages in a future commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343647
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Sanjay Patel [Tue, 2 Oct 2018 22:53:37 +0000 (22:53 +0000)]
[InstCombine] add icmp+logic tests with commuted ops; NFC
The transform in question is located in foldICmpAndConstConst(),
but as shown here, it doesn't work if operands are commuted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343646
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Reid Kleckner [Tue, 2 Oct 2018 22:28:10 +0000 (22:28 +0000)]
Relax dbg-declare-inalloca.ll test more
We don't need to match the precise type index number here. It's not
important. The type name is what matters to make this test useful.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343642
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Sam Clegg [Tue, 2 Oct 2018 22:12:15 +0000 (22:12 +0000)]
[WebAssembly] Stop generating helper functions in WebAssemblyLowerEmscriptenEHSjLj
Previously we were creating weakly defined helper function in
each translation unit:
- setThrew
- setTempRet0
Instead we now assume these will be provided at link time. In
emscripten they are provided in compiler-rt:
https://github.com/kripken/emscripten/pull/7203
Additionally we previously created three global variable which are
also now required to exist at link time instead.
- __THREW__
- _threwValue
- __tempRet0
Differential Revision: https://reviews.llvm.org/D49208
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343640
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Fangrui Song [Tue, 2 Oct 2018 22:03:31 +0000 (22:03 +0000)]
[CodeView] Try fixing DebugInfo/X86/dbg-declare-inalloca.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343639
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Daniel Sanders [Tue, 2 Oct 2018 20:51:27 +0000 (20:51 +0000)]
[globalisel] Attempt to fix llvm-clang-x86_64-expensive-checks-win
The behaviour of this bot indicates that -verify-machineinstrs has been forced
on and is therefore inserting the verifier on builds that don't expect it.
Explicitly specify whether it's enabled or disabled for each test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343633
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Aaron Smith [Tue, 2 Oct 2018 20:28:15 +0000 (20:28 +0000)]
[CodeView] Only add the Scoped flag for an enum type when it has an immediate function scope to match MSVC
Reviewers: rnk, zturner, llvm-commits
Reviewed By: rnk
Differential Revision: https://reviews.llvm.org/D52706
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343627
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Aaron Smith [Tue, 2 Oct 2018 20:21:05 +0000 (20:21 +0000)]
[CodeView] Emit function options for subprogram and member functions
Summary:
Use the newly added DebugInfo (DI) Trivial flag, which indicates if a C++ record is trivial or not, to determine Codeview::FunctionOptions.
Clang and MSVC generate slightly different Codeview for C++ records. For example, here is the C++ code for a class with a defaulted ctor,
class C {
public:
C() = default;
};
Clang will produce a LF for the defaulted ctor while MSVC does not. For more details, refer to FIXMEs in the test cases in "function-options.ll" included with this set of changes.
Reviewers: zturner, rnk, llvm-commits, aleksandr.urakov
Reviewed By: rnk
Subscribers: Hui, JDevlieghere
Differential Revision: https://reviews.llvm.org/D45123
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343626
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Matt Davis [Tue, 2 Oct 2018 19:42:46 +0000 (19:42 +0000)]
[llvm-mca] Remove unecessary forward decls. NFC.
This patch also removes an unecessary include.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343621
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Matt Morehouse [Tue, 2 Oct 2018 18:35:44 +0000 (18:35 +0000)]
Revert "X86, AArch64, ARM: Do not attach debug location to spill/reload instructions"
This reverts r343520 due to breakage of HWASan tests on Android.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343616
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Matt Davis [Tue, 2 Oct 2018 18:26:33 +0000 (18:26 +0000)]
[llvm-mca] Constify the 'notify' routines. NFC.
Also fixed up some whitespace formatting in DispatchStage.cpp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343615
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Craig Topper [Tue, 2 Oct 2018 18:16:19 +0000 (18:16 +0000)]
[X86][Disassembler] Add bizarro versions of the MOVSXD instruction that sign extend from a GR32 to GR32 or GR16.
The 0x63 opcodes in 64-bit mode have a fixed source size of 32-bits, but the destination size is controlled by REX.W and the 0x66 opsize prefix. This instruction is normally used with a REX.W prefix which provides desired behavior. The other encodings are interpretted as valid by the processor, but aren't useful.
This patch makes us recognize them for the disassembler to match objdump.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343614
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Daniel Sanders [Tue, 2 Oct 2018 17:56:58 +0000 (17:56 +0000)]
[globalisel][verifier] Run the MachineVerifier from IRTranslator onwards
-verify-machineinstrs inserts the MachineVerifier after every MachineInstr-based
pass. However, GlobalISel creates MachineInstr-based passes earlier than DAGISel
and the corresponding verifiers are not being added. This patch fixes that.
If GlobalISel triggers the fallback path then the MIR can be left in a bad
state that is going to be cleared by ResetMachineFunctions. In this situation
verifying between GlobalISel passes will prevent the fallback path from
recovering from this. As a result, we bail out of verifying a function if the
FailedISel attribute is present.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343613
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Reid Kleckner [Tue, 2 Oct 2018 16:43:52 +0000 (16:43 +0000)]
[codeview] Fix 32-bit x86 variable locations in realigned stack frames
Add the .cv_fpo_stackalign directive so that we can define $T0, or the
VFRAME virtual register, with it. This was overlooked in the initial
implementation because unlike MSVC, we push CSRs before allocating stack
space, so this value is only needed to describe local variable
locations. Variables that the compiler now addresses via ESP are instead
described as being stored at offsets from VFRAME, which for us is ESP
after alignment in the prologue.
This adds tests that show that we use the VFRAME register properly in
our S_DEFRANGE records, and that we emit the correct FPO data to define
it.
Fixes PR38857
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343603
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Simon Pilgrim [Tue, 2 Oct 2018 15:13:18 +0000 (15:13 +0000)]
[X86][Btver2] Fix BLENDV and AESDEC schedules
Match AMD Fam16h SOG + llvm-exegesis tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343597
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Krzysztof Parzyszek [Tue, 2 Oct 2018 15:05:43 +0000 (15:05 +0000)]
[Hexagon] Fix extracting subvectors of non-HVX vNi1
Patch by Brendon Cahoon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343596
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Sanjay Patel [Tue, 2 Oct 2018 15:00:56 +0000 (15:00 +0000)]
[InstCombine] add tests with undef elements; NFC
See discussion in D52747.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343595
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Diogo N. Sampaio [Tue, 2 Oct 2018 14:55:48 +0000 (14:55 +0000)]
[ARM] Emmit data symbol for constant pool data
The ARM elf emitter would omit printing data
symbol when constant data. This patch
overrides the emitFill method as to enforce that
the symbol is correctly printed.
Differential revision: https://reviews.llvm.org/D52737
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343594
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Roman Lebedev [Tue, 2 Oct 2018 13:34:50 +0000 (13:34 +0000)]
[NFC][CodeGen][X86] fma.ll, lwp-intrinsics.ll: actually spell --check-prefixes correctly :/
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343588
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Sanjay Patel [Tue, 2 Oct 2018 13:34:05 +0000 (13:34 +0000)]
[InstCombine] add more insert/extract vector tests with FP types; NFC
These are candidates for the same fold that was implemented in
D52439, but FP types require bitcasting (and that changes the
extra uses profitability calculation).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343587
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Simon Pilgrim [Tue, 2 Oct 2018 13:11:59 +0000 (13:11 +0000)]
[X86] Remove unnecessary BT(C/R/S)m(i/r) scheduler overrides
Some SchedAlias remain due to some badly setup RMW tags - but at least the overrides are all removed
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343586
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Roman Lebedev [Tue, 2 Oct 2018 13:11:08 +0000 (13:11 +0000)]
[NFC][CodeGen][X86] lwp-intrinsics.ll: fix check prefixes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343585
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Roman Lebedev [Tue, 2 Oct 2018 13:10:55 +0000 (13:10 +0000)]
[NFC][CodeGen][X86] fma.ll: fix check prefixes for -mcpu=bdver2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343584
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Simon Pilgrim [Tue, 2 Oct 2018 11:32:33 +0000 (11:32 +0000)]
[X86] Add APInt constant assembly printer helper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343577
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Oliver Stannard [Tue, 2 Oct 2018 10:04:39 +0000 (10:04 +0000)]
[AArch64][v8.5A] Add Memory Tagging instructions
This adds new instructions to manipluate tagged pointers, and to load
and store the tags associated with memory.
Patch by Pablo Barrio, David Spickett and Oliver Stannard!
Differential revision: https://reviews.llvm.org/D52490
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343572
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Oliver Stannard [Tue, 2 Oct 2018 09:54:35 +0000 (09:54 +0000)]
[AArch64][v8.5A] Add Memory Tagging system registers
This adds new system registers introduced by the Memory Tagging
extension.
Patch by Pablo Barrio!
Differential revision: https://reviews.llvm.org/D52488
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343571
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Oliver Stannard [Tue, 2 Oct 2018 09:48:43 +0000 (09:48 +0000)]
[AArch64][v8.5A] Add MTE system instructions
The Memory Tagging Extension adds system instructions for data cache
maintenance, implemented as new operands to the DC instruction.
Patch by Pablo Barrio!
Differential revision: https://reviews.llvm.org/D52487
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343570
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David Green [Tue, 2 Oct 2018 09:48:34 +0000 (09:48 +0000)]
[InstCombine] Fold ~A - Min/Max(~A, O) -> Max/Min(A, ~O) - A
This is an attempt to get out of a local-minimum that instcombine currently
gets stuck in. We essentially combine two optimisations at once, ~a - ~b = b-a
and min(~a, ~b) = ~max(a, b), only doing the transform if the result is at
least neutral. This involves using IsFreeToInvert, which has been expanded a
little to include selects that can be easily inverted.
This is trying to fix PR35875, using the ideas from Sanjay. It is a large
improvement to one of our rgb to cmy kernels.
Differential Revision: https://reviews.llvm.org/D52177
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343569
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Oliver Stannard [Tue, 2 Oct 2018 09:36:28 +0000 (09:36 +0000)]
[AArch64][v8.5A] Add MTE as an optional AArch64 extension
This adds the memory tagging extension, which is an optional extension
introduced in v8.5A. The new instructions and registers will be added by
subsequent patches.
Patch by Pablo Barrio!
Differential revision: https://reviews.llvm.org/D52486
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343563
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Simon Pilgrim [Tue, 2 Oct 2018 09:08:51 +0000 (09:08 +0000)]
[X86] Standardize floating point assembly comments
Consistently try to use APFloat::toString for floating point constant comments to get rid of differences between Constant / ConstantDataSequential values - it should help stop some of the linux-windows buildbot failures matching NaN/INF etc. as well.
Differential Revision: https://reviews.llvm.org/D52702
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343562
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David Green [Tue, 2 Oct 2018 09:06:49 +0000 (09:06 +0000)]
[InstCombine] Tests for ~A - Min/Max(~A, O) -> Max/Min(A, ~O) - A. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343561
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Matt Arsenault [Tue, 2 Oct 2018 03:50:56 +0000 (03:50 +0000)]
AMDGPU: Expand atomicrmw nand in IR
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343559
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Thomas Lively [Tue, 2 Oct 2018 01:52:21 +0000 (01:52 +0000)]
[WebAssembly] Restore slashes in SIMD conversion names
Summary: Depends on D52372 and D52442.
Reviewers: aheejin, dschuff, aardappel
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D52512
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343558
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Owen Rodley [Tue, 2 Oct 2018 00:40:08 +0000 (00:40 +0000)]
[MCA] Remove SM.hasNext() call in FetchStage::execute.
Summary:
This is redundant, as FetchStage::getNextInstruction already checks this
and returns llvm::ErrorSuccess() as appropriate.
NFC.
Reviewers: andreadb
Subscribers: gbedwell, llvm-commits
Differential Revision: https://reviews.llvm.org/D52642
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343555
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Fangrui Song [Tue, 2 Oct 2018 00:22:51 +0000 (00:22 +0000)]
[AArch64][DAGCombiner]: change -stop-after=isel to instruction-select
"isel" is registered by AMDGPU. The test will break if the AMDGPU target
is not built.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343553
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Craig Topper [Mon, 1 Oct 2018 23:09:52 +0000 (23:09 +0000)]
[SimplifyCFG] Use Value::hasNUses instead of 'getNumUses() =='. NFCI
getNumUses is linear in the number of uses. Since we're looking for a specific use count, we can use hasNUses which will stop as soon as it determines there are more than N uses instead of walking all of them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343550
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Matt Davis [Mon, 1 Oct 2018 23:01:45 +0000 (23:01 +0000)]
[llvm-mca] Rename the 'Subtract' method to 'subtract'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343549
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Craig Topper [Mon, 1 Oct 2018 22:56:11 +0000 (22:56 +0000)]
[SimplifyCFG] Update comments that refer to CondBB to say ThenBB instead. NFC
There is no variable in this function named CondBB, but there is one named ThenBB and I believe the comments are all refering to it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343548
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Zachary Turner [Mon, 1 Oct 2018 22:39:19 +0000 (22:39 +0000)]
[PDB] Add support for more kinds of PDB Sym Tags.
DIA SDK is returning several new sym tag types, so we update
the enumeration and printing code to support these.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343547
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Daniel Sanders [Mon, 1 Oct 2018 22:32:08 +0000 (22:32 +0000)]
Revert: r343521 and r343541: [globalisel] Add a combiner helpers for extending loads and use them in a pre-legalize combiner for AArch64
There's a strange assertion on two of the Green Dragon bots that goes away when
this is reverted. The assertion is in RegBankAlloc and if it is this commit then
-verify-machine-instrs should have caught it earlier in the pipeline.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343546
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Reid Kleckner [Mon, 1 Oct 2018 22:25:49 +0000 (22:25 +0000)]
[codeview] Simplify S_DEFRANGE emission code, NFC
These assembler directives are still pretty unreadable and it would be
nice to clean them up at some point.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343544
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Reid Kleckner [Mon, 1 Oct 2018 21:59:45 +0000 (21:59 +0000)]
[codeview] Emit S_FRAMEPROC and use S_DEFRANGE_FRAMEPOINTER_REL
Summary:
Before this change, LLVM would always describe locals on the stack as
being relative to some specific register, RSP, ESP, EBP, ESI, etc.
Variables in stack memory are pretty common, so there is a special
S_DEFRANGE_FRAMEPOINTER_REL symbol for them. This change uses it to
reduce the size of our debug info.
On top of the size savings, there are cases on 32-bit x86 where local
variables are addressed from ESP, but ESP changes across the function.
Unlike in DWARF, there is no FPO data to describe the stack adjustments
made to push arguments onto the stack and pop them off after the call,
which makes it hard for the debugger to find the local variables in
frames further up the stack.
To handle this, CodeView has a special VFRAME register, which
corresponds to the $T0 variable set by our FPO data in 32-bit. Offsets
to local variables are instead relative to this value.
This is part of PR38857.
Reviewers: hans, zturner, javed.absar
Subscribers: aprantl, hiraditya, JDevlieghere, llvm-commits
Differential Revision: https://reviews.llvm.org/D52217
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343543
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Reid Kleckner [Mon, 1 Oct 2018 21:39:39 +0000 (21:39 +0000)]
Fix the Windows build in GlobalISel
Clang-cl was complaining about some sort of constexpr narrowing bug:
C:\src\llvm-project\llvm\lib\CodeGen\GlobalISel\CombinerHelper.cpp(136,31): error: non-constant-expression cannot be narrowed from type 'llvm::TargetOpcode::(anonymous enum at C:\src\llvm-project\llvm\include\llvm/CodeGen/TargetOpcodes.h:22:1)' to 'unsigned int' in initializer list [-Wc++11-narrowing]
unsigned(MI.getOpcode()) == unsigned(TargetOpcode::G_LOAD)
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
C:\src\llvm-project\llvm\lib\CodeGen\GlobalISel\CombinerHelper.cpp(136,31): note: insert an explicit cast to silence this issue
unsigned(MI.getOpcode()) == unsigned(TargetOpcode::G_LOAD)
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
static_cast<unsigned int>(
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343541
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Craig Topper [Mon, 1 Oct 2018 21:35:28 +0000 (21:35 +0000)]
Recommit r343499 "[X86] Enable load folding in the test shrinking code"
Original message:
This patch adds load folding support to the test shrinking code. This was noticed missing in the review for D52669
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343540
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Craig Topper [Mon, 1 Oct 2018 21:35:26 +0000 (21:35 +0000)]
Recommit r343498 "[X86] Improve test instruction shrinking when the sign flag is used and the output of the and is truncated."
This includes a fix to prevent i16 compares with i32/i64 ands from being shrunk if bit 15 of the and is set and the sign bit is used.
Original commit message:
Currently we skip looking through truncates if the sign flag is used. But that's overly restrictive.
It's safe to look through the truncate as long as we ensure one of the 3 things when we shrink. Either the MSB of the mask at the shrunken size isn't set. If the mask bit is set then either the shrunk size needs to be equal to the compare size or the sign
There are still missed opportunities to shrink a load and fold it in here. This will be fixed in a future patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343539
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Sanjay Patel [Mon, 1 Oct 2018 20:25:49 +0000 (20:25 +0000)]
[InstCombine] add inverse test for vector trunc canonical form; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343529
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Sanjay Patel [Mon, 1 Oct 2018 20:22:28 +0000 (20:22 +0000)]
[InstCombine] regenerate test checks; NFC
These files used an old version of the script.
We regex more now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343527
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Stefan Pintilie [Mon, 1 Oct 2018 20:16:27 +0000 (20:16 +0000)]
[PowerPC] Folding XForm to DForm loads requires alignment for some DForm loads.
Going from XForm Load to DSForm Load requires that the immediate be 4 byte
aligned.
If we are not aligned we must leave the load as LDX (XForm).
This bug is causing a compile-time failure in the benchmark h264ref.
Differential Revision: https://reviews.llvm.org/D51988
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343525
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Eric Christopher [Mon, 1 Oct 2018 18:57:08 +0000 (18:57 +0000)]
Temporarily revert "[GVNHoist] Re-enable GVNHoist by default"
This reverts commit r342387 as it's showing significant performance
regressions in a number of benchmarks. Followed up with the
committer and original thread with an example and will get performance
numbers before recommitting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343522
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Daniel Sanders [Mon, 1 Oct 2018 18:56:47 +0000 (18:56 +0000)]
[globalisel] Add a combiner helpers for extending loads and use them in a pre-legalize combiner for AArch64
Summary: Depends on D45541
Reviewers: ab, aditya_nandakumar, bogner, rtereshin, volkan, rovka, javed.absar, aemerson
Subscribers: aemerson, rengolin, mgorny, javed.absar, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D45543
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343521
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Matthias Braun [Mon, 1 Oct 2018 18:56:39 +0000 (18:56 +0000)]
X86, AArch64, ARM: Do not attach debug location to spill/reload instructions
Spill/reload instructions are artificially generated by the compiler and
have no relation to the original source code. So the best thing to do is
not attach any debug location to them (instead of just taking the next
debug location we find on following instructions).
Differential Revision: https://reviews.llvm.org/D52125
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343520
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Craig Topper [Mon, 1 Oct 2018 18:52:19 +0000 (18:52 +0000)]
[X86] Add more test shrinking with truncate and sign bit usage tests. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343519
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Craig Topper [Mon, 1 Oct 2018 18:40:44 +0000 (18:40 +0000)]
Revert r343499 and r343498. X86 test improvements
There's a subtle bug in the handling of truncate from i32/i64 to i32 without minsize.
I'll be adding more test cases and trying to find a fix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343516
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Krzysztof Parzyszek [Mon, 1 Oct 2018 18:24:40 +0000 (18:24 +0000)]
[Hexagon] Remove incorrect pattern for swiz
The pattern had a couple of problems:
- It was checking for loads of bytes in the reverse order to what it
should have been looking for.
- It would replace loads of bytes with a load of a word without making
sure that the alignment was correct.
Thanks to Eli Friedman for pointing it out.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343514
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Stanislav Mekhanoshin [Mon, 1 Oct 2018 18:00:02 +0000 (18:00 +0000)]
[AMDGPU] Fixed SIInstrInfo::getOpSize to handle subregs
Currently it returns incorrect operand size for a target independet
node such as COPY if operand is a register with subreg. Instead of
correct subreg size it returns a size of the whole superreg.
Differential Revision: https://reviews.llvm.org/D52736
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343508
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Zachary Turner [Mon, 1 Oct 2018 17:55:38 +0000 (17:55 +0000)]
[PDB] Add support for dumping Typedef records.
These work a little differently because they are actually in
the globals stream and are treated as symbol records, even though
DIA presents them as types. So this also adds the necessary
infrastructure to cache records that live somewhere other than
the TPI stream as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343507
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Zachary Turner [Mon, 1 Oct 2018 17:55:16 +0000 (17:55 +0000)]
[PDB] Add support for parsing VFTable Shape records.
This allows them to be returned from the native API.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343506
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Matthias Braun [Mon, 1 Oct 2018 17:50:52 +0000 (17:50 +0000)]
MIRParser: Check that instructions only reference DILocation metadata
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343505
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Wouter van Oortmerssen [Mon, 1 Oct 2018 17:20:31 +0000 (17:20 +0000)]
[WebAssembly] Fixed AsmParser not allowing instructions with /
Summary:
The AsmParser Lexer regards these as a seperate token.
Here we expand the instruction name with them if they are
adjacent (no whitespace).
Tested: the basic-assembly.s test case has one case with a / in it.
The currently are also instructions with : in them, which we intend
to rename rather than fix them here.
Reviewers: tlively, dschuff
Subscribers: sbc100, jgravelle-google, aheejin, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D52442
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343501
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