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Rui Ueyama [Wed, 8 Jun 2016 16:54:31 +0000 (16:54 +0000)]
Remove a patch .rej file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272171
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Quentin Colombet [Wed, 8 Jun 2016 16:53:32 +0000 (16:53 +0000)]
[AArch64][RegisterBankInfo] G_OR are fine on either GPR or FPR.
Teach AArch64RegisterBankInfo that G_OR can be mapped on either GPR or
FPR for 64-bit or 32-bit values.
Add test cases demonstrating how this information is used to coalesce a
computation on a single register bank.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272170
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Quentin Colombet [Wed, 8 Jun 2016 16:45:04 +0000 (16:45 +0000)]
[RegBankSelect] Use RegisterBankInfo applyMapping method.
The RegBankSelect pass can now rely on the target to do the remapping of
the instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272169
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Vedant Kumar [Wed, 8 Jun 2016 16:39:32 +0000 (16:39 +0000)]
[ProfileData] Update llvm's copy of InstrProfData.inc
The new version of the header introduces the INSTR_PROF_VISIBILITY
macro. See http://reviews.llvm.org/D21116 for more details.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272166
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Quentin Colombet [Wed, 8 Jun 2016 16:39:21 +0000 (16:39 +0000)]
[RegisterBankInfo] Implement the method to apply a mapping.
Now, the target will be able to provide its how implementation to remap
an instruction. This open the way to crazier optimizations, but to
beginning with, we will be able to handle something else than the
default mapping.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272165
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Quentin Colombet [Wed, 8 Jun 2016 16:30:55 +0000 (16:30 +0000)]
[RegBankSelect] Use the OperandMapper class to hold remap information.
Now that we have an entity that hold the remap information the
rewritting should be easier to do.
No functional changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272164
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Quentin Colombet [Wed, 8 Jun 2016 16:24:55 +0000 (16:24 +0000)]
[RegBankSelect] Use const_iterator instead of iterator for repairReg.
The repairing code has no reason to change the source or destination of
the registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272163
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Quentin Colombet [Wed, 8 Jun 2016 16:18:13 +0000 (16:18 +0000)]
[RegisterBankInfo] Introduce OperandsMapper class.
This helper class is used to encapsulate the necessary information
to remap an instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272161
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Quentin Colombet [Wed, 8 Jun 2016 16:12:19 +0000 (16:12 +0000)]
[Target] Introduce a generic opcode for bitwise OR: G_OR.
This G_OR is used in GlobalISel to represent bitwise OR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272160
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Quentin Colombet [Wed, 8 Jun 2016 15:49:23 +0000 (15:49 +0000)]
[RegBankSelect] Introduce a command line option to override the running mode.
When the command line option is set, it overrides any thing that the
target may have set. The rationale is that we get what we asked for.
Options are respectively regbankselect-fast and regbankselect-greedy for
fast and greedy mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272158
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Quentin Colombet [Wed, 8 Jun 2016 15:40:32 +0000 (15:40 +0000)]
[RegBankSelect] Explain what it would take to support non-copy
repairing.
Copies are easy because we repair only when there is a mismatch. For
non-copy repairing, i.e., cases that involves breaking down or gathering
up the value, one of the operand may not have a register bank yet. Thus,
derivate a cost from that, requires more work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272157
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Oliver Stannard [Wed, 8 Jun 2016 15:26:34 +0000 (15:26 +0000)]
[ARM] MSR instructions implicitly set CPSR
The MSR instructions can write to the CPSR, but we did not model this
fact, so we could emit them in the middle of IT blocks, changing the
condition flags for later instructions in the block.
The tests use two calls to llvm.write_register.i32 because it is valid
to use these instructions at the end of an IT block, which if conversion
does do in some cases. With two calls, the first clobbers the flags, so
a branch has to be used to make the second one conditional.
Differential Revision: http://reviews.llvm.org/D21139
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272154
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Daniel Dunbar [Wed, 8 Jun 2016 14:41:44 +0000 (14:41 +0000)]
[lit] Ensure we get bytes when reading redirected output files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272147
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Saleem Abdulrasool [Wed, 8 Jun 2016 14:30:00 +0000 (14:30 +0000)]
Support: correct AArch64 TargetParser implementation
The architecture enumeration is shared across ARM and AArch64. However, the
data is not. The code incorrectly would index into the array using the
architecture index which was offset by the ARMv7 architecture enumeration. We
do not have a marker for indicating the architectural family to which the
enumeration belongs so we cannot be clever about offsetting the index (at least
it is not immediately apparent to me). Instead, fall back to the tried-and-true
method of slowly iterating the array (its not a large array, so the impact of
this is not too high).
Because of the incorrect indexing, if we were lucky, we would crash, but usually
we would return an invalid StringRef. We did not have any tests for the AArch64
target parser previously;. Extend the previous tests I had added for ARM to
cover AArch64 for ensuring that we return expected StringRefs.
Take the opportunity to change some iterator types to references.
This work is needed to support parsing `.arch name` directives in the AArch64
target asm parser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272145
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Davide Italiano [Wed, 8 Jun 2016 13:56:59 +0000 (13:56 +0000)]
[PM] LoopSimplify. Remove unneeded pass dependencies. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272140
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Davide Italiano [Wed, 8 Jun 2016 13:32:23 +0000 (13:32 +0000)]
[PM/SimplifyCFG] Preserve GlobalsAA even if the IR is mutated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272139
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Vasileios Kalintiris [Wed, 8 Jun 2016 13:13:15 +0000 (13:13 +0000)]
[mips] Add a proper file header in MipsFastISel.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272138
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Krzysztof Parzyszek [Wed, 8 Jun 2016 12:31:16 +0000 (12:31 +0000)]
[Hexagon] Modify HexagonExpandCondsets to handle subregisters
Also, switch to using functions from LiveIntervalAnalysis to update
live intervals, instead of performing the updates manually.
Re-committing r272045.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272135
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Diana Picus [Wed, 8 Jun 2016 10:29:02 +0000 (10:29 +0000)]
[ARM] Remove redundant check. NFC
isSwift is tested earlier and known to be false when we reach this code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272127
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Benjamin Kramer [Wed, 8 Jun 2016 10:01:20 +0000 (10:01 +0000)]
Avoid copies of std::strings and APInt/APFloats where we only read from it
As suggested by clang-tidy's performance-unnecessary-copy-initialization.
This can easily hit lifetime issues, so I audited every change and ran the
tests under asan, which came back clean.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272126
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Igor Breger [Wed, 8 Jun 2016 07:48:23 +0000 (07:48 +0000)]
[AVX512] Fix cvtusi2sd instruction Opcode, it should be 0x7B instead of 0x2A.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272122
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Matt Arsenault [Wed, 8 Jun 2016 05:18:01 +0000 (05:18 +0000)]
Make LiveDebugValues preserve CFG
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272117
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Kostya Serebryany [Wed, 8 Jun 2016 04:49:29 +0000 (04:49 +0000)]
[libFuzzer] add 'weak' back to __sanitizer_malloc_hook and __sanitizer_free_hook
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272116
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Kostya Serebryany [Wed, 8 Jun 2016 01:46:13 +0000 (01:46 +0000)]
[libFuzzer] add a test that is built w/o coverage instrumentation but has the coverage rt (it should now fail with a descriptive message)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272090
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Kostya Serebryany [Wed, 8 Jun 2016 01:31:40 +0000 (01:31 +0000)]
[libFuzzer] docs: merge two lines with cmake instructions, add -DLLVM_ENABLE_ASSERTIONS=ON
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272088
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Quentin Colombet [Wed, 8 Jun 2016 01:24:00 +0000 (01:24 +0000)]
[AArch64][RegisterBankInfo] Use the generic implementation of copyCost.
Long term we may want to give high cost at FPR to/from GPR copies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272086
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Quentin Colombet [Wed, 8 Jun 2016 01:17:10 +0000 (01:17 +0000)]
[RegisterBankInfo] Adapt the copy cost logic to give something sane by default.
The generic implementation stated that all copies were free, which is
unlikely. Now, only the copies within the same register bank are free.
We assume they will get coalesced.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272085
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Quentin Colombet [Wed, 8 Jun 2016 01:11:03 +0000 (01:11 +0000)]
[RegisterBankInfo] Add a size argument for the cost of copy.
The cost of a copy may be different based on how many bits we have to
copy around. E.g., a 8-bit copy may be different than a 32-bit copy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272084
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Quentin Colombet [Wed, 8 Jun 2016 01:04:32 +0000 (01:04 +0000)]
[RegisterBankInfo] Move a hidden function into a static method. NFC.
This will allow code reuse in the coming commits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272083
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Matthias Braun [Wed, 8 Jun 2016 00:47:07 +0000 (00:47 +0000)]
MIR: Fix parsing of stack object references in MachineMemOperands
The MachineMemOperand parser lacked the code to handle %stack.X
references (%fixed-stack.X was working).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272082
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Zachary Turner [Wed, 8 Jun 2016 00:25:08 +0000 (00:25 +0000)]
[pdb] Try to fix use after free.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272078
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Peter Collingbourne [Wed, 8 Jun 2016 00:13:39 +0000 (00:13 +0000)]
IR: Call dropAllReferences from GlobalVariable's destructor.
We were previously failing to do this and as a result failing to drop
attached metadata.
Not sure if there's a good way to test this. An in-progress patch exposed this
problem by allocating a GlobalVariable at the same address as a previously
allocated GlobalVariable.
Differential Revision: http://reviews.llvm.org/D21109
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272077
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Rui Ueyama [Tue, 7 Jun 2016 23:53:43 +0000 (23:53 +0000)]
[pdbdump] Print out # of hash buckets.
In the reference code, the field name is `cHashBuckets`.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272075
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Rui Ueyama [Tue, 7 Jun 2016 23:44:27 +0000 (23:44 +0000)]
[pdbdump] Print out TPI hash key size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272073
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Dan Liew [Tue, 7 Jun 2016 23:32:50 +0000 (23:32 +0000)]
[LibFuzzer] Declare and use sanitizer functions in ``fuzzer::ExternalFunctions``
This fixes linking problems on OSX.
Unfortunately it turns out we need to use an instance of the
``fuzzer::ExternalFunctions`` object in several places so this
commit also replaces all instances with a single global instance.
It also turns out initializing a global ``fuzzer::ExternalFunctions``
before main is entered (i.e. letting the object be initialised by the
global initializers) is not safe (on OSX the call to ``Printf()`` in the
CTOR crashes if it is called from a global initializer) so we instead
have a global ``fuzzer::ExternalFunctions*`` and initialize it inside
``FuzzerDriver()``.
Multiple unit tests depend also depend on the
``fuzzer::ExternalFunctions*`` global so a ``main()`` function has been
added that initializes it before running any tests.
Differential Revision: http://reviews.llvm.org/D20943
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272072
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Kostya Serebryany [Tue, 7 Jun 2016 23:13:54 +0000 (23:13 +0000)]
[docs] fix the build by including ScudoHardenedAllocator into toc; mention SourceBasedCodeCoverage.html in libFuzzer docs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272070
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Vedant Kumar [Tue, 7 Jun 2016 22:47:31 +0000 (22:47 +0000)]
Retry^4 "[llvm-profdata] Add option to ingest filepaths from a file"
Changes since the initial commit:
- Use echo instead of printf. This should side-step the character
escaping issues on Windows.
Differential Revision: http://reviews.llvm.org/D20980
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272068
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Daniel Dunbar [Tue, 7 Jun 2016 22:06:57 +0000 (22:06 +0000)]
[lit] Ignore errors when decoding redirected output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272066
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Easwaran Raman [Tue, 7 Jun 2016 21:46:14 +0000 (21:46 +0000)]
Use FileCheck instead of grepping for patterns. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272065
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George Burgess IV [Tue, 7 Jun 2016 21:41:18 +0000 (21:41 +0000)]
[CFLAA] Kill dead code/fix comments in StratifiedSets.
Also use default/delete instead of hand-written ctors.
Thanks to Jia Chen for bringing this stuff up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272064
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Nicolai Haehnle [Tue, 7 Jun 2016 21:37:17 +0000 (21:37 +0000)]
AMDGPU: Add amdgpu-ps-wqm-outputs function attributes
Summary:
The presence of this attribute indicates that VGPR outputs should be computed
in whole quad mode. This will be used by Mesa for prolog pixel shaders, so
that derivatives can be taken of shader inputs computed by the prolog, fixing
a bug.
The generated code could certainly be improved: if a prolog pixel shader is
used (which isn't common in modern OpenGL - they're used for gl_Color, polygon
stipples, and forcing per-sample interpolation), Mesa will use this attribute
unconditionally, because it has to be conservative. So WQM may be used in the
prolog when it isn't really needed, and furthermore a silly back-and-forth
switch is likely to happen at the boundary between prolog and main shader
parts.
Fixing this is a bit involved: we'd first have to add a mechanism by which
LLVM writes the WQM-related input requirements to the main shader part binary,
and then Mesa specializes the prolog part accordingly. At that point, we may
as well just compile a monolithic shader...
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95130
Reviewers: arsenm, tstellarAMD, mareko
Subscribers: arsenm, llvm-commits, kzhuravl
Differential Revision: http://reviews.llvm.org/D20839
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272063
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Dan Liew [Tue, 7 Jun 2016 21:23:30 +0000 (21:23 +0000)]
[LibFuzzer] Split the fuzzer-oom.test into two tests.
This is necessary because the existing fuzzer-oom.test was Linux
specific due to its use of __sanitizer_print_memory_profile() which
is only available on Linux right now and so the test would fail on OSX.
Differential Revision: http://reviews.llvm.org/D20977
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272061
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Simon Pilgrim [Tue, 7 Jun 2016 21:15:45 +0000 (21:15 +0000)]
[X86][SSE4A] Regenerated SSE4A intrinsics tests
There are no VEX encoded versions of SSE4A instructions, make sure that AVX targets give the same output
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272060
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Zachary Turner [Tue, 7 Jun 2016 20:46:39 +0000 (20:46 +0000)]
[pdb] Fix broken unit test compilation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272059
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Zachary Turner [Tue, 7 Jun 2016 20:38:37 +0000 (20:38 +0000)]
[pdb] Convert StringRefs to ArrayRef<uint8_t>s.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272058
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Reid Kleckner [Tue, 7 Jun 2016 20:27:30 +0000 (20:27 +0000)]
Add info to SourceLevelDebugging about CodeView
Adds some discussion of the nature of the format, and some developer
docs on how to work with it in LLVM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272057
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Eric Christopher [Tue, 7 Jun 2016 20:27:12 +0000 (20:27 +0000)]
Revert "Differential Revision: reviews.llvm.org/D20557"
Author: Wei Ding <wei.ding2@amd.com>
Date: Tue Jun 7 19:04:44 2016 +0000
Differential Revision: http://reviews.llvm.org/D20557
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272044
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as it was breaking the bots.
This reverts commit r272044.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272056
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Eric Christopher [Tue, 7 Jun 2016 20:27:06 +0000 (20:27 +0000)]
Reformat for some clarity and 80-columns. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272055
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Mike Aizatsky [Tue, 7 Jun 2016 20:22:15 +0000 (20:22 +0000)]
[libfuzzer] custom crossover interface function.
Differential Revision: http://reviews.llvm.org/D21089
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272054
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Etienne Bergeron [Tue, 7 Jun 2016 20:15:35 +0000 (20:15 +0000)]
[stack-protection] Add support for MSVC buffer security check
Summary:
This patch is adding support for the MSVC buffer security check implementation
The buffer security check is turned on with the '/GS' compiler switch.
* https://msdn.microsoft.com/en-us/library/
8dbf701c.aspx
* To be added to clang here: http://reviews.llvm.org/D20347
Some overview of buffer security check feature and implementation:
* https://msdn.microsoft.com/en-us/library/
aa290051(VS.71).aspx
* http://www.ksyash.com/2011/01/buffer-overflow-protection-3/
* http://blog.osom.info/2012/02/understanding-vs-c-compilers-buffer.html
For the following example:
```
int example(int offset, int index) {
char buffer[10];
memset(buffer, 0xCC, index);
return buffer[index];
}
```
The MSVC compiler is adding these instructions to perform stack integrity check:
```
push ebp
mov ebp,esp
sub esp,50h
[1] mov eax,dword ptr [__security_cookie (01068024h)]
[2] xor eax,ebp
[3] mov dword ptr [ebp-4],eax
push ebx
push esi
push edi
mov eax,dword ptr [index]
push eax
push 0CCh
lea ecx,[buffer]
push ecx
call _memset (010610B9h)
add esp,0Ch
mov eax,dword ptr [index]
movsx eax,byte ptr buffer[eax]
pop edi
pop esi
pop ebx
[4] mov ecx,dword ptr [ebp-4]
[5] xor ecx,ebp
[6] call @__security_check_cookie@4 (01061276h)
mov esp,ebp
pop ebp
ret
```
The instrumentation above is:
* [1] is loading the global security canary,
* [3] is storing the local computed ([2]) canary to the guard slot,
* [4] is loading the guard slot and ([5]) re-compute the global canary,
* [6] is validating the resulting canary with the '__security_check_cookie' and performs error handling.
Overview of the current stack-protection implementation:
* lib/CodeGen/StackProtector.cpp
* There is a default stack-protection implementation applied on intermediate representation.
* The target can overload 'getIRStackGuard' method if it has a standard location for the stack protector cookie.
* An intrinsic 'Intrinsic::stackprotector' is added to the prologue. It will be expanded by the instruction selection pass (DAG or Fast).
* Basic Blocks are added to every instrumented function to receive the code for handling stack guard validation and errors handling.
* Guard manipulation and comparison are added directly to the intermediate representation.
* lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
* lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
* There is an implementation that adds instrumentation during instruction selection (for better handling of sibbling calls).
* see long comment above 'class StackProtectorDescriptor' declaration.
* The target needs to override 'getSDagStackGuard' to activate SDAG stack protection generation. (note: getIRStackGuard MUST be nullptr).
* 'getSDagStackGuard' returns the appropriate stack guard (security cookie)
* The code is generated by 'SelectionDAGBuilder.cpp' and 'SelectionDAGISel.cpp'.
* include/llvm/Target/TargetLowering.h
* Contains function to retrieve the default Guard 'Value'; should be overriden by each target to select which implementation is used and provide Guard 'Value'.
* lib/Target/X86/X86ISelLowering.cpp
* Contains the x86 specialisation; Guard 'Value' used by the SelectionDAG algorithm.
Function-based Instrumentation:
* The MSVC doesn't inline the stack guard comparison in every function. Instead, a call to '__security_check_cookie' is added to the epilogue before every return instructions.
* To support function-based instrumentation, this patch is
* adding a function to get the function-based check (llvm 'Value', see include/llvm/Target/TargetLowering.h),
* If provided, the stack protection instrumentation won't be inlined and a call to that function will be added to the prologue.
* modifying (SelectionDAGISel.cpp) do avoid producing basic blocks used for inline instrumentation,
* generating the function-based instrumentation during the ISEL pass (SelectionDAGBuilder.cpp),
* if FastISEL (not SelectionDAG), using the fallback which rely on the same function-based implemented over intermediate representation (StackProtector.cpp).
Modifications
* adding support for MSVC (lib/Target/X86/X86ISelLowering.cpp)
* adding support function-based instrumentation (lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp, .h)
Results
* IR generated instrumentation:
```
clang-cl /GS test.cc /Od /c -mllvm -print-isel-input
```
```
*** Final LLVM Code input to ISel ***
; Function Attrs: nounwind sspstrong
define i32 @"\01?example@@YAHHH@Z"(i32 %offset, i32 %index) #0 {
entry:
%StackGuardSlot = alloca i8* <<<-- Allocated guard slot
%0 = call i8* @llvm.stackguard() <<<-- Loading Stack Guard value
call void @llvm.stackprotector(i8* %0, i8** %StackGuardSlot) <<<-- Prologue intrinsic call (store to Guard slot)
%index.addr = alloca i32, align 4
%offset.addr = alloca i32, align 4
%buffer = alloca [10 x i8], align 1
store i32 %index, i32* %index.addr, align 4
store i32 %offset, i32* %offset.addr, align 4
%arraydecay = getelementptr inbounds [10 x i8], [10 x i8]* %buffer, i32 0, i32 0
%1 = load i32, i32* %index.addr, align 4
call void @llvm.memset.p0i8.i32(i8* %arraydecay, i8 -52, i32 %1, i32 1, i1 false)
%2 = load i32, i32* %index.addr, align 4
%arrayidx = getelementptr inbounds [10 x i8], [10 x i8]* %buffer, i32 0, i32 %2
%3 = load i8, i8* %arrayidx, align 1
%conv = sext i8 %3 to i32
%4 = load volatile i8*, i8** %StackGuardSlot <<<-- Loading Guard slot
call void @__security_check_cookie(i8* %4) <<<-- Epilogue function-based check
ret i32 %conv
}
```
* SelectionDAG generated instrumentation:
```
clang-cl /GS test.cc /O1 /c /FA
```
```
"?example@@YAHHH@Z": # @"\01?example@@YAHHH@Z"
# BB#0: # %entry
pushl %esi
subl $16, %esp
movl ___security_cookie, %eax <<<-- Loading Stack Guard value
movl 28(%esp), %esi
movl %eax, 12(%esp) <<<-- Store to Guard slot
leal 2(%esp), %eax
pushl %esi
pushl $204
pushl %eax
calll _memset
addl $12, %esp
movsbl 2(%esp,%esi), %esi
movl 12(%esp), %ecx <<<-- Loading Guard slot
calll @__security_check_cookie@4 <<<-- Epilogue function-based check
movl %esi, %eax
addl $16, %esp
popl %esi
retl
```
Reviewers: kcc, pcc, eugenis, rnk
Subscribers: majnemer, llvm-commits, hans, thakis, rnk
Differential Revision: http://reviews.llvm.org/D20346
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272053
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Daniel Dunbar [Tue, 7 Jun 2016 20:14:17 +0000 (20:14 +0000)]
[lit] Fix an uninitialized var on Windows.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272052
91177308-0d34-0410-b5e6-
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Zachary Turner [Tue, 7 Jun 2016 19:32:09 +0000 (19:32 +0000)]
[yaml] Add a ScalarTraits for mapping endian aware types.
This allows mapping of any endian-aware type whose underlying
type (e.g. uint32_t) provides a ScalarTraits specialization.
Reviewed by: majnemer
Differential Revision: http://reviews.llvm.org/D21057
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272049
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Krzysztof Parzyszek [Tue, 7 Jun 2016 19:25:28 +0000 (19:25 +0000)]
Revert r272045 since GCC doesn't know how to compile it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272048
91177308-0d34-0410-b5e6-
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Krzysztof Parzyszek [Tue, 7 Jun 2016 19:06:23 +0000 (19:06 +0000)]
[Hexagon] Modify HexagonExpandCondsets to handle subregisters
Also, switch to using functions from LiveIntervalAnalysis to update
live intervals, instead of performing the updates manually.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272045
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Wei Ding [Tue, 7 Jun 2016 19:04:44 +0000 (19:04 +0000)]
Differential Revision: reviews.llvm.org/D20557
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272044
91177308-0d34-0410-b5e6-
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Zachary Turner [Tue, 7 Jun 2016 18:42:39 +0000 (18:42 +0000)]
[pdb] Fix a potential overflow and remove unnecessary comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272043
91177308-0d34-0410-b5e6-
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George Burgess IV [Tue, 7 Jun 2016 18:35:37 +0000 (18:35 +0000)]
[CFLAA] Add AttrEscaped, remove bit twiddling functions.
This patch does a few things:
- Unifies AttrAll and AttrUnknown (since they were used for more or less
the same purpose anyway).
- Introduces AttrEscaped, an attribute that notes that a value escapes
our analysis for a given set, but not that an unknown value flows into
said set.
- Removes functions that take bit indices, since we also had functions
that took bitsets, and the use of both (with similar names) was
unclear and bug-prone.
Patch by Jia Chen.
Differential Revision: http://reviews.llvm.org/D21000
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272040
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Mike Aizatsky [Tue, 7 Jun 2016 18:16:32 +0000 (18:16 +0000)]
[libfuzzer] prune_corpus option for disabling pruning during the load.
Summary:
The option is very useful for testing, plus I intend to measure
its effect on fuzzer effectiveness.
Differential Revision: http://reviews.llvm.org/D21084
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272035
91177308-0d34-0410-b5e6-
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Chris Bieneman [Tue, 7 Jun 2016 18:04:37 +0000 (18:04 +0000)]
Revert "Use CMAKE_INSTALL_BINDIR instead of hardcoding bin for tools install paths"
This reverts commit
0dc5a55f66ed06d7859c4e0474a87428d27775e6.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272033
91177308-0d34-0410-b5e6-
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Chris Bieneman [Tue, 7 Jun 2016 18:01:16 +0000 (18:01 +0000)]
Use CMAKE_INSTALL_BINDIR instead of hardcoding bin for tools install paths
Summary:
This allows customizing the location executables and symlinks get installed to,
as with --bindir in autotools.
Reviewers: loladiro, beanz
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D20934
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272031
91177308-0d34-0410-b5e6-
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Geoff Berry [Tue, 7 Jun 2016 16:48:43 +0000 (16:48 +0000)]
Reapply [AArch64] Fix isLegalAddImmediate() to return true for valid negative values.
Originally reviewed here: http://reviews.llvm.org/D17463
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272023
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Daniel Dunbar [Tue, 7 Jun 2016 16:22:24 +0000 (16:22 +0000)]
[utils/lit] Show available_features with --show-suites.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272022
91177308-0d34-0410-b5e6-
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Daniel Dunbar [Tue, 7 Jun 2016 16:13:40 +0000 (16:13 +0000)]
[lit] Improve logging with file redirection.
- This will cause lit to automatically include the first 1K of data in
redirected output files when a command fails (previously if the command
failed, but the main point of the test was, say, a `FileCheck` later on, then
the log wasn't helpful in showing why the command failed).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272021
91177308-0d34-0410-b5e6-
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Andrey Turetskiy [Tue, 7 Jun 2016 15:52:35 +0000 (15:52 +0000)]
Quick fix for the test from rL272014 "[LAA] Improve non-wrapping pointer
detection by handling loop-invariant case" (s couple of buildbots failed).
Patch by Roman Shirokiy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272019
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Haicheng Wu [Tue, 7 Jun 2016 15:17:21 +0000 (15:17 +0000)]
Revert "[MBP] Reduce code size by running tail merging in MBP."
This reverts commit r271930, r271915, r271923. They break a thumb selfhosting
bot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272017
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Simon Pilgrim [Tue, 7 Jun 2016 15:12:47 +0000 (15:12 +0000)]
[X86][AVX512] Added 512-bit integer vector non-temporal load tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272016
91177308-0d34-0410-b5e6-
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Oliver Stannard [Tue, 7 Jun 2016 14:58:48 +0000 (14:58 +0000)]
[ARM] Accept conditional versions of BXNS and BLXNS
These instructions end in "S" but are not flag-setting, so they need including
in the list of special cases in the assembly parser.
Differential Revision: http://reviews.llvm.org/D21077
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272015
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Andrey Turetskiy [Tue, 7 Jun 2016 14:55:27 +0000 (14:55 +0000)]
[LAA] Improve non-wrapping pointer detection by handling loop-invariant case.
This fixes PR26314. This patch adds new helper “isNoWrap” with detection of
loop-invariant pointer case.
Patch by Roman Shirokiy.
Ref: https://llvm.org/bugs/show_bug.cgi?id=26314
Differential Revision: http://reviews.llvm.org/D17268
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272014
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Davide Italiano [Tue, 7 Jun 2016 14:55:04 +0000 (14:55 +0000)]
[Linker/IRMover] Simplify the code a bit. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272013
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Simon Pilgrim [Tue, 7 Jun 2016 13:47:23 +0000 (13:47 +0000)]
[X86][SSE] Add general lowering of nontemporal vector loads (fixed bad merge)
Currently the only way to use the (V)MOVNTDQA nontemporal vector loads instructions is through the int_x86_sse41_movntdqa style builtins.
This patch adds support for lowering nontemporal loads from general IR, allowing us to remove the movntdqa builtins in a future patch.
We currently still fold nontemporal loads into suitable instructions, we should probably look at removing this (and nontemporal stores as well) or at least make the target's folding implementation aware that its dealing with a nontemporal memory transaction.
There is also an issue that VMOVNTDQA only acts on 128-bit vectors on pre-AVX2 hardware - so currently a normal ymm load is still used on AVX1 targets.
Differential Review: http://reviews.llvm.org/D20965
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272011
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Simon Pilgrim [Tue, 7 Jun 2016 13:34:24 +0000 (13:34 +0000)]
[X86][SSE] Add general lowering of nontemporal vector loads
Currently the only way to use the (V)MOVNTDQA nontemporal vector loads instructions is through the int_x86_sse41_movntdqa style builtins.
This patch adds support for lowering nontemporal loads from general IR, allowing us to remove the movntdqa builtins in a future patch.
We currently still fold nontemporal loads into suitable instructions, we should probably look at removing this (and nontemporal stores as well) or at least make the target's folding implementation aware that its dealing with a nontemporal memory transaction.
There is also an issue that VMOVNTDQA only acts on 128-bit vectors on pre-AVX2 hardware - so currently a normal ymm load is still used on AVX1 targets.
Differential Review: http://reviews.llvm.org/D20965
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272010
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Davide Italiano [Tue, 7 Jun 2016 13:21:17 +0000 (13:21 +0000)]
[PM] Preserve GlobalsAA for SROA.
Differential Revision: http://reviews.llvm.org/D21040
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272009
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James Molloy [Tue, 7 Jun 2016 13:10:14 +0000 (13:10 +0000)]
[Thumb-1] Add optimized constant materialization for integers [256..512)
We can materialize these integers using a MOV; ADDi8 pair.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272007
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Igor Breger [Tue, 7 Jun 2016 13:08:45 +0000 (13:08 +0000)]
[AVX512] Fix load opcode for fast isel.
Differential Revision: http://reviews.llvm.org/D21067
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272006
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Ulrich Weigand [Tue, 7 Jun 2016 12:48:22 +0000 (12:48 +0000)]
[PowerPC] Support multiple return values with fast isel
Using an LLVM IR aggregate return value type containing three
or more integer values causes an abort in the fast isel pass.
This patch adds two more registers to RetCC_PPC64_ELF_FIS to
allow returning up to four integers with fast isel, just the
same as is currently supported with regular isel (RetCC_PPC).
This is needed for Swift and (possibly) other non-clang frontends.
Fixes PR26190.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272005
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Simon Pilgrim [Tue, 7 Jun 2016 12:20:14 +0000 (12:20 +0000)]
[X86][SSE] Improved blend+zero target shuffle combining to use combined shuffle mask directly
We currently only combine to blend+zero if the target value type has 8 elements or less, but this was missing a lot of cases where the combined mask had been widened.
This change makes it so we use the combined mask to determine the blend value type, allowing us to catch more widened cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272003
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James Molloy [Tue, 7 Jun 2016 12:13:34 +0000 (12:13 +0000)]
[ARM] Shrink post-indexed LDR and STR to LDM/STM
A Thumb-2 post-indexed LDR instruction such as:
ldr.w r0, [r1], #4
Can be rewritten as:
ldm.n r1!, {r0}
LDMs can be more expensive than LDRs on some cores, so this has been enabled only in minsize mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272002
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James Molloy [Tue, 7 Jun 2016 11:47:24 +0000 (11:47 +0000)]
[ARM] Transform LDMs into writeback form to save code size
If we have an LDM that uses only low registers and doesn't write to its base register:
ldm.w r0, {r1, r2, r3}
And that base register is dead after the LDM, then we can convert it to writeback form and use a narrow encoding:
ldm.n r0!, {r1, r2, r3}
Obviously, this introduces a new register write and so can cause WAW hazards, so I've enabled it only in minsize mode. This is a code size trick that ARM Compiler 5 ("armcc") does that we don't.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272000
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George Rimar [Tue, 7 Jun 2016 11:04:49 +0000 (11:04 +0000)]
[llvm-readobj] - Teach llvm-readobj to dump .gnu.version_r sections
SHT_GNU_verneed (.gnu.version_r) is a version dependency section.
It was the last symbol versioning relative section that was not dumped,
now it is.
Differential revision: http://reviews.llvm.org/D21024
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@271998
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Peter Smith [Tue, 7 Jun 2016 10:34:33 +0000 (10:34 +0000)]
[ARM] Incorrect relocation type for Thumb2 B<cond>.w
The Thumb2 conditional branch B<cond>.W has a different encoding (T3)
to the unconditional branch B.W (T4) as it needs to record <cond>.
As the encoding is different the B<cond>.W is given a different
relocation type.
ELF for the ARM Architecture 4.6.1.6 (Table-13) states that
R_ARM_THM_JUMP19 should be used for B<cond>.W. At present the
MC layer is using the R_ARM_THM_JUMP24 from B.W.
This change makes B<cond>.W use R_ARM_THM_JUMP19 and alters the
existing test that checks for R_ARM_THM_JUMP24 to expect
R_ARM_THM_JUMP19.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@271997
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Simon Pilgrim [Tue, 7 Jun 2016 10:27:15 +0000 (10:27 +0000)]
[InstCombine][AVX2] Add support for simplifying AVX2 per-element shifts to native shifts
Unlike native shifts, the AVX2 per-element shift instructions VPSRAV/VPSRLV/VPSLLV handle out of range shift values (logical shifts set the result to zero, arithmetic shifts splat the sign bit).
If the shift amount is constant we can sometimes convert these instructions to native shifts:
1 - if all shift amounts are in range then the conversion is trivial.
2 - out of range arithmetic shifts can be clamped to the (bitwidth - 1) (a legal shift amount) before conversion.
3 - logical shifts just return zero if all elements have out of range shift amounts.
In addition, UNDEF shift amounts are handled - either as an UNDEF shift amount in a native shift or as an UNDEF in the logical 'all out of range' zero constant special case for logical shifts.
Differential Revision: http://reviews.llvm.org/D19675
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@271996
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Simon Pilgrim [Tue, 7 Jun 2016 08:18:35 +0000 (08:18 +0000)]
[InstCombine][SSE] Add MOVMSK constant folding (PR27982)
This patch adds support for folding undef/zero/constant inputs to MOVMSK instructions.
The SSE/AVX versions can be fully folded, but the MMX version can only handle undef inputs.
Differential Revision: http://reviews.llvm.org/D20998
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@271990
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Craig Topper [Tue, 7 Jun 2016 07:27:57 +0000 (07:27 +0000)]
[AVX512] Allow avx2 and sse41 nontemporal load intrinsics to select EVEX encoded instructions when VLX is enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@271988
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Craig Topper [Tue, 7 Jun 2016 07:27:54 +0000 (07:27 +0000)]
[AVX512] Remove unnecessary mayLoad, mayStore, hasSidEffects flags from instructions that have patterns that imply them. Add the same set of flags to instructions that don't have patterns to imply them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@271987
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Craig Topper [Tue, 7 Jun 2016 07:27:51 +0000 (07:27 +0000)]
[AVX512] Add NoVLX to a couple patterns that have VLX equivalents. Ordering of the patterns in the .td file protects this, but its better to be explicit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@271986
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Lang Hames [Tue, 7 Jun 2016 05:40:08 +0000 (05:40 +0000)]
[Kaleidoscope] Update Chapter 3 of the "Implementing a Language" tutorial to
take into account modernizations in r246002 and r270381.
Patch based on http://reviews.llvm.org/D20954 by Miroslav Hrncir.
Thanks Miroslav!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@271985
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Zachary Turner [Tue, 7 Jun 2016 05:32:48 +0000 (05:32 +0000)]
[pdb] Fix broken unit tests after r271982.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@271983
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Zachary Turner [Tue, 7 Jun 2016 05:28:55 +0000 (05:28 +0000)]
[pdb] Use MappedBlockStream to parse the PDB directory.
In order to efficiently write PDBs, we need to be able to make a
StreamWriter class similar to a StreamReader, which can transparently deal
with writing to discontiguous streams, and we need to use this for all
writing, similar to how we use StreamReader for all reading.
Most discontiguous streams are the typical numbered streams that appear in
a PDB file and are described by the directory, but the exception to this,
that until now has been parsed by hand, is the directory itself.
MappedBlockStream works by querying the directory to find out which blocks
a stream occupies and various other things, so naturally the same logic
could not possibly work to describe the blocks that the directory itself
resided on.
To solve this, I've introduced an abstraction IPDBStreamData, which allows
the client to query for the list of blocks occupied by the stream, as well
as the stream length. I provide two implementations of this: one which
queries the directory (for indexed streams), and one which queries the
super block (for the directory stream).
This has the side benefit of vastly simplifying the code to parse the
directory. Whereas before a mini state machine was rolled by hand, now we
simply use FixedStreamArray to read out the stream sizes, then build a
vector of FixedStreamArrays for the stream map, all in just a few lines of
code.
Reviewed By: ruiu
Differential Revision: http://reviews.llvm.org/D21046
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@271982
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Dan Liew [Tue, 7 Jun 2016 04:44:49 +0000 (04:44 +0000)]
[LibFuzzer] s/dataflow sanitizer/DataflowSanitizer/
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@271980
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Dan Liew [Tue, 7 Jun 2016 04:44:39 +0000 (04:44 +0000)]
[LibFuzzer] Disable building and running LSan tests on Apple platforms because LSan is not currently supported.
Differential Revision: http://reviews.llvm.org/D20947
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@271979
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Saleem Abdulrasool [Tue, 7 Jun 2016 03:15:07 +0000 (03:15 +0000)]
ARM: correct TLS access on WoA
TLS access requires an offset from the TLS index. The index itself is the
section-relative distance of the symbol. For ARM, the relevant relocation
(IMAGE_REL_ARM_SECREL) is applied as a constant. This means that the value may
not be an immediate and must be lowered into a constant pool. This offset will
not be base relocated. We were previously emitting the actual address of the
symbol which would be base relocated and would therefore be the vaue offset by
the ImageBase + TLS Offset.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@271974
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Saleem Abdulrasool [Tue, 7 Jun 2016 03:15:01 +0000 (03:15 +0000)]
ARM: clang-format a couple of switches, add comments
clang-format a couple of switches in preparation for a future change. Add some
enumeration comments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@271973
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Saleem Abdulrasool [Tue, 7 Jun 2016 03:14:57 +0000 (03:14 +0000)]
ARM: normalise space in the patterns
Just adjust the whitespace for the selection patterns. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@271972
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Kostya Serebryany [Tue, 7 Jun 2016 01:20:26 +0000 (01:20 +0000)]
[sanitizer] Initial implementation of a Hardened Allocator
Summary:
This is an initial implementation of a Hardened Allocator based on Sanitizer Common's CombinedAllocator.
It aims at mitigating heap based vulnerabilities by adding several features to the base allocator, while staying relatively fast.
The following were implemented:
- additional consistency checks on the allocation function parameters and on the heap chunks;
- use of checksum protected chunk header, to detect corruption;
- randomness to the allocator base;
- delayed freelist (quarantine), to mitigate use after free and overall determinism.
Additional mitigations are in the works.
Reviewers: eugenis, aizatsky, pcc, krasin, vitalybuka, glider, dvyukov, kcc
Subscribers: kubabrecka, filcab, llvm-commits
Differential Revision: http://reviews.llvm.org/D20084
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@271968
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Rui Ueyama [Tue, 7 Jun 2016 00:59:04 +0000 (00:59 +0000)]
Add comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@271967
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Reid Kleckner [Tue, 7 Jun 2016 00:02:03 +0000 (00:02 +0000)]
Re-land "[codeview] Emit information about global variables"
This reverts commit r271962 and reinstantes r271957.
MSVC's linker doesn't appear to like it if you have an empty symbol
substream, so only open a symbol substream if we're going to emit
something about globals into it.
Makes check-asan pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@271965
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Reid Kleckner [Mon, 6 Jun 2016 23:46:14 +0000 (23:46 +0000)]
Try one more time to pacify -Wpessimizing-move, MSVC, libstdc++4.7, and the world without a named variable
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@271964
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Vedant Kumar [Mon, 6 Jun 2016 23:43:56 +0000 (23:43 +0000)]
Revert "Retry^2 "[llvm-profdata] Add option to ingest filepaths from a file""
This reverts commit r271953. It's still breaking on Windows, though the
list initialization issue is fixed:
http://bb.pgr.jp/builders/ninja-clang-i686-msc19-R/builds/3751
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@271963
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Reid Kleckner [Mon, 6 Jun 2016 23:41:38 +0000 (23:41 +0000)]
Revert "[codeview] Emit information about global variables"
This reverts commit r271957, it broke check-asan on Windows.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@271962
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Michael Kuperstein [Mon, 6 Jun 2016 23:38:33 +0000 (23:38 +0000)]
[InstCombine] scalarizePHI should not assume the code it sees has been CSE'd
scalarizePHI only looked for phis that have exactly two uses - the "latch"
use, and an extract. Unfortunately, we can not assume all equivalent extracts
are CSE'd, since InstCombine itself may create an extract which is a duplicate
of an existing one. This extends it to handle several distinct extracts from
the same index.
This should fix at least some of the performance regressions from PR27988.
Differential Revision: http://reviews.llvm.org/D20983
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@271961
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