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Manman Ren [Wed, 21 Aug 2013 22:20:53 +0000 (22:20 +0000)]
TBAA: remove !tbaa from testing cases when they are not needed.
This will make it easier to turn on struct-path aware TBAA since the metadata
format will change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188944
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Andrew Kaylor [Wed, 21 Aug 2013 22:15:09 +0000 (22:15 +0000)]
Adding a document to describe the MCJIT execution engine implementation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188943
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Tom Stellard [Wed, 21 Aug 2013 22:14:17 +0000 (22:14 +0000)]
R600: Remove unnecessary casts
Spotted by Bill Wendling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188942
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Yunzhong Gao [Wed, 21 Aug 2013 22:11:15 +0000 (22:11 +0000)]
No functionality change.
Replace "(255 & value)" with "(0xFF & value)" to improve clarity.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188941
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Juergen Ributzka [Wed, 21 Aug 2013 21:53:38 +0000 (21:53 +0000)]
Teach BaseIndexOffset::match to identify base pointers in loops.
The small utility function that pattern matches Base + Index +
Offset patterns for loads and stores fails to recognize the base
pointer for loads/stores from/into an array at offset 0 inside a
loop. As a result DAGCombiner::MergeConsecutiveStores was not able
to merge all stores.
This commit fixes the issue by adding an additional pattern match
and also a test case.
Reviewer: Nadav
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188936
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David Majnemer [Wed, 21 Aug 2013 21:53:33 +0000 (21:53 +0000)]
ADT/Triple: Helper to determine if we are targeting the Windows CRT
Summary:
This support will be utilized in things like clang to help check printf
format specifiers that are only valid when using the VSCRT.
Reviewers: rnk, asl, chandlerc
Reviewed By: chandlerc
CC: llvm-commits
Differential Revision: http://llvm-reviews.chandlerc.com/D1455
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188935
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David Blaikie [Wed, 21 Aug 2013 21:30:23 +0000 (21:30 +0000)]
Basic unit tests for PointerUnion
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188933
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Bill Wendling [Wed, 21 Aug 2013 21:14:19 +0000 (21:14 +0000)]
Reorder headers according to lint.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188932
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Bill Wendling [Wed, 21 Aug 2013 20:36:42 +0000 (20:36 +0000)]
Remove use of forbidden 'iostream' header.
Also obsessively reorder the headers to be in something closer to alphabetical order.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188928
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Matt Arsenault [Wed, 21 Aug 2013 19:53:10 +0000 (19:53 +0000)]
Teach InstCombine about address spaces
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188926
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Ahmed Bougacha [Wed, 21 Aug 2013 19:40:28 +0000 (19:40 +0000)]
MC CFG: Remap enough for data too, analoguous to r188873.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188925
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Ahmed Bougacha [Wed, 21 Aug 2013 19:40:25 +0000 (19:40 +0000)]
Style cleanup following David's review for r188876.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188924
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Ahmed Bougacha [Wed, 21 Aug 2013 19:40:22 +0000 (19:40 +0000)]
Add testcase for r188873: MCTextAtom boundaries.
Check that they are correctly computed if the last instruction is
larger than 1 byte.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188923
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Argyrios Kyrtzidis [Wed, 21 Aug 2013 19:13:44 +0000 (19:13 +0000)]
[CMake] Automatically pick up subdirectories in llvm/tools as 'external projects' if they contain a 'CMakeLists.txt' file.
Allow CMake to pick up external projects in llvm/tools without the need to modify the "llvm/tools/CMakeLists.txt" file.
This makes it easier to work with projects that live in other repositories, without needing to specify each one in "llvm/tools/CMakeLists.txt".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188921
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Matt Arsenault [Wed, 21 Aug 2013 19:09:28 +0000 (19:09 +0000)]
Add test for bitcast array ptrs with address spaces
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188919
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Matt Arsenault [Wed, 21 Aug 2013 18:54:53 +0000 (18:54 +0000)]
Add enforce known alignment test with address space
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188917
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Matt Arsenault [Wed, 21 Aug 2013 18:54:50 +0000 (18:54 +0000)]
Use attribute helper function
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188916
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Matt Arsenault [Wed, 21 Aug 2013 18:54:47 +0000 (18:54 +0000)]
Fix typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188915
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Hao Liu [Wed, 21 Aug 2013 17:47:53 +0000 (17:47 +0000)]
A minor change for an obvous problem caused by r188451:
def imm0_63 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 63;}]>{
As it seems Imm <63 should be Imm <= 63. ImmLeaf is used in pattern match, but there is already a function check the shift amount range, so just remove ImmLeaf. Also add a test to check 63.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188911
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Joey Gouly [Wed, 21 Aug 2013 17:14:31 +0000 (17:14 +0000)]
Add -mcpu to two X86 tests.
These tests are failing on Haswell CPUs due to different instruction selection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188908
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Ahmed Bougacha [Wed, 21 Aug 2013 16:13:25 +0000 (16:13 +0000)]
Add basic YAML MC CFG testcase.
Drive-by llvm-objdump cleanup (don't hardcode ToolName).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188904
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NAKAMURA Takumi [Wed, 21 Aug 2013 13:47:12 +0000 (13:47 +0000)]
Unix/Process.inc: Revert r72332, "Work around a page size issue on Cygwin."
Offset in mmap(3) should be aligned to gepagesize(), 64k, or mmap(3) would fail.
TODO: Invetigate places where 4096 would be required as pagesize, or 4096 would satisfy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188903
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Mihai Popa [Wed, 21 Aug 2013 13:14:58 +0000 (13:14 +0000)]
Make "mov" work for all Thumb2 MOV encodings
According to the ARM specification, "mov" is a valid mnemonic for all Thumb2 MOV encodings.
To achieve this, the patch adds one instruction alias with a special range condition to avoid collision with the Thumb1 MOV.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188901
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Elena Demikhovsky [Wed, 21 Aug 2013 09:36:02 +0000 (09:36 +0000)]
AVX-512: Added SHIFT instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188899
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Richard Sandiford [Wed, 21 Aug 2013 09:34:56 +0000 (09:34 +0000)]
[SystemZ] Define remainig *MUL_LOHI patterns
The initial port used MLG(R) for i64 UMUL_LOHI but left the other three
combinations as not-legal-or-custom. Although 32x32->{32,32}
multiplications exist, they're not as quick as doing a normal 64-bit
multiplication, so it didn't seem like i32 SMUL_LOHI and UMUL_LOHI
would be useful. There's also no direct instruction for i64 SMUL_LOHI,
so it needs to be implemented in terms of UMUL_LOHI.
However, not defining these patterns means that we don't convert
division by a constant into multiplication, so this patch fills
in the other cases. The new i64 SMUL_LOHI sequence is simpler
than the one that we used previously for 64x64->128 multiplication,
so int-mul-08.ll now tests the full sequence.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188898
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NAKAMURA Takumi [Wed, 21 Aug 2013 09:34:22 +0000 (09:34 +0000)]
MCFunction.h: Prune \returns to fix a warning in r188881. [-Wdocumentation]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188897
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Daniel Sanders [Wed, 21 Aug 2013 09:09:52 +0000 (09:09 +0000)]
[mips][msa] Matheus Almeida pointed out a silly mistake in r188893. Fixed it.
I accidentally changed the encoding of the MSA registers to zero instead of 0
to 31. This change restores the encoding the registers had prior to r188893.
This didn't show up in the existing tests because direct-object emission isn't
implemented yet for MSA.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188896
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Richard Sandiford [Wed, 21 Aug 2013 09:04:20 +0000 (09:04 +0000)]
[SystemZ] Use FI[EDX]BRA for codegen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188895
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Richard Sandiford [Wed, 21 Aug 2013 08:58:08 +0000 (08:58 +0000)]
[SystemZ] Add FI[EDX]BRA
These are extensions of the existing FI[EDX]BR instructions, but use a spare
bit to suppress inexact conditions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188894
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Daniel Sanders [Wed, 21 Aug 2013 08:48:25 +0000 (08:48 +0000)]
[mips][msa] Define registers using foreach
No functional change
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188893
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Ahmed Bougacha [Wed, 21 Aug 2013 07:29:02 +0000 (07:29 +0000)]
MC CFG: Add YAML MCModule representation to enable MC CFG testing.
Like yaml ObjectFiles, this will be very useful for testing the MC CFG
implementation (mostly MCObjectDisassembler), by matching the output
with YAML, and for potential users of the MC CFG, by using it as an input.
There isn't much to the actual format, it is just a serialization of the
MCModule class. Of note:
- Basic block references (pred/succ, ..) are represented by the BB's
start address.
- Just as in the MC CFG, instructions are MCInsts with a size.
- Operands have a prefix representing the type (only register and
immediate supported here).
- Instruction opcodes are represented by their names; enum values aren't
stable, enum names mostly are: usually, a change to a name would need
lots of changes in the backend anyway.
Same with registers.
All in all, an example is better than 1000 words, here goes:
A simple binary:
Disassembly of section __TEXT,__text:
_main:
100000f9c: 48 8b 46 08 movq 8(%rsi), %rax
100000fa0: 0f be 00 movsbl (%rax), %eax
100000fa3: 3b 04 25 48 00 00 00 cmpl 72, %eax
100000faa: 0f 8c 07 00 00 00 jl 7 <.Lend>
100000fb0: 2b 04 25 48 00 00 00 subl 72, %eax
.Lend:
100000fb7: c3 ret
And the (pretty verbose) generated YAML:
---
Atoms:
- StartAddress: 0x0000000100000F9C
Size: 20
Type: Text
Content:
- Inst: MOV64rm
Size: 4
Ops: [ RRAX, RRSI, I1, R, I8, R ]
- Inst: MOVSX32rm8
Size: 3
Ops: [ REAX, RRAX, I1, R, I0, R ]
- Inst: CMP32rm
Size: 7
Ops: [ REAX, R, I1, R, I72, R ]
- Inst: JL_4
Size: 6
Ops: [ I7 ]
- StartAddress: 0x0000000100000FB0
Size: 7
Type: Text
Content:
- Inst: SUB32rm
Size: 7
Ops: [ REAX, REAX, R, I1, R, I72, R ]
- StartAddress: 0x0000000100000FB7
Size: 1
Type: Text
Content:
- Inst: RET
Size: 1
Ops: [ ]
Functions:
- Name: __text
BasicBlocks:
- Address: 0x0000000100000F9C
Preds: [ ]
Succs: [ 0x0000000100000FB7, 0x0000000100000FB0 ]
<snip>
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188890
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Ahmed Bougacha [Wed, 21 Aug 2013 07:28:55 +0000 (07:28 +0000)]
MC CFG: Support disassembly at arbitrary addresses in MCObjectDisassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188889
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Ahmed Bougacha [Wed, 21 Aug 2013 07:28:51 +0000 (07:28 +0000)]
MC CFG: Use data structures more appropriate than std::set.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188888
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Ahmed Bougacha [Wed, 21 Aug 2013 07:28:48 +0000 (07:28 +0000)]
MC CFG: Add an MCObjectSymbolizer in the MCObjectDisassembler.
Used to detect calls to function symbol stubs (future commit).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188887
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Ahmed Bougacha [Wed, 21 Aug 2013 07:28:44 +0000 (07:28 +0000)]
MC CFG: Add MCObjectDisassembler Mach-O implementation.
Supports:
- entrypoint, using LC_MAIN.
- static ctors/dtors, using __mod_{init,exit}_func
- translation between effective and object load address, using
dyld's VM address slide.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188886
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Ahmed Bougacha [Wed, 21 Aug 2013 07:28:40 +0000 (07:28 +0000)]
Add Mach-O entry_point_command declaration.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188885
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Ahmed Bougacha [Wed, 21 Aug 2013 07:28:37 +0000 (07:28 +0000)]
MC CFG: Add "dynamic disassembly" support to MCObjectDisassembler.
It can now disassemble code in situations where the effective load
address is different than the load address declared in the object file.
This happens for PIC, hence "dynamic".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188884
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Ahmed Bougacha [Wed, 21 Aug 2013 07:28:32 +0000 (07:28 +0000)]
MC CFG: When disassembly is impossible, fallback to data bytes.
This is the behavior of sequential disassemblers (llvm-objdump, ...),
when there is no instruction size hint (fixed-length, ...)
While there, also do some minor cleanup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188883
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Ahmed Bougacha [Wed, 21 Aug 2013 07:28:29 +0000 (07:28 +0000)]
MC CFG: Add MCObjectDisassembler support for entrypoint + static ctors.
For now, this isn't implemented for any format.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188882
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Ahmed Bougacha [Wed, 21 Aug 2013 07:28:24 +0000 (07:28 +0000)]
MC CFG: Split MCBasicBlocks to mirror atom splitting.
When an MCTextAtom is split, all MCBasicBlocks backed by it are
automatically split, with a fallthrough between both blocks, and
the successors moved to the second block.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188881
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Ahmed Bougacha [Wed, 21 Aug 2013 07:28:17 +0000 (07:28 +0000)]
MC CFG: Add a few needed methods, mainly MCModule::findFirstAtomAfter.
While there, do some minor cleanup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188880
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Ahmed Bougacha [Wed, 21 Aug 2013 07:28:13 +0000 (07:28 +0000)]
MC: ObjectSymbolizer can now recognize external function stubs.
Only implemented in the Mach-O ObjectSymbolizer.
The testcase sadly introduces a new binary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188879
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Ahmed Bougacha [Wed, 21 Aug 2013 07:28:07 +0000 (07:28 +0000)]
MC: Refactor ObjectSymbolizer to make relocation/section info generation lazy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188878
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Ahmed Bougacha [Wed, 21 Aug 2013 07:28:02 +0000 (07:28 +0000)]
MC CFG: Add entrypoint address to MCModule.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188877
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Ahmed Bougacha [Wed, 21 Aug 2013 07:27:59 +0000 (07:27 +0000)]
MC CFG: Add more MCFunction container methods (find, empty).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188876
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Ahmed Bougacha [Wed, 21 Aug 2013 07:27:55 +0000 (07:27 +0000)]
MC CFG: Keep pointer to parent MCModule in created MCFunctions.
Also, drive-by cleaning around createFunction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188875
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Ahmed Bougacha [Wed, 21 Aug 2013 07:27:50 +0000 (07:27 +0000)]
MC CFG: Don't insert preds/succs again.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188874
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Ahmed Bougacha [Wed, 21 Aug 2013 07:27:47 +0000 (07:27 +0000)]
MC CFG: Remap enough for the inserted instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188873
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Ahmed Bougacha [Wed, 21 Aug 2013 07:27:44 +0000 (07:27 +0000)]
MC CFG: uint64_t -> size_t for vector size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188872
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Ahmed Bougacha [Wed, 21 Aug 2013 07:27:40 +0000 (07:27 +0000)]
MC CFG: Add a getter for MCDataAtom's data array.
While there, switch to new-style documentation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188871
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David Majnemer [Wed, 21 Aug 2013 06:13:34 +0000 (06:13 +0000)]
DebugInfo: Do not use the DWARF Version for the .debug_pubnames or .debug_pubtypes version field
Summary:
LLVM would generate DWARF with version 3 in the .debug_pubname and
.debug_pubtypes version fields. This would lead SGI dwarfdump to fail
parsing the DWARF with (in the instance of .debug_pubnames) would exit
with:
dwarfdump ERROR: dwarf_get_globals: DW_DLE_PUBNAMES_VERSION_ERROR (123)
This fixes PR16950.
Reviewers: echristo, dblaikie
Reviewed By: echristo
CC: cfe-commits
Differential Revision: http://llvm-reviews.chandlerc.com/D1454
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188869
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Craig Topper [Wed, 21 Aug 2013 05:57:45 +0000 (05:57 +0000)]
Synchronize VEX JIT encoding code with the MCJIT version. Fix a bug in the MCJIT code where CurOp was being incremented even if the operand it was pointing at wasn't used. Maybe only matters if there are any EVEX_K instructions that aren't VEX_4V.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188868
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Nadav Rotem [Wed, 21 Aug 2013 05:03:10 +0000 (05:03 +0000)]
In LLVM FMA3 operands are dst, src1, src2, src3, however dst is not encoded as it is always src1. This was causing the encoding of the operands to be off by one.
Patch by Chris Bieneman.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188866
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Nadav Rotem [Wed, 21 Aug 2013 05:02:12 +0000 (05:02 +0000)]
Add the FMA3 feature in order to test FMA encoding using the old jit.
Patch by Chris Bieneman!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188865
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Craig Topper [Wed, 21 Aug 2013 03:57:57 +0000 (03:57 +0000)]
Rename mattr names for AVX-512 to from avx-512 -> avx512f, avx-512-pfi -> av512pf, avx-512-cdi -> avx512cd, avx-512-eri->avx512er. This matches better with official docs and what gcc patches appearto be using. I didn't touch the has* functions or the feature flag names to avoid change the td and lowering file while commits are still happening.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188859
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NAKAMURA Takumi [Wed, 21 Aug 2013 02:37:25 +0000 (02:37 +0000)]
X86TargetMachine.cpp: Clarify to emit GOT in i686-{cygming|win32}-elf for mcjit.
I suppose all "lli -use-mcjit i686-*" should require GOT, (and to fail.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188856
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NAKAMURA Takumi [Wed, 21 Aug 2013 02:37:14 +0000 (02:37 +0000)]
lli/RecordingMemoryManager.cpp: Make it complain if _GLOBAL_OFFSET_TABLE_ were not provided.
FIXME: Would it be responsible to provide GOT?
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188855
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Jakub Staszak [Wed, 21 Aug 2013 01:20:11 +0000 (01:20 +0000)]
Move #includes from .h to .cpp file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188852
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Akira Hatanaka [Wed, 21 Aug 2013 01:18:46 +0000 (01:18 +0000)]
[micromips] Print instruction alias "not" if the last operand of a nor is zero.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188851
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Bill Wendling [Tue, 20 Aug 2013 23:52:00 +0000 (23:52 +0000)]
Move registering the execution of a basic block to the beginning rather than the end.
There are situations which can affect the correctness (or at least expectation)
of the gcov output. For instance, if a call to __gcov_flush() occurs within a
block before the execution count is registered and then the program aborts in
some way, then that block will not be marked as executed. This is not normally
what the user expects.
If we move the code that's registering when a block is executed to the
beginning, we can catch these types of situations.
PR16893
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188849
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Akira Hatanaka [Tue, 20 Aug 2013 23:47:25 +0000 (23:47 +0000)]
[mips] Add support for mfhc1 and mthc1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188848
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Akira Hatanaka [Tue, 20 Aug 2013 23:38:40 +0000 (23:38 +0000)]
[mips] Add support for calling convention CC_MipsO32_FP64, which is used when the
size of floating point registers is 64-bit.
Test case will be added when support for mfhc1 and mthc1 is added.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188847
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Akira Hatanaka [Tue, 20 Aug 2013 23:21:55 +0000 (23:21 +0000)]
[mips] Remove predicates that were incorrectly or unnecessarily added.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188845
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Jakub Staszak [Tue, 20 Aug 2013 23:04:15 +0000 (23:04 +0000)]
Add some constantness.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188844
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Bill Wendling [Tue, 20 Aug 2013 23:00:25 +0000 (23:00 +0000)]
Use -disable-output and to suppress output and don't use a temporary file unless we need one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188843
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Akira Hatanaka [Tue, 20 Aug 2013 22:58:56 +0000 (22:58 +0000)]
[mips] Define register class FGRH32 for the high half of the 64-bit floating
point registers. We will need this register class later when we add
definitions for instructions mfhc1 and mthc1. Also, remove sub-register indices
sub_fpeven and sub_fpodd and use sub_lo and sub_hi instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188842
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Jakub Staszak [Tue, 20 Aug 2013 22:52:02 +0000 (22:52 +0000)]
Fix include guards.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188841
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Arnold Schwaighofer [Tue, 20 Aug 2013 21:21:45 +0000 (21:21 +0000)]
SLPVectorizer: Fix invalid iterator errors
Update iterator when the SLP vectorizer changes the instructions in the basic
block by restarting the traversal of the basic block.
Patch by Yi Jiang!
Fixes PR 16899.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188832
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Matt Arsenault [Tue, 20 Aug 2013 21:20:04 +0000 (21:20 +0000)]
Teach ConstantFolding about pointer address spaces
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188831
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Akira Hatanaka [Tue, 20 Aug 2013 21:08:22 +0000 (21:08 +0000)]
[mips] Resolve register classes dynamically using ptr_rc to reduce the number of
load/store instructions defined. Previously, we were defining load/store
instructions for each pointer size (32 and 64-bit), but now we need just one
definition.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188830
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Reed Kotler [Tue, 20 Aug 2013 20:53:09 +0000 (20:53 +0000)]
Add an option which permits the user to specify using a bitmask, that various
functions be compiled as mips32, without having to add attributes. This
is useful in certain situations where you don't want to have to edit the
function attributes in the source. For now it's only an option used for
the compiler developers when debugging the mips16 port.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188826
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Akira Hatanaka [Tue, 20 Aug 2013 20:46:51 +0000 (20:46 +0000)]
[mips] Guard micromips instructions with predicate InMicroMips. Also, fix
assembler predicate HasStdEnd so that it is false when the target is micromips.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188824
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Jim Grosbach [Tue, 20 Aug 2013 19:12:42 +0000 (19:12 +0000)]
ARM: Fix fast-isel copy/paste-o.
Update testcase to be more careful about checking register
values. While regexes are general goodness for these sorts of
testcases, in this example, the registers are constrained by
the calling convention, so we can and should check their
explicit values.
rdar://
14779513
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188819
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Andrew Kaylor [Tue, 20 Aug 2013 18:13:48 +0000 (18:13 +0000)]
Still more MCJIT PIC test XFAILs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188815
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Andrew Kaylor [Tue, 20 Aug 2013 17:01:35 +0000 (17:01 +0000)]
Clarifying two MCJIT PIC tests as XFAIL on i686-pc-linux
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188814
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Andrew Kaylor [Tue, 20 Aug 2013 16:42:22 +0000 (16:42 +0000)]
Removing duplicate XFAIL markers
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188812
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Andrew Kaylor [Tue, 20 Aug 2013 15:47:04 +0000 (15:47 +0000)]
Marking two more MCJIT PIC tests as XFAIL on i686
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188808
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Andrew Kaylor [Tue, 20 Aug 2013 15:36:04 +0000 (15:36 +0000)]
Marking MCJIT PIC tests as XFAIL on arm
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188807
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Vladimir Medic [Tue, 20 Aug 2013 13:33:18 +0000 (13:33 +0000)]
Fix style issues in AsmParser.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188798
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Elena Demikhovsky [Tue, 20 Aug 2013 11:00:29 +0000 (11:00 +0000)]
AVX-512: Added more patterns for VMOVSS, VMOVSD, VMOVD, VMOVQ
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188786
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Daniel Sanders [Tue, 20 Aug 2013 09:41:47 +0000 (09:41 +0000)]
[mips][msa] Removed fcge, fcgt, fsge, fsgt
These instructions were present in a draft spec but were removed before
publication.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188782
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Richard Sandiford [Tue, 20 Aug 2013 09:40:35 +0000 (09:40 +0000)]
[SystemZ] Update README
We now use MVST, CLST and SRST for the obvious cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188781
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Richard Sandiford [Tue, 20 Aug 2013 09:38:48 +0000 (09:38 +0000)]
[SystemZ] Use SRST to optimize memchr
SystemZTargetLowering::emitStringWrapper() previously loaded the character
into R0 before the loop and made R0 live on entry. I'd forgotten that
allocatable registers weren't allowed to be live across blocks at this stage,
and it confused LiveVariables enough to cause a miscompilation of f3 in
memchr-02.ll.
This patch instead loads R0 in the loop and leaves LICM to hoist it
after RA. This is actually what I'd tried originally, but I went for
the manual optimisation after noticing that R0 often wasn't being hoisted.
This bug forced me to go back and look at why, now fixed as r188774.
We should also try to optimize null checks so that they test the CC result
of the SRST directly. The select between null and the SRST GPR result could
then usually be deleted as dead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188779
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Benjamin Kramer [Tue, 20 Aug 2013 09:27:31 +0000 (09:27 +0000)]
memcmp is not a valid way to compare structs with padding in them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188778
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Daniel Sanders [Tue, 20 Aug 2013 09:22:54 +0000 (09:22 +0000)]
[mips][msa] Added insve
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188777
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Richard Sandiford [Tue, 20 Aug 2013 09:14:46 +0000 (09:14 +0000)]
Fix test typo and add usual "br %r14" test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188775
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Richard Sandiford [Tue, 20 Aug 2013 09:11:13 +0000 (09:11 +0000)]
Fix overly pessimistic shortcut in post-RA MachineLICM
Post-RA LICM keeps three sets of registers: PhysRegDefs, PhysRegClobbers
and TermRegs. When it sees a definition of R it adds all aliases of R
to the corresponding set, so that when it needs to test for membership
it only needs to test a single register, rather than worrying about
aliases there too. E.g. the final candidate loop just has:
unsigned Def = Candidates[i].Def;
if (!PhysRegClobbers.test(Def) && ...) {
to test whether register Def is multiply defined.
However, there was also a shortcut in ProcessMI to make sure we didn't
add candidates if we already knew that they would fail the final test.
This shortcut was more pessimistic than the final one because it
checked whether _any alias_ of the defined register was multiply defined.
This is too conservative for targets that define register pairs.
E.g. on z, R0 and R1 are sometimes used as a pair, so there is a
128-bit register that aliases both R0 and R1. If a loop used
R0 and R1 independently, and the definition of R0 came first,
we would be able to hoist the R0 assignment (because that used
the final test quoted above) but not the R1 assignment (because
that meant we had two definitions of the paired R0/R1 register
and would fail the shortcut in ProcessMI).
This patch just uses the same check for the ProcessMI shortcut as
we use in the final candidate loop.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188774
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Tim Northover [Tue, 20 Aug 2013 08:57:11 +0000 (08:57 +0000)]
ARM: implement some simple f64 materializations.
Previously we used a const-pool load for virtually all 64-bit floating values.
Actually, we can get quite a few common values (including 0.0, 1.0) via "vmov"
instructions of one stripe or another.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188773
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Michael Gottesman [Tue, 20 Aug 2013 08:56:28 +0000 (08:56 +0000)]
[stackprotector] Small cleanup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188772
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Michael Gottesman [Tue, 20 Aug 2013 08:56:26 +0000 (08:56 +0000)]
[stackprotector] Small Bit of computation hoisting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188771
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Michael Gottesman [Tue, 20 Aug 2013 08:56:23 +0000 (08:56 +0000)]
[stackprotector] Added significantly longer comment to FindPotentialTailCall to make clear its relationship to llvm::isInTailCallPosition.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188770
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Michael Gottesman [Tue, 20 Aug 2013 08:46:16 +0000 (08:46 +0000)]
Removed trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188769
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Michael Gottesman [Tue, 20 Aug 2013 08:46:13 +0000 (08:46 +0000)]
[stackprotector] Removed stale TODO.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188768
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Daniel Sanders [Tue, 20 Aug 2013 08:38:21 +0000 (08:38 +0000)]
[mips][msa] Added and.v, bmnz.v, bmz.v, bsel.v, nor.v, or.v, xor.v
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188767
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Michael Gottesman [Tue, 20 Aug 2013 08:36:53 +0000 (08:36 +0000)]
[stackprotector] Added support for emitting the llvm intrinsic stack protector check.
rdar://
13935163
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188766
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Michael Gottesman [Tue, 20 Aug 2013 08:36:50 +0000 (08:36 +0000)]
[stackprotector] Refactor out the end of isInTailCallPosition into the function returnTypeIsEligibleForTailCall.
This allows me to use returnTypeIsEligibleForTailCall in the stack protector pass.
rdar://
13935163
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188765
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Michael Gottesman [Tue, 20 Aug 2013 07:17:27 +0000 (07:17 +0000)]
Remove unused variables that crept in.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188761
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Michael Gottesman [Tue, 20 Aug 2013 07:00:16 +0000 (07:00 +0000)]
Teach selectiondag how to handle the stackprotectorcheck intrinsic.
Previously, generation of stack protectors was done exclusively in the
pre-SelectionDAG Codegen LLVM IR Pass "Stack Protector". This necessitated
splitting basic blocks at the IR level to create the success/failure basic
blocks in the tail of the basic block in question. As a result of this,
calls that would have qualified for the sibling call optimization were no
longer eligible for optimization since said calls were no longer right in
the "tail position" (i.e. the immediate predecessor of a ReturnInst
instruction).
Then it was noticed that since the sibling call optimization causes the
callee to reuse the caller's stack, if we could delay the generation of
the stack protector check until later in CodeGen after the sibling call
decision was made, we get both the tail call optimization and the stack
protector check!
A few goals in solving this problem were:
1. Preserve the architecture independence of stack protector generation.
2. Preserve the normal IR level stack protector check for platforms like
OpenBSD for which we support platform specific stack protector
generation.
The main problem that guided the present solution is that one can not
solve this problem in an architecture independent manner at the IR level
only. This is because:
1. The decision on whether or not to perform a sibling call on certain
platforms (for instance i386) requires lower level information
related to available registers that can not be known at the IR level.
2. Even if the previous point were not true, the decision on whether to
perform a tail call is done in LowerCallTo in SelectionDAG which
occurs after the Stack Protector Pass. As a result, one would need to
put the relevant callinst into the stack protector check success
basic block (where the return inst is placed) and then move it back
later at SelectionDAG/MI time before the stack protector check if the
tail call optimization failed. The MI level option was nixed
immediately since it would require platform specific pattern
matching. The SelectionDAG level option was nixed because
SelectionDAG only processes one IR level basic block at a time
implying one could not create a DAG Combine to move the callinst.
To get around this problem a few things were realized:
1. While one can not handle multiple IR level basic blocks at the
SelectionDAG Level, one can generate multiple machine basic blocks
for one IR level basic block. This is how we handle bit tests and
switches.
2. At the MI level, tail calls are represented via a special return
MIInst called "tcreturn". Thus if we know the basic block in which we
wish to insert the stack protector check, we get the correct behavior
by always inserting the stack protector check right before the return
statement. This is a "magical transformation" since no matter where
the stack protector check intrinsic is, we always insert the stack
protector check code at the end of the BB.
Given the aforementioned constraints, the following solution was devised:
1. On platforms that do not support SelectionDAG stack protector check
generation, allow for the normal IR level stack protector check
generation to continue.
2. On platforms that do support SelectionDAG stack protector check
generation:
a. Use the IR level stack protector pass to decide if a stack
protector is required/which BB we insert the stack protector check
in by reusing the logic already therein. If we wish to generate a
stack protector check in a basic block, we place a special IR
intrinsic called llvm.stackprotectorcheck right before the BB's
returninst or if there is a callinst that could potentially be
sibling call optimized, before the call inst.
b. Then when a BB with said intrinsic is processed, we codegen the BB
normally via SelectBasicBlock. In said process, when we visit the
stack protector check, we do not actually emit anything into the
BB. Instead, we just initialize the stack protector descriptor
class (which involves stashing information/creating the success
mbbb and the failure mbb if we have not created one for this
function yet) and export the guard variable that we are going to
compare.
c. After we finish selecting the basic block, in FinishBasicBlock if
the StackProtectorDescriptor attached to the SelectionDAGBuilder is
initialized, we first find a splice point in the parent basic block
before the terminator and then splice the terminator of said basic
block into the success basic block. Then we code-gen a new tail for
the parent basic block consisting of the two loads, the comparison,
and finally two branches to the success/failure basic blocks. We
conclude by code-gening the failure basic block if we have not
code-gened it already (all stack protector checks we generate in
the same function, use the same failure basic block).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188755
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Craig Topper [Tue, 20 Aug 2013 05:23:59 +0000 (05:23 +0000)]
Fix formatting. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188746
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Craig Topper [Tue, 20 Aug 2013 05:22:42 +0000 (05:22 +0000)]
Add AVX-512 and related features to the CPUID detection code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188745
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