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Diana Picus [Wed, 17 Jan 2018 15:01:19 +0000 (15:01 +0000)]
[ARM GlobalISel] Add instselect tests for G_FPEXT and G_FPTRUNC
G_FPEXT and G_FPTRUNC are handled by TableGen'erated code, just add
tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322665
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Pablo Barrio [Wed, 17 Jan 2018 14:39:29 +0000 (14:39 +0000)]
[AArch64] Fix incorrect LD1 of 16-bit FP vectors in big endian
Summary:
Loading a vector of 4 half-precision FP sometimes results in an LD1
of 2 single-precision FP + a reversal. This results in an incorrect
byte swap due to the conversion from little endian to big endian.
In order to generate the correct byte swap, it is easier to
generate the correct LD1 of 4 half-precision FP, thus avoiding the
subsequent reversal.
Reviewers: craig.topper, jmolloy, olista01
Reviewed By: olista01
Subscribers: efriedma, samparker, SjoerdMeijer, rogfer01, aemerson, rengolin, javed.absar, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D41863
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322663
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Sanjay Patel [Wed, 17 Jan 2018 14:39:28 +0000 (14:39 +0000)]
[InstCombine] fix demanded-bits propagation for zext/trunc
I was comparing the demanded-bits implementations between InstCombine
and TargetLowering as part of investigating questions in D42088 and
noticed that this was wrong in IR. We were losing all of the prior
known bits when we got back to the 'zext'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322662
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Sanjay Patel [Wed, 17 Jan 2018 14:27:35 +0000 (14:27 +0000)]
[InstCombine] add test to show hole in demanded bits; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322660
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Alex Bradbury [Wed, 17 Jan 2018 14:17:12 +0000 (14:17 +0000)]
[RISCV] Allow RISCVAsmBackend::writeNopData to generate c.nop when supported
When the compressed instruction set is enabled, the 16-bit c.nop can be
generated if necessary.
Differential Revision: https://reviews.llvm.org/D41221
Patch by Shiva Chen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322658
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Diana Picus [Wed, 17 Jan 2018 14:14:14 +0000 (14:14 +0000)]
[ARM GlobalISel] Map G_FPEXT and G_FPTRUNC to FPR
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322657
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Daniil Fukalov [Wed, 17 Jan 2018 14:05:05 +0000 (14:05 +0000)]
[AMDGPU] add LDS f32 intrinsics
added llvm.amdgcn.atomic.{add|min|max}.f32 intrinsics
to allow generate ds_{add|min|max}[_rtn]_f32 instructions
needed for OpenCL float atomics in LDS
Reviewed by: arsenm
Differential Revision: https://reviews.llvm.org/D37985
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322656
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Dmitry Preobrazhensky [Wed, 17 Jan 2018 14:00:48 +0000 (14:00 +0000)]
[AMDGPU][MC][GFX9] Enable inline constants for SDWA operands
See bug 35771: https://bugs.llvm.org/show_bug.cgi?id=35771
Differential Revision: https://reviews.llvm.org/D42058
Reviewers: vpykhtin, artem.tamazov, arsenm
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322655
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Diana Picus [Wed, 17 Jan 2018 13:34:10 +0000 (13:34 +0000)]
[ARM GlobalISel] Legalize G_FPEXT and G_FPTRUNC
Mark G_FPEXT and G_FPTRUNC as legal or libcall, depending on hardware
support, but only for conversions between float and double.
Also add the necessary boilerplate so that the LegalizerHelper can
introduce the required libcalls. This also works only for float and
double, but isn't too difficult to extend when the need arises.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322651
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Ivan A. Kosarev [Wed, 17 Jan 2018 13:29:54 +0000 (13:29 +0000)]
[Transforms] Support making mutable versions of new-format TBAA access tags
Differential Revision: https://reviews.llvm.org/D41565
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322650
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Benjamin Kramer [Wed, 17 Jan 2018 13:01:06 +0000 (13:01 +0000)]
[X86] Don't mutate shuffle arguments after early-out for AVX512
The match* functions have the annoying behavior of modifying its inputs.
Save and restore the inputs, just in case the early out for AVX512 is
hit. This is still not great and its only a matter of time this kind of
bug happens again, but I couldn't come up with a better pattern without
rewriting significant chunks of this code. Fixes PR35977.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322644
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Benjamin Kramer [Wed, 17 Jan 2018 13:00:58 +0000 (13:00 +0000)]
[X86] Constify DebugLoc parameters. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322643
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Hiroshi Inoue [Wed, 17 Jan 2018 12:29:38 +0000 (12:29 +0000)]
[NFC] fix trivial typos in comments
"the the" -> "the"
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322636
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Pavel Labath [Wed, 17 Jan 2018 11:52:13 +0000 (11:52 +0000)]
Don't emit apple accelerator tables on non-darwin targets
Summary:
Currently -glldb turns on emission of apple tables on all targets, but
lldb is only really capable of consuming them on darwin. Furthermore,
making lldb consume these tables is not straight-forward because of the
differences in how the debug info is distributed on darwin vs. elf
targets.
The darwin debug model assumes that the debug info (along with
accelerator tables) will either remain in the .o files or it will be
linked into a dsym bundle by a linker that knows how to merge these
tables. In the elf world, all present linkers will simply concatenate
these accelerator tables into the shared object. Since the tables are
not self-terminating, this renders the tables unusable, as the debugger
cannot pry the individual tables apart anymore.
It might theoretically be possible to make the tables work with split
dwarf, as that is somewhat similar to the apple .o model, but
unfortunately right now the combination of -glldb and -gsplit-dwarf
produces broken object files.
Until these issues are resolved there is no point in emitting the apple
tables for these targets. At best, it wastes space; at worst, it breaks
compilation and prevents the user from getting other benefits of -glldb.
Reviewers: probinson, aprantl, dblaikie
Subscribers: emaste, dim, llvm-commits, JDevlieghere
Differential Revision: https://reviews.llvm.org/D41986
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322633
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Pavel Labath [Wed, 17 Jan 2018 11:11:53 +0000 (11:11 +0000)]
Rewrite debugger tuning test case to not depend on apple sections
Summary:
In a follow-up commit I'll change the rules for emission of accelerator
tables, which means we won't be able to use them as a litmus test for
the debugger tuning options. Instead of sections, I base the test on the
presence/absence of some debug info attributes and opcodes:
LLDB - prefers DW_OP_form_tls_address and uses DW_AT_APPLE_optimized
GDB - prefers DW_OP_GNU_push_tls_address and does not use the optimized
attribute
SCE - prefers DW_OP_form_tls_address and does not use the optimized
attribute
Reviewers: probinson, aprantl, dblaikie
Subscribers: JDevlieghere, llvm-commits
Differential Revision: https://reviews.llvm.org/D41985
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322630
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Javed Absar [Wed, 17 Jan 2018 11:03:06 +0000 (11:03 +0000)]
[SCEV] fix typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322629
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Simon Pilgrim [Wed, 17 Jan 2018 10:56:54 +0000 (10:56 +0000)]
[X86][AVX] Add extra 'interleaved+lanepermute' shuffle test
Possible missed opportunity to use 64-bit lane permute on AVX1 in lowerShuffleAsRepeatedMaskAndLanePermute
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322628
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George Rimar [Wed, 17 Jan 2018 10:33:05 +0000 (10:33 +0000)]
[ThinLTO] - Remove code duplication. NFC.
Refactors 3 copies of isExpected.
Splitted from D42107.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322627
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Andrew V. Tischenko [Wed, 17 Jan 2018 10:12:06 +0000 (10:12 +0000)]
Allow usage of X86-prefixes as separate instrs.
Differential Revision: https://reviews.llvm.org/D42102
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322623
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Sean Eveson [Wed, 17 Jan 2018 09:01:29 +0000 (09:01 +0000)]
[MC] Fix -stack-size-section on ARM
Change symbol values in the stack_size section from being 8 bytes, to being a target dependent size.
Differential Revision: https://reviews.llvm.org/D42108
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322619
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Craig Topper [Wed, 17 Jan 2018 03:58:21 +0000 (03:58 +0000)]
[X86] In LowerBUILD_VECTOR, rename ExtVT to EltVT so it makes sense.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322616
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Craig Topper [Wed, 17 Jan 2018 03:50:21 +0000 (03:50 +0000)]
[X86] Remove duplicate lines from scheduler models. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322615
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Aaron Smith [Wed, 17 Jan 2018 03:48:07 +0000 (03:48 +0000)]
[pdbutil] Replace 0 byte PDB input with correct version to fix failing unit test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322614
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George Burgess IV [Wed, 17 Jan 2018 03:12:06 +0000 (03:12 +0000)]
[Support] Return an enum instead of an unsigned; NFC.
We seem to be (logically) returning ArchExtKinds here in all cases, so
the return type should reflect that.
The static_cast is necessary because `A.ID` is actually an `unsigned`,
presumably since we use `decltype(A)` to represent extended attributes
for both ARM and AArch64, which use distinct `ArchExtKinds`.
We can't trivially make the same change for ARM, because one of the
values it returns is the bitwise-or of two `ARM::ArchExtKind`s.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322613
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Aaron Smith [Wed, 17 Jan 2018 01:49:01 +0000 (01:49 +0000)]
Fix build error - 'default label in switch which covers all enumeration values'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322610
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Aaron Smith [Wed, 17 Jan 2018 01:22:03 +0000 (01:22 +0000)]
Fix pretty printing the unspecified param of a variadic function
Summary:
- Fix a bug in PrettyBuiltinDumper that returns "void" as the name for
an unspecified builtin type. Since the unspecified param of a variadic
function is considered a builtin of unspecified type in PDBs, we set
"..." for its name.
- Provide a method to determine if a PDBSymbolFunc is variadic in
PrettyFunctionDumper since PDBSymbolFunc::getArgument() doesn't return the
last unspecified-type param.
- Add a pretty-func-dumper.test to test pretty dumping of variadic
functions.
Reviewers: zturner, llvm-commits
Reviewed By: zturner
Differential Revision: https://reviews.llvm.org/D41801
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322608
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Evgeniy Stepanov [Tue, 16 Jan 2018 23:15:08 +0000 (23:15 +0000)]
[hwasan] Rename sized load/store callbacks to be consistent with ASan.
Summary: __hwasan_load is now __hwasan_loadN.
Reviewers: kcc
Subscribers: hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D42138
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322601
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Simon Pilgrim [Tue, 16 Jan 2018 22:15:41 +0000 (22:15 +0000)]
[X86][BTVER2] Fix scheduling of VCMPSD/VCMPSS instructions
For some reason they don't have a trailing i like the packed equivalents.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322600
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Florian Hahn [Tue, 16 Jan 2018 22:13:15 +0000 (22:13 +0000)]
[CallSiteSplitting] Pass list of (BB, Conditions) pairs to splitCallSite.
This removes some duplication from splitCallSite and makes it easier to
add additional code dealing with each predecessor. It also allows us to
split for more than 2 predecessors, although that is not enabled for
now.
Reviewers: junbuml, mcrosier, davidxl, davide
Reviewed By: junbuml
Differential Revision: https://reviews.llvm.org/D41858
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322599
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Simon Pilgrim [Tue, 16 Jan 2018 22:08:43 +0000 (22:08 +0000)]
[X86][BTVER2] Use instrs instead of instregex for low match counts (PR35955)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322598
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Simon Pilgrim [Tue, 16 Jan 2018 21:44:48 +0000 (21:44 +0000)]
[X86][BTVER2] Use instrs instead of instregex for single use matches (PR35955)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322597
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Rui Ueyama [Tue, 16 Jan 2018 20:52:32 +0000 (20:52 +0000)]
Specify inline for isWhitespace in CommandLine.cpp
Patch by Takuto Ikuta.
In chromium's component build, there are many directive sections and
commandline parsing takes much time.
This patch is for speed up of lld in RelWithDebInfo build by forcing
inline heavily called isWhitespace function.
10 times link perf stats of blink_core.dll changed like below.
master:
TotalSeconds: 9.
8764878
TotalSeconds: 10.
1455242
TotalSeconds: 10.075279
TotalSeconds: 10.
3397347
TotalSeconds: 9.
8361665
TotalSeconds: 9.
9544441
TotalSeconds: 9.
8960686
TotalSeconds: 9.
8877865
TotalSeconds: 10.
0551879
TotalSeconds: 10.
0492254
Avg: 10.
01159047
with this patch:
TotalSeconds: 8.
8696762
TotalSeconds: 9.
1021585
TotalSeconds: 9.
0233893
TotalSeconds: 9.
1886175
TotalSeconds: 9.156954
TotalSeconds: 9.
0978564
TotalSeconds: 9.
1316824
TotalSeconds: 8.
8354606
TotalSeconds: 9.
2549431
TotalSeconds: 9.
4473085
Avg: 9.
11080465
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322595
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Lang Hames [Tue, 16 Jan 2018 20:39:51 +0000 (20:39 +0000)]
[ExecutionEngine] Rename JITSymbol::isStrongDefinition to isStrong.
For symmetry with isWeak, isCommon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322594
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Guozhi Wei [Tue, 16 Jan 2018 19:28:50 +0000 (19:28 +0000)]
[PPC] Add a new register XER aliased to CARRY
When "xer" is specified as clobbered register in inline assembler, clang can accept it, but llvm simply ignore it when lowered to machine instructions. It may cause problems later in scheduler.
This patch adds a new register XER aliased to CARRY, and adds it to register class CARRYRC. Now PPCTargetLowering::getRegForInlineAsmConstraint can return correct register number for inline asm constraint "{xer}", and scheduler behave correctly.
Differential Revision: https://reviews.llvm.org/D41967
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322591
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Francis Visoiu Mistrih [Tue, 16 Jan 2018 18:55:26 +0000 (18:55 +0000)]
[CodeGen] Skip some instructions that shouldn't affect shrink-wrapping
r320606 checked for MI.isMetaInstruction which skips all DBG_VALUEs.
This also skips IMPLICIT_DEFs and other instructions that may def / read
a register.
Differential Revision: https://reviews.llvm.org/D42119
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322584
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Volkan Keles [Tue, 16 Jan 2018 18:44:05 +0000 (18:44 +0000)]
[GlobalISel][TableGen] Add support for SDNodeXForm
Summary:
This patch adds CustomRenderer which renders the matched
operands to the specified instruction.
Targets can enable the matching of SDNodeXForm by adding
a definition that inherits from GICustomOperandRenderer and
GISDNodeXFormEquiv as follows.
def gi_imm8 : GICustomOperandRenderer<"renderImm8”>,
GISDNodeXFormEquiv<imm8_xform>;
Custom renderer functions should be of the form:
void render(MachineInstrBuilder &MIB, const MachineInstr &I);
Reviewers: dsanders, ab, rovka
Reviewed By: dsanders
Subscribers: kristof.beyls, javed.absar, llvm-commits, mgrang, qcolombet
Differential Revision: https://reviews.llvm.org/D42012
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322582
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Alexey Bataev [Tue, 16 Jan 2018 18:17:01 +0000 (18:17 +0000)]
[SLP] Fix for PR32164: Improve vectorization of reverse order of extract operations.
Summary: Sometimes vectorization of insertelement instructions with extractelement operands may produce an extra shuffle operation, if these operands are in the reverse order. Patch tries to improve this situation by the reordering of the operands to remove this extra shuffle operation.
Reviewers: mkuper, hfinkel, RKSimon, spatel
Subscribers: mzolotukhin, llvm-commits
Differential Revision: https://reviews.llvm.org/D33954
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322579
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Simon Pilgrim [Tue, 16 Jan 2018 17:01:31 +0000 (17:01 +0000)]
[X86][MMX] Accept UNDEF upper bits for MOVD GR32->MMX
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322574
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Petar Jovanovic [Tue, 16 Jan 2018 15:57:03 +0000 (15:57 +0000)]
[LiveDebugValues] update kill-after-spill test with target triple
Set target triple to "x86_64-unknown-linux-gnu".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322568
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Petar Jovanovic [Tue, 16 Jan 2018 14:46:05 +0000 (14:46 +0000)]
[LiveDebugValues] recognize spilled reg killed in instruction after spill
Current condition for spill instruction recognition in LiveDebugValues does
not recognize case when register is spilled and killed in next instruction.
Patch by Nikola Prica.
Differential Revision: https://reviews.llvm.org/D41226
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322554
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Simon Pilgrim [Tue, 16 Jan 2018 14:21:28 +0000 (14:21 +0000)]
[X86][MMX] Improve MMX constant generation
Extend the MMX zero code to take any constant with zero'd upper 32-bits
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322553
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Hiroshi Inoue [Tue, 16 Jan 2018 13:19:48 +0000 (13:19 +0000)]
[NFC] fix trivial typos in documents
"the the" -> "the"
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322552
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Gadi Haber [Tue, 16 Jan 2018 11:33:45 +0000 (11:33 +0000)]
[X86][I86,I186,I286,I386,I486,PPRO, MMX]: Adding full coverage of MC encoding for the I86, I186, I286, I386, I486, PPRO and MMX isa sets.<NFC>
NFC.
Adding MC regressions tests to cover the I86, I186, I286, I386, I486, PPRO and MMX isa sets.
This patch is part of a larger task to cover MC encoding of all X86 ISA Sets.
Started in revision: https://reviews.llvm.org/D39952
Reviewers: zvi, RKSimon, AndreiGrischenko, craig.topper
Differential Revision: https://reviews.llvm.org/D40879
Change-Id: I231a35861611bfd3d23c74cc59507373f021a629
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322544
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Jonas Devlieghere [Tue, 16 Jan 2018 11:17:57 +0000 (11:17 +0000)]
[DebugInfo] Unify dumping of address ranges
Summary:
This patch unifies the printing of address ranges as [0x0, 0x1).
rdar://
34822059
Reviewers: aprantl, dblaikie
Subscribers: mehdi_amini, llvm-commits
Differential Revision: https://reviews.llvm.org/D42056
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322543
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Francis Visoiu Mistrih [Tue, 16 Jan 2018 10:53:14 +0000 (10:53 +0000)]
[CodeGen] Remove special case of printing subRegIdx from MachineInstr::print
Support in MachineOperand has been added in r320209. No need to special
case this anymore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322542
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Francis Visoiu Mistrih [Tue, 16 Jan 2018 10:53:11 +0000 (10:53 +0000)]
[CodeGen][NFC] Correct case for printSubRegIdx
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322541
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Clement Courbet [Tue, 16 Jan 2018 09:11:20 +0000 (09:11 +0000)]
Add a value_type to ArrayRef.
Summary: Not sure this needs a review or not. Erring on the safe side.
Reviewers: dblaikie
Differential Revision: https://reviews.llvm.org/D41666
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322538
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Gadi Haber [Tue, 16 Jan 2018 08:50:29 +0000 (08:50 +0000)]
[X86][XSAVE]: Adding full coverage of MC encoding for the XSAVE isa sets.<NFC>
NFC.
Adding MC regressions tests to cover the XSAVE ISA sets.
This patch is part of a larger task to cover MC encoding of all X86 ISA Sets started in revision: https://reviews.llvm.org/D39952
Reviewers: zvi, RKSimon, AndreiGrischenko, craig.topper
Differential Revision: https://reviews.llvm.org/D41282
Change-Id: I325bf8f421f78c80179a04fc39033366759cbe45
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322537
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George Rimar [Tue, 16 Jan 2018 08:09:24 +0000 (08:09 +0000)]
[FileCheck] - Fix possible buffer out of bounds access when parsing --check-prefix.
FileCheck tool crashes when trying to parse --check-prefix argument if there is no any
data after it.
For example test like following would crash if there are no symbols and no EOL mark after `boom`:
# REQUIRES: x86
# RUN: <skipped few lines>
# RUN: llvm-readobj -t %t | FileCheck %s --check-prefix=boom
Patch fixes the issue.
Differential revision: https://reviews.llvm.org/D42057
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322536
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Yonghong Song [Tue, 16 Jan 2018 07:27:20 +0000 (07:27 +0000)]
[BPF] Mark pseudo insn patterns as isCodeGenOnly
These pseudos are not supposed to be visible to user.
This patch reduced the auto-generated instruction matcher. For example,
the following words are removed from keyword list of LLVM BPF assembler.
- MCK__35_, // '#'
- MCK__COLON_, // ':'
- MCK__63_, // '?'
- MCK_ADJCALLSTACKDOWN, // 'ADJCALLSTACKDOWN'
- MCK_ADJCALLSTACKUP, // 'ADJCALLSTACKUP'
- MCK_PSEUDO, // 'PSEUDO'
- MCK_Select, // 'Select'
Acked-by: Jakub Kicinski <jakub.kicinski@netronome.com>
Acked-by: Yonghong Song <yhs@fb.com>
Signed-off-by: Jiong Wang <jiong.wang@netronome.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322535
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Yonghong Song [Tue, 16 Jan 2018 07:27:19 +0000 (07:27 +0000)]
[BPF] Teach DAG2DAG AND elimination about load intrinsics
As commented on the existing code:
// The Reg operand should be a virtual register, which is defined
// outside the current basic block. DAG combiner has done a pretty
// good job in removing truncating inside a single basic block.
However, when the Reg operand comes from bpf_load_[byte | half | word]
intrinsics, the generic optimizer doesn't understand their results are
zero extended, so these single basic block elimination opportunities were
missed.
Acked-by: Jakub Kicinski <jakub.kicinski@netronome.com>
Acked-by: Yonghong Song <yhs@fb.com>
Signed-off-by: Jiong Wang <jiong.wang@netronome.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322534
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Hiroshi Inoue [Tue, 16 Jan 2018 06:23:05 +0000 (06:23 +0000)]
[SROA] fix assetion failure
This patch fixes the assertion failure in SROA reported in PR35657.
PR35657 reports the assertion failure due to r319522 (splitting for non-whole-alloca slices), but this problem can happen even without r319522.
The problem exists in a check for reusing an existing alloca when rewriting partitions. As the original comment said, we can reuse the existing alloca if the new alloca has the same type and offset with the existing one. But the code checks only type of the alloca and then check the offset using an assert.
In a corner case with out-of-bounds access (e.g. @PR35657 function added in unit test), it is possible that the two allocas have the same type but different offsets.
This patch makes the check of the offset in the if condition, and re-enables the splitting for non-whole-alloca slices.
Differential Revision: https://reviews.llvm.org/D41981
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322533
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Craig Topper [Tue, 16 Jan 2018 06:07:16 +0000 (06:07 +0000)]
[X86] Revisit the fix I made years ago to make 'xchgl %eax, %eax' not encode using the 0x90 encoding in 64-bit mode.
Prior to this we had a separate instruction and register class that excluded eax to prevent matching the instruction that would encode with 0x90.
This patch changes this to just use an InstAlias to force xchgl %eax, %eax to use XCHG32rr instruction in 64-bit mode. This gets rid of the separate instruction and register class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322532
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Craig Topper [Tue, 16 Jan 2018 06:07:14 +0000 (06:07 +0000)]
[X86] Make 'xchgq %rax, %rax' an alias for the 0x90 nop encoding to match gas.
Previously we encoded it as 0x48 0x90.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322531
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Simon Pilgrim [Mon, 15 Jan 2018 22:40:06 +0000 (22:40 +0000)]
Avoid Wparentheses warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322526
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Simon Pilgrim [Mon, 15 Jan 2018 22:32:40 +0000 (22:32 +0000)]
[X86][MMX] Add support for MMX zero vector creation
As mentioned on PR35869, (and came up recently on D41517) we don't create a MMX zero register via the PXOR but instead perform a spill to stack from a XMM zero register.
This patch adds support for direct MMX zero vector creation and should make it easier to add better constant vector creation in the future as well.
Differential Revision: https://reviews.llvm.org/D41908
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322525
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Simon Pilgrim [Mon, 15 Jan 2018 22:18:45 +0000 (22:18 +0000)]
[X86][SSE] Add custom execution domain fixing for BLENDPD/BLENDPS/PBLENDD/PBLENDW (PR34873)
Add support for custom execution domain fixing and implement support for BLENDPD/BLENDPS/PBLENDD/PBLENDW.
Differential Revision: https://reviews.llvm.org/D42042
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322524
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Sanjay Patel [Mon, 15 Jan 2018 21:57:41 +0000 (21:57 +0000)]
[x86] add tests to show missed constant shrinking (PR35907); NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322523
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Sanjay Patel [Mon, 15 Jan 2018 21:32:39 +0000 (21:32 +0000)]
[x86] regenerate test checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322522
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Sanjay Patel [Mon, 15 Jan 2018 21:28:52 +0000 (21:28 +0000)]
[x86] regenerate test checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322521
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Brian Gesiak [Mon, 15 Jan 2018 21:23:32 +0000 (21:23 +0000)]
[docs] Only LLVM IR bitstreams begin with 'BC'
Summary:
The LLVM Bitcode File Format documentation states that all bitstreams
begin with the magic number 'BC', and that generic bitstream analyzer
tools may check for this number in order to determine whether the
stream is a bitstream.
However, in practice:
* Only LLVM IR bitcode begins with 'BC'. Other bitstreams -- Clang
AST files and precompiled headers, Clang serialized diagnostics,
Swift modules -- do not start with 'BC'. A tool that actually checked
for 'BC' would only be able to recognize LLVM IR.
* The `llvm-bcanalyzer`, arguably the most used generic bitstream
analyzer tool, does not check for a magic number 'BC' (except to
determine whether the file is LLVM IR).
Update the bitcode format documentation to make it clear that not all
bitstreams begin with 'BC', and that tools should not rely on that
particular magic number value.
Test Plan:
Build the `docs-llvm-html` target and confirm the changes render in
a Safari web browser.
Reviewers: harlanhaskins, eugenis, mehdi_amini, pcc, angerman
Reviewed By: angerman
Subscribers: angerman, llvm-commits
Differential Revision: https://reviews.llvm.org/D42002
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322520
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Sanjay Patel [Mon, 15 Jan 2018 21:22:46 +0000 (21:22 +0000)]
[x86] regenerate test checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322519
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Craig Topper [Mon, 15 Jan 2018 20:33:53 +0000 (20:33 +0000)]
[X86] Use MVT::getVectorVT instead of EVT::getVectorVT when splitting 256/512 bit build_vectors. NFC
We must be creating a legal type here which means it can be an MVT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322512
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Craig Topper [Mon, 15 Jan 2018 20:33:52 +0000 (20:33 +0000)]
[X86] Generalize some code in LowerBUILD_VECTOR. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322511
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Craig Topper [Mon, 15 Jan 2018 20:33:50 +0000 (20:33 +0000)]
[X86] Remove unnecessary if statement from LowerBUILD_VECTOR. NFCI
We were checking for 128, 256, or 512 bit vectors, but those are the only types that can get here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322510
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Dan Gohman [Mon, 15 Jan 2018 20:08:14 +0000 (20:08 +0000)]
[WebAssembly] Update README.txt.
Describe more of the current status, mention Rust as another easy
way to use this backend, and add more documentation links.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322508
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Stanislav Mekhanoshin [Mon, 15 Jan 2018 18:49:15 +0000 (18:49 +0000)]
[AMDGPU] Add HW_REG_SH_MEM_BASES symbolic name for s_getreg_b32
Differential Revision: https://reviews.llvm.org/D41617
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322500
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Krzysztof Parzyszek [Mon, 15 Jan 2018 18:43:55 +0000 (18:43 +0000)]
[Hexagon] Implement signed and unsigned multiply-high for vectors
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322499
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Krzysztof Parzyszek [Mon, 15 Jan 2018 18:33:33 +0000 (18:33 +0000)]
[Hexagon] Rewrite LowerVECTOR_SHUFFLE for 32-/64-bit vectors
The old implementation was not always correct. The new one recognizes
more shuffles that match specific instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322498
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Stanislav Mekhanoshin [Mon, 15 Jan 2018 17:55:35 +0000 (17:55 +0000)]
[AMDGPU] Copy impdefs from pseudo to real instructions
In some cases we do not copy implicit defs from pseudo to real
VOP instructions. It has no visible impact at the moment thus no
tests are affected or added.
Differential Revision: https://reviews.llvm.org/D41783
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322496
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Simon Pilgrim [Mon, 15 Jan 2018 17:55:21 +0000 (17:55 +0000)]
[X86] Fix typos in WriteVMOVNTDQSt and WriteVMOVNTPYSt pattern names. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322495
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Jan Korous [Mon, 15 Jan 2018 17:11:22 +0000 (17:11 +0000)]
[docs] Fix mention of GCC frontend
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322491
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Dan Gohman [Mon, 15 Jan 2018 17:06:23 +0000 (17:06 +0000)]
[WebAssembly] Make WasmObjectWriter's destructor public; NFC
This fixes the FIXME introduced in r315327.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322490
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Jonas Paulsson [Mon, 15 Jan 2018 15:41:26 +0000 (15:41 +0000)]
[SystemZ] Check for legality before doing LOAD AND TEST transformations.
Since a load and test instruction treat its operands as signed, it can only
replace a logical compare for EQ/NE uses.
Review: Ulrich Weigand
https://bugs.llvm.org/show_bug.cgi?id=35662
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322488
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Sam McCall [Mon, 15 Jan 2018 14:43:04 +0000 (14:43 +0000)]
Allow function_ref(nullptr) like std::function, since it's nullable already
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322487
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Clement Courbet [Mon, 15 Jan 2018 14:24:07 +0000 (14:24 +0000)]
[X86] Add missing predicates for VRNDSCALES{D,S}{m,r}
Summary: This is similar to https://reviews.llvm.org/D41983.
Reviewers: gchatelet
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D42069
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322486
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Andrew V. Tischenko [Mon, 15 Jan 2018 14:21:11 +0000 (14:21 +0000)]
Update BTVER2 sched numbers for some AVX instructions (xmm version).
Differential Revision: https://reviews.llvm.org/D40067
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322485
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Clement Courbet [Mon, 15 Jan 2018 13:37:05 +0000 (13:37 +0000)]
[X86]Add missing predicates for VMOVDQUYrm,VMOVDQUYmr.
Summary:
Due to missing parentheses.
This is similar to https://reviews.llvm.org/D41983.
Reviewers: gchatelet
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D42062
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322483
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Sander de Smalen [Mon, 15 Jan 2018 12:47:17 +0000 (12:47 +0000)]
[AArch64][AsmParser] Cleanup isSImm7s4, isSImm7s8, (etc) functions.
Reviewers: fhahn, rengolin, t.p.northover, echristo, olista01, samparker
Reviewed By: fhahn, samparker
Subscribers: samparker, aemerson, javed.absar, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D41899
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322481
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Clement Courbet [Mon, 15 Jan 2018 12:05:33 +0000 (12:05 +0000)]
[X86] Fix missing predicates HasAVX512 Predicates in avx512_sqrt_scalar.
Summary:
For example, VSQRTSDZr and VSQRTSSZr were missing the predicate.
Also fix braces indentation and braces for consistency.
Reviewers: craig.topper, RKSimon
Suscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D41983
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322478
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Pavel Labath [Mon, 15 Jan 2018 11:03:30 +0000 (11:03 +0000)]
[Support] Remove MemoryBuffer::getNewMemBuffer
all callers have been switched the the Writable version (which does not
require const_casting to be useful).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322475
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Benjamin Kramer [Mon, 15 Jan 2018 10:57:24 +0000 (10:57 +0000)]
Revert "[DAG] Elide overlapping stores"
This reverts commit r322085. Internal PPC testing is still showing the
same symptoms as when this patch landed the last time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322474
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Andrei Elovikov [Mon, 15 Jan 2018 10:56:07 +0000 (10:56 +0000)]
[LV] Don't call recordVectorLoopValueForInductionCast for newly-created IV from a trunc.
Summary:
This method is supposed to be called for IVs that have casts in their use-def
chains that are completely ignored after vectorization under PSE. However, for
truncates of such IVs the same InductionDescriptor is used during
creation/widening of both original IV based on PHINode and new IV based on
TruncInst.
This leads to unintended second call to recordVectorLoopValueForInductionCast
with a VectorLoopVal set to the newly created IV for a trunc and causes an
assert due to attempt to store new information for already existing entry in the
map. This is wrong and should not be done.
Fixes PR35773.
Reviewers: dorit, Ayal, mssimpso
Reviewed By: dorit
Subscribers: RKSimon, dim, dcaballe, hsaito, llvm-commits, hiraditya
Differential Revision: https://reviews.llvm.org/D41913
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322473
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Gadi Haber [Mon, 15 Jan 2018 09:39:08 +0000 (09:39 +0000)]
[X86][AVX512F_512]: Adding full coverage of MC encoding for the AVX512F 512 bits isa sets.<NFC>
NFC.
Adding MC regressions tests to cover the AVX512F_512 isa sets both 32 and 64 bit.
This patch is part of a larger task to cover MC encoding of all X86 ISA Sets.
started in revision: https://reviews.llvm.org/D39952
Reviewers: zvi, craig.topper, RKSimon, AndreiGrischenko
Differential Revision: https://reviews.llvm.org/D41172
Change-Id: I46aa33dd967d63d33f67d1988ad42d8df2081e39
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322471
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Mikael Holmen [Mon, 15 Jan 2018 07:05:51 +0000 (07:05 +0000)]
[GlobalsAA] Don't let dbg intrinsics affect analysis result
Summary:
This fixes PR35899.
Debug info intrinsics shouldn't affect code generation so ignore them
in GlobalsAA.
Reviewers: hfinkel, aprantl
Reviewed By: aprantl
Subscribers: aprantl, llvm-commits
Differential Revision: https://reviews.llvm.org/D41984
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322470
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Max Kazantsev [Mon, 15 Jan 2018 05:44:43 +0000 (05:44 +0000)]
[NFC] Fix comment to adjust to reality
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322468
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Davide Italiano [Mon, 15 Jan 2018 01:40:18 +0000 (01:40 +0000)]
[BasicAA] Stop crashing when dealing with pointers > 64 bits.
An alternative (and probably better) fix would be that of
making `Scale` an APInt, and there's a patch floating around
to do this. As we're still discussing it, at least stop crashing
in the meanwhile (added bonus, we now have a regression test for
this situation).
Fixes PR35843.
Thanks to Eli for suggesting the fix and Simon for reporting and
reducing the bug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322467
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Amara Emerson [Mon, 15 Jan 2018 00:44:20 +0000 (00:44 +0000)]
[GlobalISel][Legalizer] Convert some typedefs to using. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322466
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Simon Pilgrim [Sun, 14 Jan 2018 21:59:43 +0000 (21:59 +0000)]
[X86][SSE] Tag PR21137 test case
The test was added ages ago, but we didn't comment where it came from.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322465
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Craig Topper [Sun, 14 Jan 2018 20:53:49 +0000 (20:53 +0000)]
[X86] Add test cases for D41794.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322464
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Simon Pilgrim [Sun, 14 Jan 2018 19:57:50 +0000 (19:57 +0000)]
[X86][SSE] Add PR22391 test case
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322463
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Craig Topper [Sun, 14 Jan 2018 19:24:10 +0000 (19:24 +0000)]
[X86] Autoupgrade kunpck intrinsics using vector operations instead of scalar operations
Summary: This patch changes the kunpck intrinsic autoupgrade to use vXi1 shufflevector operations to perform vector extracts and concats. This more closely matches the definition of the kunpck instructions. Currently we rely on a DAG combine to turn the scalar shift/and/or code into a concat vectors operation. By doing it in the IR we get this for free.
Reviewers: spatel, RKSimon, zvi, jina.nahias
Reviewed By: RKSimon
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D42018
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322462
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Simon Pilgrim [Sun, 14 Jan 2018 19:07:41 +0000 (19:07 +0000)]
[X86] Regenerate fp128 test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322460
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Simon Pilgrim [Sun, 14 Jan 2018 18:50:34 +0000 (18:50 +0000)]
[X86][SSE] Support combining MOVLHPS undef inputs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322459
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Simon Pilgrim [Sun, 14 Jan 2018 18:38:21 +0000 (18:38 +0000)]
[X86][SSE] Add v2f64 3u shuffle test
Shows a missed opportunity to remove a unnecessary move compared to 31 shuffle mask.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322458
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Sanjay Patel [Sun, 14 Jan 2018 17:47:40 +0000 (17:47 +0000)]
[x86] auto-generate complete checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322457
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Sanjay Patel [Sun, 14 Jan 2018 15:58:18 +0000 (15:58 +0000)]
[InstSimplify] fix code comments; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322456
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Craig Topper [Sun, 14 Jan 2018 08:11:36 +0000 (08:11 +0000)]
[X86] Use ISD::TRUNCATE instead of X86ISD::VTRUNC when input and output types have the same number of elements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322455
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Craig Topper [Sun, 14 Jan 2018 08:11:33 +0000 (08:11 +0000)]
[X86] Add X86ISD::VTRUNC to computeKnownBitsForTargetNode.
We have to take special care to avoid the cases where the result of the truncate would be padded with zero elements.
Ideally we'd just use ISD::TRUNCATE for these cases instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322454
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Craig Topper [Sun, 14 Jan 2018 02:05:51 +0000 (02:05 +0000)]
[X86] Improve legalization of vXi16/vXi8 selects.
Extend vXi1 conditions of vXi8/vXi16 selects even before type legalization gets a chance to split wide vectors. Previously we would only extend 128 and 256 bit vectors. But if we start with a 512 bit vector or wider that needs to be split we wouldn't extend until after the split had taken place. By extending early we improve the results of type legalization.
Don't widen condition of 128/256 bit vXi16/vXi8 selects when we have BWI but not VLX. We can still use a mask register by widening the select to 512-bits instead. This is similar to what we do for compares already.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@322450
91177308-0d34-0410-b5e6-
96231b3b80d8