OSDN Git Service
Amaury Sechet [Wed, 13 Dec 2017 18:04:57 +0000 (18:04 +0000)]
Regenerate test-shrink.ll test results. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320602
91177308-0d34-0410-b5e6-
96231b3b80d8
Jonas Devlieghere [Wed, 13 Dec 2017 18:03:04 +0000 (18:03 +0000)]
[dsymutil] Re-enable threading
Threading was disabled in r317263 because it broke a test in combination
with `-DLLVM_ENABLE_THREADS=OFF`. This was because a ThreadPool warning
was piped to llvm-dwarfdump which was expecting to read an object from
stdin.
This patch re-enables threading and fixes the offending test.
Unfortunately this required more than just moving the ThreadPool out of
the for loop because of the TempFile refactoring that took place in the
meantime.
Differential revision: https://reviews.llvm.org/D41180
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320601
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Wed, 13 Dec 2017 17:50:40 +0000 (17:50 +0000)]
[X86] Add RET/RETF schedule tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320600
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Wed, 13 Dec 2017 17:42:25 +0000 (17:42 +0000)]
[X86] Add POP/PUSH schedule tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320598
91177308-0d34-0410-b5e6-
96231b3b80d8
Brian M. Rzycki [Wed, 13 Dec 2017 16:56:18 +0000 (16:56 +0000)]
[Function] Remove trailing end-of-line whitespace. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320595
91177308-0d34-0410-b5e6-
96231b3b80d8
Nemanja Ivanovic [Wed, 13 Dec 2017 15:28:01 +0000 (15:28 +0000)]
Fix link failure on one build bot introduced by r320584.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320589
91177308-0d34-0410-b5e6-
96231b3b80d8
Galina Kistanova [Wed, 13 Dec 2017 15:26:27 +0000 (15:26 +0000)]
Reverted r320229. It broke tests on builder llvm-clang-x86_64-expensive-checks-win.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320588
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Wed, 13 Dec 2017 15:12:02 +0000 (15:12 +0000)]
[X86] Add PREFETCH schedule tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320587
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Wed, 13 Dec 2017 15:02:10 +0000 (15:02 +0000)]
[X86] Add XCHG schedule tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320586
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Wed, 13 Dec 2017 14:51:06 +0000 (14:51 +0000)]
[X86] Add MOVNTI schedule tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320585
91177308-0d34-0410-b5e6-
96231b3b80d8
Nemanja Ivanovic [Wed, 13 Dec 2017 14:47:35 +0000 (14:47 +0000)]
[PowerPC] MachineSSA pass to reduce the number of CR-logical operations
The initial implementation of an MI SSA pass to reduce cr-logical operations.
Currently, the only operations handled by the pass are binary operations where
both CR-inputs come from the same block and the single use is a conditional
branch (also in the same block).
Committing this off by default to allow for a period of field testing. Will
enable it by default in a follow-up patch soon.
Differential Revision: https://reviews.llvm.org/D30431
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320584
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Wed, 13 Dec 2017 14:46:33 +0000 (14:46 +0000)]
[X86] Add ENTER/LEAVE schedule tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320583
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Wed, 13 Dec 2017 14:24:04 +0000 (14:24 +0000)]
[X86] Add IMUL schedule tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320582
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Wed, 13 Dec 2017 14:22:04 +0000 (14:22 +0000)]
[X86] Add RDMSR/WRMSR, RDPMC + RDTSC/RDTSCP schedule tests
Add missing RDTSCP itinerary
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320581
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Wed, 13 Dec 2017 13:54:45 +0000 (13:54 +0000)]
[X86] Add ARPL/BOUND schedule tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320580
91177308-0d34-0410-b5e6-
96231b3b80d8
Alex Bradbury [Wed, 13 Dec 2017 12:46:55 +0000 (12:46 +0000)]
[RISCV] Define sfence.vma InstAliases to match the GNU RISC-V tools
Unfortunately these aren't defined explicitly in the privileged spec, but the
GNU assembler does accept `sfence.vma` and `sfence.vma rs` as well as the
usual `sfence.vma rs, rt`.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320575
91177308-0d34-0410-b5e6-
96231b3b80d8
Igor Laevsky [Wed, 13 Dec 2017 11:49:04 +0000 (11:49 +0000)]
[FuzzMutate] Only generate loads and stores to the first class sized types
Differential Revision: https://reviews.llvm.org/D41109
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320573
91177308-0d34-0410-b5e6-
96231b3b80d8
Igor Laevsky [Wed, 13 Dec 2017 11:47:35 +0000 (11:47 +0000)]
[FuzzMutate] Avoid zero sized aggregates
Differential Revision: https://reviews.llvm.org/D41110
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320572
91177308-0d34-0410-b5e6-
96231b3b80d8
Igor Laevsky [Wed, 13 Dec 2017 11:45:53 +0000 (11:45 +0000)]
[FuzzMutate] Correctly split landingpad blocks
Differential Revision: https://reviews.llvm.org/D41112
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320571
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Wed, 13 Dec 2017 11:43:14 +0000 (11:43 +0000)]
[X86][SSE] MOVMSK only uses the sign bit from each vector element
Pass the input vector through SimplifyDemandedBits as we only need the sign bit from each vector element of MOVMSK
We'd probably get more hits if SimplifyDemandedBits was better at handling vectors...
Differential Revision: https://reviews.llvm.org/D41119
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320570
91177308-0d34-0410-b5e6-
96231b3b80d8
Alex Bradbury [Wed, 13 Dec 2017 11:37:19 +0000 (11:37 +0000)]
[RISCV] Implement floating point assembler pseudo instructions
Adds the assembler aliases for the floating point instructions
which can be mapped to a single canonical instruction. The missing
pseudo instructions (flw, fld, fsw, fsd) are marked as TODO. Other
things, like for example PCREL_LO, have to be implemented first.
This patch builds upon D40902.
Differential Revision: https://reviews.llvm.org/D41071
Patch by Mario Werner.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320569
91177308-0d34-0410-b5e6-
96231b3b80d8
Igor Laevsky [Wed, 13 Dec 2017 11:21:18 +0000 (11:21 +0000)]
Reintroduce r320049, r320014 and r319894.
OpenGL issues should be fixed by now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320568
91177308-0d34-0410-b5e6-
96231b3b80d8
Roger Ferrer Ibanez [Wed, 13 Dec 2017 10:45:21 +0000 (10:45 +0000)]
[DAG] Promote ADDCARRY / SUBCARRY
Add missing case that was not implemented yet.
Differential Revision: https://reviews.llvm.org/D38942
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320567
91177308-0d34-0410-b5e6-
96231b3b80d8
Francis Visoiu Mistrih [Wed, 13 Dec 2017 10:30:59 +0000 (10:30 +0000)]
[CodeGen] Print jump-table index operands as %jump-table.0 in both MIR and debug output
Work towards the unification of MIR and debug output by printing `%jump-table.0` instead of `<jt#0>`.
Only debug syntax is affected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320566
91177308-0d34-0410-b5e6-
96231b3b80d8
Francis Visoiu Mistrih [Wed, 13 Dec 2017 10:30:51 +0000 (10:30 +0000)]
[CodeGen] Print target index operands as target-index(target-specific) + 8 in both MIR and debug output
Work towards the unification of MIR and debug output by printing `target-index(target-specific) + 8` instead of `<ti#0+8>` and `target-index(target-specific) + 8` instead of `<ti#0-8>`.
Only debug syntax is affected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320565
91177308-0d34-0410-b5e6-
96231b3b80d8
Francis Visoiu Mistrih [Wed, 13 Dec 2017 10:30:45 +0000 (10:30 +0000)]
[CodeGen] Print constant pool index operands as %const.0 + 8 in both MIR and debug output
Work towards the unification of MIR and debug output by printing
`%const.0 + 8` instead of `<cp#0+8>` and `%const.0 - 8` instead of
`<cp#0-8>`.
Only debug syntax is affected.
Differential Revision: https://reviews.llvm.org/D41116
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320564
91177308-0d34-0410-b5e6-
96231b3b80d8
Stefan Maksimovic [Wed, 13 Dec 2017 10:13:35 +0000 (10:13 +0000)]
[mips] Provide additional DSP bitconvert patterns
Previously, v2i16 -> f32 bitcast could not be matched.
Add patterns to support matching this and similar types of bitcasts.
Differential revision: https://reviews.llvm.org/D40959
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320562
91177308-0d34-0410-b5e6-
96231b3b80d8
Pavel Labath [Wed, 13 Dec 2017 10:00:38 +0000 (10:00 +0000)]
[Testing/Support] Make the HasValue matcher composable
Summary:
This makes it possible to run an arbitrary matcher on the value
contained within the Expected<T> object.
To do this, I've needed to fully spell out the matcher, instead of using
the shorthand MATCHER_P macro.
The slight gotcha here is that standard template deduction will fail if
one tries to match HasValue(47) against an Expected<int &> -- the
workaround is to use HasValue(testing::Eq(47)).
The explanations produced by this matcher have changed a bit, since now
we delegate to the nested matcher to print the value. Since these don't
put quotes around the value, I've changed our PrintTo methods to match.
Reviewers: zturner
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D41065
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320561
91177308-0d34-0410-b5e6-
96231b3b80d8
Alex Bradbury [Wed, 13 Dec 2017 09:57:25 +0000 (09:57 +0000)]
[RISCV][NFC] Update RISCVInstrInfoC.td to match usual instruction naming convention
When an instruction mnemonic contains a '.', we usually name the instruction
with a _ in that place. e.g. fadd.s -> FADD_S.
This patch updates RISCVInstrInfoC.td to do the same, e.g. c.nop -> C_NOP.
Also includes some minor formatting changes in RISCVInstrInfoC.td to better
align it with the formatting conventions in the rest of the backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320560
91177308-0d34-0410-b5e6-
96231b3b80d8
Alex Bradbury [Wed, 13 Dec 2017 09:41:21 +0000 (09:41 +0000)]
[RISCV][NFC] Put isSImm6 and simm6 td definition in correct sorted position
We sort these helper functions and td definitions by bit width. simm6 was
previously out-of-order with respect to the others.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320559
91177308-0d34-0410-b5e6-
96231b3b80d8
Alex Bradbury [Wed, 13 Dec 2017 09:32:55 +0000 (09:32 +0000)]
[RISCV] MC layer support for the remaining RVC instructions
Differential Revision: https://reviews.llvm.org/D40003
Patch by Shiva Chen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320558
91177308-0d34-0410-b5e6-
96231b3b80d8
Gadi Haber [Wed, 13 Dec 2017 09:13:53 +0000 (09:13 +0000)]
[X86][BMI]: Adding full coverage of MC encoding for the BMI isa set.<NFC>
NFC.
Adding MC regressions tests to cover the BMI1 and BMI2 ISA sets both 32 and 64 bit.
This patch is part of a larger task to cover MC encoding of all X86 ISA Sets.
started in revision: https://reviews.llvm.org/D39952
Reviewers: zvi, craig.topper, m_zuckerman, RKSimon
Differential Revision: https://reviews.llvm.org/D41106
Change-Id: I033ce137b5b82d36e1e601cd5e0534637b43a4a9
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320557
91177308-0d34-0410-b5e6-
96231b3b80d8
Alex Bradbury [Wed, 13 Dec 2017 09:02:13 +0000 (09:02 +0000)]
[cmake] Fix host tools build in when LLVM_EXPERIMENTAL_TARGETS_TO_BUILD is set
r320413 triggered cmake configure failures when building with
-DLLVM_OPTIMIZED_TABLEGEN=True and with LLVM_EXPERIMENTAL_TARGETS_TO_BUILD set
(e.g. to RISCV). This is because that patch moved to passing through
LLVM_TARGETS_TO_BUILD, and at that point LLVM_EXPERIMENTAL_TARGETS_TO_BUILD
has been merged in to it. LLVM_EXPERIMENTAL_TARGETS_TO_BUILD must be also be
passed through to avoid errors like below:
-- Constructing LLVMBuild project information
CMake Error at CMakeLists.txt:682 (message):
The target `RISCV' does not exist.
It should be one of
AArch64;AMDGPU;ARM;BPF;Hexagon;Lanai;Mips;MSP430;NVPTX;PowerPC;Sparc;SystemZ;X86;XCore
-- Configuring incomplete, errors occurred!
See the thread
http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-
20171211/509225.html
for discussion of this fix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320556
91177308-0d34-0410-b5e6-
96231b3b80d8
Serguei Katkov [Wed, 13 Dec 2017 07:39:35 +0000 (07:39 +0000)]
Revert "[CGP] Enable select in complex addr mode"
Causes: Assertion `ScaledReg == nullptr' failed.
This actually a revert of rL320551.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320553
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Wed, 13 Dec 2017 07:26:17 +0000 (07:26 +0000)]
[Targets] Don't automatically include the scheduler class enum from *GenInstrInfo.inc with GET_INSTRINFO_ENUM. Make targets request is separately.
Most of the targets don't need the scheduler class enum.
I have an X86 scheduler model change that causes some names in the enum to become about 18000 characters long. This is because using instregex in scheduler models causes the scheduler class to get named with every instruction that matches the regex concatenated together. MSVC has a limit of 4096 characters for an identifier name. Rather than trying to come up with way to reduce the name length, I'm just going to sidestep the problem by not including the enum in X86.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320552
91177308-0d34-0410-b5e6-
96231b3b80d8
Serguei Katkov [Wed, 13 Dec 2017 06:57:59 +0000 (06:57 +0000)]
[CGP] Enable select in complex addr mode
Enable select instruction handling in complex addr modes.
Reviewers: john.brawn, reames, aaboud
Reviewed By: reames
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D40634
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320551
91177308-0d34-0410-b5e6-
96231b3b80d8
Dean Michael Berris [Wed, 13 Dec 2017 06:37:13 +0000 (06:37 +0000)]
[XRay][compiler-rt] Reduce XRay log spam
This change makes XRay print the log file output only when the verbosity
level is higher than 0. It reduces the log spam in the default case when
we want XRay running silently, except when there are actual
fatal/serious errors.
We also update the documentation to show how to get the information
after the change to the default behaviour.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320550
91177308-0d34-0410-b5e6-
96231b3b80d8
Serguei Katkov [Wed, 13 Dec 2017 05:32:46 +0000 (05:32 +0000)]
[NFC] Refactor SafepointIRVerifier
Now two classes are responsible for verification: one of them can track GC
pointers and know whether a pointer is relocated or not and another based on
that information can verify uses of GC pointers.
Patch Author: Daniil Suchkov
Reviewers: mkazantsev, anna, apilipenko
Reviewed By: mkazantsev
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D40885
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320549
91177308-0d34-0410-b5e6-
96231b3b80d8
Mohammad Shahid [Wed, 13 Dec 2017 03:08:29 +0000 (03:08 +0000)]
[SLP] Vectorize jumbled memory loads.
Summary:
This patch tries to vectorize loads of consecutive memory accesses, accessed
in non-consecutive or jumbled way. An earlier attempt was made with patch D26905
which was reverted back due to some basic issue with representing the 'use mask' of
jumbled accesses.
This patch fixes the mask representation by recording the 'use mask' in the usertree entry.
Change-Id: I9fe7f5045f065d84c126fa307ef6ebe0787296df
Reviewers: mkuper, loladiro, Ayal, zvi, danielcdh
Reviewed By: Ayal
Subscribers: mgrang, dcaballe, hans, mzolotukhin
Differential Revision: https://reviews.llvm.org/D36130
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320548
91177308-0d34-0410-b5e6-
96231b3b80d8
Florian Hahn [Wed, 13 Dec 2017 03:05:20 +0000 (03:05 +0000)]
[CallSiteSplitting] Refactor creating callsites.
Summary:
This change makes the call site creation more general if any of the
arguments is predicated on a condition in the call site's predecessors.
If we find a callsite, that potentially can be split, we collect the set
of conditions for the call site's predecessors (currently only 2
predecessors are allowed). To do that, we traverse each predecessor's
predecessors as long as it only has single predecessors and record the
condition, if it is relevant to the call site. For each condition, we
also check if the condition is taken or not. In case it is not taken,
we record the inverse predicate.
We use the recorded conditions to create the new call sites and split
the basic block.
This has 2 benefits: (1) it is slightly easier to see what is going on
(IMO) and (2) we can easily extend it to handle more complex control
flow.
Reviewers: davidxl, junbuml
Reviewed By: junbuml
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D40728
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320547
91177308-0d34-0410-b5e6-
96231b3b80d8
Matthias Braun [Wed, 13 Dec 2017 02:51:04 +0000 (02:51 +0000)]
Rename LiveIntervalAnalysis.h to LiveIntervals.h
Headers/Implementation files should be named after the class they
declare/define.
Also eliminated an `#include "llvm/CodeGen/LiveIntervalAnalysis.h"` in
favor of `class LiveIntarvals;`
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320546
91177308-0d34-0410-b5e6-
96231b3b80d8
Matthias Braun [Wed, 13 Dec 2017 02:51:01 +0000 (02:51 +0000)]
Remove unnecessary includes; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320545
91177308-0d34-0410-b5e6-
96231b3b80d8
Evgeniy Stepanov [Wed, 13 Dec 2017 01:16:34 +0000 (01:16 +0000)]
[hwasan] Inline instrumentation & fixed shadow.
Summary: This brings CPU overhead on bzip2 down from 5.5x to 2x.
Reviewers: kcc, alekseyshl
Subscribers: kubamracek, hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D41137
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320538
91177308-0d34-0410-b5e6-
96231b3b80d8
Michael Trent [Wed, 13 Dec 2017 00:36:13 +0000 (00:36 +0000)]
reverting out -r320532 because a warning is breaking the lld build
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320534
91177308-0d34-0410-b5e6-
96231b3b80d8
Michael Trent [Tue, 12 Dec 2017 23:53:46 +0000 (23:53 +0000)]
Updated llvm-objdump to display local relocations in Mach-O binaries
Summary:
llvm-objdump's Mach-O parser was updated in r306037 to display external
relocations for MH_KEXT_BUNDLE file types. This change extends the Macho-O
parser to display local relocations for MH_PRELOAD files. When used with
the -macho option relocations will be displayed in a historical format.
rdar://
35778019
Reviewers: enderby
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D41061
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320532
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Tue, 12 Dec 2017 22:23:09 +0000 (22:23 +0000)]
[EarlyCSE] add tests for commuted min/max; NFC
See PR35642: https://bugs.llvm.org/show_bug.cgi?id=35642
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320530
91177308-0d34-0410-b5e6-
96231b3b80d8
Krzysztof Parzyszek [Tue, 12 Dec 2017 21:44:04 +0000 (21:44 +0000)]
[Hexagon] Relax some checks in testcases, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320529
91177308-0d34-0410-b5e6-
96231b3b80d8
Alexey Bataev [Tue, 12 Dec 2017 20:28:46 +0000 (20:28 +0000)]
[InstCombine] Fix PR35618: Instcombine hangs on single minmax load bitcast.
Summary:
If we have pattern `store (load(bitcast(select (cmp(V1, V2), &V1,
&V2)))), bitcast)`, but the load is used in other instructions, it leads
to looping in InstCombiner. Patch adds additional check that all users
of the load instructions are stores and then replaces all uses of load
instruction by the new one with new type.
Reviewers: RKSimon, spatel, majnemer
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D41072
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320525
91177308-0d34-0410-b5e6-
96231b3b80d8
Krzysztof Parzyszek [Tue, 12 Dec 2017 20:23:12 +0000 (20:23 +0000)]
[Hexagon] Better detection of identity and undef masks in shuffles
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320523
91177308-0d34-0410-b5e6-
96231b3b80d8
Krzysztof Parzyszek [Tue, 12 Dec 2017 19:32:41 +0000 (19:32 +0000)]
[Hexagon] Fix wrong order of operands for vmux
Shuffle generation uses vmux to collapse vectors resulting from two
individual shuffles into one. The indexes of the elements selected
from the first operand were indicated by 0xFF in the constant vector
used in the compare instruction, but the compare (veqb) set the bits
corresponding to the 0x00 elements, thus inverting the selection.
Reverse the order of operands to vmux to get the correct output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320516
91177308-0d34-0410-b5e6-
96231b3b80d8
Fiona Glaser [Tue, 12 Dec 2017 19:18:02 +0000 (19:18 +0000)]
Reassociate: add global reassociation algorithm
This algorithm (explained more in the source code) takes into account
global redundancies by building a "pair map" to find common subexprs.
The primary motivation of this is to handle situations like
foo = (a * b) * c
bar = (a * d) * c
where we currently don't identify that "a * c" is redundant.
Accordingly, it prioritizes the emission of a * c so that CSE
can remove the redundant calculation later.
Does not change the actual reassociation algorithm -- only the
order in which the reassociated operand chain is reconstructed.
Gives ~1.5% floating point math instruction count reduction on
a large offline suite of graphics shaders.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320515
91177308-0d34-0410-b5e6-
96231b3b80d8
Alexey Bataev [Tue, 12 Dec 2017 19:12:34 +0000 (19:12 +0000)]
Revert "[InstCombine] Fix PR35618: Instcombine hangs on single minmax load bitcast."
This reverts commit r320510 - again sanitizers bbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320513
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjoy Das [Tue, 12 Dec 2017 19:11:31 +0000 (19:11 +0000)]
Reapply "[X86] Flag BroadWell scheduler model as complete"
This reverts commit r320508, in effect re-applying r320308. Simon has already
reverted the parts that caused the crash that motivated the revert in r320492.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320512
91177308-0d34-0410-b5e6-
96231b3b80d8
Hiroshi Yamauchi [Tue, 12 Dec 2017 19:07:43 +0000 (19:07 +0000)]
Split IndirectBr critical edges before PGO gen/use passes.
Summary:
The PGO gen/use passes currently fail with an assert failure if there's a
critical edge whose source is an IndirectBr instruction and that edge
needs to be instrumented.
To avoid this in certain cases, split IndirectBr critical edges in the PGO
gen/use passes. This works for blocks with single indirectbr predecessors,
but not for those with multiple indirectbr predecessors (splitting an
IndirectBr critical edge isn't always possible.)
Reviewers: davidxl, xur
Reviewed By: davidxl
Subscribers: efriedma, llvm-commits, mehdi_amini
Differential Revision: https://reviews.llvm.org/D40699
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320511
91177308-0d34-0410-b5e6-
96231b3b80d8
Alexey Bataev [Tue, 12 Dec 2017 18:47:00 +0000 (18:47 +0000)]
[InstCombine] Fix PR35618: Instcombine hangs on single minmax load bitcast.
Summary:
If we have pattern `store (load(bitcast(select (cmp(V1, V2), &V1,
&V2)))), bitcast)`, but the load is used in other instructions, it leads
to looping in InstCombiner. Patch adds additional check that all users
of the load instructions are stores and then replaces all uses of load
instruction by the new one with new type.
Reviewers: RKSimon, spatel, majnemer
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D41072
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320510
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjoy Das [Tue, 12 Dec 2017 18:40:58 +0000 (18:40 +0000)]
Revert "[X86] Flag BroadWell scheduler model as complete"
This reverts commit r320308. r320308 crashes LLC, please see the llvm-commits
thread for a reproducer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320508
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Tue, 12 Dec 2017 18:39:04 +0000 (18:39 +0000)]
[X86] Add a couple TODOs about missing coverage/features motivated by D40335
D40335 was wanting to add FMSUBADD support, but it discovered that there are two pieces of code to make FMADDSUB and only one of those is tested. So I've asked that review to implement the one path until we get tests that test the existing code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320507
91177308-0d34-0410-b5e6-
96231b3b80d8
Nirav Dave [Tue, 12 Dec 2017 18:25:48 +0000 (18:25 +0000)]
[X86] Cleanup type conversion of 64-bit load-store pairs.
Summary:
Simplify and generalize chain handling and search for 64-bit load-store pairs.
Nontemporal test now converts 64-bit integer load-store into f64 which it realizes directly instead of splitting into two i32 pairs.
Reviewers: craig.topper, spatel
Reviewed By: craig.topper
Subscribers: hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D40918
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320505
91177308-0d34-0410-b5e6-
96231b3b80d8
Alexandre Ganea [Tue, 12 Dec 2017 18:00:43 +0000 (18:00 +0000)]
Test commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320504
91177308-0d34-0410-b5e6-
96231b3b80d8
Geoff Berry [Tue, 12 Dec 2017 17:53:59 +0000 (17:53 +0000)]
[MachineOperand][MIR] Add isRenamable to MachineOperand.
Summary:
Add isRenamable() predicate to MachineOperand. This predicate can be
used by machine passes after register allocation to determine whether it
is safe to rename a given register operand. Register operands that
aren't marked as renamable may be required to be assigned their current
register to satisfy constraints that are not captured by the machine
IR (e.g. ABI or ISA constraints).
Reviewers: qcolombet, MatzeB, hfinkel
Subscribers: nemanjai, mcrosier, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D39400
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320503
91177308-0d34-0410-b5e6-
96231b3b80d8
Alexey Bataev [Tue, 12 Dec 2017 17:35:29 +0000 (17:35 +0000)]
Revert "[InstCombine] Fix PR35618: Instcombine hangs on single minmax load bitcast."
This reverts commit r320499 again to resolve the problem with the
sanitizers bbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320501
91177308-0d34-0410-b5e6-
96231b3b80d8
Alexey Bataev [Tue, 12 Dec 2017 17:19:15 +0000 (17:19 +0000)]
[InstCombine] Fix PR35618: Instcombine hangs on single minmax load bitcast.
Summary:
If we have pattern `store (load(bitcast(select (cmp(V1, V2), &V1,
&V2)))), bitcast)`, but the load is used in other instructions, it leads
to looping in InstCombiner. Patch adds additional check that all users
of the load instructions are stores and then replaces all uses of load
instruction by the new one with new type.
Reviewers: RKSimon, spatel, majnemer
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D41072
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320499
91177308-0d34-0410-b5e6-
96231b3b80d8
Alexey Bataev [Tue, 12 Dec 2017 17:08:48 +0000 (17:08 +0000)]
Revert "[InstCombine] Fix PR35618: Instcombine hangs on single minmax load bitcast."
This reverts commit r320496 to solve the problems with sanitizer
buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320498
91177308-0d34-0410-b5e6-
96231b3b80d8
Don Hinton [Tue, 12 Dec 2017 17:06:08 +0000 (17:06 +0000)]
[cmake] Support moving debuginfo-tests to llvm/projects
Differential Revision: https://reviews.llvm.org/D40972
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320497
91177308-0d34-0410-b5e6-
96231b3b80d8
Alexey Bataev [Tue, 12 Dec 2017 16:58:48 +0000 (16:58 +0000)]
[InstCombine] Fix PR35618: Instcombine hangs on single minmax load bitcast.
Summary:
If we have pattern `store (load(bitcast(select (cmp(V1, V2), &V1,
&V2)))), bitcast)`, but the load is used in other instructions, it leads
to looping in InstCombiner. Patch adds additional check that all users
of the load instructions are stores and then replaces all uses of load
instruction by the new one with new type.
Reviewers: RKSimon, spatel, majnemer
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D41072
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320496
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Tue, 12 Dec 2017 16:12:53 +0000 (16:12 +0000)]
[X86] Remove CompleteModel tags from CPU targets until we have better error checking (PR35636)
The checks we have for complete models are not great and miss many cases - e.g. in PR35636 it failed to recognise that only the first output (of 2) was actually tagged by the InstRW
Raised PR35639 and PR35643 as examples
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320492
91177308-0d34-0410-b5e6-
96231b3b80d8
Alex Bradbury [Tue, 12 Dec 2017 16:10:21 +0000 (16:10 +0000)]
[RISCV][NFC] Formatting fix in RISCVInstrInfo.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320491
91177308-0d34-0410-b5e6-
96231b3b80d8
Alexey Bataev [Tue, 12 Dec 2017 16:05:52 +0000 (16:05 +0000)]
Revert "[InstCombine] Fix PR35618: Instcombine hangs on single minmax load bitcast."
This reverts commit r320488 because of the failed asan buildbots..
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320490
91177308-0d34-0410-b5e6-
96231b3b80d8
Alexey Bataev [Tue, 12 Dec 2017 15:54:49 +0000 (15:54 +0000)]
[InstCombine] Fix PR35618: Instcombine hangs on single minmax load bitcast.
Summary:
If we have pattern `store (load(bitcast(select (cmp(V1, V2), &V1,
&V2)))), bitcast)`, but the load is used in other instructions, it leads
to looping in InstCombiner. Patch adds additional check that all users
of the load instructions are stores and then replaces all uses of load
instruction by the new one with new type.
Reviewers: RKSimon, spatel, majnemer
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D41072
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320488
91177308-0d34-0410-b5e6-
96231b3b80d8
Alex Bradbury [Tue, 12 Dec 2017 15:46:15 +0000 (15:46 +0000)]
[RISCV] Implement assembler pseudo instructions for RV32I and RV64I
Adds the assembler pseudo instructions of RV32I and RV64I which can
be mapped to a single canonical instruction. The missing pseudo
instructions (e.g., call, tail, ...) are marked as TODO. Other
things, like for example PCREL_LO, have to be implemented first.
Currently, alias emission is disabled by default to keep the patch
minimal. Alias emission by default will be enabled in a subsequent
patch which also updates all affected tests. Note that this patch
should actually break the floating point MC tests. However, the
used FileCheck configuration is not tight enought to detect the
breakage.
Differential Revision: https://reviews.llvm.org/D40902
Patch by Mario Werner.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320487
91177308-0d34-0410-b5e6-
96231b3b80d8
Alexey Bataev [Tue, 12 Dec 2017 15:24:17 +0000 (15:24 +0000)]
Revert "[InstCombine] Fix PR35618: Instcombine hangs on single minmax load bitcast."
This reverts commit r320483 because of the failed Windows buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320485
91177308-0d34-0410-b5e6-
96231b3b80d8
Alex Bradbury [Tue, 12 Dec 2017 15:17:45 +0000 (15:17 +0000)]
[RISCV] MC layer support for the instructions added in the privileged spec
Adds support for the instructions added in the RISC-V privileged ISA
(https://content.riscv.org/wp-content/uploads/2017/05/riscv-privileged-v1.10.pdf):
uret, sret, mret, wfi, and sfence.vma.
Note from the committer: I made very minor formatting changes prior to commit,
which didn't seem worth creating another review round-trip for.
Differential Revision: https://reviews.llvm.org/D40383
Patch by David Craven.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320484
91177308-0d34-0410-b5e6-
96231b3b80d8
Alexey Bataev [Tue, 12 Dec 2017 15:03:17 +0000 (15:03 +0000)]
[InstCombine] Fix PR35618: Instcombine hangs on single minmax load bitcast.
If we have pattern `store (load(bitcast(select (cmp(V1, V2), &V1,
&V2)))), bitcast)`, but the load is used in other instructions, it leads
to looping in InstCombiner. Patch adds additional check that all users
of the load instructions are stores and then replaces all uses of load
instruction by the new one with new type.
Reviewers: RKSimon, spatel, majnemer
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D41072
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320483
91177308-0d34-0410-b5e6-
96231b3b80d8
Ayman Musa [Tue, 12 Dec 2017 14:13:51 +0000 (14:13 +0000)]
[X86] Recognize constant arrays with special values and replace loads from it with subtract and shift instructions, which then will be replaced by X86 BZHI machine instruction.
Recognize constant arrays with the following values:
0x0, 0x1, 0x3, 0x7, 0xF, 0x1F, .... , 2^(size - 1) -1
where //size// is the size of the array.
the result of a load with index //idx// from this array is equivalent to the result of the following:
(0xFFFFFFFF >> (sub 32, idx)) (assuming the array of type 32-bit integer).
And the result of an 'AND' operation on the returned value of such a load and another input, is exactly equivalent to the X86 BZHI instruction behavior.
See test cases in the LIT test for better understanding.
Differential Revision: https://reviews.llvm.org/D34141
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320481
91177308-0d34-0410-b5e6-
96231b3b80d8
Anna Thomas [Tue, 12 Dec 2017 14:12:33 +0000 (14:12 +0000)]
[InstComineLoadStoreAlloca] Optimize stores to GEP off null base
Summary:
Currently, in InstCombineLoadStoreAlloca, we have simplification
rules for the following cases:
1. load off a null
2. load off a GEP with null base
3. store to a null
This patch adds support for the fourth case which is store into a
GEP with null base. Since this is UB as well (and directly analogous to
the load off a GEP with null base), we can substitute the stored val
with undef in instcombine, so that SimplifyCFG can optimize this code
into unreachable code.
Note: Right now, simplifyCFG hasn't been taught about optimizing
this to unreachable and adding an llvm.trap (this is already done for
the above 3 cases).
Reviewers: majnemer, hfinkel, sanjoy, davide
Reviewed by: sanjoy, davide
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D41026
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320480
91177308-0d34-0410-b5e6-
96231b3b80d8
Nemanja Ivanovic [Tue, 12 Dec 2017 12:33:09 +0000 (12:33 +0000)]
[PowerPC] Add branch flag on asm parser-only branch instructions
This flag was missing but it wasn't an issue as nothing depended on it
for these asm parser-only instructions. Now that LLDB support is slowly
landing, it is important to get this right.
Committing on behalf of Leonardo Bianconi.
Differential revision: https://reviews.llvm.org/D40846
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320475
91177308-0d34-0410-b5e6-
96231b3b80d8
Nemanja Ivanovic [Tue, 12 Dec 2017 12:09:34 +0000 (12:09 +0000)]
[PowerPC] Follow-up to r318436 to get the missed CSE opportunities
The last of the three patches that https://reviews.llvm.org/D40348 was
broken up into.
Canonicalize the materialization of constants so that they are more likely
to be CSE'd regardless of the bit-width of the use. If a constant can be
materialized using PPC::LI, materialize it the same way always.
For example:
li 4, -1
li 4, 255
li 4, 65535
are equivalent if the uses only use the low byte. Canonicalize it to the
first form.
Differential Revision: https://reviews.llvm.org/D40348
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320473
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Tue, 12 Dec 2017 11:34:25 +0000 (11:34 +0000)]
Revert r320461 - causing ICE in windows buildss
[X86] Use regular expressions more aggressively to reduce the number of scheduler entries needed for FMA3 instructions.
When the scheduler tables are generated by tablegen, the instructions are divided up into groups based on their default scheduling information and how they are referenced by groups for each processor. For any set of instructions that are matched by a specific InstRW line, that group of instructions is guaranteed to not be in a group with any other instructions. So in general, the more InstRW class definitions are created, the more groups we end up with in the generated files. Particularly if a lot of the InstRW lines only match to single instructions, which is true of a large number of the Intel scheduler models.
This change alone reduces the number of instructions groups from ~6000 to ~5500. And there's lots more we could do.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320470
91177308-0d34-0410-b5e6-
96231b3b80d8
Jonas Devlieghere [Tue, 12 Dec 2017 11:32:21 +0000 (11:32 +0000)]
[dsymutil] Accept line tables up to DWARFv5.
This patch removes the hard-coded check for DWARFv2 line tables. Now
dsymutil accepts line tables for DWARF versions 2 to 5 (inclusive).
Differential revision: https://reviews.llvm.org/D41084
rdar://
35968319
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320469
91177308-0d34-0410-b5e6-
96231b3b80d8
Eugene Leviant [Tue, 12 Dec 2017 10:12:46 +0000 (10:12 +0000)]
Revert r320464 as it breaks gold plugin tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320467
91177308-0d34-0410-b5e6-
96231b3b80d8
Igor Laevsky [Tue, 12 Dec 2017 10:03:39 +0000 (10:03 +0000)]
Revert r320049, r320014 and r319894
They were causing failures of the piglit OpenGL tests with AMD GPUs using the
Mesa radeonsi driver.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320466
91177308-0d34-0410-b5e6-
96231b3b80d8
Serguei Katkov [Tue, 12 Dec 2017 09:44:41 +0000 (09:44 +0000)]
[NFC][SafepointIRVerifier] Add alias for set of available values
Introduces usage of AvailableValueSet alias name instead of
DenseSet<const Value *> for better reading.
Patch Author: Daniil Suchkov
Reviewers: mkazantsev, anna, apilipenko
Reviewed By: anna
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D41002
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320465
91177308-0d34-0410-b5e6-
96231b3b80d8
Eugene Leviant [Tue, 12 Dec 2017 09:12:32 +0000 (09:12 +0000)]
[ThinLTO] Remove unused code from thinLTOInternalizeModule
Differential revision: https://reviews.llvm.org/D40970
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320464
91177308-0d34-0410-b5e6-
96231b3b80d8
Dorit Nuzman [Tue, 12 Dec 2017 08:57:43 +0000 (08:57 +0000)]
[LV] Ignore the cost of values that will not appear in the vectorized loop
VecValuesToIgnore holds values that will not appear in the vectorized loop.
We should therefore ignore their cost when VF > 1.
Differential Revision: https://reviews.llvm.org/D40883
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320463
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Tue, 12 Dec 2017 08:17:04 +0000 (08:17 +0000)]
[X86] Use regular expressions more aggressively to reduce the number of scheduler entries needed for FMA3 instructions.
When the scheduler tables are generated by tablegen, the instructions are divided up into groups based on their default scheduling information and how they are referenced by groups for each processor. For any set of instructions that are matched by a specific InstRW line, that group of instructions is guaranteed to not be in a group with any other instructions. So in general, the more InstRW class definitions are created, the more groups we end up with in the generated files. Particularly if a lot of the InstRW lines only match to single instructions, which is true of a large number of the Intel scheduler models.
This change alone reduces the number of instructions groups from ~6000 to ~5500. And there's lots more we could do.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320461
91177308-0d34-0410-b5e6-
96231b3b80d8
Mikael Holmen [Tue, 12 Dec 2017 07:29:57 +0000 (07:29 +0000)]
[CallSiteSplitting] Don't let debug intrinsics affect optimizations
Summary:
This solves PR35616.
We don't want the compiler to generate different code when we compile
with/without -g, so we now ignore debug intrinsics when determining if
the optimization can trigger or not.
Reviewers: junbuml
Subscribers: davide, JDevlieghere, llvm-commits
Differential Revision: https://reviews.llvm.org/D41068
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320460
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Tue, 12 Dec 2017 07:06:35 +0000 (07:06 +0000)]
[X86] Use Ld scheduler classes for instructions with folded loads.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320459
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Tue, 12 Dec 2017 07:06:32 +0000 (07:06 +0000)]
[X86] Correct the FMA3 regular expressions in the znver1 scheduler model.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320458
91177308-0d34-0410-b5e6-
96231b3b80d8
Tony Tye [Tue, 12 Dec 2017 05:47:00 +0000 (05:47 +0000)]
[AMDGPU] Rename Bonaire target to be gfx704; remove gfx800 and make Iceland and Tonga both use gfx802; update target feature handling
Correct committed version to match intended accepted review D40051 id=123417
- Rename Bonaire target to be gfx704.
- Eliminate gfx800 and make Iceland and Tonga both use gfx802 as they use the same code.
- List target features supported by each processor in the processor table together with the default value.
- Add xnack flag to e_flags.
- Remove xnack from kernel metadata and kernel descriptor since it is now a whole code object property.
Differential Revision: https://reviews.llvm.org/D40051
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320457
91177308-0d34-0410-b5e6-
96231b3b80d8
Vedant Kumar [Mon, 11 Dec 2017 23:34:50 +0000 (23:34 +0000)]
[llvm-cov] Simplify a test case. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320439
91177308-0d34-0410-b5e6-
96231b3b80d8
Max Moroz [Mon, 11 Dec 2017 23:17:46 +0000 (23:17 +0000)]
[llvm-cov] Add an option for "export" command to emit only file summary data.
Summary:
That allows to get the same data as produced by "llvm-cov report",
but in JSON format, which is better for further processing by end users.
Reviewers: vsk
Reviewed By: vsk
Differential Revision: https://reviews.llvm.org/D41085
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320435
91177308-0d34-0410-b5e6-
96231b3b80d8
Sam Clegg [Mon, 11 Dec 2017 23:03:38 +0000 (23:03 +0000)]
Reland "[WebAssembly] Import the linear memory and function table."
Original change: https://reviews.llvm.org/D40875
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320432
91177308-0d34-0410-b5e6-
96231b3b80d8
Richard Trieu [Mon, 11 Dec 2017 22:25:04 +0000 (22:25 +0000)]
Revert r318704 - [Sparc] efficient pattern for UINT_TO_FP conversion
See bug https://bugs.llvm.org/show_bug.cgi?id=35631
r318704 is giving a fatal error on some code with unsigned to floating point
conversions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320429
91177308-0d34-0410-b5e6-
96231b3b80d8
Matt Arsenault [Mon, 11 Dec 2017 21:38:43 +0000 (21:38 +0000)]
LSR: Check more intrinsic pointer operands
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320424
91177308-0d34-0410-b5e6-
96231b3b80d8
Hans Wennborg [Mon, 11 Dec 2017 21:15:27 +0000 (21:15 +0000)]
Revert r320407 "[InstCombine] Fix PR35618: Instcombine hangs on single minmax load bitcast."
The tests fail (opt asserts) on Windows.
> Summary:
> If we have pattern `store (load(bitcast(select (cmp(V1, V2), &V1,
> &V2)))), bitcast)`, but the load is used in other instructions, it leads
> to looping in InstCombiner. Patch adds additional check that all users
> of the load instructions are stores and then replaces all uses of load
> instruction by the new one with new type.
>
> Reviewers: RKSimon, spatel, majnemer
>
> Subscribers: llvm-commits
>
> Differential Revision: https://reviews.llvm.org/D41072
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320421
91177308-0d34-0410-b5e6-
96231b3b80d8
Evandro Menezes [Mon, 11 Dec 2017 21:09:27 +0000 (21:09 +0000)]
[CodeGen] Improve the consistency of instruction fusion*
When either instruction in a fused pair has no other dependency, besides on
the other instruction, make sure that other instructions do not get
scheduled between them. Additionally, avoid fusing an instruction more than
once along the same dependency chain.
Differential revision: https://reviews.llvm.org/D36704
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320420
91177308-0d34-0410-b5e6-
96231b3b80d8
Adrian Prantl [Mon, 11 Dec 2017 20:43:21 +0000 (20:43 +0000)]
ASAN: Provide reliable debug info for local variables at -O0.
The function stack poisioner conditionally stores local variables
either in an alloca or in malloc'ated memory, which has the
unfortunate side-effect, that the actual address of the variable is
only materialized when the variable is accessed, which means that
those variables are mostly invisible to the debugger even when
compiling without optimizations.
This patch stores the address of the local stack base into an alloca,
which can be referred to by the debug info and is available throughout
the function. This adds one extra pointer-sized alloca to each stack
frame (but mem2reg can optimize it away again when optimizations are
enabled, yielding roughly the same debug info quality as before in
optimized code).
rdar://problem/
30433661
Differential Revision: https://reviews.llvm.org/D41034
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320415
91177308-0d34-0410-b5e6-
96231b3b80d8
Tony Jiang [Mon, 11 Dec 2017 20:42:37 +0000 (20:42 +0000)]
[PowerPC] Partially enable the ISEL expansion pass.
The pass to expand ISEL instructions into if-then-else sequences in patch D23630
is currently disabled. This patch partially enable it by always removing the
unnecessary ISELs (all registers used by the ISELs are the same one) and folding
the ISELs which have the same input registers into unconditional copies.
Differential Revision: https://reviews.llvm.org/D40497
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320414
91177308-0d34-0410-b5e6-
96231b3b80d8
Justin Bogner [Mon, 11 Dec 2017 19:53:23 +0000 (19:53 +0000)]
[cmake] Pass TARGETS_TO_BUILD through to host tools build
In r319620, the host build was changed to use Native for
TARGETS_TO_BUILD because passing semicolons through add_custom_command
is surprisingly difficult. However, Native really doesn't make any
sense here, and it only works because we don't technically do any
codegen in the host tools so pretty well anything will "work".
The problem here is that passing something other than the correct
value is very fragile - as evidence note how the llvm-config in the
host tools acts differently than the target one now, and misreports
the targets to build. Similarly, if there is any logic conditional on
the targets in tablegen (now or in the future), it will do the wrong
thing.
To fix this, we need to escape the semicolons in the targets string
and pass it through to the child cmake invocation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320413
91177308-0d34-0410-b5e6-
96231b3b80d8
George Burgess IV [Mon, 11 Dec 2017 19:22:59 +0000 (19:22 +0000)]
Ensure moved-from container is cleared on move
In all cases except for this optimistic attempt to reuse memory, the
moved-from TinyPtrVector was left `empty()` at the end of this
assignment. Though using a container after it's been moved from can be a
bit sketchy, it's probably best to just be consistent here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320408
91177308-0d34-0410-b5e6-
96231b3b80d8