OSDN Git Service
Simon Pilgrim [Thu, 21 Dec 2017 16:34:46 +0000 (16:34 +0000)]
[DAGCombiner] Generalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) combine to work on non-splat vectors
The knownbits_mask_or_shuffle_uitofp change is interesting - shuffle combines manage to kick in, removing the AND constant mask load. For targets with fast-variable-shuffle this should reduce further to VPOR+VPSHUFB+VCVTDQ2PS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321279
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Simon Pilgrim [Thu, 21 Dec 2017 16:08:41 +0000 (16:08 +0000)]
[X86] Add (or (and X, c1), c2) -> (and (or X, c2), c1|c2) non-splat vector test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321278
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Tony Jiang [Thu, 21 Dec 2017 15:42:50 +0000 (15:42 +0000)]
[PowerPC] Fix parest build failure in SPEC2017.
The build failure was caused by an assertion in pre-legalization DAGCombine:
Combining: t6: ppcf128 = uint_to_fp t5
... into: t20: f32 = PPCISD::FCFIDUS t19
which is clearly wrong since ppcf128 are definitely different type with f32 and
we cannot change the node value type when do DAGCombine. The fix is don't
handle ppc_fp128 or i1 conversions in PPCTargetLowering::combineFPToIntToFP and
leave it to downstream to legalize it and expand it to small legal types.
Differential Revision: https://reviews.llvm.org/D41411
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321276
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Simon Pilgrim [Thu, 21 Dec 2017 15:17:29 +0000 (15:17 +0000)]
[DAGCombiner] Generalize (and (or x, C), D) -> D iff (C & D) == D combine to work on non-splat vectors
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321275
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Simon Dardis [Thu, 21 Dec 2017 15:14:07 +0000 (15:14 +0000)]
[mips] Fix the invalid EVA test
During the review of D40362 I spotted that this test wasn't actually
testing the eva instructions due to '-mattr==eva', rather than '-mattr=+eva',
which resulted in test having no effect.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321273
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Simon Pilgrim [Thu, 21 Dec 2017 14:33:40 +0000 (14:33 +0000)]
[X86] Add (and (or x, C), D) -> D iff (C & D) == D non-splat vector test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321268
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Simon Pilgrim [Thu, 21 Dec 2017 13:18:19 +0000 (13:18 +0000)]
[X86] Add v48i8 AVG test case, based on discussion on D41440
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321261
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Sam Parker [Thu, 21 Dec 2017 12:55:04 +0000 (12:55 +0000)]
[DAGCombine] Improve ReduceLoadWidth for SRL
If the SRL node is only used by an AND, we may be able to set the
ExtVT to the width of the mask, making the AND redundant. To support
this, another check has been added in isLegalNarrowLoad which queries
whether the load is valid.
Differential Revision: https://reviews.llvm.org/D41350
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321259
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Pavel Labath [Thu, 21 Dec 2017 11:27:21 +0000 (11:27 +0000)]
[Support] Remove MemoryBuffer::getNewUninitMemBuffer
There is nothing useful that can be done with a read-only uninitialized
buffer without const_casting its contents to initialize it. A better
solution is to obtain a writable buffer
(WritableMemoryBuffer::getNewUninitMemBuffer), and then convert it to a
read-only buffer after initialization. All callers of this function have
already been updated to do this, so this function is now unused.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321257
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Sam Parker [Thu, 21 Dec 2017 11:17:49 +0000 (11:17 +0000)]
[ARM] Armv8-R DFB instruction
Implement MC support for the Armv8-R 'Data Full Barrier' instruction.
Differential Revision: https://reviews.llvm.org/D41430
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321256
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Simon Atanasyan [Thu, 21 Dec 2017 10:46:20 +0000 (10:46 +0000)]
[llvm-readobj] Fix ambiguous call to the `printNumber`
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321254
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Simon Atanasyan [Thu, 21 Dec 2017 10:26:02 +0000 (10:26 +0000)]
[llvm-readobj] Support 'GNU' style for MIPS GOT/PLT dumping
This change adds `printMipsGOT` and `printMipsPLT` methods to the
`DumpStyle` class and overrides them in the `GNUStyle` and `LLVMStyle`
descendants. To pass information about GOT/PLT layout into these
methods, the `MipsGOTParser` class has been extended to hold all
necessary data.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321253
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Craig Topper [Thu, 21 Dec 2017 08:22:51 +0000 (08:22 +0000)]
[X86] Use PSHUFB for v32i16 shuffles before falling back to VPERMW/VPERMI2W.
PSHUFB has the ability to implicitly 0 elements which VPERMI2W can't do. So give a chance to use it first.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321251
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Craig Topper [Thu, 21 Dec 2017 07:31:30 +0000 (07:31 +0000)]
[X86] Use VPERMI2B for v16i8 shuffles if we have VBMI+VLX and would have otherwise used two PSHUFBs ORed together.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321249
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Craig Topper [Thu, 21 Dec 2017 05:58:31 +0000 (05:58 +0000)]
[X86] Use VPERMB/VPERMI2B for v32i8 shuffle lowering if VBMI and VLX are supported.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321248
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Craig Topper [Thu, 21 Dec 2017 03:58:31 +0000 (03:58 +0000)]
[X86] Add avx512vbmi command lines to vector-shuffle-256-v32.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321247
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Sam Clegg [Thu, 21 Dec 2017 03:16:34 +0000 (03:16 +0000)]
[WebAssembly] Remove unneeded sub-directory
This is the only wasm def (and likely likely will be
for the foreseeable) file so no need for a sub-directory
Differential Revision: https://reviews.llvm.org/D41476
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321246
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Sanjoy Das [Thu, 21 Dec 2017 02:34:39 +0000 (02:34 +0000)]
Revert "Expose a TargetMachine::getTargetTransformInfo function"
This reverts commit r321234. It breaks the -DBUILD_SHARED_LIBS=ON build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321243
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Sam Clegg [Thu, 21 Dec 2017 02:30:38 +0000 (02:30 +0000)]
[WebAssembly] Fix local references to weak aliases
When weak aliases are used with in same translation
unit we need to be able to directly reference to alias
and not just the thing it is aliases. We do this by
defining both a wasm import and a wasm export in this
case that result in a single Symbol. This change is
a partial revert of rL314245. A corresponding lld
change address the previous issues we had with this.
See: https://github.com/WebAssembly/tool-conventions/issues/34
Differential Revision: https://reviews.llvm.org/D41472
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321242
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Michael Zolotukhin [Thu, 21 Dec 2017 01:22:13 +0000 (01:22 +0000)]
[SimplifyCFG] Avoid quadratic on a predecessors number behavior in instruction sinking.
If a block has N predecessors, then the current algorithm will try to
sink common code to this block N times (whenever we visit a
predecessor). Every attempt to sink the common code includes going
through all predecessors, so the complexity of the algorithm becomes
O(N^2).
With this patch we try to sink common code only when we visit the block
itself. With this, the complexity goes down to O(N).
As a side effect, the moment the code is sunk is slightly different than
before (the order of simplifications has been changed), that's why I had
to adjust two tests (note that neither of the tests is supposed to test
SimplifyCFG):
* test/CodeGen/AArch64/arm64-jumptable.ll - changes in this test mimic
the changes that previous implementation of SimplifyCFG would do.
* test/CodeGen/ARM/avoid-cpsr-rmw.ll - in this test I disabled common
code sinking by a command line flag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321236
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Sanjoy Das [Thu, 21 Dec 2017 01:06:58 +0000 (01:06 +0000)]
Expose a TargetMachine::getTargetTransformInfo function
Summary:
This makes the TargetMachine interface a bit simpler. We still need
the std::function in TargetIRAnalysis to avoid having to add a
dependency from Analysis to Target.
See discussion:
http://lists.llvm.org/pipermail/llvm-dev/2017-December/119749.html
I avoided adding all of the backend owners to this review since the
change is simple, but let me know if you feel differently about this.
Reviewers: echristo, MatzeB, hfinkel
Reviewed By: hfinkel
Subscribers: jholewinski, jfb, arsenm, dschuff, mcrosier, sdardis, nemanjai, nhaehnle, javed.absar, sbc100, jgravelle-google, aheejin, kbarton, llvm-commits
Differential Revision: https://reviews.llvm.org/D41464
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321234
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Reid Kleckner [Thu, 21 Dec 2017 00:28:34 +0000 (00:28 +0000)]
Attempt to pacify 4.8.5 with makeArrayRef
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321233
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Simon Dardis [Wed, 20 Dec 2017 22:26:41 +0000 (22:26 +0000)]
[orc][cmake] Check if 8 byte atomics require libatomic for unittest
rL319838 introduced SymbolStringPool which uses 8 byte atomics for
reference counters. On systems which do not support such atomics
natively such as MIPS32, explicitly add libatomic as one of the
libraries for SymbolStringPool's unittest.
Reviewers: lhames, beanz
Differential Revision: https://reviews.llvm.org/D41010
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321225
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Joel Galenson [Wed, 20 Dec 2017 22:25:39 +0000 (22:25 +0000)]
[ARM] Optimize {s,u}{add,sub}.with.overflow.
The AArch64 backend contains code to optimize {s,u}{add,sub}.with.overflow during SelectionDAG. This commit ports that code to the ARM backend.
Differential revision: https://reviews.llvm.org/D35635
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321224
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Krzysztof Parzyszek [Wed, 20 Dec 2017 20:54:13 +0000 (20:54 +0000)]
[Hexagon] Use ArrayRef member functions instead of custom ones
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321221
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Krzysztof Parzyszek [Wed, 20 Dec 2017 20:49:43 +0000 (20:49 +0000)]
[Hexagon] Allow construction of HVX vector predicates
Handle BUILD_VECTOR of boolean values.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321220
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Krzysztof Parzyszek [Wed, 20 Dec 2017 20:33:49 +0000 (20:33 +0000)]
[Hexagon] Legalize vector elements to i32 in buildVector32/64
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321218
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Aaron Ballman [Wed, 20 Dec 2017 20:09:30 +0000 (20:09 +0000)]
Do not generate an empty switch statement as it causes MSVC to issue diagnostics about switch statements without case or default labels.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321217
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Yonghong Song [Wed, 20 Dec 2017 19:39:58 +0000 (19:39 +0000)]
bpf: add support for objdump -print-imm-hex
Add support for 'objdump -print-imm-hex' for imm64, operand imm
and branch target. If user programs encode immediate values
as hex numbers, such an option will make it easy to correlate
asm insns with source code. This option also makes it easy
to correlate imm values with insn encoding.
There is one changed behavior in this patch. In old way, we
print the 64bit imm as u64:
O << (uint64_t)Op.getImm();
and the new way is:
O << formatImm(Op.getImm());
The formatImm is defined in llvm/MC/MCInstPrinter.h as
format_object<int64_t> formatImm(int64_t Value)
So the new way to print 64bit imm is i64 type.
If a 64bit value has the highest bit set, the old way
will print the value as a positive value and the
new way will print as a negative value. The new way
is consistent with x86_64.
For the code (see the test program):
...
if (a == 0xABCDABCDabcdabcdULL)
...
x86_64 objdump, with and without -print-imm-hex, looks like:
48 b8 cd ab cd ab cd ab cd ab movabsq $-
6067004223159161907, %rax
48 b8 cd ab cd ab cd ab cd ab movabsq $-0x5432543254325433, %rax
Signed-off-by: Yonghong Song <yhs@fb.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321215
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David Blaikie [Wed, 20 Dec 2017 19:36:54 +0000 (19:36 +0000)]
PR35705: Fix Chapter 9 example code for API changes to DIBuilder
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321214
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Craig Topper [Wed, 20 Dec 2017 19:36:43 +0000 (19:36 +0000)]
[X86] Refactor DomainReassignment pass to make the Closure class not stores references to the main data structures of the pass itself
Multiple Closure objects can be created and stored for a single function. It's not a good idea to devote so many fields of it to storing pointers and references to global data structures of the pass. The closure class should only store the things needed to represent the closure itself.
This patch refactors many of the methods of Closure to belong to the pass object and to pass around a reference to the current Closure. The Closure class gains a few simple methods to add instructions and edges, and to return iterators to edges and instructions
Differential Revision: https://reviews.llvm.org/D41327
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321213
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Matt Arsenault [Wed, 20 Dec 2017 19:36:28 +0000 (19:36 +0000)]
TableGen: Allow setting SDNodeProperties on intrinsics
Allows preserving MachineMemOperands on intrinsics
through selection. For reasons I don't understand, this
is a static property of the pattern and the selector
deliberately goes out of its way to drop if not present.
Intrinsics already inherit from SDPatternOperator allowing
them to be used directly in instruction patterns. SDPatternOperator
has a list of SDNodeProperty, but you currently can't set them on
the intrinsic. Without SDNPMemOperand, when the node is selected
any memory operands are always dropped. Allowing setting this
on the intrinsics avoids needing to introduce another equivalent
target node just to have SDNPMemOperand set.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321212
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Matthew Simpson [Wed, 20 Dec 2017 19:26:37 +0000 (19:26 +0000)]
[ICP] Expose unconditional call promotion interface
This patch modifies the indirect call promotion utilities by exposing and using
an unconditional call promotion interface. The unconditional promotion
interface (i.e., call promotion without creating an if-then-else) can be used
if it's known that an indirect call has only one possible callee. The existing
conditional promotion interface uses this unconditional interface to promote an
indirect call after it has been versioned and placed within the "then" block.
A consequence of unconditional promotion is that the fix-up operations for phi
nodes in the normal destination of invoke instructions are changed. This is
necessary because the existing implementation assumed that an invoke had been
versioned, creating a "merge" block where a return value bitcast could be
placed. In the new implementation, the edge between a promoted invoke's parent
block and its normal destination is split if needed to add a bitcast for the
return value. If the invoke is also versioned, the phi node merging the return
value of the promoted and original invoke instructions is placed in the "merge"
block.
Differential Revision: https://reviews.llvm.org/D40751
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321210
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Craig Topper [Wed, 20 Dec 2017 19:25:33 +0000 (19:25 +0000)]
[X86] Remove zext from vXi32 to vXi64 on indices of gather/scatter instructions if we can prove the pre-extended value is positive.
Gather/scatter can implicitly sign extend from i32->i64 on indices. So if we know the sign bit of the input to a zext is 0 we can use the implicit extension.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321209
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Matt Arsenault [Wed, 20 Dec 2017 19:11:59 +0000 (19:11 +0000)]
DAG: Tolerate non-MemSDNodes for OPC_RecordMemRef
When intrinsics are allowed to have mem operands, there
are two ways this can happen. First is an intrinsic
that is marked has having a mem operand, but is not handled
by getTgtMemIntrinsic.
The second way can occur even for intrinsics which do not
have a mem operand. It seems the selector table does
some kind of sorting based on the opcode, and the
mem ref recording can happen in the same scope for
intrinsics that both do and do not have mem refs.
I haven't been able to figure out exactly why this happens
(although it happens even with the matcher optimizations disabled).
I'm not sure if it's worth trying to avoid hitting this for
these nodes since I think it's still reasonable to handle
this in case getTgtMemIntrinic is not implemented.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321208
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Warren Ristow [Wed, 20 Dec 2017 19:11:31 +0000 (19:11 +0000)]
Improve the test for r320216. NFC.
Patch by Matthew Voss!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321207
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Adam Nemet [Wed, 20 Dec 2017 19:08:12 +0000 (19:08 +0000)]
[opt-viewer] Also demangle indirect-call promotion targets
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321206
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Stefan Pintilie [Wed, 20 Dec 2017 19:07:44 +0000 (19:07 +0000)]
[PowerPC] Added an assert to make sure that the MBBI iterator is valid.
The function createTailCallBranchInstr assumes that the iterator MBBI is valid.
However, only one use of MBBI is guarded in the function.
Fix this by adding an assert.
Differential Revision: https://reviews.llvm.org/D41358
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321205
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Nirav Dave [Wed, 20 Dec 2017 19:06:47 +0000 (19:06 +0000)]
[DAG] Fix condition on overlapping store check.
Prevent overlapping store elision when overlapping store is
pre-inc/dec as analysis is wrong in these cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321204
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Evgeniy Stepanov [Wed, 20 Dec 2017 19:05:44 +0000 (19:05 +0000)]
[hwasan] Implement -fsanitize-recover=hwaddress.
Summary: Very similar to AddressSanitizer, with the exception of the error type encoding.
Reviewers: kcc, alekseyshl
Subscribers: cfe-commits, kubamracek, llvm-commits, hiraditya
Differential Revision: https://reviews.llvm.org/D41417
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321203
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Matt Arsenault [Wed, 20 Dec 2017 18:52:57 +0000 (18:52 +0000)]
[AMDGPU, AsmParser] Enable the mnemonic spell corrector.
Patch by Dmitry Venikov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321202
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Craig Topper [Wed, 20 Dec 2017 18:05:15 +0000 (18:05 +0000)]
[X86] Implement the fusing of MUL+SUBADD to FMSUBADD
This patch turns shuffles of fadd/fsub with fmul into fmsubadd.
Patch by Dmitry Venikov
Differential Revision: https://reviews.llvm.org/D40335
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321200
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Teresa Johnson [Wed, 20 Dec 2017 17:53:10 +0000 (17:53 +0000)]
[PGO] Function section hotness prefix should look at all blocks
Summary:
The function section prefix for PGO based layout (e.g. hot/unlikely)
should look at the hotness of all blocks not just the entry BB.
A function with a cold entry but a very hot loop should be placed in the
hot section, for example, so that it is located close to other hot
functions it may call. For SamplePGO it was already looking at the
branch weights on calls, and I made that code conditional on whether
this is SamplePGO since it was essentially a noop for instrumentation
PGO anyway.
Reviewers: davidxl
Subscribers: eraman, llvm-commits
Differential Revision: https://reviews.llvm.org/D41395
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321197
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Florian Hahn [Wed, 20 Dec 2017 17:16:59 +0000 (17:16 +0000)]
[InstCombine] Add debug location to new caller.
Reviewers: rnk, aprantl, majnemer
Reviewed By: aprantl
Differential Revision: https://reviews.llvm.org/D414
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321191
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Nemanja Ivanovic [Wed, 20 Dec 2017 15:44:32 +0000 (15:44 +0000)]
[JumpTables] Let targets decide which switch instructions are suitable
This commits the non-controversial part of https://reviews.llvm.org/D41029
(making the queries virtual). The PPC-specific portion of this will be
committed in a subsequent patch once some of the finer points are ironed out.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321182
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Mohammad Shahid [Wed, 20 Dec 2017 15:26:59 +0000 (15:26 +0000)]
Revert r320548:[SLP] Vectorize jumbled memory loads
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321181
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Krzysztof Parzyszek [Wed, 20 Dec 2017 15:15:04 +0000 (15:15 +0000)]
Add optional SelectionDAG* parameter to SValue::dump and SDValue::dumpr
These functions simply call their counterparts in the associated SDNode,
which do take an optional SelectionDAG. This change makes the legalization
debug trace a little easier to read, since target-specific nodes will
now have their names shown instead of "Unknown node #123".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321180
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Javed Absar [Wed, 20 Dec 2017 15:06:26 +0000 (15:06 +0000)]
[SCEV] Fix Typo. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321179
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Alexey Bataev [Wed, 20 Dec 2017 14:55:10 +0000 (14:55 +0000)]
[NVPTX] Initial adaptation of MCAsmStreamer/MCTargetStreamer for debug info in Cuda.
Summary:
Initial changes in interfaces of MCAsmStreamer/MCTargetStreamer for
correct debug info emission for Cuda.
1. PTX foramt does not support `.ascii` directives. Added the ability to
nullify it.
2. The initial function label must follow the first debug `.loc`
directive, not be followed by.
3. DWARF sections must be enclosed in braces.
Reviewers: hfinkel, probinson, jlebar, rafael, echristo
Subscribers: sdardis, nemanjai, llvm-commits, aprantl
Differential Revision: https://reviews.llvm.org/D40033
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321178
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Krzysztof Parzyszek [Wed, 20 Dec 2017 14:44:05 +0000 (14:44 +0000)]
[Hexagon] Adjust the value type for BCvt in LowerFormalArguments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321177
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Daniel Sanders [Wed, 20 Dec 2017 14:41:51 +0000 (14:41 +0000)]
[globalisel][tablegen] Allow ImmLeaf predicates to use InstructionSelector members
NFC for currently supported targets. This resolves a problem encountered by
targets such as RISCV that reference `Subtarget` in ImmLeaf predicates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321176
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Ilya Biryukov [Wed, 20 Dec 2017 14:39:07 +0000 (14:39 +0000)]
Allow to apply cherry-picks when building Docker images.
Reviewers: mehdi_amini, ioeric, klimek
Reviewed By: ioeric
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D41393
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321175
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Florian Hahn [Wed, 20 Dec 2017 13:28:38 +0000 (13:28 +0000)]
[LV] Remove unnecessary DoExtraAnalysis guard (silent bug)
canVectorize is only checking if the loop has a normalized pre-header if DoExtraAnalysis is true.
This doesn't make sense to me because reporting analysis information shouldn't alter legality
checks. This is probably the result of a last minute minor change before committing (?).
Patch by Diego Caballero.
Reviewed By: fhahn
Differential Revision: https://reviews.llvm.org/D40973
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321172
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Simon Pilgrim [Wed, 20 Dec 2017 13:12:34 +0000 (13:12 +0000)]
[X86][AVX2] Split more shuffle tests into 'slow' and 'fast' variable shuffles
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321171
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Sander de Smalen [Wed, 20 Dec 2017 12:45:40 +0000 (12:45 +0000)]
Trivial commit to force LLVM to run TableGen for Mips target after
a change to the AsmMatcherEmitter, and should fix the buildbot
failure on llvm-clang-x86_64-expensive-checks-win.
The issue is also described here:
http://lists.llvm.org/pipermail/llvm-dev/2017-December/119617.html
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321170
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Florian Hahn [Wed, 20 Dec 2017 11:32:43 +0000 (11:32 +0000)]
[TargetParser] Check size before accessing architecture version.
Summary:
This fixes a crash when invalid -march options like `armv` are provided.
Based on a patch by Will Lovett.
Reviewers: rengolin, samparker, mcrosier
Reviewed By: samparker
Subscribers: aemerson, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D41429
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321166
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Diana Picus [Wed, 20 Dec 2017 11:27:10 +0000 (11:27 +0000)]
[ARM GlobalISel] Fix assertion in RegBankSelect
We get an assertion in RegBankSelect for code along the lines of
my_32_bit_int = my_64_bit_int, which tends to translate into a 64-bit
load, followed by a G_TRUNC, followed by a 32-bit store. This appears in
a couple of places in the test-suite.
At the moment, the legalizer doesn't distinguish between integer and
floating point scalars, so a 64-bit load will be marked as legal for
targets with VFP, and so will the rest of the sequence, leading to a
slightly bizarre G_TRUNC reaching RegBankSelect.
Since the current support for 64-bit integers is rather immature, this
patch works around the issue by explicitly handling this case in
RegBankSelect and InstructionSelect. In the future, we may want to
revisit this decision and make sure 64-bit integer loads are narrowed
before reaching RegBankSelect.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321165
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Florian Hahn [Wed, 20 Dec 2017 11:13:57 +0000 (11:13 +0000)]
[ARM] Lower unsigned saturation to USAT
Summary:
Implement lower of unsigned saturation on an interval [0, k] where k + 1 is a power of two using USAT instruction in a similar way to how [~k, k] is lowered using SSAT on ARM models that supports it.
Patch by Marten Svanfeldt
Reviewers: t.p.northover, pbarrio, eastig, SjoerdMeijer, javed.absar, fhahn
Reviewed By: fhahn
Subscribers: fhahn, aemerson, javed.absar, llvm-commits, kristof.beyls
Differential Revision: https://reviews.llvm.org/D41348
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321164
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Sander de Smalen [Wed, 20 Dec 2017 11:02:42 +0000 (11:02 +0000)]
[AArch64][SVE] Re-submit patch series for ZIP1/ZIP2
This patch resubmits the SVE ZIP1/ZIP2 patch series consisting of
of r320992, r320986, r320973, and r320970 by reverting
https://reviews.llvm.org/rL321024.
The issue that caused r321024 has been addressed in https://reviews.llvm.org/rL321158,
so this patch-series should be safe to resubmit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321163
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Tim Northover [Wed, 20 Dec 2017 10:45:39 +0000 (10:45 +0000)]
AArch64: fix one more place movi.2d could be created.
Somehow got missed out of r320965.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321162
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Bjorn Steinbrink [Wed, 20 Dec 2017 10:01:30 +0000 (10:01 +0000)]
Give up on array allocas in getPointerDereferenceableBytes
Summary:
As suggested by Eli Friedman, don't try to handle array allocas here,
because of possible overflows, instead rely on instcombine converting
them to allocations of array types.
Reviewers: efriedma
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D41398
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321159
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Sander de Smalen [Wed, 20 Dec 2017 09:45:45 +0000 (09:45 +0000)]
[AArch64] Asm: Fix parsing of register aliases that have a name starting with 'z'
Summary: This fixes an issue as identified by @rnk in https://reviews.llvm.org/rL321029.
Reviewers: rnk, fhahn, rengolin, efriedma, echristo, olista01
Reviewed By: rnk, fhahn
Subscribers: aemerson, javed.absar, kristof.beyls, llvm-commits, rnk
Differential Revision: https://reviews.llvm.org/D41382
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321158
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Sam Parker [Wed, 20 Dec 2017 08:56:41 +0000 (08:56 +0000)]
[AArch64] CCSIDR2 system register
Implement the 'Current Cache Size' register that has been introduced
as part of the Armv8.3 architecture. I originally missed this, and
(hopefully) should be the final patch for assembler support.
Differential Revision: https://reviews.llvm.org/D41396
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321155
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Gadi Haber [Wed, 20 Dec 2017 08:28:24 +0000 (08:28 +0000)]
[X86][CLFLUSH]: Adding full coverage of MC encoding for the CLFLUSH isa sets.<NFC>
NFC.
Adding MC regressions tests to cover the CLFLSH and CLFLUSHOPT isa sets.
This patch is part of a larger task to cover MC encoding of all X86 isa sets started in revision: https://reviews.llvm.org/D39952
Reviewers: zvi, RKSimon, craig.topper, m_zuckerman
Differential Revision: https://reviews.llvm.org/D41331
Change-Id: Ifa643dd52f1b7184c52bc1806038dc74b234fc65
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321153
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Craig Topper [Wed, 20 Dec 2017 07:36:59 +0000 (07:36 +0000)]
[X86] Optimize sign extends on index operand to gather/scatter to not sign extend past i32.
The gather instruction will implicitly sign extend to the pointer width, we don't need to further extend it. This can prevent unnecessary splitting in some cases.
There's still an issue that lowering on non-VLX can introduce another sign extend that doesn't get combined with shifts from a lowered sign_extend_inreg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321152
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Martin Storsjo [Wed, 20 Dec 2017 06:51:45 +0000 (06:51 +0000)]
[AArch64] Implement stack probing for windows
Differential Revision: https://reviews.llvm.org/D41131
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321150
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Craig Topper [Wed, 20 Dec 2017 06:44:50 +0000 (06:44 +0000)]
[X86] Add a missing return to combineGatherScatter after sucessful combine.
Not sure how to test this cause I think the worst that happens is that we don't revisit the node a second time to look for additional combines. We used UpdateNodeOperands so the updating the DAG work was already done.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321148
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Hiroshi Inoue [Wed, 20 Dec 2017 05:18:19 +0000 (05:18 +0000)]
[PowerPC] fix a bug in redundant compare elimination
This patch fixes a bug in the redundant compare elimination reported in https://reviews.llvm.org/rL320786 and re-enables the optimization.
The redundant compare elimination assumes that we can replace signed comparison with unsigned comparison for the equality check. But due to the difference in the sign extension behavior we cannot change the opcode if the comparison is against an immediate and the most significant bit of the immediate is one.
Differential Revision: https://reviews.llvm.org/D41385
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321147
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Dan Gohman [Wed, 20 Dec 2017 01:36:25 +0000 (01:36 +0000)]
[memcpyopt] Teach memcpyopt to optimize across basic blocks
This teaches memcpyopt to make a non-local memdep query when a local query
indicates that the dependency is non-local. This notably allows it to
eliminate many more llvm.memcpy calls in common Rust code, often by 20-30%.
This is r319482 and r319483, along with fixes for PR35519: fix the
optimization that merges stores into memsets to preserve cached memdep
info, and fix memdep's non-local caching strategy to not assume that larger
queries are always more conservative than smaller ones.
Fixes PR28958 and PR35519.
Differential Revision: https://reviews.llvm.org/D40802
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321138
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Craig Topper [Wed, 20 Dec 2017 01:26:36 +0000 (01:26 +0000)]
[X86] Improve coverage of fma negations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321137
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Craig Topper [Wed, 20 Dec 2017 01:26:35 +0000 (01:26 +0000)]
[X86] Fix probable typo in fma fneg test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321136
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Craig Topper [Wed, 20 Dec 2017 01:00:01 +0000 (01:00 +0000)]
[X86] Remove code from combineSext that looks for MVT::i1 after operation legalization which can never happen.
Type legalization guarantees this to be impossible since MVT::i1 isn't a legal type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321132
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Dan Gohman [Wed, 20 Dec 2017 00:59:28 +0000 (00:59 +0000)]
[WebAssembly] Disable tee_local optimizations when targeting the ELF ABI.
These optimizations depend on the ExplicitLocals pass to lower TEE
instructions, which is disabled in the ELF ABI, so disable them too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321131
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Dan Gohman [Wed, 20 Dec 2017 00:10:28 +0000 (00:10 +0000)]
[WebAssembly] Remove an obsolete comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321127
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Adrian McCarthy [Tue, 19 Dec 2017 23:34:37 +0000 (23:34 +0000)]
Revert "Fix faulty assertion in debug info"
This reverts commit
e32def3f7ebe1136b7038336eff56a415a962bf2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321125
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Adrian McCarthy [Tue, 19 Dec 2017 23:01:17 +0000 (23:01 +0000)]
Fix faulty assertion in debug info
It appears the code uses nullptr to represent a void type in debug metadata,
which led to an assertion failure when building DeltaAlgorithm.cpp with a
self-hosted clang on Windows.
I'm not sure why/if the problem was Windows-specific.
Fixes bug https://bugs.llvm.org/show_bug.cgi?id=35543
Differential Revision: https://reviews.llvm.org/D41264
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321122
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Craig Topper [Tue, 19 Dec 2017 22:38:09 +0000 (22:38 +0000)]
[X86] Add an assert to indicate that there is only once specific VT allowed at a certain point in LowerMULH.
Helps with code readability a little.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321118
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Adrian Prantl [Tue, 19 Dec 2017 22:05:25 +0000 (22:05 +0000)]
Silence a bunch of implicit fallthrough warnings
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321114
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Francis Visoiu Mistrih [Tue, 19 Dec 2017 21:47:14 +0000 (21:47 +0000)]
[CodeGen] Move printing MO_BlockAddress operands to MachineOperand::print
Work towards the unification of MIR and debug output by refactoring the
interfaces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321113
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Francis Visoiu Mistrih [Tue, 19 Dec 2017 21:47:10 +0000 (21:47 +0000)]
[CodeGen] Move printing MO_IntrinsicID operands to MachineOperand::print
Work towards the unification of MIR and debug output by refactoring the
interfaces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321112
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Francis Visoiu Mistrih [Tue, 19 Dec 2017 21:47:05 +0000 (21:47 +0000)]
[CodeGen] Move printing MO_IntrinsicID operands to MachineOperand::print
Work towards the unification of MIR and debug output by refactoring the
interfaces.
Also add support for printing with a null TargetIntrinsicInfo and no
MachineFunction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321111
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Francis Visoiu Mistrih [Tue, 19 Dec 2017 21:47:00 +0000 (21:47 +0000)]
[CodeGen] Move printing MO_FPImmediate operands to MachineOperand::print
Work towards the unification of MIR and debug output by refactoring the
interfaces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321110
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Francis Visoiu Mistrih [Tue, 19 Dec 2017 21:46:55 +0000 (21:46 +0000)]
[CodeGen] Refactor printOffset from MO and MIRPrinter
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321109
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Haicheng Wu [Tue, 19 Dec 2017 20:53:32 +0000 (20:53 +0000)]
[CGP] Format. NFC
Clang-format.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321107
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Matthias Braun [Tue, 19 Dec 2017 20:24:12 +0000 (20:24 +0000)]
TargetLoweringBase: Fix darwinHasSinCos()
Another followup to my refactoring in r321036: Turns out we can end up
with an x86 darwin target that is not macos (simulator triples can look
like i386-apple-ios) so we need the x86/32bit check in all cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321104
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Jonas Devlieghere [Tue, 19 Dec 2017 19:42:32 +0000 (19:42 +0000)]
[dwarfdump][test] Add test case for r321064
Verify that -lookup takes a 64-bit address.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321101
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Mark Searles [Tue, 19 Dec 2017 19:26:23 +0000 (19:26 +0000)]
[AMDGPU] Turn off MergeConsecutiveStores() before Instruction Selection for AMDGPU. Commit
dbbb6c5fc3642987430866dffdf710df4f616ac7 turned on MergeConsecutiveStores() before Instruction Selection for all targets. Enough AMDGPU compiles go into an infinite loop ( MergeConsecutiveStores() merges two stores; LegalizeStoreOps() un-merges; MergeConsecutiveStores() re-merges, etc. ) to warrant turning it off until the issues can be addressed.
Differential Revision: https://reviews.llvm.org/D41377
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321100
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Haicheng Wu [Tue, 19 Dec 2017 18:49:21 +0000 (18:49 +0000)]
[SeparateConstOffsetFromGEP] Fix a typo. NFC.
do CSE for to => do CSE to
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321098
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Simon Pilgrim [Tue, 19 Dec 2017 18:05:13 +0000 (18:05 +0000)]
[X86] Regenerate popcnt tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321093
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Amara Emerson [Tue, 19 Dec 2017 17:21:35 +0000 (17:21 +0000)]
[GlobalISel][Legalizer] Fix crash when trying to lower G_FNEG of fp128 types.
This doesn't add legalizer support, just prevents crashing so that we
can gracefully fall back to SDAG.
Fixes PR35690.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321091
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Nirav Dave [Tue, 19 Dec 2017 17:10:56 +0000 (17:10 +0000)]
[DAG] Elide overlapping store
Summary:
Extend overlapping store elision to handle overwrites of stores by
larger stores.
Nontemporal tests have been modified to add memory dependencies to
prevent store elision.
Reviewers: craig.topper, rnk, t.p.northover
Subscribers: javed.absar, hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D40969
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321089
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Simon Pilgrim [Tue, 19 Dec 2017 16:54:07 +0000 (16:54 +0000)]
[X86][AVX512] Attempt target shuffle combining to different types instead of early-out
We try to prevent shuffle combining to value types that would stop the folding of masked operations, but by just returning early, we were failing to try different shuffle types.
The TODOs are all still relevant here to improve codegen but we're lacking test examples.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321085
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Francis Visoiu Mistrih [Tue, 19 Dec 2017 16:51:52 +0000 (16:51 +0000)]
[CodeGen] Move printing MO_CFIIndex operands to MachineOperand::print
Work towards the unification of MIR and debug output by refactoring the
interfaces.
Before this patch we printed "<call frame instruction>" in the debug
output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321084
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Francis Visoiu Mistrih [Tue, 19 Dec 2017 15:20:18 +0000 (15:20 +0000)]
[CFGVPrinter] Fix -dot-cfg-only
The refactoring in r281640 made -dot-cfg-only ignore the "-only" part.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321079
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Ben Dunbobbin [Tue, 19 Dec 2017 14:49:33 +0000 (14:49 +0000)]
[ThinLTO][C-API] Correct api comments
Negative values never disabled the pruning - they simply set high values for the pruning interval.
The behaviour now is that negative values set the maximum pruning interval (which appears to have been the intention from the start) see https://reviews.llvm.org/D41231.
I have adjusted the comments to reflect this, removed any inaccurate statements, and corrected any typos I spotted in the English.
Differential Revision: https://reviews.llvm.org/D41279
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321078
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Ben Dunbobbin [Tue, 19 Dec 2017 14:42:38 +0000 (14:42 +0000)]
[Support][CachePruning] Disable cache pruning regression fix
borked by: rL284966 (see: https://reviews.llvm.org/D25730).
Previously, Interval was unsigned (see: CachePruning.h), replacing the type with std::chrono::seconds (which is signed) causes a regression in behaviour because the c-api intends negative values to translate to large positive intervals to *effectively* disable the pruning (see comments on: setCachePruningInterval()).
Differential Revision: https://reviews.llvm.org/D41231
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321077
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Simon Pilgrim [Tue, 19 Dec 2017 14:34:35 +0000 (14:34 +0000)]
[X86] Fix uninitialized variable sanitizer warning from rL321074
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321076
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Haicheng Wu [Tue, 19 Dec 2017 13:42:58 +0000 (13:42 +0000)]
[InlineCost] Skip volatile loads when looking for repeated loads
This is a follow-up fix of r320814. A test case is also added.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321075
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Simon Pilgrim [Tue, 19 Dec 2017 13:16:43 +0000 (13:16 +0000)]
[X86][SSE] Add cpu feature for aggressive combining to variable shuffles
As mentioned in D38318 and D40865, modern Intel processors prefer to combine multiple shuffles to a variable shuffle mask (PSHUFB/VPERMPS etc.) instead of having multiple stage 'fixed' shuffles which put more pressure on Port 5 (at the expense of extra shuffle mask loads).
This patch provides a FeatureFastVariableShuffle target flag for Haswell+ CPUs that prefers combining 2 or more fixed shuffles to a single variable shuffle (default is 3 shuffles).
The long term aim is to drive more of this from schedule data (probably via the MC) but we're not close to being ready for that yet.
Differential Revision: https://reviews.llvm.org/D41323
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321074
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David Green [Tue, 19 Dec 2017 12:19:08 +0000 (12:19 +0000)]
[ARM] Register the Thumb2SizeReducePass. NFC
Also adds a simple test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321072
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