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David Zarzycki [Tue, 4 Jun 2019 11:33:49 +0000 (11:33 +0000)]
Unbreak my hasty "unbreak" cmake fix
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362492
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Peter Smith [Tue, 4 Jun 2019 11:28:22 +0000 (11:28 +0000)]
[AARCH64][ELF][llvm-readobj] Support for AArch64 .note.gnu.property
ELF for the 64-bit Arm Architecture defines a processor specific property
type GNU_PROPERTY_AARCH64_FEATURE_1_AND as GNU_PROPERTY_LOPROC. This
property works in a similar way to the existing X86 processor specific
property GNU_PROPERTY_GNU_X86_FEATURE_1_AND.
Two feature bits are defined for GNU_PROPERTY_AARCH64_FEATURE_1_AND:
- GNU_PROPERTY_AARCH64_FEATURE_1_BTI 0x1
- GNU_PROPERTY_AARCH64_FEATURE_1_PAC 0x2
This patch defines the property, feature bits and implements support for
printing in llvm-readobj.
Differential Revision: https://reviews.llvm.org/D62595
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362490
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Roman Lebedev [Tue, 4 Jun 2019 11:06:21 +0000 (11:06 +0000)]
[DAGCombine][X86][AArch64][MIPS][LANAI] (C - x) - y -> C - (x + y) fold (PR41952)
Summary:
This *might* be the last fold for `sink-addsub-of-const.ll`, but i'm not sure yet.
As far as i can tell, there are no regressions here (ignoring x86-32),
all changes are either good or neutral.
This, almost surprisingly to me, fixes the motivational tests (in `shift-amount-mod.ll`)
`@reg32_lshr_by_sub_from_negated` from [[ https://bugs.llvm.org/show_bug.cgi?id=41952 | PR41952 ]].
https://rise4fun.com/Alive/vMd3
Reviewers: RKSimon, t.p.northover, craig.topper, spatel, efriedma
Reviewed By: RKSimon
Subscribers: sdardis, javed.absar, arichardson, kristof.beyls, jrtc27, atanasyan, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62774
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362488
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Roman Lebedev [Tue, 4 Jun 2019 11:06:08 +0000 (11:06 +0000)]
[DAGCombine][X86][AArch64][ARM] (C - x) + y -> (y - x) + C fold
Summary:
All changes except ARM look **great**.
https://rise4fun.com/Alive/R2M
The regression `test/CodeGen/ARM/addsubcarry-promotion.ll`
is recovered fully by D62392 + D62450.
Reviewers: RKSimon, craig.topper, spatel, rogfer01, efriedma
Reviewed By: efriedma
Subscribers: dmgreen, javed.absar, kristof.beyls, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62266
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362487
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Simon Pilgrim [Tue, 4 Jun 2019 10:49:06 +0000 (10:49 +0000)]
[SelectionDAG] ComputeNumSignBits - support constant pool values from target
As I mentioned on D61887 we don't get many hits on ComputeNumSignBits as we did on computeKnownBits.
The case we do get is interesting though - it allows us to use the 'ConditionalNegate' combine in combineLogicBlendIntoPBLENDV to remove a select.
It comes too late for SSE41 (BLENDV) cases, but SSE2 tests can hit it now. We should probably try to make use of this for SSE41+ targets as well - avoiding variable blends is usually a good idea. I'll investigate as a followup.
Differential Revision: https://reviews.llvm.org/D62777
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362486
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Simon Pilgrim [Tue, 4 Jun 2019 10:17:56 +0000 (10:17 +0000)]
[SelectionDAG] ComputeNumSignBits - clang-format + improve *EXTLOAD comments. NFCI.
Pre-commit requested for D62777.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362485
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Owen Reynolds [Tue, 4 Jun 2019 10:13:03 +0000 (10:13 +0000)]
[llvm-ar] Reapply Fix relative thin archive path handling
Includes a fix for an introduced build failure due to a post c++11 use of std::mismatch.
This fixes some thin archive relative path issues, paths are shortened where possible and paths are output correctly when using the display table command.
Differential Revision: https://reviews.llvm.org/D59491
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362484
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Simon Pilgrim [Tue, 4 Jun 2019 10:04:55 +0000 (10:04 +0000)]
[SelectionDAG] Add fpto[us]i(undef) --> undef constant fold
Follow up to D62807.
Differential Revision: https://reviews.llvm.org/D62811
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362483
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Mikhail Maltsev [Tue, 4 Jun 2019 09:39:55 +0000 (09:39 +0000)]
[ARM] Add FP16 vector insert/extract patterns
This change adds two FP16 extraction and two insertion patterns
(one per possible vector length).
Extractions are handled by copying a Q/D register into one of VFP2
class registers, where single FP32 sub-registers can be accessed. Then
the extraction of even lanes are simple sub-register extractions
(because we don't care about the top parts of registers for FP16
operations). Odd lanes need an additional VMOVX instruction.
Unfortunately, insertions cannot be handled in the same way, because:
* There is no instruction to insert FP16 into an even lane (VINS only
works with odd lanes)
* The patterns for odd lanes will have a form of a DAG (not a tree),
and will not be implementable in pure tablegen
Because of this insertions are handled in the same way as 16-bit
integer insertions (with conversions between FP registers and GPRs
using VMOVHR instructions).
Without these patterns the ARM backend would sometimes fail during
instruction selection.
This patch also adds patterns which combine:
* an FP16 element extraction and a store into a single VST1
instruction
* an FP16 load and insertion into a single VLD1 instruction
Differential Revision: https://reviews.llvm.org/D62651
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362482
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Dmitri Gribenko [Tue, 4 Jun 2019 09:31:07 +0000 (09:31 +0000)]
Silenced a warning "implicit conversion turns string literal into bool" introduced in r362473
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362480
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Dmitri Gribenko [Tue, 4 Jun 2019 09:16:35 +0000 (09:16 +0000)]
Include what you use in PPC.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362477
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Dmitri Gribenko [Tue, 4 Jun 2019 09:16:31 +0000 (09:16 +0000)]
Include what you use in PPCMachineScheduler.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362476
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Dmitri Gribenko [Tue, 4 Jun 2019 09:13:08 +0000 (09:13 +0000)]
Include what you use in PPCRegisterInfo.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362475
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Eugene Leviant [Tue, 4 Jun 2019 09:04:53 +0000 (09:04 +0000)]
[HWASAN][CMake] Allow instrumenting LLVM/clang
Differential revision: https://reviews.llvm.org/D62813
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362474
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Yevgeny Rouban [Tue, 4 Jun 2019 09:03:39 +0000 (09:03 +0000)]
Make SwitchInstProfUpdateWrapper safer
While prof branch_weights inconsistencies are being fixed patch
by patch (pass by pass) we need SwitchInstProfUpdateWrapper to
be safe with respect to inconsistent metadata that can come from
passes that have not been fixed yet. See the bug found by @nikic
in https://reviews.llvm.org/D62126.
This patch introduces one more state (called Invalid) to the
wrapper class that allows users to work with the underlying
SwitchInst ignoring the prof metadata changes.
Created a unit test for the SwitchInstProfUpdateWrapper class.
Reviewers: davidx, nikic, eraman, reames, chandlerc
Reviewed By: davidx
Differential Revision: https://reviews.llvm.org/D62656
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362473
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QingShan Zhang [Tue, 4 Jun 2019 08:53:53 +0000 (08:53 +0000)]
[DAGCombine] Match a pattern where a wide type scalar value is stored by several narrow stores
This opportunity is found from spec 2017 557.xz_r. And it is used by the sha encrypt/decrypt. See sha-2/sha512.c
static void store64(u64 x, unsigned char* y)
{
for(int i = 0; i != 8; ++i)
y[i] = (x >> ((7-i) * 8)) & 255;
}
static u64 load64(const unsigned char* y)
{
u64 res = 0;
for(int i = 0; i != 8; ++i)
res |= (u64)(y[i]) << ((7-i) * 8);
return res;
}
The load64 has been implemented by https://reviews.llvm.org/D26149
This patch is trying to implement the store pattern.
Match a pattern where a wide type scalar value is stored by several narrow
stores. Fold it into a single store or a BSWAP and a store if the targets
supports it.
Assuming little endian target:
i8 *p = ...
i32 val = ...
p[0] = (val >> 0) & 0xFF;
p[1] = (val >> 8) & 0xFF;
p[2] = (val >> 16) & 0xFF;
p[3] = (val >> 24) & 0xFF;
>
*((i32)p) = val;
i8 *p = ...
i32 val = ...
p[0] = (val >> 24) & 0xFF;
p[1] = (val >> 16) & 0xFF;
p[2] = (val >> 8) & 0xFF;
p[3] = (val >> 0) & 0xFF;
>
*((i32)p) = BSWAP(val);
Differential Revision: https://reviews.llvm.org/D61843
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362472
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QingShan Zhang [Tue, 4 Jun 2019 08:45:07 +0000 (08:45 +0000)]
[NFC] Update the test to check the endianness after the CodeGenPrepare instead of checking the assembly instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362471
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Simon Tatham [Tue, 4 Jun 2019 08:28:48 +0000 (08:28 +0000)]
[ARM] Turn some undefined encoding bits into 0s.
The family of 32-bit Thumb instruction encodings that include t2ORR,
t2AND and t2EOR are all listed in the ArmARM as having (0) in bit 15.
The Tablegen descriptions of those instructions listed them as ?. This
change tightens that up by making them into 0 + Unpredictable.
In the specific case of t2ORR, we tighten it up still further by
making the zero bit mandatory. This change comes from Arm v8.1-M, in
which encodings with that bit equal to 1 will now be used for
different instructions.
Reviewers: dmgreen, samparker, SjoerdMeijer, efriedma
Reviewed By: dmgreen, efriedma
Subscribers: efriedma, javed.absar, kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D60705
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362470
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Chen Zheng [Tue, 4 Jun 2019 06:48:14 +0000 (06:48 +0000)]
[PowerPC] add testcases for reordering LSR and PPCCTRLoops - NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362468
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Roman Lebedev [Mon, 3 Jun 2019 23:00:51 +0000 (23:00 +0000)]
[NFC][X86] Fixup FileCheck prefixes - drop duplicates
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362460
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Craig Topper [Mon, 3 Jun 2019 22:34:15 +0000 (22:34 +0000)]
[X86] Add test cases for 32 and 64 bit versions of PR42118. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362457
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Roman Lebedev [Mon, 3 Jun 2019 22:30:18 +0000 (22:30 +0000)]
[NFC][Codegen] Add tests for hoisting and-by-const from "logical shift", when then eq-comparing with 0
This was initially reported as: https://reviews.llvm.org/D62818
https://rise4fun.com/Alive/oPH
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362455
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Jason Liu [Mon, 3 Jun 2019 22:22:03 +0000 (22:22 +0000)]
Fix DWARF DebugInfo unit test errors when cross-compiling
Summary:
When building with a Default Target set we can experience issues
in the DWARF DebugInfo unit tests because:
They assume we can generate object files for the host platform.
Some tests assume the endianess of the target we are generating
DWARF for and the host match.
This patch correct these issues by ensuring the tests which
generate objects in memory are run with respect to
LVM_DEFAULT_TARGET_TRIPLE and it's endianess.
We also make sure we don't use the hosts address size for line test
and split the triple util function in DwarfUtils into a version
that takes an address size and one that doesn't.
See also for discussion:
http://lists.llvm.org/pipermail/llvm-dev/2019-March/131212.html
Patch by: daltenty
Differential Revision: https://reviews.llvm.org/D62084
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362454
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Craig Topper [Mon, 3 Jun 2019 22:14:54 +0000 (22:14 +0000)]
Revert r362451 "foo" and r362452 "[X86] Add test cases for 32 and 64 bit versions of PR42118. NFC"
I failed to squash these properly
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362453
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Craig Topper [Mon, 3 Jun 2019 22:11:40 +0000 (22:11 +0000)]
[X86] Add test cases for 32 and 64 bit versions of PR42118. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362452
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Craig Topper [Mon, 3 Jun 2019 22:11:30 +0000 (22:11 +0000)]
foo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362451
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Lang Hames [Mon, 3 Jun 2019 22:02:48 +0000 (22:02 +0000)]
[ORC] Use uint8_t for bitfields in SymbolTableEntry.
This allows for better struct packing on MSVC, and as a bonus will eliminate a
warning on GCC builds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362450
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Cameron McInally [Mon, 3 Jun 2019 21:53:56 +0000 (21:53 +0000)]
[SCCP] Add UnaryOperator visitor to SCCP for unary FNeg
Differential Revision: https://reviews.llvm.org/D62819
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362449
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Michael Berg [Mon, 3 Jun 2019 21:53:26 +0000 (21:53 +0000)]
Propagate fmf for setcc in SDAG for select folds
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362448
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Matt Arsenault [Mon, 3 Jun 2019 21:33:22 +0000 (21:33 +0000)]
AMDGPU: Disable stack realignment for kernels
This is something of a workaround, and the state of stack realignment
controls is kind of a mess. Ideally, we would be able to specify the
stack is infinitely aligned on entry to a kernel.
TargetFrameLowering provides multiple controls which apply at
different points. The StackRealignable field is used during
SelectionDAG, and for some reason distinct from this
hook. StackAlignment is a single field not dependent on the
function. It would probably be better to make that dependent on the
calling convention, and the maximum value for kernels.
Currently this doesn't really change anything, since the frame
lowering mostly does its own thing. This helps avoid regressions in a
future change which will rely more heavily on hasFP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362447
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Jessica Paquette [Mon, 3 Jun 2019 20:47:20 +0000 (20:47 +0000)]
[AArch64][GlobalISel] Optimize G_FCMP + G_SELECT pairs when G_SELECT is fp
Instead of emitting all of the test stuff for a compare when it's only used by
a select, instead, just emit the compare + select. The select will use the
value of NZCV correctly, so we don't need to emit all of the test instructions
etc.
For now, only support fp selects which use G_FCMP. Also only support condition
codes which will only require one select to represent.
Also add a test.
Differential Revision: https://reviews.llvm.org/D62695
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362446
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Peter Collingbourne [Mon, 3 Jun 2019 20:40:07 +0000 (20:40 +0000)]
gn build: Merge r361896.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362445
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George Burgess IV [Mon, 3 Jun 2019 19:56:22 +0000 (19:56 +0000)]
CFLAA: reflow comments; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362442
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Craig Topper [Mon, 3 Jun 2019 19:35:52 +0000 (19:35 +0000)]
[CFLGraph] Add FAdd to visitConstantExpr.
This looks like an oversight as all the other binary operators are present.
Accidentally noticed while auditing places that need FNeg handling.
No test because as noted in the review it would be contrived and amount to "don't crash"
Differential Revision: https://reviews.llvm.org/D62790
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362441
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Craig Topper [Mon, 3 Jun 2019 19:29:14 +0000 (19:29 +0000)]
[X86] Fix the pattern for merge masked vcvtps2pd.
r362199 fixed it for zero masking, but not zero masking. The load
folding in the peephole pass hid the bug. This patch turns off
the peephole pass on the relevant test to ensure coverage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362440
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Michael Berg [Mon, 3 Jun 2019 19:12:15 +0000 (19:12 +0000)]
Propagate fmf for setcc/select folds
Summary: This change facilitates propagating fmf which was placed on setcc from fcmp through folds with selects so that back ends can model this path for arithmetic folds on selects in SDAG.
Reviewers: qcolombet, spatel
Reviewed By: qcolombet
Subscribers: nemanjai, jsji
Differential Revision: https://reviews.llvm.org/D62552
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362439
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Nemanja Ivanovic [Mon, 3 Jun 2019 19:09:15 +0000 (19:09 +0000)]
[PowerPC] Look through copies for compare elimination
We currently miss the opportunities for optmizing comparisons in the peephole
optimizer if the input is the result of a COPY since we look for record-form
versions of the producing instruction.
This patch simply lets the optimization peek through copies.
Differential revision: https://reviews.llvm.org/D59633
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362438
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Matt Arsenault [Mon, 3 Jun 2019 18:41:34 +0000 (18:41 +0000)]
TTI: Improve default costs for addrspacecast
For some reason multiple places need to do this, and the variant the
loop unroller and inliner use was not handling it.
Also, introduce a new wrapper to be slightly more precise, since on
AMDGPU some addrspacecasts are free, but not no-ops.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362436
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Nico Weber [Mon, 3 Jun 2019 18:29:00 +0000 (18:29 +0000)]
gn build: Merge r362371
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362433
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Artur Pilipenko [Mon, 3 Jun 2019 18:26:45 +0000 (18:26 +0000)]
Add ScalarEvolutionsTest::SCEVExpandInsertCanonicalIV tests
Test insertion of canonical IV in canonical expansion mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362432
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Nikita Popov [Mon, 3 Jun 2019 18:19:54 +0000 (18:19 +0000)]
[ConstantRange] Add sdiv() support
The implementation is conceptually simple: We separate the LHS and
RHS into positive and negative components and then also compute the
positive and negative components of the result, taking into account
that e.g. only pos/pos and neg/neg will give a positive result.
However, there's one significant complication: SignedMin / -1 is UB
for sdiv, and we can't just ignore it, because the APInt result of
SignedMin would break the sign segregation. Instead we drop SignedMin
or -1 from the corresponding ranges, taking into account some edge
cases with wrapped ranges.
Because of the sign segregation, the implementation ends up being
nearly fully precise even for wrapped ranges (the remaining
imprecision is due to ranges that are both signed and unsigned
wrapping and are divided by a trivial divisor like 1). This means
that the testing cannot just check the signed envelope as we
usually do. Instead we collect all possible results in a bitvector
and construct a better sign wrapped range (than the full envelope).
Differential Revision: https://reviews.llvm.org/D61238
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362430
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Reid Kleckner [Mon, 3 Jun 2019 18:15:38 +0000 (18:15 +0000)]
[PDB] Copy inlinee lines records into the PDB
Summary:
- Fixes inline call frame line table display in windbg.
- Improve llvm-pdbutil to dump extra file ids.
- Warn on unknown subsections so we don't have this kind of bug in the
future.
Reviewers: inglorion, akhuang, aganea
Subscribers: eraman, zturner, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62701
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362429
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Nico Weber [Mon, 3 Jun 2019 18:13:29 +0000 (18:13 +0000)]
gn build: Merge r362352
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362428
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Andrew Kaylor [Mon, 3 Jun 2019 17:54:15 +0000 (17:54 +0000)]
Fix a crash when the default of a switch is removed
This patch fixes a problem that occurs in LowerSwitch when a switch statement has a PHI node as its condition, and the PHI node only has two incoming blocks, and one of those incoming blocks is through an unreachable default in the switch statement. When this condition occurs, LowerSwitch holds a pointer to the condition value, but removes the switch block as a predecessor of the PHI block, causing the PHI node to be replaced. LowerSwitch then tries to use its stale pointer to the original condition value, causing a crash.
Differential Revision: https://reviews.llvm.org/D62560
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362427
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Philip Reames [Mon, 3 Jun 2019 17:41:12 +0000 (17:41 +0000)]
[Tests] Add LFTR tests for multiple exit loops (try 2)
(Recommit after fixing a keymash in the run line. Sorry for breakage.)
This is preparation for D62625 <https://reviews.llvm.org/D62625>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362426
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96231b3b80d8
Saleem Abdulrasool [Mon, 3 Jun 2019 17:17:09 +0000 (17:17 +0000)]
tools: add `llvm-nm` and `llvm-objcopy` to tools
Add `nm` and `objcopy` to the default value for the tools that we install now
that they are sufficiently feature complete to replace bintuils' implementation.
Patch by Jiang Yi!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362425
91177308-0d34-0410-b5e6-
96231b3b80d8
Dmitri Gribenko [Mon, 3 Jun 2019 17:02:15 +0000 (17:02 +0000)]
Include what you use in Lanai.h
Other files were not relying on these transitive includes, so I'm
submitting this change separately.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362423
91177308-0d34-0410-b5e6-
96231b3b80d8
Dmitri Gribenko [Mon, 3 Jun 2019 17:02:07 +0000 (17:02 +0000)]
Include what you use in LanaiAsmPrinter.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362422
91177308-0d34-0410-b5e6-
96231b3b80d8
Dmitri Gribenko [Mon, 3 Jun 2019 17:02:02 +0000 (17:02 +0000)]
Include what you use in LanaiMemAluCombiner.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362421
91177308-0d34-0410-b5e6-
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Dmitri Gribenko [Mon, 3 Jun 2019 17:01:57 +0000 (17:01 +0000)]
Include what you use in LanaiISelDAGToDAG.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362420
91177308-0d34-0410-b5e6-
96231b3b80d8
Dmitri Gribenko [Mon, 3 Jun 2019 17:01:52 +0000 (17:01 +0000)]
Include what you use in LanaiFrameLowering.{cpp,h}
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362419
91177308-0d34-0410-b5e6-
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Dmitri Gribenko [Mon, 3 Jun 2019 16:58:11 +0000 (16:58 +0000)]
Revert "[Tests] Add LFTR tests for multiple exit loops"
This reverts commit r362417. There's a syntax error in the RUN line.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362418
91177308-0d34-0410-b5e6-
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Philip Reames [Mon, 3 Jun 2019 16:46:03 +0000 (16:46 +0000)]
[Tests] Add LFTR tests for multiple exit loops
This is preparation for D62625
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362417
91177308-0d34-0410-b5e6-
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Dmitri Gribenko [Mon, 3 Jun 2019 16:31:37 +0000 (16:31 +0000)]
Include what you use in LanaiRegisterInfo.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362416
91177308-0d34-0410-b5e6-
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Philip Reames [Mon, 3 Jun 2019 16:23:20 +0000 (16:23 +0000)]
[LoopPred] Convert a second member function to a static helper [NFC]
(And remember to actually mark the first one static.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362415
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Mon, 3 Jun 2019 16:21:58 +0000 (16:21 +0000)]
[WebAssembly] Remove fptosi(undef) and fptoui(undef) from reduced test case.
Pre-commit for D62811 - which adds DAG fpto[us]i(undef) --> undef constant fold
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362414
91177308-0d34-0410-b5e6-
96231b3b80d8
Dmitri Gribenko [Mon, 3 Jun 2019 16:21:37 +0000 (16:21 +0000)]
Revert "[llvm-ar] Fix relative thin archive path handling"
This reverts commit r362407. It broke compilation of
llvm/lib/Object/ArchiveWriter.cpp:
error: type 'llvm::sys::path::const_iterator' does not provide a call
operator
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362413
91177308-0d34-0410-b5e6-
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Nemanja Ivanovic [Mon, 3 Jun 2019 16:20:59 +0000 (16:20 +0000)]
[PowerPC] Set PROT_READ flag for MF_EXEC to prevent segfaults on PPC machines
The big endian PPC buildbots are all failing now due to calls to cache
invalidation in unit tests on data that has only the PROT_EXEC flag set.
This has been an issue all along on FreeBSD but it can affect Linux machines
depending on configuration.
This patch mitigates the issue the same way it is mitigated on FreeBSD.
Since this is needed to bring the buildbots back to green, I plan to commit this
and allow for post-commit review, but I thought I would also post it here for
ease of access/readability.
Differential revision: https://reviews.llvm.org/D62741
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362412
91177308-0d34-0410-b5e6-
96231b3b80d8
Philip Reames [Mon, 3 Jun 2019 16:17:14 +0000 (16:17 +0000)]
[LoopPred] Convert member function to free helper function [NFC]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362411
91177308-0d34-0410-b5e6-
96231b3b80d8
Dmitri Gribenko [Mon, 3 Jun 2019 15:26:25 +0000 (15:26 +0000)]
Include what you use in LanaiInstrInfo.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362408
91177308-0d34-0410-b5e6-
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Owen Reynolds [Mon, 3 Jun 2019 15:26:07 +0000 (15:26 +0000)]
[llvm-ar] Fix relative thin archive path handling
This fixes some thin archive relative path issues, paths are shortened where possible and paths are output correctly when using the display table command.
Differential Revision: https://reviews.llvm.org/D59491
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362407
91177308-0d34-0410-b5e6-
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Dmitri Gribenko [Mon, 3 Jun 2019 15:04:05 +0000 (15:04 +0000)]
Include what you use in PPCInstrInfo.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362405
91177308-0d34-0410-b5e6-
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Michal Gorny [Mon, 3 Jun 2019 14:50:03 +0000 (14:50 +0000)]
[llvm] [test] Remove non-portable EISDIR test from macho-disassemble-g-dsym.test
Remove the test checking error message for 'is a directory'. It does
not seem to serve any real purpose, and it relies on matching platform
error strings which are unpredictable and makes the test fragile.
Furthermore, it fails on NetBSD where read() works on directories,
and therefore does not return EISDIR at all.
Fixes r362141.
Differential Revision: https://reviews.llvm.org/D62773
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362404
91177308-0d34-0410-b5e6-
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Dmitri Gribenko [Mon, 3 Jun 2019 14:37:26 +0000 (14:37 +0000)]
Include what you use in NVPTX.h
Other files were not relying on these transitive includes, so I'm
submitting this change separately.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362403
91177308-0d34-0410-b5e6-
96231b3b80d8
Dmitri Gribenko [Mon, 3 Jun 2019 14:26:50 +0000 (14:26 +0000)]
Include what you use in NVPTX.h
I also fixed all other files that were including NVPTX.h and were
relying on transitive includes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362402
91177308-0d34-0410-b5e6-
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Dmitry Preobrazhensky [Mon, 3 Jun 2019 13:51:24 +0000 (13:51 +0000)]
[AMDGPU][MC] Added support of SCC, VCCZ and EXECZ operands
See bug 39292: https://bugs.llvm.org/show_bug.cgi?id=39292
Reviewers: rampitec, arsenm
Differential Revision: https://reviews.llvm.org/D62660
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362400
91177308-0d34-0410-b5e6-
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David Zarzycki [Mon, 3 Jun 2019 13:39:49 +0000 (13:39 +0000)]
Unbreak non-PIC builds after r362390 / D62720
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362399
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Mon, 3 Jun 2019 13:02:07 +0000 (13:02 +0000)]
[SelectionDAG] Add [us]itofp(undef) --> 0 constant fold (PR39205)
We were missing this fold in the DAG, which I've copied directly from llvm::ConstantFoldCastInstruction
Differential Revision: https://reviews.llvm.org/D62807
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362397
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Mon, 3 Jun 2019 12:58:36 +0000 (12:58 +0000)]
[SystemZ] Remove sitofp(undef) from reduced test case.
Pre-commit for D62807 - which adds DAG [us]itofp(undef) --> 0 constant fold
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362396
91177308-0d34-0410-b5e6-
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Dmitri Gribenko [Mon, 3 Jun 2019 12:53:05 +0000 (12:53 +0000)]
Include what you use in LanaiInstPrinter.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362395
91177308-0d34-0410-b5e6-
96231b3b80d8
Dmitri Gribenko [Mon, 3 Jun 2019 12:42:48 +0000 (12:42 +0000)]
Include what you use in LanaiMCCodeEmitter.cpp
LanaiMCCodeEmitter.cpp was not using any APIs from Lanai.h, and was only
including it for transitive dependencies. Doing so is problematic from
include-what-you-use perspective, but it is also a layering issue (it
creates a dependency cycle between the primary Lanai target library and
the MCTargetDesc library).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362394
91177308-0d34-0410-b5e6-
96231b3b80d8
Dmitri Gribenko [Mon, 3 Jun 2019 12:37:11 +0000 (12:37 +0000)]
Include what you use in LanaiDisassembler.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362392
91177308-0d34-0410-b5e6-
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Nicolai Haehnle [Mon, 3 Jun 2019 12:07:41 +0000 (12:07 +0000)]
AMDGPU/GFX10: V_CMPX_xxx instructions still have an omod operand
Summary: Change-Id: If6ee98e4a723b643bc37254fc6ef8b3812db16da
Reviewers: rampitec
Subscribers: arsenm, kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62720
Change-Id: Id547ef152b2f92b24dc1c0efbf7e4467c4fb4b6e
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362390
91177308-0d34-0410-b5e6-
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Dmitri Gribenko [Mon, 3 Jun 2019 11:41:22 +0000 (11:41 +0000)]
Include what you use in HexagonInstPrinter.cpp
HexagonInstPrinter.cpp was not using any APIs from HexagonAsmPrinter.h.
Doing so is problematic from include-what-you-use perspective, but it is
also a layering issue (it creates a dependency cycle between the primary
Hexagon target library and the MCTargetDesc library).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362389
91177308-0d34-0410-b5e6-
96231b3b80d8
Dmitri Gribenko [Mon, 3 Jun 2019 11:41:18 +0000 (11:41 +0000)]
Include what you use in HexagonAsmPrinter.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362388
91177308-0d34-0410-b5e6-
96231b3b80d8
Dmitri Gribenko [Mon, 3 Jun 2019 11:25:37 +0000 (11:25 +0000)]
Include what you use in HexagonMCInstrInfo.cpp
HexagonMCInstrInfo.cpp was not using any APIs from Hexagon.h. Doing so
is problematic from include-what-you-use perspective, but it is also a
layering issue (it creates a dependency cycle between the primary
Hexagon target library and the MCTargetDesc library).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362387
91177308-0d34-0410-b5e6-
96231b3b80d8
Dmitri Gribenko [Mon, 3 Jun 2019 11:20:53 +0000 (11:20 +0000)]
Include what you use in HexagonMCCodeEmitter.cpp
HexagonMCCodeEmitter.cpp was not using any APIs from Hexagon.h. Doing
so is problematic from include-what-you-use perspective, but it is also
a layering issue (it creates a dependency cycle between the primary
Hexagon target library and the MCTargetDesc library).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362386
91177308-0d34-0410-b5e6-
96231b3b80d8
Dmitri Gribenko [Mon, 3 Jun 2019 11:20:48 +0000 (11:20 +0000)]
Include what you use in HexagonMCCompound.cpp
HexagonMCCompound.cpp was not using any APIs from Hexagon.h. Doing so
is problematic from include-what-you-use perspective, but it is also a
layering issue (it creates a dependency cycle between the primary
Hexagon target library and the MCTargetDesc library).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362385
91177308-0d34-0410-b5e6-
96231b3b80d8
Dmitri Gribenko [Mon, 3 Jun 2019 11:14:20 +0000 (11:14 +0000)]
Include what you use in HexagonShuffler.cpp
HexagonShuffler.cpp was not using any APIs from Hexagon.h, and was only
including it for transitive dependencies. Doing so is problematic from
include-what-you-use perspective, but it is also a layering issue (it
creates a dependency cycle between the primary Hexagon target library
and the MCTargetDesc library).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362384
91177308-0d34-0410-b5e6-
96231b3b80d8
Dmitri Gribenko [Mon, 3 Jun 2019 11:14:15 +0000 (11:14 +0000)]
Include what you use in HexagonMCChecker.cpp
HexagonMCChecker.cpp was not using any APIs from Hexagon.h. Doing so is
problematic from include-what-you-use perspective, but it is also a
layering issue (it creates a dependency cycle between the primary
Hexagon target library and the MCTargetDesc library).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362383
91177308-0d34-0410-b5e6-
96231b3b80d8
Dmitri Gribenko [Mon, 3 Jun 2019 11:14:10 +0000 (11:14 +0000)]
Include what you use in HexagonMCTargetDesc.cpp
HexagonMCTargetDesc.cpp was not using any APIs from Hexagon.h. Doing so
is problematic from include-what-you-use perspective, but it is also a
layering issue (it creates a dependency cycle between the primary
Hexagon target library and the MCTargetDesc library).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362382
91177308-0d34-0410-b5e6-
96231b3b80d8
Dmitri Gribenko [Mon, 3 Jun 2019 11:14:05 +0000 (11:14 +0000)]
Include what you use in HexagonMCShuffler.cpp
HexagonMCShuffler.cpp was not using any APIs from Hexagon.h. Doing so
is problematic from include-what-you-use perspective, but it is also a
layering issue (it creates a dependency cycle between the primary
Hexagon target library and the MCTargetDesc library).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362381
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Tatham [Mon, 3 Jun 2019 11:02:53 +0000 (11:02 +0000)]
[ARM] Fix recent breakage of -mfpu=none.
The recent change D60691 introduced a bug in clang when handling
option combinations such as `-mcpu=cortex-m4 -mfpu=none`. Those
options together should select Cortex-M4 but disable all use of
hardware FP, but in fact, now hardware FP instructions can still be
generated in that mode.
The reason is because the handling of FPUVersion::NONE disables all
the same feature names it used to, of which the base one is `vfp2`.
But now there are further features below that, like `vfp2d16fp` and
(following D60694) `fpregs`, which also need to be turned off to
disable hardware FP completely.
Added a tiny test which double-checks that compiling a simple FP
function doesn't access the FP registers.
Reviewers: SjoerdMeijer, dmgreen
Reviewed By: dmgreen
Subscribers: lebedev.ri, javed.absar, kristof.beyls, hiraditya, cfe-commits, llvm-commits
Tags: #clang, #llvm
Differential Revision: https://reviews.llvm.org/D62729
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362380
91177308-0d34-0410-b5e6-
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Cullen Rhodes [Mon, 3 Jun 2019 10:42:02 +0000 (10:42 +0000)]
[AArch64][SVE2] Add CPU and arch directive tests
Summary:
This patch adds tests for directives .arch, .arch_extension and .cpu for
all features defined in Arm SVE2 architecture extension.
Reviewed By: chill
Differential Revision: https://reviews.llvm.org/D62602
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362378
91177308-0d34-0410-b5e6-
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George Rimar [Mon, 3 Jun 2019 09:58:41 +0000 (09:58 +0000)]
[llvm-readobj] - Convert gnu-sections.test to use YAML.
gnu-sections.test currently use relocs.obj.elf-x86_64 and
relocs.obj.elf-i386 precompiled objects as an inputs.
These inputs actually initially were introduced to test the
dump of relocations and have almost nothing common with dumping
sections.
Patch converts the test to use yaml2obj. That allows to remove
relocs.obj.elf-i386 binary.
(relocs.obj.elf-x86_64 is still used by another test and can't be removed atm).
Differential revision: https://reviews.llvm.org/D62659
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362377
91177308-0d34-0410-b5e6-
96231b3b80d8
Dmitri Gribenko [Mon, 3 Jun 2019 09:56:40 +0000 (09:56 +0000)]
Include what you use in HexagonELFObjectWriter.cpp
HexagonELFObjectWriter.cpp was not using any APIs from Hexagon.h, and
was only including it for transitive dependencies. Doing so is
problematic from include-what-you-use perspective, but it is also a
layering issue (it creates a dependency cycle between the primary
Hexagon target library and the MCTargetDesc library).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362376
91177308-0d34-0410-b5e6-
96231b3b80d8
George Rimar [Mon, 3 Jun 2019 09:52:32 +0000 (09:52 +0000)]
[llvm-readobj/llvm-readelf] - Remove gnu-relocations.test completely.
rL362089 introduced a set of yaml based reloc-types-*.test test cases
(instead of huge reloc-types.test that used a lot of precompiled binaries)
These test cases checks LLVM-styled dumping of the relocations.
gnu-relocations.test was a test case to check GNU styled relocations dumping.
It did that only for elf-x86 and elf-x86_64 targets. It did not test all of the
relocations though.
Now, after rL362089, it does not make sence to keep it.
This patch updates reloc-types-elf-i386.test and reloc-types-elf-x64.test tests
with llvm-readelf calls to check GNU styled output in one place.
It removes gnu-relocations.test completely.
One of intentions of doing this is also to get rid of relocs.obj.elf-i386 and
relocs.obj.elf-x86_64 precompiled objects completely (they are used in other tests still).
Differential revision: https://reviews.llvm.org/D62655
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362374
91177308-0d34-0410-b5e6-
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Nikola Prica [Mon, 3 Jun 2019 09:48:29 +0000 (09:48 +0000)]
[LiveDebugValues] Close range for previous variable's location when adding newly deduced location
When LiveDebugValues deduces new variable's location from spill, restore or
register copy instruction it should close old variable's location. Otherwise
we can have multiple block output locations for same variable. That could lead
to inserting two DBG_VALUEs for same variable to the beginning of the successor
block which results to ignoring of first DBG_VALUE.
Reviewers: aprantl, jmorse, wolfgangp, dstenb
Reviewed By: aprantl
Subscribers: probinson, asowda, ivanbaev, petarj, djtodoro
Tags: #debug-info
Differential Revision: https://reviews.llvm.org/D62196
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362373
91177308-0d34-0410-b5e6-
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Dmitri Gribenko [Mon, 3 Jun 2019 09:43:05 +0000 (09:43 +0000)]
Include what you use in HexagonAsmBackend.cpp
HexagonAsmBackend.cpp was not using any APIs from Hexagon.h. Doing so
is problematic from include-what-you-use perspective, but it is also a
layering issue (it creates a dependency cycle between the primary
Hexagon target library and the MCTargetDesc library).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362372
91177308-0d34-0410-b5e6-
96231b3b80d8
Dmitri Gribenko [Mon, 3 Jun 2019 09:38:48 +0000 (09:38 +0000)]
Include what you use in HexagonAsmParser.cpp
HexagonAsmParser.cpp was not using any APIs from Hexagon.h. Doing so is
problematic from include-what-you-use perspective, but it is also a
layering issue (it creates a dependency cycle between the primary
Hexagon target library and the AsmParser library).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362370
91177308-0d34-0410-b5e6-
96231b3b80d8
Dmitri Gribenko [Mon, 3 Jun 2019 09:33:48 +0000 (09:33 +0000)]
Include what you use in HexagonShuffler.h
HexagonShuffler.h was not using any APIs from Hexagon.h, and was only
including it for transitive dependencies. Doing so is problematic from
include-what-you-use perspective, but it is also a layering issue (it
creates a dependency cycle between the primary Hexagon target library
and the MCTargetDesc library).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362369
91177308-0d34-0410-b5e6-
96231b3b80d8
Dmitri Gribenko [Mon, 3 Jun 2019 09:29:51 +0000 (09:29 +0000)]
Include what you use in BPFMCTargetDesc.cpp
BPFMCTargetDesc.cpp was not using any APIs from BPF.h. Doing so is
problematic from include-what-you-use perspective, but it is also a
layering issue (it creates a dependency cycle between the primary
BPF target library and the MCTargetDesc library).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362368
91177308-0d34-0410-b5e6-
96231b3b80d8
Diogo N. Sampaio [Mon, 3 Jun 2019 08:58:05 +0000 (08:58 +0000)]
[ARM][FIX] Ran out of registers due tail recursion
Summary:
- pr42062
When compiling for MinSize,
ARMTargetLowering::LowerCall decides to indirect
multiple calls to a same function. However,
it disconsiders the limitation that thumb1
indirect calls require the callee to be in a
register from r0 to r3 (llvm limiation).
If all those registers are used by arguments, the
compiler dies with "error: run out of registers
during register allocation".
This patch tells the function
IsEligibleForTailCallOptimization if we intend to
perform indirect calls, as to avoid tail call
optimization.
Reviewers: dmgreen, efriedma
Reviewed By: efriedma
Subscribers: javed.absar, kristof.beyls, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62683
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362366
91177308-0d34-0410-b5e6-
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Sam Parker [Mon, 3 Jun 2019 08:49:17 +0000 (08:49 +0000)]
[AArch64] Check for simple type in FPToUInt
DAGCombiner was hitting a SimpleType assertion when trying to combine
a v3f32 before type legalization.
bugzilla: https://bugs.llvm.org/show_bug.cgi?id=41916
Differential Revision: https://reviews.llvm.org/D62734
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362365
91177308-0d34-0410-b5e6-
96231b3b80d8
Roman Lebedev [Mon, 3 Jun 2019 08:44:09 +0000 (08:44 +0000)]
[NFC][X86] extract-{low,}bits.ll: one more pattern c with truncation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362364
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Mikael Holmen [Mon, 3 Jun 2019 06:38:01 +0000 (06:38 +0000)]
[TableGen] Fix std::array initializer to avoid warnings with older tool chains. NFC
A std::array is implemented as a template with an array inside a struct.
Older versions of clang, like 3.6, require an extra set of curly braces
around std::array initializations to avoid warnings.
The C++ language was changed regarding this by CWG 1270. So more modern
tool chains does not complain even if leaving out one level of braces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362360
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Jim Lin [Mon, 3 Jun 2019 02:31:07 +0000 (02:31 +0000)]
[AVR] Fix incorrect source regclass of LDWRdPtr
Summary:
LDWRdPtr would be expanded to ld+ldd. ldd only accepts the pointer register is Y or Z.
So the register class of pointer of LDWRdPtr should be PTRDISPREGS instead of PTRREGS.
Reviewers: dylanmckay
Reviewed By: dylanmckay
Subscribers: dylanmckay, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62300
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362351
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Florian Hahn [Mon, 3 Jun 2019 01:30:19 +0000 (01:30 +0000)]
Recommit r360171: [DAGCombiner] Avoid creating large tokenfactors in visitTokenFactor.
If we hit the limit, we do expand the outstanding tokenfactors.
Otherwise, we might drop nodes with users in the unexpanded
tokenfactors. This fixes the crashes reported by Jordan Rupprecht.
Reviewers: niravd, spatel, craig.topper, rupprecht
Reviewed By: niravd
Differential Revision: https://reviews.llvm.org/D62633
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362350
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Nico Weber [Sun, 2 Jun 2019 23:48:28 +0000 (23:48 +0000)]
llvm-undname: Add coverage for some error paths
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362346
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Mike Spertus [Sun, 2 Jun 2019 23:33:32 +0000 (23:33 +0000)]
Update MSVC Visualizer to reflect new variadic PointerUnion
This changed updates the MSVC Visualizer to work with the recent change
of PointerUnion into a variadic template. As an extra bonus, we
fix some bit rot in the SmallPtrSet visualizer as well
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362345
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