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Ilia Mirkin [Wed, 17 Jun 2015 19:07:14 +0000 (15:07 -0400)]
glsl: handle conversions to double when comparing param matches
This allows mod(int, int) to become selected as float mod when doubles
are supported.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Cc: "10.6" <mesa-stable@lists.freedesktop.org>
Emil Velikov [Thu, 18 Jun 2015 11:59:28 +0000 (12:59 +0100)]
ilo: remove missing ilo_fence.h from the sources list
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Boyan Ding [Tue, 16 Jun 2015 03:08:33 +0000 (11:08 +0800)]
egl/x11: Set version of swrastLoader to 2
which it actually implements instead of the newest version defined in
dri_interface.h
Cc: "10.5 10.6" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Boyan Ding <boyan.j.ding@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Eric Anholt [Wed, 17 Jun 2015 20:24:06 +0000 (13:24 -0700)]
vc4: Move tile state/alloc allocation into the kernel.
This avoids a security issue where userspace could have written the tile
state/tile alloc behind the GPU's back, and will apparently be necessary
for fixing stability bugs (tile state buffers are missing some top bits
for the tile alloc's address).
Eric Anholt [Wed, 10 Jun 2015 19:36:47 +0000 (12:36 -0700)]
vc4: Move RCL generation into the kernel.
There weren't that many variations of RCL generation, and this lets us
skip all the in-kernel validation for what we generated.
Eric Anholt [Wed, 17 Jun 2015 20:51:55 +0000 (13:51 -0700)]
vc4: Add dumping of VC4_PACKET_TILE_BINNING_MODE_CONFIG.
Eric Anholt [Thu, 18 Jun 2015 06:49:19 +0000 (23:49 -0700)]
vc4: Fix memory leak from simple_list conversion.
I accidentally shadowed the outside declaration, so we always returned
NULL even when we'd found something in the cache.
Eric Anholt [Thu, 18 Jun 2015 05:56:15 +0000 (22:56 -0700)]
vc4: Track the number of BOs allocated and their size.
This is useful for BO leak debugging.
Iago Toral Quiroga [Tue, 24 Feb 2015 18:02:50 +0000 (19:02 +0100)]
i965: Fix textureGrad with cube samplers
We can't use sampler messages with gradient information (like
sample_g or sample_d) to deal with this scenario because according
to the PRM:
"The r coordinate and its gradients are required only for surface
types that use the third coordinate. Usage of this message type on
cube surfaces assumes that the u, v, and gradients have already been
transformed onto the appropriate face, but still in [-1,+1] range.
The r coordinate contains the faceid, and the r gradients are ignored
by hardware."
Instead, we should lower this to compute the LOD manually based on the
gradients and use a different sample message that takes the computed
LOD instead of the gradients. This is already being done in
brw_lower_texture_gradients.cpp, but it is restricted to shadow
samplers only, although there is a comment stating that we should
probably do this also for samplerCube and samplerCubeArray.
Because of this, both dEQP and Piglit test cases for textureGrad with
cube maps currently fail.
This patch does two things:
1) Activates the texturegrad lowering pass for all cube samplers.
2) Corrects the computation of the LOD value for cube samplers.
I had to do 2) because for cube maps the calculations implemented
in the lowering pass always compute a value of rho that is twice
the value we want (so we get a LOD value one unit larger than we
want). This only happens for cube map samplers (all kinds). I am
not sure about why we need to do this, but I suspect that it is
related to the fact that cube map coordinates, when transported
to a specific face in the cube, are in the range [-1, 1] instead of
[0, 1] so we probably need to divide the derivatives by 2 when
we compute the LOD. Doing that would produce the same result as
dividing the final rho computation by 2 (or removing a unit
from the computed LOD, which is what we are doing here).
Fixes the following piglit tests:
bin/tex-miplevel-selection textureGrad Cube -auto -fbo
bin/tex-miplevel-selection textureGrad CubeArray -auto -fbo
bin/tex-miplevel-selection textureGrad CubeShadow -auto -fbo
Fixes 10 dEQP tests in the following category:
dEQP-GLES3.functional.shaders.texture_functions.texturegrad.*cube*
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Ilia Mirkin [Thu, 18 Jun 2015 02:18:09 +0000 (22:18 -0400)]
nvc0/ir: can't have a join on a load with an indirect source
Triggers an INVALID_OPCODE warning on GK208. Seems rare enough to not
warrant verification on other chips. Fixes the new piglits:
ubo_array_indexing/fs-nonuniform-control-flow.shader_test
ubo_array_indexing/vs-nonuniform-control-flow.shader_test
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.5 10.6" <mesa-stable@lists.freedesktop.org>
Kevin Rogovin [Wed, 17 Jun 2015 10:29:59 +0000 (13:29 +0300)]
docs: mark GL_ARB_framebuffer_no_attachments done for i965
Mark GL_ARB_framebuffer_no_attachments as done for i965.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Kevin Rogovin <kevin.rogovin@intel.com>
Kevin Rogovin [Wed, 17 Jun 2015 10:29:58 +0000 (13:29 +0300)]
i965: enable ARB_framebuffer_no_attachments for Gen7+
Enable GL_ARB_framebuffer_no_attachments in i965 for Gen7 and higher.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Kevin Rogovin <kevin.rogovin@intel.com>
Kevin Rogovin [Wed, 17 Jun 2015 10:29:57 +0000 (13:29 +0300)]
i965: execution of frag-shader when it has atomic buffer
Ensure that the GPU spawns the fragment shader thread for those
fragment shaders with atomic buffer access.
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Signed-off-by: Kevin Rogovin <kevin.rogovin@intel.com>
Kevin Rogovin [Wed, 17 Jun 2015 10:29:56 +0000 (13:29 +0300)]
mesa: function for testing if current frag-shader has atomics
Add helper function that checks if current fragment shader active
of gl_context has atomic buffer access.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Kevin Rogovin <kevin.rogovin@intel.com>
Kevin Rogovin [Wed, 17 Jun 2015 10:29:55 +0000 (13:29 +0300)]
i965: Use _mesa_geometric_ functions appropriately
Change references to gl_framebuffer::Width, Height, MaxNumLayers
and Visual::samples to use the _mesa_geometry_ convenience functions
for those places where the geometry of the gl_framebuffer is needed
(in contrast to the geometry of the intersection of the attachments
of the gl_framebuffer).
This patch is to pave the way to enable GL_ARB_framebuffer_no_attachments
on Gen7 and higher in i965.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Kevin Rogovin <kevin.rogovin@intel.com>
Kevin Rogovin [Wed, 17 Jun 2015 10:29:54 +0000 (13:29 +0300)]
mesa: helper function for scissor box of gl_framebuffer
Add helper convenience function that intersects the scissor values
against a passed bounding box. In addition, to avoid replicated code,
make the function _mesa_scissor_bounding_box() use this new function.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Kevin Rogovin <kevin.rogovin@intel.com>
Kevin Rogovin [Wed, 17 Jun 2015 10:29:53 +0000 (13:29 +0300)]
mesa: add helper functions for geometry of gl_framebuffer
Add convenience helper functions for fetching geometry of gl_framebuffer
that return the geometry of the gl_framebuffer instead of the geometry of
the buffers of the gl_framebuffer when then the gl_framebuffer has no
attachments.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Kevin Rogovin <kevin.rogovin@intel.com>
Kevin Rogovin [Wed, 17 Jun 2015 10:29:52 +0000 (13:29 +0300)]
PATCH 03/10] mesa: Complete ARB_framebuffer_no_attachments in Mesa core
Implement GL_ARB_framebuffer_no_attachments in Mesa core
- changes to conditions for framebuffer completenss
- implement set/get functions for framebuffers for
new functions in GL_ARB_framebuffer_no_attachments
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Kevin Rogovin <kevin.rogovin@intel.com>
Kevin Rogovin [Wed, 17 Jun 2015 10:29:51 +0000 (13:29 +0300)]
mesa: Constants and functions for ARB_framebuffer_no_attachments
Define the enumeration constants, function entry points and
glGet for the GL_ARB_framebuffer_no_attachments.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Kevin Rogovin <kevin.rogovin@intel.com>
Kevin Rogovin [Wed, 17 Jun 2015 10:29:50 +0000 (13:29 +0300)]
mesa: Define infrastructure for ARB_framebuffer_no_attachments
Define the infrastructure for the extension GL_ARB_framebuffer_no_attachments:
- extension table
- additions to gl_framebuffer
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Kevin Rogovin <kevin.rogovin@intel.com>
Eric Anholt [Mon, 15 Jun 2015 22:05:36 +0000 (15:05 -0700)]
vc4: Make sure that direct texture clamps have a minimum value of 0.
I was thinking of the MIN opcode in terms of unsigned math, but it's
signed, so if you used a negative array index, you could read before the
UBO. Fixes segfaults under simulation in piglit array indexing tests with
mprotect-based guard pages.
Eric Anholt [Tue, 16 Jun 2015 00:47:12 +0000 (17:47 -0700)]
vc4: Swap around which src we spill to ra31/rb31.
I wanted to assert that src1 came from a non-unspilled register in shader
validation, and this easily gets us that. And, as a bonus:
total instructions in shared programs: 93347 -> 92723 (-0.67%)
instructions in affected programs: 60524 -> 59900 (-1.03%)
Eric Anholt [Tue, 16 Jun 2015 19:03:10 +0000 (12:03 -0700)]
vc4: R4 is not a valid register for clamped direct texturing.
Our array only goes to R3, and R4 is a special case that shouldn't be
used.
Eric Anholt [Mon, 15 Jun 2015 21:54:26 +0000 (14:54 -0700)]
vc4: Factor out the live clamp register getter.
Eric Anholt [Mon, 15 Jun 2015 18:41:06 +0000 (11:41 -0700)]
vc4: Drop the unused "stride" field of surfaces.
We're always looking at the slice anyway, when we would have needed it.
Eric Anholt [Fri, 12 Jun 2015 19:47:47 +0000 (12:47 -0700)]
vc4: Handle refcounting the exec BO like we do in the kernel.
This reduces the diff to the kernel, and will be useful when I make the
kernel allocate more BOs as part of validation.
Eric Anholt [Thu, 11 Jun 2015 23:08:11 +0000 (16:08 -0700)]
vc4: Use VC4_SET/GET_FIELD for some RCL packets.
Eric Anholt [Wed, 10 Jun 2015 20:20:25 +0000 (13:20 -0700)]
vc4: Make symbolic values for packet sizes.
Eric Anholt [Wed, 10 Jun 2015 19:58:47 +0000 (12:58 -0700)]
vc4: Use symbolic values in texture ptype validation.
Eric Anholt [Wed, 10 Jun 2015 19:47:56 +0000 (12:47 -0700)]
vc4: Move vc4_packet.h to the kernel/ directory, since it's also shared.
I want to notice discrepancies when I diff -u between Mesa and the kernel.
Anuj Phogat [Wed, 15 Apr 2015 05:06:50 +0000 (22:06 -0700)]
i965/gen9: Disable Mip Tail for YF/YS tiled surfaces
Disabling miptails fixed the buffer corruption happening in FBO
which use YF/YS tiled renderbuffer or texture as color attachment.
Spec recommends disabling mip tails only for non-mip-mapped surfaces.
But, without disabling miptails I couldn't get correct data out of
mipmapped YF/YS tiled surface.
We need better understanding of miptails before start using them.
For now this patch helps move things forward.
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Anuj Phogat [Wed, 15 Apr 2015 05:06:48 +0000 (22:06 -0700)]
i965/gen9: Set vertical and horizontal surface alignments
Patch sets the alignments for texture and renderbuffer surfaces.
V3: Make changes inside horizontal_alignment() and
vertical_alignment() (Topi)
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Anuj Phogat [Wed, 15 Apr 2015 05:06:48 +0000 (22:06 -0700)]
i965: Use BRW_SURFACE_* in place of GL_TEXTURE_*
Makes no functional changes in the code.
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Anuj Phogat [Wed, 15 Apr 2015 05:06:48 +0000 (22:06 -0700)]
i965: Rename use_linear_1d_layout() and make it global
This function will be utilised in later patches.
V2: Make both pointers constants (Topi)
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Anuj Phogat [Wed, 15 Apr 2015 05:06:48 +0000 (22:06 -0700)]
i965/gen9: Set tiled resource mode in surface state
This patch sets the tiled resource mode for texture and renderbuffer
surfaces.
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Haixia Shi [Fri, 12 Jun 2015 17:10:58 +0000 (10:10 -0700)]
egl/dri2: implement platform_surfaceless
The surfaceless platform is for off-screen rendering only. Render node support
is required.
Only consider the render nodes. Do not use normal nodes as they require
auth hooks.
v3: change platform_null to platform_surfaceless
v4: make libdrm required for surfaceless
v5: remove modified include guards with defined(HAVE_SURFACELESS_PLATFORM)
v6: use O_CLOEXEC for drm fd
Signed-off-by: Haixia Shi <hshi@chromium.org>
Signed-off-by: Zach Reizner <zachr@google.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>
Neil Roberts [Thu, 28 May 2015 18:35:44 +0000 (19:35 +0100)]
i965/vec4: Fix the source register for indexed samplers
Previously when setting up the sample instruction for an indirect
sampler the vec4 backend was directly passing the pseudo opcode's
src0. However vec4_visitor::visit(ir_texture *) doesn't set the
texture operation's src0 -- it's left as BAD_FILE, which when
translated into a brw_reg gives the null register. In brw_SAMPLE,
gen6_resolve_implied_move() inserts a MOV from the inst->base_mrf and
sets the src0 appropriately. The indirect sampler case did not have a
call to gen6_resolve_implied_move().
The fs backend avoids this because the platforms that support dynamic
indexing of samplers (IVB+) have been converted to not use the
fake-MRF hack, and instead send from proper GRFs.
This patch makes it call gen6_resolve_implied_move before setting up
the indirect message. This is similar to what is done for constant
sampler numbers in brw_SAMPLE.
The Piglit tests for sampler array indexing didn't pick this up
because they were using a texture with a solid colour so it didn't
matter what texture coordinates were actually used. The tests have now
been changed to be more thorough in this commit:
http://cgit.freedesktop.org/piglit/commit/?id=
4f9caf084eda7
With that patch the tests for gs and vs are currently failing on
Ivybridge, but this patch fixes them. There are no other changes to a
Piglit run on Ivybridge.
On Skylake the gs tests were failing even without the Piglit patch
because Skylake needs the source registers to work correctly in order
to send a message header to select SIMD4x2 mode.
(The explanation in the commit message is partially written by Matt
Turner)
Tested-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Marek Olšák [Mon, 6 Apr 2015 23:10:17 +0000 (01:10 +0200)]
st/mesa: improve assertions in vp/fp translation
Reviewed-by: Brian Paul <brianp@vmware.com>
Marek Olšák [Sun, 14 Jun 2015 14:37:02 +0000 (16:37 +0200)]
mesa: don't rebind constant buffers after every state change if GS is active
Reviewed-by: Brian Paul <brianp@vmware.com>
Chris Forbes [Sun, 21 Sep 2014 00:07:55 +0000 (12:07 +1200)]
mesa: generalize sso stage interleaving check
For tessellation.
v2: cleanup by Marek Olšák
Reviewed-by: Brian Paul <brianp@vmware.com>
Marek Olšák [Sat, 13 Jun 2015 11:02:20 +0000 (13:02 +0200)]
mesa: remove unused variables from gl_program
Reviewed-by: Brian Paul <brianp@vmware.com>
Chris Forbes [Sun, 7 Sep 2014 07:24:15 +0000 (19:24 +1200)]
glsl: add ir reader support for ir_barrier
Picked from the tessellation branch.
Reviewed-by: Brian Paul <brianp@vmware.com>
Marek Olšák [Thu, 19 Mar 2015 22:28:25 +0000 (23:28 +0100)]
glsl: print locations of variables
Reviewed-by: Brian Paul <brianp@vmware.com>
Marek Olšák [Sat, 6 Jun 2015 11:24:11 +0000 (13:24 +0200)]
configure.ac: rename LLVM_VERSION_PATCH to avoid conflict with llvm-config.h
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Timothy Arceri [Mon, 15 Jun 2015 11:00:47 +0000 (21:00 +1000)]
Revert "glsl: remove restriction on unsized arrays in GLSL ES 3.10"
This reverts commit
adee54f8269c5e9f4fde91d19f0e465afc8f14d8.
Further down in the GLSL ES 3.10 spec it say:
"If an array is declared as the last member of a shader storage block
and the size is not specified at compile-time, it is sized at run-time.
In all other cases, arrays are sized only at compile-time."
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Tapani Pälli [Tue, 16 Jun 2015 10:46:47 +0000 (13:46 +0300)]
mesa: set override_version per api version override
Before
9b5e92f get_gl_override was called only once, but now it is
called for multiple APIs (GLES2, GL), version needs to be set always.
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90797
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Martin Peres <martin.peres@linux.intel.com>
Tested-by: Martin Peres <martin.peres@linux.intel.com>
Neil Roberts [Thu, 11 Jun 2015 15:59:07 +0000 (16:59 +0100)]
i965: Fix aligning to the block size in intel_miptree_copy_slice
This function was trying to align the width and height to a multiple
of the block size for compressed textures. It was using align_w/h as a
shortcut to get the block size as up until Gen9 this always happens to
match. However in Gen9+ the alignment values are expressed as
multiples of the block size so in effect the alignment values are
always 4 for compressed textures as that is the minimum value we can
pick. This happened to work for most compressed formats because the
block size is also 4, but for FXT1 this was breaking because it has a
block width of 8.
This fixes some Piglit tests testing FXT1 such as
spec@3dfx_texture_compression_fxt1@fbo-generatemipmap-formats
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Ilia Mirkin [Mon, 15 Jun 2015 19:48:58 +0000 (15:48 -0400)]
nv50,nvc0: clamp uniform size to 64k
The state tracker will pass through requests from buggy applications
which will have the buffer size larger than the max allowed (64k). Clamp
the size to 64k so that we don't get errors when uploading the constbuf
data.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.5 10.6" <mesa-stable@lists.freedesktop.org>
Ilia Mirkin [Fri, 12 Jun 2015 14:09:05 +0000 (16:09 +0200)]
nvc0/ir: fix collection of first uses for texture barrier insertion
One of the places we have to insert texbars is in situations where the
result of the tex gets overwritten by a different instruction (e.g. in a
conditional statement). However in some situations it can actually
appear as though the original tex itself is an overwriting instruction.
This can naturally never really happen, so just ignore the tex
instruction when it comes up.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90347
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.5 10.6" <mesa-stable@lists.freedesktop.org>
Eric Anholt [Tue, 9 Jun 2015 19:16:19 +0000 (12:16 -0700)]
egl: Drop check for driver != NULL.
Back in 2013, a patch was added (with 2 reviewers!) at the end of the
block to early exit the loop in this case, without noticing that the loop
already did. I added another early exit case, again without noticing, but
Rob caught me. Just drop the loop condition that apparently surprises
most of us, instead of leaving the end of the loop conspicuously not
exiting on success.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Rob Clark <robdclark@gmail.com>
Eric Anholt [Tue, 9 Jun 2015 18:45:05 +0000 (11:45 -0700)]
gallium: Drop the gallium-specific Android sw winsys.
This was part of gallium_egl, and we now have the normal libEGL Android
winsys support to handle it.
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Eric Anholt [Wed, 3 Jun 2015 17:15:31 +0000 (10:15 -0700)]
vc4: Add support for building on Android.
v2: Add a comment explaining why we link libmesa_glsl. Drop warning
option from freedreno. Add vc4 to the documentation for
BOARD_GPU_DRIVERS.
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Eric Anholt [Sun, 7 Jun 2015 18:57:46 +0000 (11:57 -0700)]
gallium: Enable build of NIR support on Android.
v2: Add a comment explaining why we link libmesa_glsl.
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Eric Anholt [Sun, 7 Jun 2015 23:47:25 +0000 (16:47 -0700)]
egl/dri2: Fix Android Lollipop build on ARM.
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Anuj Phogat [Fri, 15 May 2015 13:01:15 +0000 (06:01 -0700)]
meta: Abort texture upload if pixels == null and no pixel unpack buffer set
in case of glTexImage{1,2,3}D(). Texture has already been allocated
at this point and we have no data to upload. With out this patch,
with create_pbo = true, we end up creating a temporary pbo and then
uploading uninitialzed texture data.
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Neil Roberts <neil@linux.intel.com>
Anuj Phogat [Tue, 12 May 2015 11:17:04 +0000 (04:17 -0700)]
meta: Abort meta path if ReadPixels need rgb to luminance conversion
After recent addition of pbo testing in piglit test getteximage-luminance,
it fails on i965. This patch makes a sub test pass.
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Anuj Phogat [Fri, 1 May 2015 07:05:18 +0000 (00:05 -0700)]
mesa: Turn need_rgb_to_luminance_conversion() in to a global function
This will be used by _mesa_meta_pbo_GetTexSubImage() in a later patch.
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Anuj Phogat [Fri, 1 May 2015 06:36:18 +0000 (23:36 -0700)]
mesa: Use helper function need_rgb_to_luminance_conversion()
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Anuj Phogat [Fri, 1 May 2015 06:35:20 +0000 (23:35 -0700)]
mesa: Handle integer formats in need_rgb_to_luminance_conversion()
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Anuj Phogat [Mon, 1 Jun 2015 16:32:55 +0000 (09:32 -0700)]
meta: Use is_power_of_two() helper function
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Anuj Phogat [Tue, 5 May 2015 06:10:28 +0000 (23:10 -0700)]
i965: Check for miptree pitch alignment before using intel_miptree_map_movntdqa()
We have an assert() in intel_miptree_map_movntdqa() which expects
the pitch to be 16 byte aligned.
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Anuj Phogat [Thu, 28 May 2015 21:48:51 +0000 (14:48 -0700)]
i965: Remove break after return
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Jürgen Rühle [Sat, 6 Jun 2015 16:37:20 +0000 (18:37 +0200)]
nv50/ir: OP_JOIN is a flow instruction
OP_JOIN instructions are assumed to be flow instructions and mercilessly
casted to FlowInstruction.
This patch fixes an instance where an OP_JOIN is created as a plain
instruction. This can cause crashes in the ir printer.
[imirkin: add ->fixed = 1]
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Emil Velikov [Sun, 14 Jun 2015 15:43:21 +0000 (16:43 +0100)]
docs: add news item and link release notes for mesa 10.6.0
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Emil Velikov [Sun, 14 Jun 2015 15:40:00 +0000 (16:40 +0100)]
docs: Add sha256sums for the 10.6.0 release
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
(cherry picked from commit
5d327b373531861f86a726db669b3d656f1b5f8d)
Emil Velikov [Sun, 14 Jun 2015 15:26:40 +0000 (16:26 +0100)]
docs: Update 10.6.0 release notes
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
(cherry picked from commit
3b9cde5c8138fb5cc45c652f2a5c15c5fa222bd7)
Chia-I Wu [Mon, 15 Jun 2015 03:24:47 +0000 (11:24 +0800)]
ilo: add ilo_state_raster_{line,poly}_stipple
Initialize hardware stipple states on bound instead of on emission.
Chia-I Wu [Mon, 15 Jun 2015 04:01:29 +0000 (12:01 +0800)]
ilo: add ilo_state_sample_pattern
Move sample pattern initialization from ilo_render to
ilo_state_sample_pattern.
Chia-I Wu [Mon, 15 Jun 2015 03:57:10 +0000 (11:57 +0800)]
ilo: add 3DSTATE_AA_LINE_PARAMETERS to ilo_state_raster
Utilize ilo_state_raster to avoid redundant state change.
Marek Olšák [Sun, 10 May 2015 18:35:15 +0000 (20:35 +0200)]
gallium/util: add util_last_bit64
This will be needed by radeonsi.
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Marek Olšák [Sat, 6 Jun 2015 12:12:34 +0000 (14:12 +0200)]
glsl: fix "tesselation" typo
Trivial.
Marek Olšák [Fri, 5 Jun 2015 17:09:21 +0000 (19:09 +0200)]
r600g: handle TGSI input/output array declarations correctly
Most of this code could be removed if r600g used tgsi_shader_info.
Chia-I Wu [Wed, 10 Jun 2015 23:36:28 +0000 (07:36 +0800)]
ilo: merge ilo_state_3d*.[ch] to ilo_state.[ch]
With most code replaced to ilo_state_*, what was left did not belong there
anymore.
Chia-I Wu [Fri, 12 Jun 2015 07:08:02 +0000 (15:08 +0800)]
ilo: add ilo_state_ps to ilo_shader_cso
Chia-I Wu [Fri, 12 Jun 2015 06:47:02 +0000 (14:47 +0800)]
ilo: add ilo_state_{vs,hs,ds,gs} to ilo_shader_cso
Chia-I Wu [Tue, 2 Jun 2015 15:09:53 +0000 (23:09 +0800)]
ilo: embed ilo_state_sbe in ilo_shader
Chia-I Wu [Tue, 2 Jun 2015 06:57:48 +0000 (14:57 +0800)]
ilo: embed ilo_state_vf in ilo_ve_state
Chia-I Wu [Thu, 28 May 2015 05:43:56 +0000 (13:43 +0800)]
ilo: embed ilo_state_urb in ilo_state_vector
Chia-I Wu [Fri, 29 May 2015 07:25:13 +0000 (15:25 +0800)]
ilo: embed ilo_state_sol in ilo_shader
Chia-I Wu [Mon, 11 May 2015 11:48:52 +0000 (19:48 +0800)]
ilo: embed ilo_state_cc in ilo_blend_state
Chia-I Wu [Fri, 5 Jun 2015 02:23:24 +0000 (10:23 +0800)]
ilo: embed ilo_state_raster in ilo_rasterizer_state
Chia-I Wu [Sun, 17 May 2015 16:00:37 +0000 (00:00 +0800)]
ilo: embed ilo_state_viewport in ilo_viewport_state
Chia-I Wu [Thu, 21 May 2015 09:18:37 +0000 (17:18 +0800)]
ilo: replace ilo_sampler_cso with ilo_state_sampler
Chia-I Wu [Wed, 20 May 2015 13:44:30 +0000 (21:44 +0800)]
ilo: replace ilo_view_surface with ilo_state_surface
Chia-I Wu [Mon, 18 May 2015 15:32:10 +0000 (23:32 +0800)]
ilo: replace ilo_zs_surface with ilo_state_zs
Chia-I Wu [Fri, 12 Jun 2015 06:56:56 +0000 (14:56 +0800)]
ilo: add ilo_state_ps
We want to make ilo_shader_cso a union of ilo_state_{vs,hs,ds,gs,ps}.
Chia-I Wu [Fri, 29 May 2015 16:58:51 +0000 (00:58 +0800)]
ilo: add ilo_state_{vs,hs,ds,gs}
We want to make ilo_shader_cso a union of ilo_state_{vs,hs,ds,gs} and ps
payload.
Chia-I Wu [Fri, 12 Jun 2015 06:02:37 +0000 (14:02 +0800)]
ilo: add ilo_state_sbe
We want to replace ilo_kernel_routing with ilo_state_sbe.
Chia-I Wu [Sat, 30 May 2015 16:00:49 +0000 (00:00 +0800)]
ilo: add ilo_state_vf
We want to replace ilo_ve_state with ilo_state_vf.
Chia-I Wu [Thu, 28 May 2015 05:21:02 +0000 (13:21 +0800)]
ilo: add ilo_state_urb
Chia-I Wu [Fri, 29 May 2015 05:08:18 +0000 (13:08 +0800)]
ilo: add ilo_state_sol
Chia-I Wu [Mon, 11 May 2015 06:23:49 +0000 (14:23 +0800)]
ilo: add ilo_state_cc
We want to replace ilo_dsa_state and ilo_blend_state with ilo_state_cc.
Chia-I Wu [Sun, 10 May 2015 05:52:21 +0000 (13:52 +0800)]
ilo: add ilo_state_raster
We want to replace ilo_rasterizer_state with ilo_state_raster.
Chia-I Wu [Tue, 12 May 2015 15:43:50 +0000 (23:43 +0800)]
ilo: add ilo_state_viewport
We want to replace ilo_viewport_cso and ilo_scissor_state with
ilo_state_viewport.
Chia-I Wu [Wed, 13 May 2015 05:10:54 +0000 (13:10 +0800)]
ilo: add ilo_state_sampler
We want to replace ilo_sampler_cso with ilo_state_sampler.
Chia-I Wu [Thu, 14 May 2015 01:46:42 +0000 (09:46 +0800)]
ilo: add ilo_state_surface
We want to replace ilo_view_surface with ilo_state_surface.
Chia-I Wu [Sat, 16 May 2015 00:27:24 +0000 (08:27 +0800)]
ilo: add ilo_state_zs
We want to replace ilo_zs_surface with ilo_state_zs. One noteworthy
difference is that ilo_state_zs always aligns level 0 to 8x4 when HiZ is
enabled. HiZ will not be enabled for 1D surfaces as a result.
Chia-I Wu [Sat, 9 May 2015 13:39:34 +0000 (21:39 +0800)]
ilo: update genhw headers
Generate these new enums
enum gen_reorder_mode;
enum gen_clip_mode;
enum gen_front_winding;
enum gen_fill_mode;
enum gen_cull_mode;
enum gen_pixel_location;
enum gen_sample_count;
enum gen_inputattr_select;
enum gen_msrast_mode;
enum gen_prefilter_op;
Correct the type of GEN6_SAMPLER_DW0_BASE_LOD. Rename gen_logicop_function,
gen_sampler_mip_filter, gen_sampler_map_filter, gen_sampler_aniso_ratio, and
others.
Chia-I Wu [Fri, 22 May 2015 06:21:22 +0000 (14:21 +0800)]
ilo: add ilo_image_disable_aux()
When aux bo allocation fails, ilo_image_disable_aux() should be called to
disable aux buffer.
Chia-I Wu [Tue, 26 May 2015 07:46:44 +0000 (15:46 +0800)]
ilo: add array_size and level_count to ilo_image
We will use them for bound checking.