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Zachary Turner [Thu, 11 Apr 2019 17:29:48 +0000 (17:29 +0000)]
[PDB Docs] Add skeleton of documentation for CodeView symbols.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358197
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Kevin P. Neal [Thu, 11 Apr 2019 17:16:03 +0000 (17:16 +0000)]
New document skeleton describing how to add a constrained floating-point
intrinsic.
Reviewed by: andrew.w.kaylor, cameron.mcinally
Differential Revision: https://reviews.llvm.org/D59833
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358194
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Simon Pilgrim [Thu, 11 Apr 2019 16:39:31 +0000 (16:39 +0000)]
[ConstantFold] ExtractConstantBytes - handle shifts on large integer types
Use APInt instead of getZExtValue from the ConstantInt until we can confirm that the shift amount is in range.
Reduced from OSS-Fuzz #14169 - https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=14169
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358192
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Sanjay Patel [Thu, 11 Apr 2019 15:59:47 +0000 (15:59 +0000)]
[DAGCombiner] refactor narrowing of extracted vector binop; NFC
There's a TODO comment about handling patterns with insert_subvector,
and we do want to match that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358187
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Simon Pilgrim [Thu, 11 Apr 2019 15:29:15 +0000 (15:29 +0000)]
[X86] SimplifyDemandedVectorElts - add X86ISD::VPERMV3 mask support
Completes SimplifyDemandedVectorElts's basic variable shuffle mask support which should help D60512 + D60562
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358186
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Serge Guelton [Thu, 11 Apr 2019 15:22:48 +0000 (15:22 +0000)]
Make llvm-nm -help great again
Only display help from the llvm-nm category instead of all llvm options, which make it much more usable.
There's still an issue with -s, which is probably a bug in llvm::cl and worth another commit.
Differential Revision: https://reviews.llvm.org/D60411
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358185
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Roger Ferrer Ibanez [Thu, 11 Apr 2019 15:13:12 +0000 (15:13 +0000)]
[RISCV] Diagnose invalid second input register operand when using %tprel_add
RISCVMCCodeEmitter::expandAddTPRel asserts that the second operand must be
x4/tp. As we are not currently checking this in the RISCVAsmParser, the assert
is easy to trigger due to wrong assembly input.
This patch does a late check of this constraint.
An alternative could be using a singleton register class for x4/tp similar to
the current one for sp. Unfortunately it does not result in a good diagnostic.
Because add is an overloaded mnemonic, if no matching is possible, the
diagnostic of the first failing alternative seems to be used as the diagnostic
itself. This means that this case the %tprel_add is diagnosed as an invalid
operand (because the real add instruction only has 3 operands).
Differential Revision: https://reviews.llvm.org/D60528
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358183
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Simon Pilgrim [Thu, 11 Apr 2019 15:09:03 +0000 (15:09 +0000)]
[X86][AVX] Tweak X86ISD::VPERMV3 demandedelts test
Original test was too dependent on the order of the combines that could cause the inserted element being demanded after all
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358182
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Luo, Yuanke [Thu, 11 Apr 2019 15:01:03 +0000 (15:01 +0000)]
[X86] Add MM register mapping from CodeView to MC register id
Differential Revision: https://reviews.llvm.org/D60437
Change-Id: I2183a6d825d0284b22705d423b88882992b236c5
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358179
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Michal Gorny [Thu, 11 Apr 2019 14:58:39 +0000 (14:58 +0000)]
[llvm] [lit] Add target-x86* features
Add a 'target-x86' and 'target-x86_64' feature sthat indicates that
the default target is 32-bit or 64-bit x86, appropriately. Combined
with 'native' feature, we're going to use this to control x86-specific
LLDB native process tests.
Differential Revision: https://reviews.llvm.org/D60474
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358177
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Pavel Labath [Thu, 11 Apr 2019 14:57:34 +0000 (14:57 +0000)]
YAMLIO: Fix serialization of strings with embedded nuls
Summary:
A bug/typo in Output::scalarString caused us to round-trip a StringRef
through a const char *. This meant that any strings with embedded nuls
were unintentionally cut short at the first such character. (It also
could have caused accidental buffer overruns, but it seems that all
StringRefs coming into this functions were formed from null-terminated
strings.)
This patch fixes the bug and adds an appropriate test.
Reviewers: sammccall, jhenderson
Subscribers: kristina, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D60505
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358176
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Simon Pilgrim [Thu, 11 Apr 2019 14:48:46 +0000 (14:48 +0000)]
[X86][AVX] Add X86ISD::VPERMV3 demandedelts test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358175
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Simon Pilgrim [Thu, 11 Apr 2019 14:35:45 +0000 (14:35 +0000)]
[X86] SimplifyDemandedVectorElts - add X86ISD::VPERMV mask support
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358174
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Simon Pilgrim [Thu, 11 Apr 2019 14:26:32 +0000 (14:26 +0000)]
[X86][AVX] Add X86ISD::VPERMV demandedelts test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358173
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Sanjay Patel [Thu, 11 Apr 2019 14:21:57 +0000 (14:21 +0000)]
[DAGCombiner][x86] scalarize inserted vector FP ops
// bo (build_vec ...undef, x, undef...), (build_vec ...undef, y, undef...) -->
// build_vec ...undef, (bo x, y), undef...
The lifetime of the nodes in these examples is different for variables versus constants,
but they are all build vectors briefly, so I'm proposing to catch them in this form to
handle all of the leading examples in the motivating test file.
Before we have build vectors, we might have insert_vector_element. After that, we might
have scalar_to_vector and constant pool loads.
It's going to take more work to ensure that FP vector operands are getting simplified
with undef elements, so this transform can apply more widely. In a non-loose FP environment,
we are likely simplifying FP elements to NaN values rather than undefs.
We also need to allow more opcodes down this path. Eg, we don't handle FP min/max flavors
yet.
Differential Revision: https://reviews.llvm.org/D60514
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358172
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Diogo N. Sampaio [Thu, 11 Apr 2019 14:19:43 +0000 (14:19 +0000)]
[AArch64] Add lowering pattern for llvm.aarch64.neon.vcvtfxs2fp.f16.i64
Summary: Add lowering pattern for llvm.aarch64.neon.vcvtfxs2fp.f16.i64
Reviewers: pbarrio, DavidSpickett, LukeGeeson
Reviewed By: LukeGeeson
Subscribers: javed.absar, kristof.beyls, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D60259
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358171
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Simon Pilgrim [Thu, 11 Apr 2019 14:15:01 +0000 (14:15 +0000)]
[X86] SimplifyDemandedVectorElts - add X86ISD::VPERMILPV mask support
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358170
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Simon Pilgrim [Thu, 11 Apr 2019 14:09:35 +0000 (14:09 +0000)]
[X86][AVX] Add X86ISD::VPERMILPV demandedelts tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358168
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Simon Pilgrim [Thu, 11 Apr 2019 14:04:19 +0000 (14:04 +0000)]
[X86] SimplifyDemandedVectorElts - add X86ISD::VPERMIL2 mask support
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358167
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Simon Pilgrim [Thu, 11 Apr 2019 13:52:43 +0000 (13:52 +0000)]
[X86][XOP] Add X86ISD::VPERMIL2 demandedelts test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358166
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Simon Pilgrim [Thu, 11 Apr 2019 13:30:38 +0000 (13:30 +0000)]
[X86] SimplifyDemandedVectorElts - add VPPERM support
We need to add support for all variable shuffle mask ops, but VPPERM is the only one that already has test coverage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358165
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Sander de Smalen [Thu, 11 Apr 2019 13:02:19 +0000 (13:02 +0000)]
[ValueTracking] Change if-else chain into switch in computeKnownBitsFromAssume
This is a follow-up patch to D60504 to further improve
performance issues in computeKnownBitsFromAssume.
The patch is NFC, but may improve compile-time performance
if the compiler isn't clever enough to do the optimization
itself.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358163
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Oliver Stannard [Thu, 11 Apr 2019 12:53:33 +0000 (12:53 +0000)]
Test commit access
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358162
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Fangrui Song [Thu, 11 Apr 2019 10:25:41 +0000 (10:25 +0000)]
Use llvm::lower_bound. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358161
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Andrea Di Biagio [Thu, 11 Apr 2019 10:15:04 +0000 (10:15 +0000)]
[MCA] Remove wrong comments from a test. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358160
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Ilya Biryukov [Thu, 11 Apr 2019 09:00:36 +0000 (09:00 +0000)]
[ADT] Fix template parameter names of llvm::{upper|lower}_bound
Summary:
Rename template parameter for a search value from 'ForwardIt' to 'T'.
While here, also use perfect forwarding to pass the value to STL algos.
Reviewers: sammccall
Reviewed By: sammccall
Subscribers: dexonsmith, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D60510
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358158
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Hans Wennborg [Thu, 11 Apr 2019 07:46:25 +0000 (07:46 +0000)]
try to fix the sphinx build some more
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358156
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Hans Wennborg [Thu, 11 Apr 2019 07:30:56 +0000 (07:30 +0000)]
Try to fix the shpinx build
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358154
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Roman Lebedev [Thu, 11 Apr 2019 07:20:50 +0000 (07:20 +0000)]
[llvm-exegesis] Fix serialization/deserialization of special NoRegister register (PR41448)
Summary:
A *lot* of instructions have this special register.
It seems this never really worked, but i finally noticed it only
because it happened to break for `CMOV16rm` instruction.
We serialized that register as "" (empty string), which is naturally
'ignored' during deserialization, so we re-create a `MCInst` with
too few operands.
And when we then happened to try to resolve variant sched class
for this mis-serialized instruction, and the variant predicate
tried to read an operand that was out of bounds since we got less operands,
we crashed.
Fixes [[ https://bugs.llvm.org/show_bug.cgi?id=41448 | PR41448 ]].
Reviewers: craig.topper, courbet
Reviewed By: courbet
Subscribers: tschuett, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D60517
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358153
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Shiva Chen [Thu, 11 Apr 2019 04:59:13 +0000 (04:59 +0000)]
[RISCV] Put data smaller than eight bytes to small data section
Because of gp = sdata_start_address + 0x800, gp with signed twelve-bit offset
could covert most of the small data section. Linker relaxation could transfer
the multiple data accessing instructions to a gp base with signed twelve-bit
offset instruction.
Differential Revision: https://reviews.llvm.org/D57493
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358150
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Fangrui Song [Thu, 11 Apr 2019 02:02:44 +0000 (02:02 +0000)]
[DWARF] Set discriminator to 0 for DW_LNS_copy
Summary:
Make DW_LNS_copy set the discriminator register to 0, to conform to
DWARF 4 & 5: "Then it sets the discriminator register to 0, and sets the
basic_block, prologue_end and epilogue_begin registers to false."
Because all of DW_LNE_end_sequence, DN_LNS_copy, and special opcodes reset
discriminator to 0, we can move discriminator=0 to appendRowToMatrix.
Also, make DW_LNS_copy print before appending the row, as it is similar
to a address+=0,line+=0 special opcode, which prints before appending
the row.
Reviewers: dblaikie, probinson, aprantl
Reviewed By: dblaikie
Subscribers: danielcdh, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D60364
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358148
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Erik Pilkington [Wed, 10 Apr 2019 23:42:11 +0000 (23:42 +0000)]
Fix a hang when lowering __builtin_dynamic_object_size
If the ObjectSizeOffsetEvaluator fails to fold the object size call, then it may
litter some unused instructions in the function. When done repeatably in
InstCombine, this results in an infinite loop. Fix this by tracking the set of
instructions that were inserted, then removing them on failure.
rdar://
49172227
Differential revision: https://reviews.llvm.org/D60298
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358146
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Amara Emerson [Wed, 10 Apr 2019 23:06:14 +0000 (23:06 +0000)]
[AArch64][GlobalISel] Make <2 x p0> = G_BUILD_VECTOR legal.
The existing isel support already works for p0 once the legalizer accepts it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358144
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Amara Emerson [Wed, 10 Apr 2019 23:06:11 +0000 (23:06 +0000)]
[AArch64][GlobalISel] Add legalizer support for <8 x s16> and <16 x s8> G_ADD.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358143
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Amara Emerson [Wed, 10 Apr 2019 23:06:08 +0000 (23:06 +0000)]
[AArch64][GlobalISel] Scalarize vector SDIV.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358142
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Craig Topper [Wed, 10 Apr 2019 22:35:32 +0000 (22:35 +0000)]
[X86] Add SSE1 command line to atomic-fp.ll and atomic-non-integer.ll. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358141
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Craig Topper [Wed, 10 Apr 2019 22:35:24 +0000 (22:35 +0000)]
[X86] Autogenerate complete checks. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358140
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Craig Topper [Wed, 10 Apr 2019 21:42:08 +0000 (21:42 +0000)]
[X86] Teach foldMaskedShiftToScaledMask to look through an any_extend from i32 to i64 between the and & shl
foldMaskedShiftToScaledMask tries to reorder and & shl to enable the shl to fold into an LEA. But if there is an any_extend between them it doesn't work.
This patch modifies the code to look through any_extend from i32 to i64 when the and mask only uses bits that weren't from the extended part.
This will prevent a regression from D60358 caused by 64-bit SHL being narrowed to 32-bits when their upper bits aren't demanded.
Differential Revision: https://reviews.llvm.org/D60532
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358139
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Craig Topper [Wed, 10 Apr 2019 21:29:41 +0000 (21:29 +0000)]
[X86] Make _Int instructions the preferred instructon for the assembly parser and disassembly parser to remove inconsistencies between VEX and EVEX.
Many of our instructions have both a _Int form used by intrinsics and a form
used by other IR constructs. In the EVEX space the _Int versions usually cover
all the capabilities include broadcasting and rounding. While the other version
only covers simple register/register or register/load forms. For this reason
in EVEX, the non intrinsic form is usually marked isCodeGenOnly=1.
In the VEX encoding space we were less consistent, but usually the _Int version
was the isCodeGenOnly version.
This commit makes the VEX instructions match the EVEX instructions. This was
done by manually studying the AsmMatcher table so its possible I missed some
cases, but we should be closer now.
I'm thinking about using the isCodeGenOnly bit to simplify the EVEX2VEX
tablegen code that disambiguates the _Int and non _Int versions. Currently it
checks register class sizes and Record the memory operands come from. I have
some other changes I was looking into for D59266 that may break the memory check.
I had to make a few scheduler hacks to keep the _Int versions from being treated
differently than the non _Int version.
Differential Revision: https://reviews.llvm.org/D60441
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358138
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David Green [Wed, 10 Apr 2019 19:18:58 +0000 (19:18 +0000)]
[ARM] Add an extra test for constant hoist. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358128
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Craig Topper [Wed, 10 Apr 2019 19:09:06 +0000 (19:09 +0000)]
[X86] Add test case for LEA formation regression seen with D60358. NFC
If we have an (add X, (and (aext (shl Y, C1)), C2)), we can pull the shift through and+aext to fold into an LEA with the.
Assuming C1 is small enough and C2 masks off all of the extend bits.
This pattern showed up in D60358. And we need to handle it to prevent a regression.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358124
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Craig Topper [Wed, 10 Apr 2019 19:08:59 +0000 (19:08 +0000)]
[X86] Replace some if statements in isel address matching that should never be true with asserts. And move them earlier before we looked through operands that don't change size. NFC
These ifs were ensuring we don't have to handle types larger than 64 bits probably because we use getZExtValue in several places below them.
None of the callers of this code pass types larger than 64-bits so we can just assert instead of branching in release code.
I've also moved them earlier since we're just looking through operations that don't effect bit width.
This is prep work for some refactoring I plan to do to the (and (shl)) handling code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358123
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Nick Desaulniers [Wed, 10 Apr 2019 19:01:44 +0000 (19:01 +0000)]
[X86AsmPrinter] refactor to limit use of Modifier. NFC
Summary:
The Modifier memory operands is used in 2 cases of memory references
(H & P ExtraCodes). Rather than pass around the likely nullptr Modifier,
refactor the handling of the Modifier out from printOperand().
The refactorings in this patch:
- Don't forward declare printOperand, move its definition up.
- The diff makes it look like there's a change to printPCRelImm
(narrator: there's not).
- Create printModifiedOperand()
- Move logic for Modifier to there from printOperand
- Use printModifiedOperand in 3 call sites that actually create
Modifiers.
- Remove now unused Modifier parameter from printOperand
- Remove default parameter from printLeaMemReference as it only has 1
call site that explicitly passes a parameter.
- Remove default parameter from printMemReference, make call lone call
site explicitly pass nullptr.
- Drop Modifier parameter from printIntelMemReference, as Intel style
memory references don't support the Modifiers in question.
This will allow future changes to printOperand() to make it a pure virtual
method on the base AsmPrinter class, allowing for more generic handling
of some architecture generic constraints. X86AsmPrinter was the only
derived class of AsmPrinter to have additional parameters on its
printOperand function.
Reviewers: craig.topper, echristo
Reviewed By: echristo
Subscribers: hiraditya, llvm-commits, srhines
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D60526
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358122
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Ali Tamur [Wed, 10 Apr 2019 18:30:03 +0000 (18:30 +0000)]
[llvm] Non-functional change: declared a local variable as const.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358120
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Zachary Turner [Wed, 10 Apr 2019 18:26:51 +0000 (18:26 +0000)]
[PDB Docs] Start documenting CodeView Type Records.
This puts the general layout of the document in place and fully
describes 1 simple type record. Followups will fill out more
pieces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358119
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Roman Lebedev [Wed, 10 Apr 2019 18:26:42 +0000 (18:26 +0000)]
[X86] X86ScheduleBdVer2: use !listsplat operator to cleanup loadres calculation
The problem is that one can't concatenate an empty list
(implied all-ones) with non-empty list here. The result
will be the non-empty list, and it won't match the length
of the ExePorts list.
The problems begin when LoadRes != 1 here,
which is the case in PdWriteResYMMPair,
and more importantly i think it will be the case for PdWriteResExPair.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358118
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Roman Lebedev [Wed, 10 Apr 2019 18:26:36 +0000 (18:26 +0000)]
[TableGen] Introduce !listsplat 'binary' operator
Summary:
```
``!listsplat(a, size)``
A list value that contains the value ``a`` ``size`` times.
Example: ``!listsplat(0, 2)`` results in ``[0, 0]``.
```
I plan to use this in X86ScheduleBdVer2.td for LoadRes handling.
This is a little bit controversial because unlike every other binary operator
the types aren't identical.
Reviewers: stoklund, javed.absar, nhaehnle, craig.topper
Reviewed By: javed.absar
Subscribers: llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D60367
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358117
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Roman Lebedev [Wed, 10 Apr 2019 18:26:23 +0000 (18:26 +0000)]
[kate] Add '!mul' operator that was introduced in D58775
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358116
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David Green [Wed, 10 Apr 2019 18:05:57 +0000 (18:05 +0000)]
[ARM] Add an extra constant hoisting test. NFC
This adds a simple extra test for constant hoisting to show it's
usefulness with constant addresses like those seen in memory
mapped registers in embedded systems.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358114
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David Green [Wed, 10 Apr 2019 18:00:41 +0000 (18:00 +0000)]
Revert rL357745: [SelectionDAG] Compute known bits of CopyFromReg
Certain optimisations from ConstantHoisting and CGP rely on Selection DAG not
seeing through to the constant in other blocks. Revert this patch while we come
up with a better way to handle that.
I will try to follow this up with some better tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358113
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Nico Weber [Wed, 10 Apr 2019 17:31:34 +0000 (17:31 +0000)]
llvm-undname: Fix another crash-on-invalid
This fixes a regression from https://reviews.llvm.org/D60354. We used to
SymbolNode *Symbol = demangleEncodedSymbol(MangledName, QN);
if (Symbol) {
Symbol->Name = QN;
}
but changed that to
SymbolNode *Symbol = demangleEncodedSymbol(MangledName, QN);
if (Error)
return nullptr;
Symbol->Name = QN;
and one branch somewhere returned a nullptr without setting Error.
Looking at the code changed in r340083 and r340710 that branch looks
like a remnant from an earlier attempt to demangle RTTI descriptors
that has since been rewritten -- so just remove this branch. It
shouldn't change behavior for correctly mangled symbols.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358112
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Matt Arsenault [Wed, 10 Apr 2019 17:27:56 +0000 (17:27 +0000)]
GlobalISel: Move computeValueLLTs
Call lowering should use this directly instead of going through the
EVT version, but more work is needed to deal with this (mostly the
passing of the IR type pointer instead of the relevant properties in
ArgInfo).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358111
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Matt Arsenault [Wed, 10 Apr 2019 17:27:55 +0000 (17:27 +0000)]
GlobalISel: Fix invoke lowering creating invalid type registers
Unlike the call handling, this wasn't checking for void results and
creating a register with the invalid LLT
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358110
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Matt Arsenault [Wed, 10 Apr 2019 17:27:53 +0000 (17:27 +0000)]
GlobalISel: Support legalizing G_CONSTANT with irregular breakdown
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358109
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Craig Topper [Wed, 10 Apr 2019 17:27:29 +0000 (17:27 +0000)]
[AArch64] Teach getTestBitOperand to look through ANY_EXTENDS
This patch teach getTestBitOperand to look through ANY_EXTENDs when the extended bits aren't used. The test case changed here is based what D60358 did to test16 in tbz-tbnz.ll. So this patch will avoid that regression.
Differential Revision: https://reviews.llvm.org/D60482
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358108
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Matt Arsenault [Wed, 10 Apr 2019 17:07:56 +0000 (17:07 +0000)]
GlobalISel: Handle odd breakdowns for bit ops
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358105
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Nick Desaulniers [Wed, 10 Apr 2019 16:38:44 +0000 (16:38 +0000)]
add FIXME: as per echristo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358102
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Nick Desaulniers [Wed, 10 Apr 2019 16:38:43 +0000 (16:38 +0000)]
[AsmPrinter] refactor to remove remove AsmVariant. NFC
Summary:
The InlineAsm::AsmDialect is only required for X86; no architecture
makes use of it and as such it gets passed around between arch-specific
and general code while being unused for all architectures but X86.
Since the AsmDialect is queried from a MachineInstr, which we also pass
around, remove the additional AsmDialect parameter and query for it deep
in the X86AsmPrinter only when needed/as late as possible.
This refactor should help later planned refactors to AsmPrinter, as this
difference in the X86AsmPrinter makes it harder to make AsmPrinter more
generic.
Reviewers: craig.topper
Subscribers: jholewinski, arsenm, dschuff, jyknight, dylanmckay, sdardis, nemanjai, jvesely, nhaehnle, javed.absar, sbc100, jgravelle-google, eraman, hiraditya, aheejin, kbarton, fedor.sergeev, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, jsji, llvm-commits, peter.smith, srhines
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D60488
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358101
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Nikita Popov [Wed, 10 Apr 2019 16:32:15 +0000 (16:32 +0000)]
[InstCombine] Handle ssubo always overflow
Following D60483 and D60497, this adds support for AlwaysOverflows
handling for ssubo. This is the last case we can handle right now.
Differential Revision: https://reviews.llvm.org/D60518
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358100
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Nikita Popov [Wed, 10 Apr 2019 16:27:36 +0000 (16:27 +0000)]
[InstCombine] ssubo X, C -> saddo X, -C
ssubo X, C is equivalent to saddo X, -C. Make the transformation in
InstCombine and allow the logic implemented for saddo to fold prior
usages of add nsw or sub nsw with constants.
Patch by Dan Robertson.
Differential Revision: https://reviews.llvm.org/D60061
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358099
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Sander de Smalen [Wed, 10 Apr 2019 16:24:48 +0000 (16:24 +0000)]
Improve compile-time performance in computeKnownBitsFromAssume.
This patch changes the order of pattern matching by first testing
a compare instruction's predicate, before doing the pattern
match for the whole expression tree.
Patch by Paul Walker.
Reviewed By: spatel
Differential Revision: https://reviews.llvm.org/D60504
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358097
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Simon Pilgrim [Wed, 10 Apr 2019 16:24:47 +0000 (16:24 +0000)]
[X86][AVX] getTargetConstantBitsFromNode - extract bits from X86ISD::SUBV_BROADCAST
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358096
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Nikita Popov [Wed, 10 Apr 2019 16:18:01 +0000 (16:18 +0000)]
[InstCombine] Handle saddo always overflow
Followup to D60483: Handle AlwaysOverflow conditions for saddo as
well.
Differential Revision: https://reviews.llvm.org/D60497
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358095
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Alexander Kornienko [Wed, 10 Apr 2019 15:42:53 +0000 (15:42 +0000)]
Fix a typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358092
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Fangrui Song [Wed, 10 Apr 2019 14:52:37 +0000 (14:52 +0000)]
[MachineOutliner] Replace ostringstream based string concatenation with Twine
This makes my libLLVMCodeGen.so.9svn 4936 bytes smaller.
While here, delete unused #include <map>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358089
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Robert Widmann [Wed, 10 Apr 2019 14:19:05 +0000 (14:19 +0000)]
[LLVM-C] Correct The Current Debug Location Accessors (Again)
Summary: Resubmitting D60484 with the conflicting Go bindings renamed to avoid collisions.
Reviewers: whitequark, deadalnix
Subscribers: hiraditya, llvm-commits, sammccall
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D60511
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358086
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Diogo N. Sampaio [Wed, 10 Apr 2019 13:34:18 +0000 (13:34 +0000)]
[AArch64] Add lowering pattern for scalar fp16 facge and facgt
Summary: The fp16 scalar version of facge and facgt requires a custom patter matching, as the result type is not the same width of the operands.
Reviewers: olista01, javed.absar, pbarrio
Reviewed By: javed.absar
Subscribers: kristof.beyls, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D60212
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358083
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Sam McCall [Wed, 10 Apr 2019 13:29:37 +0000 (13:29 +0000)]
Revert "[LLVM-C] Correct The Current Debug Location Accessors"
This reverts commit r358039, which added symbols that conflict with the
Go bindings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358082
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Diogo N. Sampaio [Wed, 10 Apr 2019 13:28:06 +0000 (13:28 +0000)]
[ARM] [FIX] Add missing f16 vector operations lowering
Summary:
Add missing <8xhalf> shufflevectors pattern, when using concat_vector dag node.
As well, allows <8xhalf> and <4xhalf> vldup1 operations.
These instructions are required for v8.2a fp16 lowering of vmul_n_f16, vmulq_n_f16 and vmulq_lane_f16 intrinsics.
Reviewers: olista01, pbarrio, LukeGeeson, efriedma
Reviewed By: efriedma
Subscribers: efriedma, javed.absar, kristof.beyls, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D60319
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358081
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Clement Courbet [Wed, 10 Apr 2019 13:18:05 +0000 (13:18 +0000)]
[NFC] Fix unused variable warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358080
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Roman Lebedev [Wed, 10 Apr 2019 12:47:47 +0000 (12:47 +0000)]
[llvm-exegesis] Pacify bots - don't std::move() - prevents copy elision
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358079
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Xing GUO [Wed, 10 Apr 2019 12:47:21 +0000 (12:47 +0000)]
[llvm-readobj] Should declare `ListScope` for `verneed` entries.
Summary: YAML mappings require keys to be unique. See: https://yaml.org/spec/1.2/spec.html#id2764652
Reviewers: jhenderson, grimar, rupprecht, espindola, ruiu
Reviewed By: ruiu
Subscribers: ruiu, emaste, arichardson, MaskRay, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D60438
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358078
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Roman Lebedev [Wed, 10 Apr 2019 12:20:14 +0000 (12:20 +0000)]
[llvm-exegesis] YamlContext: fix some missing spaces/quotes/newlines in error strings
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358077
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Roman Lebedev [Wed, 10 Apr 2019 12:19:57 +0000 (12:19 +0000)]
[llvm-exegesis] Fix error propagation from yaml writing (from serialization)
Investigating https://bugs.llvm.org/show_bug.cgi?id=41448
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358076
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David Stenberg [Wed, 10 Apr 2019 11:28:28 +0000 (11:28 +0000)]
[DebugInfo] Track multiple registers in DbgEntityHistoryCalculator
Summary:
When calculating the debug value history, DbgEntityHistoryCalculator
would only keep track of register clobbering for the latest debug value
per inlined entity. This meant that preceding register-described debug
value fragments would live on until the next overlapping debug value,
ignoring any potential clobbering. This patch amends
DbgEntityHistoryCalculator so that it keeps track of all registers that
a inlined entity's currently live debug values are described by.
The DebugInfo/COFF/pieces.ll test case has had to be changed since
previously a register-described fragment would incorrectly outlive its
basic block.
The parent patch D59941 is expected to increase the coverage slightly,
as it makes sure that location list entries are inserted after clobbered
fragments, and this patch is expected to decrease it, as it stops
preceding register-described from living longer than they should. All in
all, this patch and the preceding patch has a negligible effect on the
output from `llvm-dwarfdump -statistics' for a clang-3.4 binary built
using the RelWithDebInfo build profile. "Scope bytes covered" increases
by 0.5%, and "variables with location" increases from
2212083 to
2212088, but it should improve the accuracy quite a bit.
This fixes PR40283.
Reviewers: aprantl, probinson, dblaikie, rnk, bjope
Reviewed By: aprantl
Subscribers: llvm-commits
Tags: #debug-info, #llvm
Differential Revision: https://reviews.llvm.org/D59942
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358073
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David Stenberg [Wed, 10 Apr 2019 11:28:20 +0000 (11:28 +0000)]
[DebugInfo] Improve handling of clobbered fragments
Summary:
Currently the DbgValueHistorymap only keeps track of clobbered registers
for the last debug value that it has encountered. This could lead to
preceding register-described debug values living on longer in the
location lists than they should. See PR40283 for an example. This
patch does not introduce tracking of multiple registers, but changes
the DbgValueHistoryMap structure to allow for that in a follow-up
patch. This patch is not NFC, as it at least fixes two bugs in
DwarfDebug (both are covered in the new clobbered-fragments.mir test):
* If a debug value was clobbered (its End pointer set), the value would
still be added to OpenRanges, meaning that the succeeding location list
entries could potentially contain stale values.
* If a debug value was clobbered, and there were non-overlapping
fragments that were still live after the clobbering, DwarfDebug would
not create a location list entry starting directly after the
clobbering instruction. This meant that the location list could have
a gap until the next debug value for the variable was encountered.
Before this patch, the history map was represented by <Begin, End>
pairs, where a new pair was created for each new debug value. When
dealing with partially overlapping register-described debug values, such
as in the following example:
DBG_VALUE $reg2, $noreg, !1, !DIExpression(DW_OP_LLVM_fragment, 32, 32)
[...]
DBG_VALUE $reg3, $noreg, !1, !DIExpression(DW_OP_LLVM_fragment, 64, 32)
[...]
$reg2 = insn1
[...]
$reg3 = insn2
the history map would then contain the entries `[<DV1, insn1>, [<DV2, insn2>]`.
This would leave it up to the users of the map to be aware of
the relative order of the instructions, which e.g. could make
DwarfDebug::buildLocationList() needlessly complex. Instead, this patch
makes the history map structure monotonically increasing by dropping the
End pointer, and replacing that with explicit clobbering entries in the
vector. Each debug value has an "end index", which if set, points to the
entry in the vector that ends the debug value. The ending entry can
either be an overlapping debug value, or an instruction which clobbers
the register that the debug value is described by. The ending entry's
instruction can thus either be excluded or included in the debug value's
range. If the end index is not set, the debug value that the entry
introduces is valid until the end of the function.
Changes to test cases:
* DebugInfo/X86/pieces-3.ll: The range of the first DBG_VALUE, which
describes that the fragment (0, 64) is located in RDI, was
incorrectly ended by the clobbering of RAX, which the second
(non-overlapping) DBG_VALUE was described by. With this patch we
get a second entry that only describes RDI after that clobbering.
* DebugInfo/ARM/partial-subreg.ll: This test seems to indiciate a bug
in LiveDebugValues that is caused by it not being aware of fragments.
I have added some comments in the test case about that. Also, before
this patch DwarfDebug would incorrectly include a register-described
debug value from a preceding block in a location list entry.
Reviewers: aprantl, probinson, dblaikie, rnk, bjope
Reviewed By: aprantl
Subscribers: javed.absar, kristof.beyls, jdoerfert, llvm-commits
Tags: #debug-info, #llvm
Differential Revision: https://reviews.llvm.org/D59941
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358072
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Simon Pilgrim [Wed, 10 Apr 2019 11:09:58 +0000 (11:09 +0000)]
[TargetLowering] Move shouldFoldShiftPairToMask next to preferShiftsToClearExtremeBits. NFCI.
As discussed on PR41359, we're probably going to keep both of these but we need to make it more explicit how they complement each other.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358071
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Fangrui Song [Wed, 10 Apr 2019 10:35:10 +0000 (10:35 +0000)]
[AsmPrinter] Delete unused RangeSpanList::addRange
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358068
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Fangrui Song [Wed, 10 Apr 2019 10:30:22 +0000 (10:30 +0000)]
MCSymbolicELF: simplify. (Flags & (x << s)) >> s is equivalent to Flags >> s & x
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358067
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Fangrui Song [Wed, 10 Apr 2019 09:41:48 +0000 (09:41 +0000)]
MCDwarf: use write_zeroes for MCDwarfLineAddr::FixedEncode
This is more efficient than allocating a std::vector<uint8_t>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358066
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Diana Picus [Wed, 10 Apr 2019 09:31:28 +0000 (09:31 +0000)]
Fixup r358063
Fix warning/error about mixed signedness.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358065
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Diana Picus [Wed, 10 Apr 2019 09:14:37 +0000 (09:14 +0000)]
[ARM GlobalISel] Add some asserts. NFC.
Make sure some arm opcodes don't unintentionally sneak into thumb mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358064
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Diana Picus [Wed, 10 Apr 2019 09:14:32 +0000 (09:14 +0000)]
[ARM GlobalISel] Select G_FCONSTANT for VFP3
Make it possible to TableGen code for FCONSTS and FCONSTD.
We need to make two changes to the TableGen descriptions of vfp_f32imm
and vfp_f64imm respectively:
* add GISelPredicateCode to check that the immediate fits in 8 bits;
* extract the SDNodeXForms into separate definitions and create a
GISDNodeXFormEquiv and a custom renderer function for each of them.
There's a lot of boilerplate to get the actual value of the immediate,
but it basically just boils down to calling ARM_AM::getFP32Imm or
ARM_AM::getFP64Imm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358063
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Diana Picus [Wed, 10 Apr 2019 09:14:24 +0000 (09:14 +0000)]
[ARM GlobalISel] Select G_FCONSTANT into pools
Put all floating point constants into constant pools and load their
values from there.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358062
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Diana Picus [Wed, 10 Apr 2019 09:14:16 +0000 (09:14 +0000)]
[ARM GlobalISel] Map G_FCONSTANT
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358061
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David Stenberg [Wed, 10 Apr 2019 09:07:43 +0000 (09:07 +0000)]
[DebugInfo] Rename DbgValueHistoryMap::{InstrRange -> Entry}, NFC
Summary:
In an upcoming commit the history map will be changed so that it
contains explicit entries for instructions that clobber preceding debug
values, rather than Begin- End range pairs, so generalize the name to
"Entry".
Also, prefix the iterator variable names in buildLocationList() with
"E". In an upcoming commit the entry will have query functions such as
"isD(e)b(u)gValue", which could at a glance make one confuse it for
iterations over MachineInstrs, so make the iterator names a bit more
distinct to avoid that.
Reviewers: aprantl
Reviewed By: aprantl
Subscribers: llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D59939
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358060
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David Stenberg [Wed, 10 Apr 2019 09:07:32 +0000 (09:07 +0000)]
[DebugInfo] Make InstrRange into a class, NFC
Summary:
Replace use of std::pair by creating a class for the debug value
instruction ranges instead. This is a preparatory refactoring for
improving handling of clobbered fragments.
In an upcoming commit the Begin pointer will become a PointerIntPair, so
it will be cleaner to have a getter for that.
Reviewers: aprantl
Subscribers: llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D59938
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358059
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Florian Hahn [Wed, 10 Apr 2019 09:03:03 +0000 (09:03 +0000)]
[ScheduleDAG] Add statistics for maintaining the topological order.
This is helpful to measure the impact of D60125 on maintaining
topological orders.
Reviewers: MatzeB, atrick, efriedma, niravd
Reviewed By: efriedma
Differential Revision: https://reviews.llvm.org/D60187
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358058
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David Stenberg [Wed, 10 Apr 2019 08:44:57 +0000 (08:44 +0000)]
Add REQUIRES: asserts to test using -debug-only
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358057
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Florian Hahn [Wed, 10 Apr 2019 08:17:28 +0000 (08:17 +0000)]
[VPLAN] Minor improvement to testing and debug messages.
1. Use computed VF for stress testing.
2. If the computed VF does not produce vector code (VF smaller than 2), force VF to be 4.
3. Test vectorization of i64 data on AArch64 to make sure we generate VF != 4 (on X86 that was already tested on AVX).
Patch by Francesco Petrogalli <francesco.petrogalli@arm.com>
Differential Revision: https://reviews.llvm.org/D59952
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358056
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Fangrui Song [Wed, 10 Apr 2019 07:44:23 +0000 (07:44 +0000)]
[DWARF] Simplify LineTable::findRowInSeq
We want the last row whose address is less than or equal to Address.
This can be computed as upper_bound - 1, which is simpler than
lower_bound followed by skipping equal rows in a loop.
Since FirstRow (LowPC) does not satisfy the predicate (OrderByAddress)
while LastRow-1 (HighPC) satisfies the predicate. We can decrease the
search range by two, i.e.
upper_bound [FirstRow,LastRow) = upper_bound [FirstRow+1,LastRow-1)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358053
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Nikita Popov [Wed, 10 Apr 2019 07:10:53 +0000 (07:10 +0000)]
[InstCombine] Handle usubo always overflow
Check AlwaysOverflow condition for usubo. The implementation is the
same as the existing handling for uaddo and umulo. Handling for saddo
and ssubo will follow (smulo doesn't have the necessary ValueTracking
support).
Differential Revision: https://reviews.llvm.org/D60483
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358052
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Nikita Popov [Wed, 10 Apr 2019 07:10:44 +0000 (07:10 +0000)]
[InstCombine] Directly call computeOverflow methods in OptimizeOverflowCheck; NFC
Instead of using the willOverflow helpers. This makes it easier to
extend handling of AlwaysOverflows.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358051
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Chen Zheng [Wed, 10 Apr 2019 06:52:09 +0000 (06:52 +0000)]
[InstCombine] Canonicalize (-X s/ Y) to -(X s/ Y).
Differential Revision: https://reviews.llvm.org/D60395
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358050
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Akira Hatanaka [Wed, 10 Apr 2019 06:20:20 +0000 (06:20 +0000)]
[ObjC][ARC] Convert the retainRV marker that is passed as a named
metadata into a module flag in the auto-upgrader and make the ARC
contract pass read the marker as a module flag.
This is needed to fix a bug where ARC contract wasn't inserting the
retainRV marker when LTO was enabled, which caused objects returned
from a function to be auto-released.
rdar://problem/
49464214
Differential Revision: https://reviews.llvm.org/D60303
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358047
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Craig Topper [Wed, 10 Apr 2019 05:43:20 +0000 (05:43 +0000)]
[X86] Move the 2 byte VEX optimization for MOV instructions back to the X86AsmParser::processInstruction where it used to be. Block when {vex3} prefix is present.
Years ago I moved this to an InstAlias using VR128H/VR128L. But now that we support {vex3} pseudo prefix, we need to block the optimization when it is set to match gas behavior.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358046
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Fangrui Song [Wed, 10 Apr 2019 05:31:21 +0000 (05:31 +0000)]
[llvm-objdump] Don't print trailing space in dumpBytes
In disassembly output, dumpBytes prints a space, followed by a tab
printed by printInstr. Remove the extra space.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358045
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Fangrui Song [Wed, 10 Apr 2019 04:46:01 +0000 (04:46 +0000)]
[llvm-objdump] Accept and ignore --wide/-w
This is similar to what we do for llvm-readobj (--wide/-W is for GNU
readelf compatibility).
The test will be added in D60376.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358043
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Jim Lin [Wed, 10 Apr 2019 01:56:32 +0000 (01:56 +0000)]
[Sparc] Fix incorrect MI insertion position for spilling f128.
Summary:
Obviously, new built MI (sethi+add or sethi+xor+add) for constructing large offset
should be inserted before new created MI for storing even register into memory.
So the insertion position should be *StMI instead of II.
before fixed:
std %f0, [%g1+80]
sethi 4, %g1 <<<
add %g1, %sp, %g1 <<< this two instructions should be put before "std %f0, [%g1+80]".
sethi 4, %g1
add %g1, %sp, %g1
std %f2, [%g1+88]
after fixed:
sethi 4, %g1
add %g1, %sp, %g1
std %f0, [%g1+80]
sethi 4, %g1
add %g1, %sp, %g1
std %f2, [%g1+88]
Reviewers: venkatra, jyknight
Reviewed By: jyknight
Subscribers: jyknight, fedor.sergeev, jrtc27, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D60397
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358042
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Craig Topper [Wed, 10 Apr 2019 01:29:59 +0000 (01:29 +0000)]
[X86] Support the EVEX versions vcvt(t)ss2si and vcvt(t)sd2si with the {evex} pseudo prefix in the assembler.
The EVEX versions are ambiguous with the VEX versions based on operands alone so we had explicitly dropped
them from the AsmMatcher table. Unfortunately, when we add them they incorrectly show in the table before
their VEX counterparts. This is different how the prioritization normally works.
To fix this we have to explicitly reject the instructions unless the {evex} prefix has been seen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358041
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