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Jose Maria Casanova Crespo [Sat, 1 Jul 2017 06:19:17 +0000 (08:19 +0200)]
i965/fs: Add byte scattered read message and fs support
v2: Fix alignment style (Topi Pohjolainen)
(Jason Ekstrand)
- Enable bit_size parameter to scattered messages to enable different
bitsizes byte/word/dword.
- Remove use of brw_send_indirect_scattered_message in favor of
brw_send_indirect_surface_message.
- Move scattered messages to surface messages namespace.
- Assert align1 for scattered messages and assume Gen8+.
- Inline brw_set_dp_byte_scattered_read.
v3: (Jason Ekstrand)
- Use renamed brw_byte_scattered_data_element_from_bit_size method
- Assert scattered read for Gen8+ and Haswell.
- Use conditional expresion at components_read.
- Include comment about params for scattered opcodes.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Alejandro Piñeiro [Sat, 29 Jul 2017 14:10:02 +0000 (16:10 +0200)]
i965/fs: Predicate byte scattered writes if needed
While on Untyped Surface messages the bits of the execution mask are
ANDed with the corresponding bits of the Pixel/Sample Mask, that is
not the case for byte scattered writes. That is needed to avoid ssbo
stores writing on helper invocations. So when that can affect, we load
the sample mask, and predicate the send message.
Note: the need for this patch was tested with a custom test. Right now
the 16 bit storage CTS tests doesnt need this path in order to get a
full pass.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Alejandro Piñeiro [Sat, 1 Jul 2017 06:17:09 +0000 (08:17 +0200)]
i965/fs: Use byte_scattered_write on 16-bit store_ssbo
We need to rely on byte scattered writes as untyped writes are 32-bit
size. We could try to keep using 32-bit messages when we have two or
four 16-bit elements, but for simplicity sake, we use the same message
for any component number. We revisit this aproach in the follwing
patches.
v2: Removed use of stride = 2 on 16-bit sources (Jason Ekstrand)
v3: (Jason Ekstrand)
- Include bit_size to scattered write message and remove namespace
- specific for scattered messages.
- Move comment to proper place.
- Squashed with i965/fs: Adjust type_size/type_slots on store_ssbo.
(Jose Maria Casanova)
- Take into account that get_nir_src returns now WORD types for
16-bit sources instead of DWORD.
v4: (Jason Ekstrand)
- Rename lenght variable to num_components.
- Include assertions before emit_untyped_write.
- Remove type_slot in favor of num_slot and first_slot.
Signed-off-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Signed-off-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Jose Maria Casanova Crespo [Sat, 1 Jul 2017 06:16:01 +0000 (08:16 +0200)]
i965/fs: Add byte scattered write message and fs support
v2: (Jason Ekstrand)
- Enable bit_size parameter to scattered messages to enable different
bitsizes byte/word/dword.
- Remove use of brw_send_indirect_scattered_message in favor of
brw_send_indirect_surface_message.
- Move scattered messages to surface messages namespace.
- Assert align1 for scattered messages and assume Gen8+.
- Inline brw_set_dp_byte_scattered_write.
v3: - Remove leftover newline (Topi Pohjolainen)
- Rename brw_data_size to brw_scattered_data_element and use
defines instead of an enum (Jason Ekstrand)
- Assert scattered write for Gen8+ and Haswell (Jason Ekstrand)
Signed-off-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Signed-off-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Alejandro Piñeiro [Sat, 1 Jul 2017 06:14:56 +0000 (08:14 +0200)]
i965/fs: Add remove_extra_rounding_modes optimization
Although from SPIR-V point of view, rounding modes are attached to the
operation/destination, on i965 it is a status, so we don't need to
explicitly set the rounding mode if the one we want is already set.
Taking into account that the default mode is RTE, one possible
optimization would be optimize out the first RTE set for each
block. For in order to work, we would need to take into account block
interrelationships. At this point, it is not worth to complicate the
optimization for such small gain.
v2: Use a single SHADER_OPCODE_RND_MODE opcode taking an immediate
with the rounding mode (Curro)
v3: Reset optimization for every block. (Jason Ekstrand)
Signed-off-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Signed-off-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Alejandro Piñeiro [Sat, 1 Jul 2017 06:14:09 +0000 (08:14 +0200)]
i965/fs: Enable rounding mode on f2f16 ops
By default we don't set the rounding mode. We only set
round-to-near-even or round-to-zero mode if explicitly set from nir.
v2: Use a single SHADER_OPCODE_RND_MODE opcode taking an immediate
with the rounding mode (Curro)
v3: Use new helper brw_rnd_mode_from_nir_op (Jason Ekstrand)
Signed-off-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Signed-off-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Alejandro Piñeiro [Sat, 1 Jul 2017 06:12:59 +0000 (08:12 +0200)]
i965/fs: Define new shader opcode to set rounding modes
Although it is possible to emit them directly as AND/OR on brw_fs_nir,
having a specific opcode makes it easier to remove duplicate settings
later.
v2: (Curro)
- Set thread control to 'switch' when using the control register
- Use a single SHADER_OPCODE_RND_MODE opcode taking an immediate
with the rounding mode.
- Avoid magic numbers setting rounding mode field at control register.
v3: (Curro)
- Remove redundant and add missing whitespace lines.
- Match printing instruction to IR opcode "rnd_mode"
v4: (Topi Pohjolainen)
- Fix code style.
Signed-off-by: Alejandro Piñeiro <apinheiro@igalia.com>
Signed-off-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Jose Maria Casanova Crespo [Sat, 1 Jul 2017 06:11:58 +0000 (08:11 +0200)]
i965: Add support for control register
Control register cr0 in i965 can be used to change the rounding modes
in 32-bit to 16-bit floating-point conversions.
From intel Skylake PRM, vol 07, section "Register and Tegister Regions",
subsection "Control Register" (page 754):
"Subregister cr0.0:ud contains normal operation control fields such as the
floating-point mode ... "
Floating-point Rounding mode is changed at bits 5:4 of cr0.0:
"Rounding Mode. This field specifies the FPU rounding mode. It is
initialized by Thread Dispatch."
00b = Round to Nearest or Even (RTNE)
01b = Round Up, toward +inf (RU)
10b = Round Down, toward -inf (RD)
11b = Round Toward Zero (RTZ)"
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Alejandro Piñeiro [Sat, 1 Jul 2017 06:11:05 +0000 (08:11 +0200)]
i965/fs: Handle 32-bit to 16-bit conversions
Conversions to 16-bit need having aligment between the 16-bit
and 32-bit types. So the conversion operations unpack 16-bit types
to with an stride=2 and then applies a MOV with the conversion.
v2 (Jason Ekstrand):
- Avoid the general use of stride=2 for 16-bit register types.
v3 (Topi Pohjolainen)
- Code style fix
(Jason Ekstrand)
- Now nir_op_f2f16 was renamed to nir_op_f2f16_undef
because conversion to f16 with undefined rounding is explicit
Signed-off-by: Eduardo Lima <elima@igalia.com>
Signed-off-by: Alejandro Piñeiro <apinheiro@igalia.com>
Signed-off-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Alejandro Piñeiro [Sat, 1 Jul 2017 06:08:20 +0000 (08:08 +0200)]
i965/fs: Remove BRW_REGISTER_TYPE_HF assert at get_exec_type
Note that we don't remove the assert at i965/vec4. At this point half
float support is only for the scalar backend.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Jose Maria Casanova Crespo [Sat, 1 Jul 2017 06:06:45 +0000 (08:06 +0200)]
i965: Support for 16-bit base types in helper functions
v2: Fixed calculation of scalar size for 16-bit types. (Jason Ekstrand)
v3: Fix coding style (Topi Pohjolainen)
Signed-off-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Signed-off-by: Eduardo Lima <elima@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Alejandro Piñeiro [Sat, 1 Jul 2017 06:06:17 +0000 (08:06 +0200)]
i965/vec4: Handle 16-bit types at type_size_xvec4
These types have similar vec4 sizes as their 32-bit counterparts.
The vec4 backend doesn't support 16-bit types and probably never will,
but this method is called by the scalar backend at
fs_visitor::nir_setup_outputs(), so we still need to provide valid vec4
sizes for 16-bit types. In the future, something different should be
implemented to avoid this dependency.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Eduardo Lima Mitev [Sat, 1 Jul 2017 06:02:45 +0000 (08:02 +0200)]
spirv/nir: Add support for SPV_KHR_16bit_storage
v2: Minor changes after rebase against recent master (Alejandro
Pinheiro)
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Jose Maria Casanova Crespo [Sat, 1 Jul 2017 06:05:55 +0000 (08:05 +0200)]
spirv: Enable FPRoundingMode decorator to nir operations
SpvOpFConvert now manages the FPRoundingMode decorator for the
returning values enabling the nir_rounding_mode in the conversion
operation to fp16 values.
v2: Fixed breaking of specialization constants. (Jason Ekstrand)
v3: Avoid nir_rounding_mode * casting. (Jason Ekstrand)
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Eduardo Lima Mitev [Sat, 1 Jul 2017 06:04:40 +0000 (08:04 +0200)]
spirv/nir: Handle 16-bit types
v2: Added more missing implementations of 16-bit types. (Jason Ekstrand)
v3: Store values in values[0].u16[i] (Jason Ekstrand)
Include switches based on bitsize for 16-bit types
(Chema Casanova)
v4: Coding style fixes (Jason Ekstrand)
Use vtn_u64_literal and u64[0] at 64-bit SpvOpConstant (Jason Ekstrand)
Signed-off-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Signed-off-by: Eduardo Lima <elima@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Jose Maria Casanova Crespo [Sat, 1 Jul 2017 05:58:26 +0000 (07:58 +0200)]
nir: Handle fp16 rounding modes at nir_type_conversion_op
nir_type_conversion enables new operations to handle rounding modes to
convert to fp16 values. Two new opcodes are enabled nir_op_f2f16_rtne
and nir_op_f2f16_rtz.
The undefined behaviour doesn't has any effect and uses the original
nir_op_f2f16 operation.
v2: Indentation fixed (Jason Ekstrand)
v3: Use explicit case for undefined rounding and assert if
rounding mode is used for non 16-bit float conversions
(Jason Ekstrand)
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Eduardo Lima Mitev [Sat, 1 Jul 2017 06:01:21 +0000 (08:01 +0200)]
nir: Populate conversion opcodes to 16-bit types
This will include the following NIR ALU opcodes:
* nir_op_i2i16
* nir_op_i2f16
* nir_op_u2u16
* nir_op_u2f16
* nir_op_f2i16
* nir_op_f2u16
* nir_op_f2f16
v2: Remove "from" 16-bit in commit subject (Topi Pohjolainen)
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Jose Maria Casanova Crespo [Sat, 1 Jul 2017 05:56:51 +0000 (07:56 +0200)]
nir: Add rounding modes enum
v2: Added comments describing each of the rounding modes. (Jason
Ekstrand)
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Eduardo Lima Mitev [Sat, 1 Jul 2017 05:54:50 +0000 (07:54 +0200)]
nir: Add support for 16-bit types (half float, int16 and uint16)
v2: Renamed glsl_half_float_type() to glsl_float16_t_type().
(Jason Ekstrand)
Signed-off-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Signed-off-by: Eduardo Lima <elima@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Eduardo Lima Mitev [Thu, 17 Aug 2017 07:51:22 +0000 (09:51 +0200)]
mesa/st: Handle 16-bit types at st_glsl_storage_type_size()
This is basically to avoid "not handle in switch" warnings.
v2: Let the new types hit the assertion instead. (Marek Olšák
and Jason Ekstrand)
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Eduardo Lima Mitev [Sat, 1 Jul 2017 05:46:41 +0000 (07:46 +0200)]
glsl: Add 16-bit types
Adds new INT16, UINT16 and FLOAT16 base types.
The corresponding GL types for half floats were reused from the
AMD_gpu_shader_half_float extension. The int16 and uint16 types come from
NV_gpu_shader_5 extension.
This adds the builtins and the lexer support.
To avoid a bunch of warnings due to cases not handled in switch, the
new types have been added to a few places using same behavior as
their 32-bit counterparts, except for a few trivial cases where they are
already handled properly. Subsequent patches in this set will provide
correct 16-bit implementations when needed.
v2: * Use FLOAT16 instead of HALF_FLOAT as name of the base type.
* Removed float16_t from builtin types.
* Don't copy 16-bit types as if they were 32-bit values in
copy_constant_to_storage().
* Use get_scalar_type() instead of adding a new custom switch
statement.
(Jason Ekstrand)
v3: Use GL_FLOAT16_NV instead of GL_HALF_FLOAT for consistency
(Ilia Mirkin)
v4: Add missing 16-bit base types support in glsl_to_nir (Eduardo Lima).
v5: Fix coding style (Topi Poholainen).
Signed-off-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Signed-off-by: Eduardo Lima <elima@igalia.com>
Signed-off-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Jason Ekstrand [Thu, 19 Oct 2017 01:02:49 +0000 (18:02 -0700)]
anv: Add support for the variablePointers feature
Not to be confused with variablePointersStorageBuffer which is the
subset of VK_KHR_variable_pointers required to enable the extension.
This means we now have "full" support for variable pointers.
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Jason Ekstrand [Fri, 1 Dec 2017 00:55:45 +0000 (16:55 -0800)]
spirv: Allow OpPtrAccessChain for block indices
The SPIR-V spec is a bit underspecified when it comes to exactly how
you're allowed to use OpPtrAccessChain and what it means in certain edge
cases. In particular, what if the base pointer of the OpPtrAccessChain
points to the base struct of an SSBO instead of an element in that SSBO.
The original variable pointers implementation in mesa assumed that you
weren't allowed to do an OpPtrAccessChain that adjusted the block index
and asserted such. However, there are some CTS tests that do this and,
if the CTS does it, someone will do it in the wild so we should probably
handle it. With this commit, we significantly reduce our assumptions
and should be able to handle more-or-less anything.
The one assumption we still make for correctness is that if we see an
OpPtrAccessChain on a pointer to a struct decorated block that the block
index should be adjusted. In theory, someone could try to put an array
stride on such a pointer and try to make the SSBO an implicit array of
the base struct and we would not give them what they want. That said,
any index other than 0 would count as an out-of-bounds access which is
invalid.
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Jason Ekstrand [Fri, 1 Dec 2017 01:13:56 +0000 (17:13 -0800)]
anv: Handle nir_intrinsic_vulkan_resource_reindex
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Jason Ekstrand [Thu, 30 Nov 2017 23:56:39 +0000 (15:56 -0800)]
nir: Add a vulkan_resource_reindex intrinsic
This is required for being able to handle OpPtrAccessChain in SPIR-V
where the base type of the incoming pointer requires us to add to the
block index instead of the byte offset.
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Jason Ekstrand [Thu, 19 Oct 2017 00:59:47 +0000 (17:59 -0700)]
spirv: Add support for lowering workgroup access to offsets
Before, we always left workgroup variables as shared nir_variables and
let the driver call nir_lower_io. This adds an option to do the
lowering directly in spirv_to_nir. To do this, we implicitly assign the
variables a std430 layout and then treat them like a UBO or SSBO and
immediately lower all the way to an offset.
As a side-effect, the spirv_to_nir pass now handles variable pointers
for workgroup variables.
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Jason Ekstrand [Thu, 19 Oct 2017 14:40:59 +0000 (07:40 -0700)]
spirv: Rename get_shared_nir_atomic_op to get_var_nir_atomic_op
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Jason Ekstrand [Thu, 19 Oct 2017 00:58:11 +0000 (17:58 -0700)]
spirv: Add theoretical support for single component pointers
Up until now, all pointers have been ivec2s. We're about to add support
for pointers to workgroup storage and those are going to be uints.
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Jason Ekstrand [Thu, 19 Oct 2017 16:23:07 +0000 (09:23 -0700)]
spirv: Use offset_pointer_dereference to instead of get_vulkan_resource_index
There is no good reason why we should have the same logic repeated in
get_vulkan_resource_index and vtn_ssa_offset_pointer_dereference. If
we're a bit more careful about how we do things, we can just use the one
function and get rid of the other entirely. This also makes the push
constant special case a lot more clear.
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Jason Ekstrand [Thu, 19 Oct 2017 00:38:57 +0000 (17:38 -0700)]
spirv: Refactor a couple of pointer query helpers
This commit moves them both into vtn_variables.c towards the top, makes
them take a vtn_builder, and replaces a hand-rolled instance of
is_external_block with a function call.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Jason Ekstrand [Wed, 18 Oct 2017 23:40:39 +0000 (16:40 -0700)]
spirv: Refactor the base case of offset_pointer_dereference
This makes us key off of !offset instead of !block_index. It also puts
the guts inside a switch statement so that we can handle more than just
UBOs and SSBOs.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Jason Ekstrand [Wed, 18 Oct 2017 23:36:04 +0000 (16:36 -0700)]
spirv: Add a switch statement for the block store opcode
This parallels what we do for vtn_block_load except that we don't yet
support anything except SSBO loads through this path.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Jason Ekstrand [Wed, 18 Oct 2017 23:33:32 +0000 (16:33 -0700)]
spirv: Use a dereference instead of vtn_variable_resource_index
This is equivalent and means we don't have resource index code scattered
about.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Brian Paul [Tue, 5 Dec 2017 19:05:48 +0000 (12:05 -0700)]
mesa: add const qualifier on _mesa_is_renderable_texture_format()
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Brian Paul [Tue, 5 Dec 2017 19:05:18 +0000 (12:05 -0700)]
mesa: add const qualifier on _mesa_base_fbo_format()
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Brian Paul [Tue, 5 Dec 2017 16:57:23 +0000 (09:57 -0700)]
mesa: s/%u/%d/ in _mesa_error() call in check_layer()
The layer parameter is signed. Fixes the error message seen when
running the arb_texture_multisample-errors test which checks a
negative layer value.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Brian Paul [Tue, 5 Dec 2017 16:27:52 +0000 (09:27 -0700)]
mesa: simplify/improve some _mesa_error() calls in teximage.c
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Brian Paul [Tue, 5 Dec 2017 14:14:08 +0000 (07:14 -0700)]
mesa: trivial whitespace fixes in transformfeedback.c
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Brian Paul [Tue, 5 Dec 2017 04:27:54 +0000 (21:27 -0700)]
mesa: add const qualifier in test_attachment_completeness()
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Brian Paul [Tue, 5 Dec 2017 14:13:53 +0000 (07:13 -0700)]
st/mesa: remove unneeded #include in st_format.h
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Brian Paul [Tue, 5 Dec 2017 04:32:33 +0000 (21:32 -0700)]
st/mesa: rename a few vars to 'bindings'
To be consistent.
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Brian Paul [Tue, 5 Dec 2017 04:28:34 +0000 (21:28 -0700)]
st/mesa: whitespace fixes in st_format.c
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Rob Clark [Tue, 5 Dec 2017 20:58:31 +0000 (15:58 -0500)]
freedreno/a5xx: hide ARB_base_instance
Grrr..
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Tue, 5 Dec 2017 13:40:18 +0000 (08:40 -0500)]
freedreno/ir3: handle input/output component
After the mesa/st nir linking support, we start to see inputs/outputs
like:
decl_var shader_out INTERP_MODE_NONE float packed:uv (VARYING_SLOT_VAR9.x, 1, 0)
decl_var shader_out INTERP_MODE_NONE float packed:uv@0 (VARYING_SLOT_VAR9.y, 1, 0)
(ie. were location_frac != .x)
Unfortunately I overlooked the addition of the component parameter to
load_input/store_output, so when we started encountering inputs/outputs
with component other than .x, we'd end up loading/storing the wrong
input/output.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Tue, 5 Dec 2017 14:53:56 +0000 (09:53 -0500)]
mesa/st: move cloning of NIR shader for compute
Since in the NIR case, driver takes ownership of the NIR shader, we need
to clone what is passed to the driver. Normally this is done as part of
creating the shader variant (where is clone is anyways needed). But
compute shaders have no variants, so we were cloning earlier.
The problem is that after the NIR linking optimizations, we ended up
cloning *before* all the lowering passes where done.
So move this into st_get_cp_variant(), to make compute shaders work more
like other shader stages.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Dave Airlie [Fri, 3 Nov 2017 01:33:44 +0000 (11:33 +1000)]
r600: refactor and export some shader selector code for compute
This just moves some code around to make it easier to add compute.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Fri, 3 Nov 2017 01:27:23 +0000 (11:27 +1000)]
r600: add compute support to compressed resource handling.
This just adds support for decompressing compute resources.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Fri, 3 Nov 2017 01:23:55 +0000 (11:23 +1000)]
r600: update max threads per block for evergreen compute
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Fri, 3 Nov 2017 01:14:28 +0000 (11:14 +1000)]
r600/shader: add local memory support to shader assembler.
This is needed for compute shaders.
v1.1: make work for vectors, fix missing lds ops.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Fri, 3 Nov 2017 01:11:15 +0000 (11:11 +1000)]
r600/cs: add support for compute to image/buffers/atomics state
This just adds the compute paths to state handling for the
main objects
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Fri, 3 Nov 2017 02:23:26 +0000 (12:23 +1000)]
r600: handle compute null key shader state
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 27 Nov 2017 06:54:00 +0000 (06:54 +0000)]
r600: add some missing cayman register defines
These are just taken from the kernel, and were seen in some fglrx dumps.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Thu, 23 Nov 2017 04:05:05 +0000 (14:05 +1000)]
r600: don't set EOP on pop or loop end
This appears to bad, compute shaders hang without it.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Tue, 5 Dec 2017 08:41:35 +0000 (08:41 +0000)]
r600/ssbo: refactor out buffer coord calcs and use for atomic path.
The atomic rat path has a bug in the ssbo path, refactor out the
address calcs from the load/store paths and reuse to fix the bug
in the buffer rat atomic path.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Tue, 5 Dec 2017 08:38:26 +0000 (08:38 +0000)]
r600/ssbo: fix multi-dword buffer loads.
This fixes loading from different channels.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Tue, 5 Dec 2017 08:35:24 +0000 (08:35 +0000)]
r600/ssbo: use r32ui format for ssbo resources.
This works best for returning the correct values and sizes in
tests.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Tue, 5 Dec 2017 08:34:26 +0000 (08:34 +0000)]
r600: refactor out the immediate setup code.
This just refactors the same code out of the images/buffers paths.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Tue, 5 Dec 2017 08:28:13 +0000 (08:28 +0000)]
r600/shader: fix ssbo atomic operations formats.
Don't try and use the image format for ssbo, just 32-bit uint.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Tue, 5 Dec 2017 08:27:38 +0000 (08:27 +0000)]
r600/shader: fix thread id loading.
This just changes how thread id loading is done, it makes
smaller shaders if we don't use thread id gprs.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Rob Herring [Tue, 5 Dec 2017 00:35:48 +0000 (18:35 -0600)]
Android: enable noreturn and returns_nonnull attributes
Commit
94ca8e04adf6 ("spirv: Add vtn_fail and vtn_assert helpers") broke
Android builds which have -Werror enabled with the following errors:
external/mesa3d/src/compiler/spirv/spirv_to_nir.c:272:1: error: control may reach end of non-void function [-Werror,-Wreturn-type]
external/mesa3d/src/compiler/spirv/spirv_to_nir.c:810:1: error: control may reach end of non-void function [-Werror,-Wreturn-type]
...
The problem is the noreturn attribute is not enabled and we to define
HAVE_FUNC_ATTRIBUTE_NORETURN.
Auditing src/util/macros.h, we're also missing
HAVE_FUNC_ATTRIBUTE_RETURNS_NONNULL and HAVE_FUNC_ATTRIBUTE_WARN_UNUSED_RESULT,
so add them too.
Fixes:
94ca8e04adf6 ("spirv: Add vtn_fail and vtn_assert helpers")
Cc: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Marek Olšák [Fri, 1 Dec 2017 02:05:18 +0000 (03:05 +0100)]
gallium/u_upload_mgr: allow drivers to specify pipe_resource::flags
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Fri, 1 Dec 2017 01:07:05 +0000 (02:07 +0100)]
winsys/amdgpu: add RADEON_FLAG_READ_ONLY
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 30 Nov 2017 23:14:51 +0000 (00:14 +0100)]
gallium/radeon: remove RADEON_HEAP_VRAM_GTT
Only winsyses can set VRAM|GTT. Drivers shouldn't if they want to use
winsys allocators.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 30 Nov 2017 23:06:34 +0000 (00:06 +0100)]
gallium/radeon: move setting VRAM|GTT into winsyses
The combined VRAM|GTT heap will be removed.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 30 Nov 2017 21:46:39 +0000 (22:46 +0100)]
radeonsi: flush the context after resource_copy_region for buffer exports
Cc: 17.2 17.3 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Mauro Rossi [Sat, 2 Dec 2017 12:36:57 +0000 (13:36 +0100)]
Android: gallium/radeon: fix libmesa_amd_common dependency
libmesa_amd_common static dependency is added in Android build
to avoid the following building errors:
In file included from external/mesa/src/gallium/drivers/radeon/r600_buffer_common.c:24:
In file included from external/mesa/src/gallium/drivers/radeonsi/si_pipe.h:26:
external/mesa/src/gallium/drivers/radeonsi/si_shader.h:138:10: fatal error: 'ac_binary.h' file not found
^~~~~~~~~~~~~
1 error generated.
...
In file included from external/mesa/src/gallium/drivers/radeon/r600_gpu_load.c:34:
In file included from external/mesa/src/gallium/drivers/radeonsi/si_pipe.h:26:
external/mesa/src/gallium/drivers/radeonsi/si_shader.h:138:10: fatal error: 'ac_binary.h' file not found
^~~~~~~~~~~~~
1 error generated.
Fixes:
950221f923 ("radeonsi: remove r600_common_screen")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Dave Airlie [Fri, 3 Nov 2017 02:23:01 +0000 (12:23 +1000)]
st/mesa: handle compute atomics
Just reuse the cs atomics bit and emit the hw atomic state.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Fri, 1 Dec 2017 04:06:19 +0000 (04:06 +0000)]
r600/atomic: add cayman version of atomic save/restore from GDS (v2)
On Cayman we don't use the append/consume counters (fglrx doesn't)
and they don't seem to work well with compute shaders.
This just uses GDS instead to do the atomic operations.
v1.1: remove unused line.
v2: use EOS on cayman, it appears to work.
Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Fri, 1 Dec 2017 04:02:33 +0000 (04:02 +0000)]
r600/atomic: refactor out evergreen atomic setup/save code.
For cayman we want to use different code paths.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Timothy Arceri [Thu, 23 Nov 2017 00:29:59 +0000 (11:29 +1100)]
radeonsi: pass llvm type directly to buffer_load()
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Dylan Baker [Tue, 14 Nov 2017 01:58:51 +0000 (17:58 -0800)]
meson: build gallium nine state_tracker
v2: - set d3d_drivers_path instead of dri_drivers_path
- Fix nine guard to check for all relavent gallium drivers
- Link with libswdri and libswkmsdri when necessary
- Fix pkg-config generation
- Add missing comma
Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Dylan Baker [Tue, 31 Oct 2017 00:40:30 +0000 (17:40 -0700)]
meson: build gallium xa state tracker
Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Dylan Baker [Mon, 30 Oct 2017 22:49:37 +0000 (15:49 -0700)]
meson: build gallium va state tracker
Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Dylan Baker [Mon, 30 Oct 2017 22:23:06 +0000 (15:23 -0700)]
meson: build gallium omx state tracker
Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Dylan Baker [Mon, 30 Oct 2017 21:32:30 +0000 (14:32 -0700)]
meson: build gallium xvmc state tracker
Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Dylan Baker [Mon, 30 Oct 2017 21:04:21 +0000 (14:04 -0700)]
meson: build gallium vdpau state tracker
Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Dylan Baker [Tue, 31 Oct 2017 22:12:20 +0000 (15:12 -0700)]
meson: drop gallium-media argument
This argument is the wrong approach for handling gallium media state
trackers, since it doesn't allow for an auto option. Instead we'll use
tristates, which do allow for auto.
This option has never been wired to anything anyway.
Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Dylan Baker [Fri, 10 Nov 2017 01:52:31 +0000 (17:52 -0800)]
meson: extend install_megadrivers script to handle symmlinking
Which is required for the gallium media state trackers.
v2: - Make symlinks local instead of absolute
Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Dylan Baker [Wed, 29 Nov 2017 17:46:25 +0000 (09:46 -0800)]
meson: Add osmesa.sym script as a link dependency (gallium-osmesa)
v2: - Add this patch
Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Dylan Baker [Wed, 15 Nov 2017 22:00:19 +0000 (14:00 -0800)]
meson: use driver_deps for gallium osmesa
v2: - Put driver_swrast in the correct field (dependencies)
- Remove unused osmesa_deps
Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Acked-by: Eric Engestrom <eric.engestrom@imgtec.com>
Dylan Baker [Wed, 15 Nov 2017 18:50:11 +0000 (10:50 -0800)]
meson: Use driver dependencies for libgl-xlib target
v2: - put driver_swrast in the right field
- add dep_threads (dep_llvm requires threads, so it masked this
previously)
Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Acked-by: Eric Engestrom <eric.engestrom@imgtec.com>
Dylan Baker [Wed, 15 Nov 2017 18:45:29 +0000 (10:45 -0800)]
meson: use the driver dependencies for the gallium dri target
Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Dylan Baker [Wed, 15 Nov 2017 18:43:20 +0000 (10:43 -0800)]
meson: define driver dependencies
This allow us to encapsulate the compiler and linkage requirements of
each driver in a reusable way. The result will be that each target that
needs a specific driver can simply add `driver_<name>` to its
dependencies line and the necessary libraries and compiler args will be
added. This will allow for a lot of code de-duplication between gallium
targets.
Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Dylan Baker [Wed, 15 Nov 2017 18:41:42 +0000 (10:41 -0800)]
meson: sort gallium drivers after winsys
This is a requirement of the next patch. Since meson does not have
forward declarations, and we're going to define the driver dependencies
in the drivers folder they need to be after the winsys so that the
winsys libs are defined first.
Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Dylan Baker [Tue, 28 Nov 2017 22:30:27 +0000 (14:30 -0800)]
meson: Combine gallium target subdirs
So that state trackers, targets, and special winsys requirements are all
in a single if statement. This is a cosmetic only cleanup with no
functional changes.
Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Nanley Chery [Fri, 1 Dec 2017 22:18:21 +0000 (14:18 -0800)]
i965/cnl: Avoid fast-clearing sRGB render buffers
Gen10 doesn't automatically decode the clear color of sRGB buffers. To
get correct rendering, avoid fast-clearing such buffers for now.
The driver now passes the following piglit tests:
* spec@arb_framebuffer_srgb@msaa-fast-clear
* spec@ext_texture_srgb@multisample-fast-clear gl_ext_texture_srgb
Suggested-by: Kenneth Graunke <kenneth@whitecape.org>
Suggested-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Dylan Baker [Fri, 1 Dec 2017 22:54:31 +0000 (14:54 -0800)]
meson: Fix overlinkage of dri3 loader
This was covering for underinkage elsewhere. With that fixed these can
be removed.
v2: - sort dependencies
Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Jon Turney <jon.turney@dronecode.org.uk> (v1)
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com> (v1)
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Dylan Baker [Fri, 1 Dec 2017 22:51:11 +0000 (14:51 -0800)]
meson: fix underlinkage without dri3
There are some case where the dri3 loader is covering for underlinkage
for GLX and EGL, provide the linkage that they actually need.
v2: - remove dep_xcb_dri3 from glx. This was an oversight in v1 and is
not needed.
Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Jon Turney <jon.turney@dronecode.org.uk> (v1)
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com> (v1)
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Dylan Baker [Fri, 1 Dec 2017 22:46:42 +0000 (14:46 -0800)]
meson: Reformat glx code to match more common style
Generally in our meson build large arrays are formated in the form:
[
..., ..., ..., $
...,
]
So use that form
Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Jon Turney <jon.turney@dronecode.org.uk>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Samuel Pitoiset [Mon, 4 Dec 2017 14:32:58 +0000 (15:32 +0100)]
radv: fix a crash in radv_can_dump_shader()
module can be NULL, oops.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Chad Versace [Wed, 29 Nov 2017 18:56:26 +0000 (10:56 -0800)]
intel/isl: Declare private array as static const
It's array isl_drm.c:modifier_info[] .
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Dylan Baker [Fri, 1 Dec 2017 22:01:40 +0000 (14:01 -0800)]
meson: Install dri.pc file when building gallium dri drivers
Currently this pkg-config file is only installed if a classic dri driver
is built. This is wrong, it should be installed if any dri driver is
installed, which includes the gallium dri target.
Reported-by: Marc Dietrich <marvin24@gmx.de>
Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Lionel Landwerlin [Mon, 4 Dec 2017 15:22:12 +0000 (15:22 +0000)]
anv: query CS timestamp frequency from the kernel
The reference value in gen_device_info isn't going to be acurate on
Gen10+. We should query it from the kernel, which reads a couple of
register to compute the actual value.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Lionel Landwerlin [Mon, 6 Nov 2017 11:11:42 +0000 (11:11 +0000)]
i965: read CS timestamp frequency from the kernel on Gen10+
We cannot figure this value out of the PCI-id anymore. Let's read it
from the kernel (which computes this from a few registers).
When running on a (upcoming) 4.16-rc1+ kernel, this will fixes piglit
tests on CNL :
spec@arb_timer_query@query gl_timestamp
spec@arb_timer_query@timestamp-get
spec@ext_timer_query@time-elapsed
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Lionel Landwerlin [Mon, 4 Dec 2017 15:12:40 +0000 (15:12 +0000)]
drm-uapi: Update drm/i915 headers from drm-next
Taken from drm-next
ca797d29cd63e7b71b4eea29aff3b1cefd1ecb59
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Jason Ekstrand [Fri, 17 Nov 2017 01:15:27 +0000 (17:15 -0800)]
radv: Implement VK_KHR_get_surface_capabilities2
The WSI core code does all the hard work. Just add the wrappers and
turn it on.
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Jason Ekstrand [Thu, 16 Nov 2017 20:49:27 +0000 (12:49 -0800)]
vulkan/wsi: Initialize individual WSI interfaces in wsi_device_init
Now that we have anv_device_init/finish functions, there's no reason to
have the individual driver do any more work than that.
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Jason Ekstrand [Thu, 16 Nov 2017 20:38:26 +0000 (12:38 -0800)]
vulkan/wsi: Drop some unneeded cruft from the API
This drops the unneeded callbacks struct as well as the queue_get_family
callback we were using before we'd pulled QueuePresent inside.
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Jason Ekstrand [Thu, 16 Nov 2017 20:26:26 +0000 (12:26 -0800)]
vulkan/wsi: Add wrappers for all of the surface queries
This lets us move wsi_interface to wsi_common_private.h
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Jason Ekstrand [Thu, 16 Nov 2017 20:05:35 +0000 (12:05 -0800)]
vulkan/wsi: Drop the can_handle_different_gpu parameter from get_support
Both anv and radv can handle prime now.
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>