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Craig Topper [Mon, 13 Mar 2017 00:36:49 +0000 (00:36 +0000)]
[AVX-512] EVEX2VEX, don't reject intrinsic instructions when both have a memory operand. We should just continue to check other operands instead.
This exposed that we have several intrinsic instructions that have identical TSFlags to other instructions. We should merge their patterns and kill of the duplicate. I'll fix that in a follow up patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297596
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Craig Topper [Mon, 13 Mar 2017 00:36:46 +0000 (00:36 +0000)]
[X86] Minor formatting tweaks in EVEX to VEX tables. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297595
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Craig Topper [Sun, 12 Mar 2017 23:05:03 +0000 (23:05 +0000)]
[X86] Remove unused SDTypeProfile. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297594
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Craig Topper [Sun, 12 Mar 2017 23:05:00 +0000 (23:05 +0000)]
[X86] Lower SSE/AVX cmpps/pd intrinsics directly to X86ISD::CMPP SDNodes.
This allows us to remove a duplicate set of patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297593
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Craig Topper [Sun, 12 Mar 2017 22:29:12 +0000 (22:29 +0000)]
[AVX-512] Fix the valid immediates for the scatter/gather prefetch intrinsics.
The immediate should be 1 or 2, not 0 or 1. This was found while adding bounds checking to clang. In fact the existing clang builtin test failed if we ran it all the way to assembly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297591
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Sanjay Patel [Sun, 12 Mar 2017 18:28:48 +0000 (18:28 +0000)]
[x86] don't blindly transform SETB into SBB
I noticed unnecessary 'sbb' instructions in D30472 and while looking at 'ptest' codegen recently.
This happens because we were transforming any 'setb' - even when we only wanted a single-bit result.
This patch moves those transforms under visitAdd/visitSub, so we we're only creating sbb/adc when it
is a win. I don't know why we need a SETCC_CARRY node type, but I'm not proposing to change that
existing behavior in this patch.
Also, I'm skeptical that sbb/adc are a win for all micro-arches, so I added comments to the test files
where this transform still fires.
The test changes here are all cases where we no longer produce sbb/adc. Avoiding partial register
stalls (generating an xor to clear a register) is not handled in some cases, but that's a separate
issue.
Differential Revision: https://reviews.llvm.org/D30611
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297586
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Anna Thomas [Sun, 12 Mar 2017 14:06:41 +0000 (14:06 +0000)]
[LVI] Add Datalayout to the class LazyValueInfo since all its Impls require it. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297583
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Azharuddin Mohammed [Sun, 12 Mar 2017 14:02:32 +0000 (14:02 +0000)]
Remove CRC32 instructions from AArch64InstrInfo::hasShiftedReg
Summary:
A53 scheduler causes an assertion failure on all CRC instructions:
include/llvm/CodeGen/MachineInstr.h:280: const llvm::MachineOperand
&llvm::MachineInstr::getOperand(unsigned int) const: Assertion `i <
getNumOperands() && "getOperand() out of range!"' failed.
The case statements corresponding to CRC instructions are incorrect and should
be removed.
Also adding a testcase while on this.
Reviewers: t.p.northover, javed.absar, apazos, rengolin
Reviewed By: rengolin
Subscribers: evandro, aemerson, llvm-commits, rengolin
Differential Revision: https://reviews.llvm.org/D30274
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297582
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Igor Breger [Sun, 12 Mar 2017 13:20:10 +0000 (13:20 +0000)]
[X86] Add vector zext tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297581
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Gil Rapaport [Sun, 12 Mar 2017 12:31:38 +0000 (12:31 +0000)]
[LV] A unified scalarizeInstruction() for Vectorizer and Unroller; NFC
Unroller's specialized scalarizeInstruction() is mostly duplicating Vectorizer's
variant. OTOH Vectorizer's scalarizeInstruction() already supports the special
case of VF==1 except for avoiding mask-bit extraction in that case. This patch
removes Unroller's specialized version in favor of a unified method.
The only functional difference between the two variants seems to be setting
memcheck metadata for loads and stores only in Vectorizer's variant, which is a
bug in Unroller. To keep this patch an NFC the unified method doesn't set
memcheck metadata for VF==1.
Differential Revision: https://reviews.llvm.org/D30715
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297580
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Ayal Zaks [Sun, 12 Mar 2017 09:48:06 +0000 (09:48 +0000)]
Test commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297579
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Daniel Berlin [Sun, 12 Mar 2017 04:46:45 +0000 (04:46 +0000)]
Split NewGVN class into a legacy pass and an impl, instead of a merged class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297576
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Daniel Berlin [Sun, 12 Mar 2017 04:46:41 +0000 (04:46 +0000)]
Add documentation on debug counters to Programmers Manual.
Reviewers: mehdi_amini
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D30842
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297575
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Craig Topper [Sun, 12 Mar 2017 03:37:37 +0000 (03:37 +0000)]
[AVX-512] Fix a bad use of a high GR8 register after copying from a mask register during fast isel. This ends up extracting from bits 15:8 instead of the lower bits of the mask.
I'm pretty sure there are more problems lurking here. But I think this fixes PR32241.
I've added the test case from that bug and added asserts that will fail if we ever try to copy between high registers and mask registers again.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297574
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Craig Topper [Sun, 12 Mar 2017 03:37:34 +0000 (03:37 +0000)]
[AVX-512] Add test case for PR32241. Fix coming in another commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297573
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Craig Topper [Sun, 12 Mar 2017 03:37:32 +0000 (03:37 +0000)]
[AVX-512] Remove unused field in X86VectorVTInfo tablegen class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297572
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Simon Pilgrim [Sat, 11 Mar 2017 20:42:31 +0000 (20:42 +0000)]
[X86][SSE] Improve extraction of elements from v16i8 (pre-SSE41)
Without SSE41 (pextrb) we currently extract byte elements from a vector by spilling to stack and reloading the byte.
This patch is an initial attempt at using MOVD/PEXTRW to extract the relevant DWORD/WORD from the vector and then shift+truncate to collect the correct byte.
Extraction of multiple bytes this way would result in code bloat, but as explained in the patch we could probably afford to be more aggressive with the supported extractions before again falling back on spilling - possibly through counting the number of extracts and which DWORD/WORD they originate?
Differential Revision: https://reviews.llvm.org/D29841
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297568
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Simon Pilgrim [Sat, 11 Mar 2017 20:23:59 +0000 (20:23 +0000)]
Remove unnecessary whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297567
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Simon Pilgrim [Sat, 11 Mar 2017 19:38:22 +0000 (19:38 +0000)]
Fix signed/unsigned comparison warning
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297565
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Craig Topper [Sat, 11 Mar 2017 18:26:00 +0000 (18:26 +0000)]
[X86] Add avx2 gather tests cases that show a failure to remove zeroing of the source when the mask is all ones.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297564
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Craig Topper [Sat, 11 Mar 2017 18:25:56 +0000 (18:25 +0000)]
[X86] Remove unnecessary commented out code. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297563
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Simon Pilgrim [Sat, 11 Mar 2017 13:02:31 +0000 (13:02 +0000)]
Fix signed/unsigned comparison warnings
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297561
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Simon Pilgrim [Sat, 11 Mar 2017 12:56:02 +0000 (12:56 +0000)]
Fix -Wsentinel warning
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297560
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Amaury Sechet [Sat, 11 Mar 2017 11:24:03 +0000 (11:24 +0000)]
Use setBits in SelectionDAG
Summary: As per title.
Reviewers: RKSimon
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D30836
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297559
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Matt Arsenault [Sat, 11 Mar 2017 05:51:16 +0000 (05:51 +0000)]
AMDGPU: Remove packf16 intrinsic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297557
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Matt Arsenault [Sat, 11 Mar 2017 05:40:40 +0000 (05:40 +0000)]
AMDGPU: Keep track of modifiers when converting v_mac to v_mad
Since v_max_f32_e64/v_max_f16_e64 can be folded if the target
instruction supports the clamp bit, we also need to maintain
modifiers when converting v_mac to v_mad.
This fixes a rendering issue with Dirt Rally because a v_mac
instruction with the clamp bit set was converted to a v_mad
but that bit was lost during the conversion.
Fixes:
e184e01dd79 ("AMDGPU: Fold FP clamp as modifier bit")
Patch by Samuel Pitoiset <samuel.pitoiset@gmail.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297556
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Kostya Serebryany [Sat, 11 Mar 2017 05:14:49 +0000 (05:14 +0000)]
[libFuzzer] add more iterations to LLVMFuzzer-Memcmp64BytesTest
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297554
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Zachary Turner [Sat, 11 Mar 2017 02:52:48 +0000 (02:52 +0000)]
[ADT] Add a DenseMapInfo<T> for shorts.
Differential Revision: https://reviews.llvm.org/D30857
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297552
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Kostya Serebryany [Sat, 11 Mar 2017 02:50:47 +0000 (02:50 +0000)]
[libFuzzer] reduce the number of vector resizes during merge (https://github.com/google/oss-fuzz/issues/445)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297551
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Zachary Turner [Sat, 11 Mar 2017 02:50:18 +0000 (02:50 +0000)]
Fix line endings of DenseMapInfo.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297550
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Zachary Turner [Sat, 11 Mar 2017 02:47:59 +0000 (02:47 +0000)]
Remove eol-style:native from DenseMapInfo.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297549
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Zachary Turner [Sat, 11 Mar 2017 02:45:50 +0000 (02:45 +0000)]
[Support] Add a formatv provider for Twine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297548
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Kostya Serebryany [Sat, 11 Mar 2017 02:26:20 +0000 (02:26 +0000)]
[libFuzzer] print how much memory is consumed by the outer merge process (https://github.com/google/oss-fuzz/issues/445)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297546
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Eric Fiselier [Sat, 11 Mar 2017 02:24:13 +0000 (02:24 +0000)]
Revert r297516 - Respect CMAKE_INSTALL_MANDIR for sphinx generated manpages
When CMAKE_INSTALL_MANDIR isn't defined it ends up attempting to install
the man pages under "/man1" and we really don't want to accidentally install
stuff at the filesystem root.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297545
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Kostya Serebryany [Sat, 11 Mar 2017 01:54:06 +0000 (01:54 +0000)]
[libFuzzer] add test/LargeTest.cpp, mostly for manual experiments with large number of edges, not yet suitable for unit testing
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297544
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Kostya Serebryany [Sat, 11 Mar 2017 01:48:54 +0000 (01:48 +0000)]
[libFuzzer] remove fuzzer-jobs.test which is flaky and not very useful
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297543
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Daniel Berlin [Sat, 11 Mar 2017 01:41:03 +0000 (01:41 +0000)]
Remove opt-bisect support for "cases" in favor of debug counters
Summary:
Ths "cases" support was not quite finished, is unused, and is really just debug counters.
(well, almost, debug counters are slightly more powerful, in that they can skip things at the start, too).
Note, opt-bisect itself could also be implemented as a wrapper around
debug counters, but not sure it's worth it ATM.
I'll shove it on a todo list if we think it is.
Reviewers: MatzeB, chandlerc
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D30856
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297542
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Jordan Rose [Sat, 11 Mar 2017 01:24:56 +0000 (01:24 +0000)]
[unittest] Explicitly specify alignment when using BumpPtrAllocator.
r297310 began inserting red zones around allocations under ASan, which
perturbs the alignment of subsequent allocations. Deliberately specify
this in two places where it matters.
Fixes failures when these tests are run under ASan and UBSan together.
Reviewed by Duncan Exon Smith.
rdar://problem/
30980047
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297540
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Sanjoy Das [Sat, 11 Mar 2017 01:15:48 +0000 (01:15 +0000)]
Use a WeakVH for UnknownInstructions in AliasSetTracker
Summary:
This change solves the same problem as D30726, except that this only
throws out the bathwater.
AST was not correctly tracking and deleting UnknownInstructions via
handles. The existing code only tracks "pointers" in its
`ASTCallbackVH`, so an UnknownInstruction (that isn't also def'ing a
pointer used by another memory instruction) never gets a
`ASTCallbackVH`.
There are two other ways to solve this problem:
- Use the `PointerRec` scheme for both known and unknown instructions.
- Use a `CallbackVH` that erases the offending Instruction from the
UnknownInstruction list.
Both of the above changes seemed to be significantly (and unnecessarily
IMO) more complex than this.
Reviewers: chandlerc, dberlin, hfinkel, reames
Subscribers: mcrosier, llvm-commits
Differential Revision: https://reviews.llvm.org/D30849
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297539
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Daniel Berlin [Sat, 11 Mar 2017 00:51:01 +0000 (00:51 +0000)]
VNCoercion: Make the function signatures all consistent
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297537
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Stanislav Mekhanoshin [Sat, 11 Mar 2017 00:29:27 +0000 (00:29 +0000)]
[AMDGPU] Remove getBidirectionalReasonRank
This method inverts the Reason field of a scheduling candidate.
It does right comparison between RegCritical and RegExcess, but
everything else is broken. In fact it can prefer less strong reason
such as Weak over RegCritical because Weak > -RegCritical.
The CandReason enum is properly sorted, so just remove artificial
ranking.
Differential Revision: https://reviews.llvm.org/D30557
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297536
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Quentin Colombet [Sat, 11 Mar 2017 00:28:33 +0000 (00:28 +0000)]
[IRTranslator] Simplify error handling for translating constants. NFC.
We don't need to check whether the fallback path is enabled to return
false. Just do that all the time on error cases, the caller knows (or
at least should know!) how to handle the failing case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297535
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Stanislav Mekhanoshin [Sat, 11 Mar 2017 00:14:52 +0000 (00:14 +0000)]
Fix subreg value numbers in handleMoveUp
The problem can occur in presence of subregs. If we are swapping two
instructions defining different subregs of the same register we will
get a new liveout from a block. We need to preserve value number for
block's liveout for successor block's livein to match.
Differential Revision: https://reviews.llvm.org/D30558
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297534
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Simon Pilgrim [Fri, 10 Mar 2017 22:53:19 +0000 (22:53 +0000)]
Strip trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297529
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Simon Pilgrim [Fri, 10 Mar 2017 22:44:47 +0000 (22:44 +0000)]
Fix redundant condition (PR32138)
'!A || (A && B)' is equivalent to '!A || B'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297527
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Krzysztof Parzyszek [Fri, 10 Mar 2017 22:44:24 +0000 (22:44 +0000)]
[RDF] Remove the map of reaching defs from copy propagation
Use Liveness::getNearestAliasedRef to find the reaching def instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297526
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Krzysztof Parzyszek [Fri, 10 Mar 2017 22:42:17 +0000 (22:42 +0000)]
[RDF] Implement Liveness::getNearestAliasedRef(Reg, Inst)
This function will find the closest ref node aliased to Reg that is
in an instruction preceding Inst. This could be used to identify the
hypothetical reaching def of Reg, if Reg was a member of Inst.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297524
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Simon Pilgrim [Fri, 10 Mar 2017 22:35:07 +0000 (22:35 +0000)]
[X86][SSE] Fix load folding for (V)CVTDQ2PD
This only requires a 64-bit memory source, not the whole 128-bits. But the 128-bit case is still supported via X86InstrInfo::foldMemoryOperandImpl
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297523
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Simon Pilgrim [Fri, 10 Mar 2017 22:10:34 +0000 (22:10 +0000)]
[X86] Fix Wunused-lambda-capture warning
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297521
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Simon Pilgrim [Fri, 10 Mar 2017 21:55:24 +0000 (21:55 +0000)]
[X86][RTM] Regenerate RTM intrinsic tests for 32/64-bit targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297518
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Jonathan Roelofs [Fri, 10 Mar 2017 21:44:16 +0000 (21:44 +0000)]
Respect CMAKE_INSTALL_MANDIR for sphinx generated manpages
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297516
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Peter Collingbourne [Fri, 10 Mar 2017 21:37:10 +0000 (21:37 +0000)]
LTO: Hash type identifier resolutions for WholeProgramDevirt.
Differential Revision: https://reviews.llvm.org/D30555
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297514
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Peter Collingbourne [Fri, 10 Mar 2017 21:35:17 +0000 (21:35 +0000)]
LTO: Hash type identifier resolutions for LowerTypeTests.
Differential Revision: https://reviews.llvm.org/D30553
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297513
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Volkan Keles [Fri, 10 Mar 2017 21:25:09 +0000 (21:25 +0000)]
[GlobalISel] LegalizerHelper: Lower (G_FSUB X, Y) to (G_FADD X, (G_FNEG Y))
Summary: No test case as none of the in-tree targets with GlobalISel support has this condition.
Reviewers: qcolombet, aditya_nandakumar, dsanders, t.p.northover, ab
Reviewed By: qcolombet
Subscribers: dberris, rovka, kristof.beyls, llvm-commits, igorb
Differential Revision: https://reviews.llvm.org/D30786
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297512
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Volkan Keles [Fri, 10 Mar 2017 21:23:13 +0000 (21:23 +0000)]
GlobalISel: Translate ConstantAggregateZero vectors
Reviewers: qcolombet, aditya_nandakumar, dsanders, ab, t.p.northover, javed.absar
Reviewed By: qcolombet
Subscribers: dberris, rovka, llvm-commits, kristof.beyls
Differential Revision: https://reviews.llvm.org/D30259
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297509
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Eric Christopher [Fri, 10 Mar 2017 21:20:17 +0000 (21:20 +0000)]
Sink accessing TII to fix release Werror builds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297507
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Davide Italiano [Fri, 10 Mar 2017 20:50:51 +0000 (20:50 +0000)]
[ProfileSummaryInfo] Remove unneeded braces. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297506
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Daniel Berlin [Fri, 10 Mar 2017 20:44:39 +0000 (20:44 +0000)]
Fix all these headers to properly mark the doxygen comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297505
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Evandro Menezes [Fri, 10 Mar 2017 20:20:04 +0000 (20:20 +0000)]
[AArch64, X86] Additional debug information for MacroFusion
In order to make it easier to parse information about the performance of
MacroFusion, this patch adds the function and the instruction names to the
debug output of this pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297504
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Peter Collingbourne [Fri, 10 Mar 2017 20:13:58 +0000 (20:13 +0000)]
WholeProgramDevirt: Implement export/import support for VCP.
Differential Revision: https://reviews.llvm.org/D30017
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297503
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Peter Collingbourne [Fri, 10 Mar 2017 20:09:11 +0000 (20:09 +0000)]
WholeProgramDevirt: Implement export/import support for unique ret val opt.
Differential Revision: https://reviews.llvm.org/D29917
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297502
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Dehao Chen [Fri, 10 Mar 2017 19:45:16 +0000 (19:45 +0000)]
Refactor the PSI to extract getCallSiteCount and remove checks for profile type.
Summary: There is no need to check profile count as only CallInst will have metadata attached.
Reviewers: eraman
Reviewed By: eraman
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D30799
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297500
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Konstantin Zhuravlyov [Fri, 10 Mar 2017 19:39:07 +0000 (19:39 +0000)]
[AMDGPU] Split R600/SI getFrameIndexReference and emit stack object offsets for SI
Differential Revision: https://reviews.llvm.org/D29674
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297499
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Yaxun Liu [Fri, 10 Mar 2017 19:35:43 +0000 (19:35 +0000)]
Rename PT_NOTE namespace name used in AMDGPUPTNote.h
Patch by Guansong Zhang.
Differential Revision: https://reviews.llvm.org/D30750
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297498
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Volkan Keles [Fri, 10 Mar 2017 19:08:28 +0000 (19:08 +0000)]
[GlobalISel] Translate insertelement and extractelement
Reviewers: qcolombet, aditya_nandakumar, dsanders, ab, t.p.northover, javed.absar
Reviewed By: qcolombet
Subscribers: dberris, rovka, llvm-commits, kristof.beyls
Differential Revision: https://reviews.llvm.org/D30761
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297495
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Daniel Berlin [Fri, 10 Mar 2017 19:05:04 +0000 (19:05 +0000)]
NewGVN: Rename InitialClass to TOP, which is what most people would expect it to be called
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297494
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Michael Kuperstein [Fri, 10 Mar 2017 18:59:07 +0000 (18:59 +0000)]
[SLP] Revert everything that has to do with memory access sorting.
This reverts r293386, r294027, r294029 and r296411.
Turns out the SLP tree isn't actually a "tree" and we don't handle
accessing the same packet of loads in several different orders well,
causing miscompiles.
Revert until we can fix this properly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297493
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Simon Pilgrim [Fri, 10 Mar 2017 18:36:46 +0000 (18:36 +0000)]
[SelectionDAG] Add support for BUILD_VECTOR to ComputeNumSignBits
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297492
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Volkan Keles [Fri, 10 Mar 2017 18:34:57 +0000 (18:34 +0000)]
[GlobalISel] Make LegalizerInfo accessible in LegalizerHelper
Summary:
We don’t actually use LegalizerInfo in Legalizer pass, it’s just passed
as an argument.
In order to check if an instruction is legal or not, we need to get LegalizerInfo
by calling `MI.getParent()->getParent()->getSubtarget().getLegalizerInfo()`.
Instead, make LegalizerInfo accessible in LegalizerHelper.
Reviewers: qcolombet, aditya_nandakumar, dsanders, ab, t.p.northover, kristof.beyls
Reviewed By: qcolombet
Subscribers: dberris, llvm-commits, rovka
Differential Revision: https://reviews.llvm.org/D30838
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297491
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Matthias Braun [Fri, 10 Mar 2017 18:34:37 +0000 (18:34 +0000)]
CODE_OWNERS: Take code ownership of instruction scheduling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297490
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Matthias Braun [Fri, 10 Mar 2017 18:34:33 +0000 (18:34 +0000)]
CODE_OWNERS: Sort names
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297489
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Zachary Turner [Fri, 10 Mar 2017 18:33:41 +0000 (18:33 +0000)]
[Support] Don't return an error if realPath fails.
In openFileForRead, we would not previously return an error
if real_path resolution failed. After a recent patch, we
started propagating this error up. This caused a failure
in clang when trying to call openFileForRead("nul"). This
patch restores the previous behavior of not propagating this
error up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297488
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Simon Pilgrim [Fri, 10 Mar 2017 18:01:53 +0000 (18:01 +0000)]
[X86][SSE] Added tests showing missed truncations for sitofp conversion
SelectionDAG::ComputeNumSignBits is poor at build_vector handling, meaning that we can't see that all the vXi64 sources are in fact sign extended i32 or smaller.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297486
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Zachary Turner [Fri, 10 Mar 2017 17:47:13 +0000 (17:47 +0000)]
Fix test failure when Home directory cannot be found.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297484
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Zachary Turner [Fri, 10 Mar 2017 17:39:21 +0000 (17:39 +0000)]
Add llvm::sys::fs::real_path.
LLVM already has real_path like functionality, but it is
cumbersome to use and involves clean up after (e.g. you have
to call openFileForRead, then close the resulting FD).
Furthermore, on Windows it doesn't work for directories since
opening a directory and opening a file require slightly
different flags.
So I add a simple function `real_path` which works for all
paths on all platforms and has a simple to use interface.
In doing so, I add the ability to opt in to resolving tilde
expressions (e.g. ~/foo), which are normally handled by
the shell.
Differential Revision: https://reviews.llvm.org/D30668
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297483
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Amaury Sechet [Fri, 10 Mar 2017 17:26:44 +0000 (17:26 +0000)]
[SelectionDAG] Make SelectionDAG aware of the known bits in USUBO and SSUBO and SUBC.
Summary:
Depends on D30379
This improves the state of things for the sub class of operation.
Reviewers: jyknight, nemanjai, mkuper, spatel, RKSimon, zvi, bkramer
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D30436
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297482
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Simon Pilgrim [Fri, 10 Mar 2017 17:23:55 +0000 (17:23 +0000)]
[X86][MMX] Add tests showing missed opportunities to use MMX sitofp conversions
If we are transferring MMX registers to XMM for conversion we could use the MMX equivalents (CVTPI2PD + CVTPI2PS) without affecting rounding/exceptions etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297481
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Amaury Sechet [Fri, 10 Mar 2017 17:06:52 +0000 (17:06 +0000)]
[SelectionDAG] Make SelectionDAG aware of the known bits in UADDO and SADDO.
Summary: As per title. This is extracted from D29872 and I threw SADDO in.
Reviewers: jyknight, nemanjai, mkuper, spatel, RKSimon, zvi, bkramer
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D30379
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297479
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Simon Pilgrim [Fri, 10 Mar 2017 16:59:43 +0000 (16:59 +0000)]
[X86][MMX] Add tests showing missed opportunities to use MMX fptosi conversions
If we are transferring XMM conversion results to MMX registers we could use the MMX equivalents (CVTPD2PI/CVTTPD2PI + CVTPS2PI/CVTTPS2PI) with affecting rounding/expections etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297476
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Simon Pilgrim [Fri, 10 Mar 2017 16:18:50 +0000 (16:18 +0000)]
[X86][MMX] Updated bad stack spill shift value test to actually show the problem
Cleaning up the ir had stopped showing the issue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297475
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Simon Pilgrim [Fri, 10 Mar 2017 16:07:39 +0000 (16:07 +0000)]
[X86][MMX] Regenerate mmx bitcast tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297474
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Simon Pilgrim [Fri, 10 Mar 2017 15:53:41 +0000 (15:53 +0000)]
[X86][MMX] Add test showing bad stack spill of shift value
i32 is spilled to stack but 64-bit mmx is reloaded - leaving garbage in the other half of the register
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297471
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Simon Pilgrim [Fri, 10 Mar 2017 15:41:05 +0000 (15:41 +0000)]
[X86][MMX] Regenerate mmx load folding tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297470
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Simon Pilgrim [Fri, 10 Mar 2017 14:16:55 +0000 (14:16 +0000)]
Fix signed/unsigned comparison warnings
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297460
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Simon Pilgrim [Fri, 10 Mar 2017 14:01:50 +0000 (14:01 +0000)]
Fix Wdocumentation warning
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297459
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Simon Pilgrim [Fri, 10 Mar 2017 13:44:32 +0000 (13:44 +0000)]
[APInt] Add APInt::insertBits() method to insert an APInt into a larger APInt
We currently have to insert bits via a temporary variable of the same size as the target with various shift/mask stages, resulting in further temporary variables, all of which require the allocation of memory for large APInts (MaskSizeInBits > 64).
This is another of the compile time issues identified in PR32037 (see also D30265).
This patch adds the APInt::insertBits() helper method which avoids the temporary memory allocation and masks/inserts the raw bits directly into the target.
Differential Revision: https://reviews.llvm.org/D30780
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297458
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Simon Dardis [Fri, 10 Mar 2017 13:27:14 +0000 (13:27 +0000)]
[mips][msa] Accept more values for constant splats
This patches teaches the MIPS backend to accept more values for constant
splats. Previously, only 10 bit signed immediates or values that could be
loaded using an ldi.[bhwd] instruction would be acceptted. This patch relaxes
that constraint so that any constant value that be splatted is accepted.
As a result, the constant pool is used less for vector operations, and the
suite of bit manipulation instructions b(clr|set|neg)i can now be used with
the full range of their immediate operand.
Reviewers: slthakur
Differential Revision: https://reviews.llvm.org/D30640
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297457
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Artyom Skrobov [Fri, 10 Mar 2017 13:21:12 +0000 (13:21 +0000)]
imm_comp_XFORM (defined in ARMInstrThumb.td) duplicates imm_not_XFORM (defined in ARMInstrInfo.td)
Reviewers: grosbach, rengolin, jmolloy
Reviewed By: jmolloy
Subscribers: aemerson, llvm-commits
Differential Revision: https://reviews.llvm.org/D30782
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297456
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Sanne Wouda [Fri, 10 Mar 2017 13:08:20 +0000 (13:08 +0000)]
[Assembler] Add location info to unary expressions.
Summary:
This is a continuation of D28861. Add an SMLoc to MCUnaryExpr such that
a better diagnostic can be given in case of an error in later stages of
assembling.
Reviewers: rengolin, grosbach, javed.absar, olista01
Reviewed By: olista01
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D30581
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297454
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Artyom Skrobov [Fri, 10 Mar 2017 12:41:33 +0000 (12:41 +0000)]
Refactor the multiply-accumulate combines to act on
ARMISD::ADD[CE] nodes, instead of the generic ISD::ADD[CE].
Summary:
This allows for some simplification because the combines
are no longer limited to just one go at the node before
it gets legalized into an ARM target-specific one.
Reviewers: jmolloy, rogfer01
Subscribers: aemerson, llvm-commits, rengolin
Differential Revision: https://reviews.llvm.org/D30401
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297453
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George Rimar [Fri, 10 Mar 2017 10:31:56 +0000 (10:31 +0000)]
WholeProgramDevirt: Fixed compilation error under MSVS2015.
It was introduced in:
r296945
WholeProgramDevirt: Implement exporting for single-impl devirtualization.
---------------------
r296939
WholeProgramDevirt: Add any unsuccessful llvm.type.checked.load devirtualizations to the list of llvm.type.test users.
---------------------
Microsoft Visual Studio Community 2015
Version 14.0.23107.0 D14REL
Does not compile that code without additional brackets, showing multiple error like below:
WholeProgramDevirt.cpp(1216): error C2958: the left bracket '[' found at 'c:\access_softek\llvm\lib\transforms\ipo\wholeprogramdevirt.cpp(1216)' was not matched correctly
WholeProgramDevirt.cpp(1216): error C2143: syntax error: missing ']' before '}'
WholeProgramDevirt.cpp(1216): error C2143: syntax error: missing ';' before '}'
WholeProgramDevirt.cpp(1216): error C2059: syntax error: ']'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297451
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Simon Atanasyan [Fri, 10 Mar 2017 08:22:25 +0000 (08:22 +0000)]
[llvm-readobj] Support SHT_MIPS_DWARF section type flag
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297448
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Simon Atanasyan [Fri, 10 Mar 2017 08:22:20 +0000 (08:22 +0000)]
[MC] Set SHT_MIPS_DWARF section type for all .debug_* sections on MIPS
All MIPS .debug_* sections should be marked with ELF type SHT_MIPS_DWARF
accordingly the specification [1]. Also the same section type is assigned
to these sections by GNU tools.
[1] ftp.software.ibm.com/software/os390/czos/dwarf/mips_extensions.pdf
Differential Revision: https://reviews.llvm.org/D29789
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297447
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Simon Atanasyan [Fri, 10 Mar 2017 08:22:13 +0000 (08:22 +0000)]
[MC] Accept a numeric value as an ELF section header's type
GAS supports specification of section header's type using a numeric
value [1]. This patch brings the same functionality to LLVM. That allows
to setup some target-specific section types belong to the SHT_LOPROC -
SHT_HIPROC range. If we attempt to print unknown section type, MCSectionELF
class shows an error message. It's better than print sole '@' sign
without any section type name.
In case of MIPS, example of such section's type is SHT_MIPS_DWARF.
Without the patch we will have to implement some workarounds
in probably not-MIPS-specific part of code base to convert SHT_MIPS_DWARF
to the @progbits while printing assembly and to assign SHT_MIPS_DWARF for
@progbits sections named .debug_* if we encounter such section in
an input assembly.
[1] https://sourceware.org/binutils/docs/as/Section.html
Differential Revision: https://reviews.llvm.org/D29719
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297446
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Artyom Skrobov [Fri, 10 Mar 2017 07:40:27 +0000 (07:40 +0000)]
For Thumb1, lower ADDC/ADDE/SUBC/SUBE via the glueless ARMISD nodes,
same as already done for ARM and Thumb2.
Reviewers: jmolloy, rogfer01, efriedma
Subscribers: aemerson, llvm-commits, rengolin
Differential Revision: https://reviews.llvm.org/D30400
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297443
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Yaron Keren [Fri, 10 Mar 2017 07:09:20 +0000 (07:09 +0000)]
Implement getPassName() for IR printing passes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297442
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Matt Arsenault [Fri, 10 Mar 2017 05:25:49 +0000 (05:25 +0000)]
AMDGPU: Fix insertion point when reducing load intrinsics
The insertion point may be later than the next instruction,
so it is necessary to set it when replacing the call.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297439
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Daniel Berlin [Fri, 10 Mar 2017 04:54:10 +0000 (04:54 +0000)]
Move memory coercion functions from GVN.cpp to VNCoercion.cpp so they can be shared between GVN and NewGVN.
Summary:
These are the functions used to determine when values of loads can be
extracted from stores, etc, and to perform the necessary insertions to
do this. There are no changes to the functions themselves except
reformatting, and one case where memdep was informed of a removed load
(which was pushed into the caller).
Reviewers: davide
Subscribers: mgorny, llvm-commits, Prazek
Differential Revision: https://reviews.llvm.org/D30478
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297438
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Dehao Chen [Fri, 10 Mar 2017 01:44:37 +0000 (01:44 +0000)]
Do not use branch metadata to check if a basic block is hot.
Summary: We should not use that to check basic block hotness as optimization may mess it up.
Reviewers: eraman
Reviewed By: eraman
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D30800
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297437
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Sanjay Patel [Fri, 10 Mar 2017 00:55:29 +0000 (00:55 +0000)]
[x86] add tests for vec div/rem with 0 element in divisor; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297433
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