OSDN Git Service
Tao Zhou [Wed, 7 Aug 2019 02:28:54 +0000 (10:28 +0800)]
drm/amdgpu: replace readq/writeq with atomic64 operations
what we really want is a read or write that is guaranteed to be 64 bits
at a time, atomic64 operations are supported on all architectures
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hariprasad Kelam [Mon, 5 Aug 2019 17:21:38 +0000 (22:51 +0530)]
gpu: drm: amd: powerplay: Remove logically dead code
Result of pointer airthmentic is never null
fix coverity defect:
1451876
Signed-off-by: Hariprasad Kelam <hariprasad.kelam@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nathan Chancellor [Sun, 4 Aug 2019 20:37:13 +0000 (13:37 -0700)]
drm/amd/powerplay: Zero initialize some variables
Clang warns (only Navi warning shown but Arcturus warns as well):
drivers/gpu/drm/amd/amdgpu/../powerplay/navi10_ppt.c:1534:4: warning:
variable 'asic_default_power_limit' is used uninitialized whenever '?:'
condition is false [-Wsometimes-uninitialized]
smu_read_smc_arg(smu, &asic_default_power_limit);
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../powerplay/inc/amdgpu_smu.h:588:3: note:
expanded from macro 'smu_read_smc_arg'
((smu)->funcs->read_smc_arg? (smu)->funcs->read_smc_arg((smu), (arg)) : 0)
^~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../powerplay/navi10_ppt.c:1550:30: note:
uninitialized use occurs here
smu->default_power_limit = asic_default_power_limit;
^~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../powerplay/navi10_ppt.c:1534:4: note:
remove the '?:' if its condition is always true
smu_read_smc_arg(smu, &asic_default_power_limit);
^
drivers/gpu/drm/amd/amdgpu/../powerplay/inc/amdgpu_smu.h:588:3: note:
expanded from macro 'smu_read_smc_arg'
((smu)->funcs->read_smc_arg? (smu)->funcs->read_smc_arg((smu), (arg)) : 0)
^
drivers/gpu/drm/amd/amdgpu/../powerplay/navi10_ppt.c:1517:35: note:
initialize the variable 'asic_default_power_limit' to silence this
warning
uint32_t asic_default_power_limit;
^
= 0
1 warning generated.
As the code is currently written, if read_smc_arg were ever NULL, arg
would fail to be initialized but the code would continue executing as
normal because the return value would just be zero.
There are a few different possible solutions to resolve this class
of warnings which have appeared in these drivers before:
1. Assume the function pointer will never be NULL and eliminate the
wrapper macros.
2. Have the wrapper macros initialize arg when the function pointer is
NULL.
3. Have the wrapper macros return an error code instead of 0 when the
function pointer is NULL so that the callsites can properly bail out
before arg can be used.
4. Initialize arg at the top of its function.
Number four is the path of least resistance right now as every other
change will be driver wide so do that here. I only make the comment
now as food for thought.
Fixes:
b4af964e75c4 ("drm/amd/powerplay: make power limit retrieval as asic specific")
Link: https://github.com/ClangBuiltLinux/linux/issues/627
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Nathan Chancellor <natechancellor@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Oded Gabbay [Thu, 4 Jul 2019 06:32:20 +0000 (09:32 +0300)]
MAINTAINERS: update amdkfd maintainer (v3)
I'm leaving the role of amdkfd maintainer. Therefore, update the relevant
entry in the MAINTAINERS file with the name of the new maintainer.
Good Luck!
v3: update mailing list, file list (Alex)
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> (v2)
Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Andrey Grodzovsky [Fri, 2 Aug 2019 20:48:08 +0000 (16:48 -0400)]
drm/amdgpu: Fix GPU reset crash regression.
amdgpu_ip_block.status.hw for GMC wasn't set to
false on suspend during GPU reset and so on resume gmc_v9_0_resume
wasn't called.
Caused by 'drm/amdgpu: fix double ucode load by PSP(v3)'
Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Tue, 6 Aug 2019 08:14:22 +0000 (16:14 +0800)]
drm/amd/powerplay: check before issuing messages for max sustainable clocks
Those messages are not supported on Arcturus and should not be
issued.
Affected ASIC: Arcturus
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Mon, 5 Aug 2019 08:19:45 +0000 (16:19 +0800)]
drm/amdgpu/discovery: move common discovery code out of navi1*_reg_base_init()
move amdgpu_discovery_reg_base_init() from navi1*_reg_base_init() to a
common function nv_reg_base_init().
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
tiancyin [Mon, 5 Aug 2019 09:32:45 +0000 (17:32 +0800)]
drm/amdgpu/soc15: fix external_rev_id for navi14
fix the hard code external_rev_id.
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: tiancyin <tianci.yin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Mon, 5 Aug 2019 07:48:30 +0000 (15:48 +0800)]
drm/amdgpu: update ras sysfs feature info
remove confused ras error type info
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Mon, 5 Aug 2019 06:53:12 +0000 (14:53 +0800)]
drm/amd/powerplay: skip pcie params override on Arcturus V2
This is not supported on Arcturus.
Affected ASIC: Arcturus
V2: minor cosmetic fix
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
xinhui pan [Mon, 5 Aug 2019 06:53:49 +0000 (14:53 +0800)]
drm/amdgpu: Fix panic during gpu reset
Clear the flag after hw suspend, otherwise it skips the corresponding hw
resume.
Signed-off-by: xinhui pan <xinhui.pan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Fri, 2 Aug 2019 07:18:57 +0000 (15:18 +0800)]
drm/amdgpu: pin the csb buffer on hw init for gfx v8
Without this pin, the csb buffer will be filled with inconsistent
data after S3 resume. And that will causes gfx hang on gfxoff
exit since this csb will be executed then.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Tested-by: Paul Gover <pmw.gover@yahoo.co.uk>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nicholas Kazlauskas [Fri, 2 Aug 2019 14:45:11 +0000 (10:45 -0400)]
drm/amd/display: Block immediate flips for non-fast updates
[Why]
Underflow can occur in the case where we change buffer pitch, DCC state,
rotation or mirroring for a plane while also performing an immediate
flip. It can also generate a p-state warning stack trace on DCN1 which
is typically observed during the cursor handler pipe locking because of
how frequent cursor updates can occur.
[How]
Store the update type on each CRTC - every plane will have access to
the CRTC state if it's flipping. If the update type is not
UPDATE_TYPE_FAST then the immediate flip should be disallowed.
No changes to the target vblank sequencing need to be done, we just
need to ensure that the surface registers do a double buffered update.
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: David Francis <david.francis@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nicholas Kazlauskas [Fri, 2 Aug 2019 14:31:29 +0000 (10:31 -0400)]
drm/amd/display: Validate dc_plane_info and dc_plane_size in atomic check
[Why]
Pitch, DCC, rotation and mirroring can result in updates that are not
UPDATE_TYPE_FAST but UPDATE_TYPE_MED instead. DC needs dc_plane_info
and dc_plane_size to make this determination and we aren't currently
passing this into DC during atomic check.
Underflow (visible or non-visible) can occur if we don't validate this
correctly. This also will generally trigger p-state warnings, typically
via the cursor handler when locking.
[How]
Get the framebuffer tiling flags and generate the required structures
for DC in dm_determine_update_type_for_commit.
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: David Francis <david.francis@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
shaoyunl [Fri, 26 Jul 2019 19:19:02 +0000 (14:19 -0500)]
drm/amdgpu: enable Navi12 kfd support for amdgpu
Navi12 has the same interface as Navi10
Signed-off-by: shaoyunl <shaoyun.liu@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Roman Li [Tue, 16 Jul 2019 21:26:14 +0000 (17:26 -0400)]
drm/amd/display: Add missing NV12 asic IDs
Add missing navi12 asic ids.
Signed-off-by: Roman Li <Roman.Li@amd.com>
Reviewed-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leo Li [Tue, 16 Jul 2019 22:12:13 +0000 (18:12 -0400)]
drm/amdgpu: Add nv12 DC ip block
Load DC and amdgpu display manager
Signed-off-by: Leo Li <sunpeng.li@amd.com>
Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leo Li [Tue, 16 Jul 2019 15:50:06 +0000 (11:50 -0400)]
drm/amd/display: Add ASICREV_IS_NAVI macros
They are used by DC to determine ASIC revs.
Signed-off-by: Leo Li <sunpeng.li@amd.com>
Reviewed-by: Roman Li <Roman.Li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Boyuan Zhang [Thu, 18 Jul 2019 21:39:07 +0000 (17:39 -0400)]
drm/amdgpu: enable DPG mode for Navi12
Enable Dynamic Power Gating VCN for Navi12.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Boyuan Zhang [Thu, 18 Jul 2019 14:13:23 +0000 (10:13 -0400)]
drm/amdgpu: add VCN ip block for Navi12
Add VCN2 ip block for Navi12
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Boyuan Zhang [Thu, 18 Jul 2019 13:17:24 +0000 (09:17 -0400)]
drm/amdgpu: add Navi12 VCN firmware support
Add Navi12 to VCN family
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Wed, 17 Jul 2019 18:54:29 +0000 (02:54 +0800)]
drm/amdgpu: add psp ip block for navi12
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Mon, 15 Jul 2019 19:26:49 +0000 (03:26 +0800)]
drm/amdgpu: add smu ip block for navi12
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Wed, 17 Jul 2019 21:00:00 +0000 (05:00 +0800)]
drm/amdgpu: start autoload till RLCG fw for navi12
rlc save restore list is not ready yet for navi12
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Fri, 2 Aug 2019 13:59:36 +0000 (08:59 -0500)]
drm/amdgpu/psp11: add psp support for navi12
Same as other navi asics.
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Thu, 1 Aug 2019 19:54:59 +0000 (14:54 -0500)]
drm/amdgpu/smu11: add smu support for navi12
Same as other Navi asics.
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Sun, 14 Jul 2019 21:12:21 +0000 (05:12 +0800)]
drm/amdgpu: correct smu rlc handshake enablement bit
Correct the enablement bit of SMU RLC handshake.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Wed, 10 Jul 2019 10:50:20 +0000 (18:50 +0800)]
drm/amdgpu: add CGTT_GS_NGG_CLK_CTRL register to gc header
gc 10.1.2 introduced this new register
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Tue, 9 Jul 2019 06:17:08 +0000 (14:17 +0800)]
drm/amdgpu/sdma5: add golden settings for navi12 (v2)
common golden settings are put in golden_settings_sdma_5 array
v2: update settings (Alex)
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Tue, 9 Jul 2019 06:16:22 +0000 (14:16 +0800)]
drm/amdgpu/gfx10: add golden settings for navi12 (v2)
Add initial golden settings for navi12 gfx.
v2: update settings
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Wed, 26 Jun 2019 11:19:57 +0000 (19:19 +0800)]
drm/amdgpu: enable virtual display for navi12
Virtual display is a sw display interface for
bring up and virtualization or for cards without
display hardware.
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Tue, 29 Jan 2019 14:36:15 +0000 (22:36 +0800)]
drm/amdgpu/gfx10: set tcp harvest for navi12
Same as navi10.
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Thu, 16 May 2019 11:58:19 +0000 (19:58 +0800)]
drm/amdgpu: add ip blocks for navi12
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Thu, 16 May 2019 10:05:37 +0000 (18:05 +0800)]
drm/amdgpu/gmc10: set gart size and vm size for navi12
Same as other navi asics.
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Mon, 17 Dec 2018 10:07:22 +0000 (18:07 +0800)]
drm/amdgpu/sdma5: add placeholder for navi12 golden settings
None yet.
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Mon, 17 Dec 2018 10:05:32 +0000 (18:05 +0800)]
drm/amdgpu/sdma5: declare sdma firmwares for navi12
Declare the firmwares and load the proper ones for navi12.
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Thu, 16 May 2019 12:02:14 +0000 (20:02 +0800)]
drm/amdgpu/gfx10: set rlc funcs for navi12
Same as other navi asics.
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Thu, 16 May 2019 12:01:03 +0000 (20:01 +0800)]
drm/amdgpu/gfx10: set number of me(c)/pipe/queue for navi12
Same as other navi asics.
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Tue, 11 Jun 2019 03:16:54 +0000 (11:16 +0800)]
drm/amdgpu/gfx10: add placeholder for navi12 golden settings
Not used yet.
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Tue, 11 Jun 2019 03:16:38 +0000 (11:16 +0800)]
drm/amdgpu/gfx10: declare cp/rlc firmwares for navi12
Set the name properly to load the right ucode.
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Thu, 16 May 2019 11:01:19 +0000 (19:01 +0800)]
drm/amdgpu/gfx10: add gfx config for navi12
got from mmCP_MAX_CONTEXT and mmPA_SC_FIFO_SIZE
v2: squash all navi asics together because the
settings are the same.
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Thu, 16 May 2019 11:03:01 +0000 (19:03 +0800)]
drm/amdgpu/gfx10: set gfx cg for navi12
Same as other navi asics.
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Thu, 16 May 2019 11:51:12 +0000 (19:51 +0800)]
drm/amdgpu: set nbio/hdp cg for navi12
Same as navi10.
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Thu, 16 May 2019 11:47:33 +0000 (19:47 +0800)]
drm/amdgpu: initialize cg/pg flags and external rev id for navi12
don't enable any cg/pg features yet.
v2: calculate external revision id from revision id so that we can
differentiate navi12 A0 from A1 directly.
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Mon, 17 Dec 2018 10:04:19 +0000 (18:04 +0800)]
drm/amdgpu: use front door firmware loading for navi12
Same as other navi asics.
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Thu, 16 May 2019 09:36:41 +0000 (17:36 +0800)]
drm/amdgpu: set asic family and ip blocks for navi12
same with navi10
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Mon, 17 Dec 2018 10:01:38 +0000 (18:01 +0800)]
drm/amdgpu: add gpu_info firmware for navi12
gpu_info firmare store asic configuration details.
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Mon, 17 Dec 2018 10:00:26 +0000 (18:00 +0800)]
drm/amdgpu: add navi12 asic type
Add asic type.
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Tue, 14 May 2019 07:22:53 +0000 (15:22 +0800)]
drm/amdgpu: initialize reg base for navi12
Set up the register offset map for navi12.
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Tue, 14 May 2019 07:18:19 +0000 (15:18 +0800)]
drm/amdgpu: add ip offset header for navi12 (v2)
This adds the absolute offsets of each IP regiser block.
v2: Squash in MP1 update
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
John Clements [Thu, 1 Aug 2019 07:16:12 +0000 (15:16 +0800)]
drm/amdgpu: update SDMA V4 microcode init
Removed loading duplicate instances of SDMA FW for Arcturus.
We use a single image for all instances.
Signed-off-by: John Clements <john.clements@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
John Clements [Thu, 1 Aug 2019 09:59:55 +0000 (17:59 +0800)]
drm/amdgpu: extend PSP FW loading support to 8 SDMA instances
Arcturus has 8 instances of SDMA. Update host to PSP interface
to handle it.
Signed-off-by: John Clements <john.clements@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
John Clements [Wed, 31 Jul 2019 08:11:08 +0000 (16:11 +0800)]
drm/amdgpu: disable MEC2 JT context init for Arcturus
We don't need to handle it like other asics.
Signed-off-by: John Clements <john.clements@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
John Clements [Thu, 25 Jul 2019 07:29:11 +0000 (15:29 +0800)]
drm/amdgpu: update PSP CMD fail response status print
Print the response in hex with the apprpriate mask.
Signed-off-by: John Clements <john.clements@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
John Clements [Mon, 22 Jul 2019 10:06:58 +0000 (18:06 +0800)]
drm/amdgpu: add PSP KDB loading support for Arcturus
Add support for the arcturus specific psp metadata to the
amdgpu firmware and properly parse it when loading it.
Signed-off-by: John Clements <john.clements@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
John Clements [Thu, 1 Aug 2019 10:05:50 +0000 (18:05 +0800)]
drm/amdgpu: add PSP SW init support for Arcturus
Add arcturus cases to psp init sewquence.
Signed-off-by: John Clements <john.clements@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
John Clements [Wed, 31 Jul 2019 08:11:38 +0000 (16:11 +0800)]
drm/amdgpu: removed duplicate line
Remove duplicate break.
Signed-off-by: John Clements <john.clements@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Fri, 2 Aug 2019 08:38:32 +0000 (16:38 +0800)]
drm/amd/powerplay: correct navi10 vcn powergate
vcn dpm on is a prerequisite for vcn power gate control.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Wed, 31 Jul 2019 02:34:36 +0000 (10:34 +0800)]
drm/amd/powerplay: enable SW SMU power profile switch support in KFD
Hook up the SW SMU power profile switch in KFD routine.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Mon, 29 Jul 2019 07:17:27 +0000 (15:17 +0800)]
drm/amd/powerplay: support power profile retrieval and setting on arcturus
Enable arcturus power profile retrieval and setting.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Tue, 30 Jul 2019 08:39:45 +0000 (16:39 +0800)]
drm/amd/powerplay: guard consistency between CPU copy and local VRAM
This can prevent CPU to use the out-dated copy.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Thu, 1 Aug 2019 09:30:35 +0000 (17:30 +0800)]
drm/amdgpu: replace AMDGPU_RAS_UE with AMDGPU_RAS_SUCCESS
ce can also trigger interrupt, and even both ce and ue error can be
found in one ras query, distinguishing between ce and ue in interrupt
handler is uncessary.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Suggested-by: Guchun Chen <guchun.chen@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Thu, 1 Aug 2019 04:52:54 +0000 (12:52 +0800)]
drm/amdgpu: only uncorrectable error needs gpu reset
we only read error information for correctable error in interrupt
handler, gpu reset is unnecessary since there is no data lost
in correctable error
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Mon, 29 Jul 2019 09:19:57 +0000 (17:19 +0800)]
drm/amdgpu: update the calc algorithm of umc ecc error count
the initial value of ecc error count can be adjusted
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Mon, 29 Jul 2019 09:01:39 +0000 (17:01 +0800)]
drm/amdgpu: implement umc ras init function
enable umc ce interrupt and initialize ecc error count
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Mon, 29 Jul 2019 08:04:33 +0000 (16:04 +0800)]
drm/amdgpu: support ce interrupt in ras module
correctable error can also trigger interrupt in some ras blocks
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Thu, 1 Aug 2019 03:41:39 +0000 (11:41 +0800)]
drm/amdgpu: add error address query for umc ras
umc error address query can get ce/ue error address and clear error
status
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Thu, 1 Aug 2019 03:37:25 +0000 (11:37 +0800)]
drm/amdgpu: apply umc_for_each_channel macro to umc_6_1
use umc_for_each_channel to make code simpler
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Mon, 29 Jul 2019 06:50:35 +0000 (14:50 +0800)]
drm/amdgpu: add macro of umc for each channel
common function for all umc versions, loop for each umc channel is
a frequent used operation in umc block, define it as a macro to
simplify code
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Mon, 29 Jul 2019 06:28:35 +0000 (14:28 +0800)]
drm/amdgpu: initialize new parameters and functions for amdgpu_umc structure
add initialization for new members of amdgpu_umc structure
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Mon, 29 Jul 2019 06:10:54 +0000 (14:10 +0800)]
drm/amdgpu: add more parameters and functions to amdgpu_umc structure
expose more parameters and functions of specific umc version to common
umc layer, so amdgpu_umc layer and other blocks could access them
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Mon, 29 Jul 2019 02:28:57 +0000 (10:28 +0800)]
drm/amdgpu: remove the clear of MCA_ADDR
clearing MCA_STATUS is enough to reset the whole MCA, writing zero to
MCA_ADDR is unnecessary
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kevin Wang [Fri, 2 Aug 2019 04:01:00 +0000 (12:01 +0800)]
drm/amd/powerplay: honor hw limit on fetching metrics data for navi10
too frequently to update mertrics table will cause smu internal error.
Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nicholas Kazlauskas [Wed, 31 Jul 2019 14:33:54 +0000 (10:33 -0400)]
drm/amd/display: Don't replace the dc_state for fast updates
[Why]
DRM private objects have no hw_done/flip_done fencing mechanism on their
own and cannot be used to sequence commits accordingly.
When issuing commits that don't touch the same set of hardware resources
like page-flips on different CRTCs we can run into the issue below
because of this:
1. Client requests non-blocking Commit #1, has a new dc_state #1,
state is swapped, commit tail is deferred to work queue
2. Client requests non-blocking Commit #2, has a new dc_state #2,
state is swapped, commit tail is deferred to work queue
3. Commit #2 work starts, commit tail finishes,
atomic state is cleared, dc_state #1 is freed
4. Commit #1 work starts,
commit tail encounters null pointer deref on dc_state #1
In order to change the DC state as in the private object we need to
ensure that we wait for all outstanding commits to finish and that
any other pending commits must wait for the current one to finish as
well.
We do this for MEDIUM and FULL updates. But not for FAST updates, nor
would we want to since it would cause stuttering from the delays.
FAST updates that go through dm_determine_update_type_for_commit always
create a new dc_state and lock the DRM private object if there are
any changed planes.
We need the old state to validate, but we don't actually need the new
state here.
[How]
If the commit isn't a full update then the use after free can be
resolved by simply discarding the new state entirely and retaining
the existing one instead.
With this change the sequence above can be reexamined. Commit #2 will
still free Commit #1's reference, but before this happens we actually
added an additional reference as part of Commit #2.
If an update comes in during this that needs to change the dc_state
it will need to wait on Commit #1 and Commit #2 to finish. Then it'll
swap the state, finish the work in commit tail and drop the last
reference on Commit #2's dc_state.
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=204181
Fixes:
004b3938e637 ("drm/amd/display: Check scaling info when determing update type")
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: David Francis <david.francis@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nicholas Kazlauskas [Wed, 31 Jul 2019 13:45:16 +0000 (09:45 -0400)]
drm/amd/display: Skip determining update type for async updates
[Why]
By passing through the dm_determine_update_type_for_commit for atomic
commits that can be done asynchronously we are incurring a
performance penalty by locking access to the global private object
and holding that access until the end of the programming sequence.
This is also allocating a new large dc_state on every access in addition
to retaining all the references on each stream and plane until the end
of the programming sequence.
[How]
Shift the determination for async update before validation. Return early
if it's going to be an async update.
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: David Francis <david.francis@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nicholas Kazlauskas [Mon, 10 Jun 2019 12:47:57 +0000 (08:47 -0400)]
drm/amd/display: Allow cursor async updates for framebuffer swaps
[Why]
We previously allowed framebuffer swaps as async updates for cursor
planes but had to disable them due to a bug in DRM with async update
handling and incorrect ref counting. The check to block framebuffer
swaps has been added to DRM for a while now, so this check is redundant.
The real fix that allows this to properly in DRM has also finally been
merged and is getting backported into stable branches, so dropping
this now seems to be the right time to do so.
[How]
Drop the redundant check for old_fb != new_fb.
With the proper fix in DRM, this should also fix some cursor stuttering
issues with xf86-video-amdgpu since it double buffers the cursor.
IGT tests that swap framebuffers (-varying-size for example) should
also pass again.
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: David Francis <david.francis@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Colin Ian King [Thu, 1 Aug 2019 11:01:45 +0000 (12:01 +0100)]
drm/amdgpu: fix unsigned variable instance compared to less than zero
Currenly the error check on variable instance is always false because
it is a uint32_t type and this is never less than zero. Fix this by
making it an int type.
Addresses-Coverity: ("Unsigned compared against 0")
Fixes:
7d0e6329dfdc ("drm/amdgpu: update more sdma instances irq support")
Signed-off-by: Colin Ian King <colin.king@canonical.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Matt Coffin [Wed, 31 Jul 2019 20:14:35 +0000 (14:14 -0600)]
drm/amd/powerplay: Allow changing of fan_control in smu_v11_0
[Why]
Before this change, the fan control state on smu_v11 was not able to be
changed because the capability check for checking if the fan control
capability existed was inverted.
[How]
The capability check for fan control in smu_v11_0_auto_fan_control was
inverted, to correctly check for the absence, instead of presence of fan
control capabilities.
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Matt Coffin <mcoffin13@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Colin Ian King [Thu, 1 Aug 2019 08:39:41 +0000 (09:39 +0100)]
drm/amd/powerplay: fix a few spelling mistakes
There are a few spelling mistakes "unknow" -> "unknown" and
"enabeld" -> "enabled". Fix these.
Signed-off-by: Colin Ian King <colin.king@canonical.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jia-Ju Bai [Mon, 29 Jul 2019 08:36:44 +0000 (16:36 +0800)]
gpu: drm: radeon: Fix a possible null-pointer dereference in radeon_connector_set_property()
In radeon_connector_set_property(), there is an if statement on line 743
to check whether connector->encoder is NULL:
if (connector->encoder)
When connector->encoder is NULL, it is used on line 755:
if (connector->encoder->crtc)
Thus, a possible null-pointer dereference may occur.
To fix this bug, connector->encoder is checked before being used.
This bug is found by a static analysis tool STCheck written by us.
Signed-off-by: Jia-Ju Bai <baijiaju1990@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Colin Ian King [Thu, 1 Aug 2019 11:15:41 +0000 (12:15 +0100)]
drm/amd/powerplay: fix off-by-one upper bounds limit checks
There are two occurrances of off-by-one upper bound checking of indexes
causing potential out-of-bounds array reads. Fix these.
Addresses-Coverity: ("Out-of-bounds read")
Fixes:
cb33363d0e85 ("drm/amd/powerplay: add smu feature name support")
Fixes:
6b294793e384 ("drm/amd/powerplay: add smu message name support")
Signed-off-by: Colin Ian King <colin.king@canonical.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
KyleMahlkuch [Wed, 31 Jul 2019 22:10:14 +0000 (17:10 -0500)]
drm/radeon: Fix EEH during kexec
During kexec some adapters hit an EEH since they are not properly
shut down in the radeon_pci_shutdown() function. Adding
radeon_suspend_kms() fixes this issue.
Signed-off-by: KyleMahlkuch <kmahlkuc@linux.vnet.ibm.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jay Cornwall [Thu, 18 Jul 2019 21:57:22 +0000 (16:57 -0500)]
drm/amdkfd: Extend CU mask to 8 SEs (v3)
Following bitmap layout logic introduced by:
"drm/amdgpu: support get_cu_info for Arcturus".
v2: squash in fixup for gfx_v9_0.c (Alex)
v3: squash in debug print output fix
Signed-off-by: Jay Cornwall <Jay.Cornwall@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Le Ma [Mon, 8 Jul 2019 12:17:48 +0000 (20:17 +0800)]
drm/amdgpu: support get_cu_info for Arcturus
This change is because SE/SH layout on Arcturus is 8*1, different from
4*2(or 4*1) on Vega ASICs.
Currently the cu bitmap array is 4x4 size, and besides the bitmap is used widely
across SW stack. To mostly reduce the scale of impact, we make the cu bitmap
array compatible with SE/SH layout on Arcturus. Then the store of cu bits of
each shader array for Arcturus will be like below:
SE0,SH0 --> bitmap[0][0]
SE1,SH0 --> bitmap[1][0]
SE2,SH0 --> bitmap[2][0]
SE3,SH0 --> bitmap[3][0]
SE4,SH0 --> bitmap[0][1]
SE5,SH0 --> bitmap[1][1]
SE6,SH0 --> bitmap[2][1]
SE7,SH0 --> bitmap[3][1]
Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kent Russell [Wed, 31 Jul 2019 13:24:32 +0000 (09:24 -0400)]
drm/amdgpu: Fix pcie_bw on Vega20
The registers used for VG20 are different in that certain performance
counters were split off to TXCLK3/4. Vega10/12 doesn't have this, so add
a new vg20_get_pcie_usage to reflect this change.
Signed-off-by: Kent Russell <kent.russell@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kent Russell [Wed, 31 Jul 2019 13:23:45 +0000 (09:23 -0400)]
drm/amdgpu: Update NBIO headers to add TXCLK3/4
These are added for VG20, and are needed for PCIe bandwidth.
Signed-off-by: Kent Russell <kent.russell@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Andrey Grodzovsky [Thu, 1 Aug 2019 15:44:17 +0000 (11:44 -0400)]
drm/amdgpu: Add amdgpu_asic_funcs.reset_method for Vega20
Fixes GPU reset crash.
Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Felix Kuehling [Tue, 9 Jul 2019 00:01:22 +0000 (20:01 -0400)]
drm/amdgpu: Mark KFD VRAM allocations for wipe on release
Memory used by KFD applications can contain sensitive information that
should not be leaked to other processes. The current approach to prevent
leaks is to clear VRAM at allocation time. This is not effective because
memory can be reused in other ways without being cleared. Synchronously
clearing memory on the allocation path also carries a significant
performance penalty.
Stop clearing memory at allocation time. Instead mark the memory for
wipe on release.
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Felix Kuehling [Tue, 9 Jul 2019 23:12:44 +0000 (19:12 -0400)]
drm/amdgpu: Implement VRAM wipe on release
Wipe VRAM memory containing sensitive data when moving or releasing
BOs. Clearing the memory is pipelined to minimize any impact on
subsequent memory allocation latency. Use of a poison value should
help debug future use-after-free bugs.
When moving BOs, the existing ttm_bo_pipelined_move ensures that the
memory won't be reused before being wiped.
When releasing BOs, the BO is fenced with the memory fill operation,
which results in queuing the BO for a delayed delete.
v2: Move amdgpu_amdkfd_unreserve_memory_limit into
amdgpu_bo_release_notify so that KFD can use memory that's still
being cleared in the background
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Felix Kuehling [Tue, 9 Jul 2019 00:09:21 +0000 (20:09 -0400)]
drm/amdgpu: Add flag to wipe VRAM on release
This memory allocation flag will be used to indicate BOs containing
sensitive data that should not be leaked to other processes.
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Felix Kuehling [Tue, 9 Jul 2019 23:09:42 +0000 (19:09 -0400)]
drm/ttm: Add release_notify callback to ttm_bo_driver
This notifies the driver that a BO is about to be released.
Releasing a BO also invokes the move_notify callback from
ttm_bo_cleanup_memtype_use, but that happens too late for anything
that would add fences to the BO and require a delayed delete.
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leo Li [Thu, 25 Jul 2019 17:12:24 +0000 (13:12 -0400)]
drm/amd/display: Use switch table for dc_to_smu_clock_type
Using a static int array will cause errors if the given dm_pp_clk_type
is out-of-bounds. For robustness, use a switch table, with a default
case to handle all invalid values.
v2: 0 is a valid clock type for smu_clk_type. Return SMU_CLK_COUNT
instead on invalid mapping.
Signed-off-by: Leo Li <sunpeng.li@amd.com>
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nathan Chancellor [Thu, 4 Jul 2019 05:52:16 +0000 (22:52 -0700)]
drm/amd/display: Use proper enum conversion functions
clang warns:
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_pp_smu.c:336:8:
warning: implicit conversion from enumeration type 'enum smu_clk_type'
to different enumeration type 'enum amd_pp_clock_type'
[-Wenum-conversion]
dc_to_smu_clock_type(clk_type),
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_pp_smu.c:421:14:
warning: implicit conversion from enumeration type 'enum
amd_pp_clock_type' to different enumeration type 'enum smu_clk_type'
[-Wenum-conversion]
dc_to_pp_clock_type(clk_type),
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
There are functions to properly convert between all of these types, use
them so there are no longer any warnings.
Fixes:
a43913ea50a5 ("drm/amd/powerplay: add function get_clock_by_type_with_latency for navi10")
Fixes:
e5e4e22391c2 ("drm/amd/powerplay: add interface to get clock by type with latency for display (v2)")
Link: https://github.com/ClangBuiltLinux/linux/issues/586
Signed-off-by: Nathan Chancellor <natechancellor@gmail.com>
Reviewed-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Monk Liu [Wed, 31 Jul 2019 08:47:56 +0000 (16:47 +0800)]
drm/amdgpu: fix double ucode load by PSP(v3)
previously the ucode loading of PSP was repreated, one executed in
phase_1 init/re-init/resume and the other in fw_loading routine
Avoid this double loading by clearing ip_blocks.status.hw in suspend or reset
prior to the FW loading and any block's hw_init/resume
v2:
still do the smu fw loading since it is needed by bare-metal
v3:
drop the change in reinit_early_sriov, just clear all block's status.hw
in the head place and set the status.hw after hw_init done is enough
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Emily Deng <Emily.Deng@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Monk Liu [Tue, 30 Jul 2019 09:32:27 +0000 (17:32 +0800)]
drm/amdgpu: fix incorrect judge on sos fw version
for SRIOV the SOS fw of PSP is loaded in hypervisor thus
guest won't tell the version of it, and judging feature by
reading the sos fw version in guest side is completely wrong
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Emily Deng <Emily.Deng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Monk Liu [Tue, 30 Jul 2019 09:21:19 +0000 (17:21 +0800)]
drm/amdgpu: cleanup vega10 SRIOV code path
we can simplify all those unnecessary function under
SRIOV for vega10 since:
1) PSP L1 policy is by force enabled in SRIOV
2) original logic always set all flags which make itself
a dummy step
besides,
1) the ih_doorbell_range set should also be skipped
for VEGA10 SRIOV.
2) the gfx_common registers should also be skipped
for VEGA10 SRIOV.
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Emily Deng <Emily.Deng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kevin Wang [Wed, 31 Jul 2019 07:37:07 +0000 (15:37 +0800)]
drm/amd/powerplay: sort feature status index by asic feature id for smu
before this change, the pp_feature sysfs show feature enable state by
logic feature id, it is not easy to read.
this change will sort pp_features show index by asic feature id.
before:
features high: 0x00000623 low: 0xb3cdaffb
00. DPM_PREFETCHER ( 0) : enabeld
01. DPM_GFXCLK ( 1) : enabeld
02. DPM_UCLK ( 3) : enabeld
03. DPM_SOCCLK ( 4) : enabeld
04. DPM_MP0CLK ( 5) : enabeld
05. DPM_LINK ( 6) : enabeld
06. DPM_DCEFCLK ( 7) : enabeld
07. DS_GFXCLK (10) : enabeld
08. DS_SOCCLK (11) : enabeld
09. DS_LCLK (12) : disabled
10. PPT (23) : enabeld
11. TDC (24) : enabeld
12. THERMAL (33) : enabeld
13. RM (35) : disabled
......
after:
features high: 0x00000623 low: 0xb3cdaffb
00. DPM_PREFETCHER ( 0) : enabeld
01. DPM_GFXCLK ( 1) : enabeld
02. DPM_GFX_PACE ( 2) : disabled
03. DPM_UCLK ( 3) : enabeld
04. DPM_SOCCLK ( 4) : enabeld
05. DPM_MP0CLK ( 5) : enabeld
06. DPM_LINK ( 6) : enabeld
07. DPM_DCEFCLK ( 7) : enabeld
08. MEM_VDDCI_SCALING ( 8) : enabeld
09. MEM_MVDD_SCALING ( 9) : enabeld
10. DS_GFXCLK (10) : enabeld
11. DS_SOCCLK (11) : enabeld
12. DS_LCLK (12) : disabled
13. DS_DCEFCLK (13) : enabeld
......
Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Fri, 26 Jul 2019 19:15:12 +0000 (14:15 -0500)]
drm/amdkfd: enable KFD support for navi14
Same as navi10.
Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dennis Li [Tue, 23 Jul 2019 10:23:44 +0000 (18:23 +0800)]
drm/amdgpu: disable inject for failed subblocks of gfx
some subblocks of gfx fail in inject test, disable them
Signed-off-by: Dennis Li <Dennis.Li@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dennis Li [Wed, 31 Jul 2019 12:45:50 +0000 (20:45 +0800)]
drm/amdgpu: support gfx ras error injection and err_cnt query
check gfx error count in both ras querry function and
ras interrupt handler.
gfx ras is still disabled by default due to known stability
issue found in gpu reset.
Signed-off-by: Dennis Li <Dennis.Li@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>