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Sanjay Patel [Wed, 14 Nov 2018 19:12:54 +0000 (19:12 +0000)]
[InstSimplify] add tests for funnel shift with select; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346881
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Sam Clegg [Wed, 14 Nov 2018 18:36:24 +0000 (18:36 +0000)]
[WebAssembly] Add support for dylink section in object format
See https://github.com/WebAssembly/tool-conventions/blob/master/DynamicLinking.md.
Differential Revision: https://reviews.llvm.org/D54490
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346880
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Craig Topper [Wed, 14 Nov 2018 18:16:21 +0000 (18:16 +0000)]
[X86] Allow pmulh to be formed from narrow vXi16 vectors under -x86-experimental-vector-widening-legalization
Narrower vectors will be widened to 128 bits without changing the element size. And generic type legalization can already handle widening mulhu/mulhs.
Differential Revision: https://reviews.llvm.org/D54513
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346879
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Mandeep Singh Grang [Wed, 14 Nov 2018 17:55:07 +0000 (17:55 +0000)]
[InstCombine] Remove a couple of asserts based on incorrect assumptions
Summary:
These asserts are based on the assumption that the order of true/false operands in a select and those in the compare would always be the same.
This fixes PR39595.
Reviewers: craig.topper, spatel, dmgreen
Reviewed By: craig.topper
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D54359
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346874
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Sanjay Patel [Wed, 14 Nov 2018 16:03:36 +0000 (16:03 +0000)]
[InstCombine] fix formatting for matchBSwap(); NFC
We should have a similar function for matching rotate and/or
funnel shift, so tidy up the related existing call.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346871
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Florian Hahn [Wed, 14 Nov 2018 15:58:40 +0000 (15:58 +0000)]
[VPlan, SLP] Use SmallPtrSet for Candidates.
This slightly improves the candidate handling in getBest().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346870
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John Brawn [Wed, 14 Nov 2018 15:27:07 +0000 (15:27 +0000)]
[SimplifyCFG] Regenerate preserve-branchweights.ll test. NFC
Regenerate this test using update_test_checks.py in preparation for an
upcomming commit, to make it not depend on the names of instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346869
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Simon Pilgrim [Wed, 14 Nov 2018 15:04:08 +0000 (15:04 +0000)]
[TTI] getOperandInfo - a broadcast shuffle means the result is OK_UniformValue
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346868
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Paul Robinson [Wed, 14 Nov 2018 13:43:19 +0000 (13:43 +0000)]
Document how to comment an actual parameter.
Differential Revision: https://reviews.llvm.org/D54446
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346861
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Florian Hahn [Wed, 14 Nov 2018 13:33:44 +0000 (13:33 +0000)]
[VPlan] Remove LLVM_DEBUG from VPlanSlp::dumpBundle.
The caller should take care of only calling it with debug enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346860
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Simon Pilgrim [Wed, 14 Nov 2018 13:23:28 +0000 (13:23 +0000)]
[TTI] Pull out repeated 'ConcreteTTI' static_casts. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346859
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Florian Hahn [Wed, 14 Nov 2018 13:21:26 +0000 (13:21 +0000)]
[VPlan] Update ifdef.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346858
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Florian Hahn [Wed, 14 Nov 2018 13:11:49 +0000 (13:11 +0000)]
[VPlan, SLP] Add simple SLP analysis on top of VPlan.
This patch adds an initial implementation of the look-ahead SLP tree
construction described in 'Look-Ahead SLP: Auto-vectorization in the Presence
of Commutative Operations, CGO 2018 by Vasileios Porpodas, Rodrigo C. O. Rocha,
Luís F. W. Góes'.
It returns an SLP tree represented as VPInstructions, with combined
instructions represented as a single, wider VPInstruction.
This initial version does not support instructions with multiple
different users (either inside or outside the SLP tree) or
non-instruction operands; it won't generate any shuffles or
insertelement instructions.
It also just adds the analysis that builds an SLP tree rooted in a set
of stores. It does not include any cost modeling or memory legality
checks. The plan is to integrate it with VPlan based cost modeling, once
available and to only apply it to operations that can be widened.
A follow-up patch will add a support for replacing instructions in a
VPlan with their SLP counter parts.
Reviewers: Ayal, mssimpso, rengolin, mkuper, hfinkel, hsaito, dcaballe, vporpo, RKSimon, ABataev
Reviewed By: rengolin
Differential Revision: https://reviews.llvm.org/D4949
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346857
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Simon Pilgrim [Wed, 14 Nov 2018 12:24:50 +0000 (12:24 +0000)]
[CostModel] Add generic expansion funnel shift cost support
Add support for the expansion of funnelshift/rotates to getIntrinsicInstrCost.
This also required us to move the X86 fshl/fshr costs to the same place as the rotates to avoid expansion and get correct scalarization vs vectorization costs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346854
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Xing GUO [Wed, 14 Nov 2018 11:30:34 +0000 (11:30 +0000)]
[llvm-objdump] Improve ELF file type checking statements (D54509)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346851
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Simon Pilgrim [Wed, 14 Nov 2018 11:26:35 +0000 (11:26 +0000)]
[X86][AVX512] Remove constant pool shuffle decoding from SelectionDAG
This patch removes the last use of the constant pool shuffle decode helper and consistently uses the 'getTargetShuffleMaskIndices' versions instead. The constant pool versions are now purely used for assembly comments.
The avx512vbmi intrinsic upgrades had to be altered as they were being decoded as broadcasts, similar to what I fixed in rL346032. I don't think the change is critical - although its annoying that we lose the {k}{z} instruction test coverage as they are tricky to generate....
Differential Revision: https://reviews.llvm.org/D54083
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346850
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Heejin Ahn [Wed, 14 Nov 2018 10:11:22 +0000 (10:11 +0000)]
[WebAssembly] Make sure event-section XFAILs for build options
rL346840 temporarily marked event-section.ll as XFAIL because it was
failing for builds with LLVM_ENABLE_EXPENSIVE_CHECKS turned on, but
to make sure it XFAILs even without LLVM_ENABLE_EXPENSIVE_CHECKS on we
need this `-verify-machineinstrs` flag, which was missing in the
previous commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346845
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Sven van Haastregt [Wed, 14 Nov 2018 10:05:28 +0000 (10:05 +0000)]
Print newline after banner for ModulePass
Before this commit, `llc -print-after-all` would print something like:
*** IR Dump After Pre-ISel Intrinsic Lowering ***; ModuleID = ...
Emit a newline such that ModuleID appears on a line by its own.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346844
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Florian Hahn [Wed, 14 Nov 2018 10:04:30 +0000 (10:04 +0000)]
Recommit r346483: [CallSiteSplitting] Only record conditions up to the IDom(call site).
The underlying problem causing the expensive-check failure was fixed in
rL346769.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346843
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Heejin Ahn [Wed, 14 Nov 2018 09:51:21 +0000 (09:51 +0000)]
[WebAssembly] Temporarily disable event-section.ll
This test is failing in builds with LLVM_ENABLE_EXPENSIVE_CHECKS after
rL346825 not because of the patch but due to a pre-existing codegen
problem. Marking this as XFAIL temporarily until the bug is fixed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346840
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Craig Topper [Wed, 14 Nov 2018 07:51:26 +0000 (07:51 +0000)]
[X86] Add -x86-experimental-vector-widening command lines to pmulh.ll
I've only added sse2 and sse4.1 variants as I'm only interested in the two v4i16 tests and I don't expect that to different with AVX other than a v prefix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346834
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David Blaikie [Wed, 14 Nov 2018 07:19:21 +0000 (07:19 +0000)]
Correctly instantiate `iterator_adaptor_base` when defining `pointer_iterator`
The definition of `pointer_iterator` omits what should be a `iterator_traits::<>::iterator_category` parameter from `iterator_adaptor_base`. As a result, iterators based on `pointer_iterator` always have defaulted value types and the wrong iterator category.
The definition of `pointee_iterator` just a few lines above does this correctly.
This resolves [[ https://bugs.llvm.org/show_bug.cgi?id=39617 | bug 39617 ]].
Patch by Dylan MacKenzie!
Reviewers: dblaikie
Differential Revision: https://reviews.llvm.org/D54377
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346833
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Heejin Ahn [Wed, 14 Nov 2018 02:46:21 +0000 (02:46 +0000)]
[WebAssembly] Add support for the event section
Summary:
This adds support for the 'event section' specified in the exception
handling proposal. (This was named 'exception section' first, but later
renamed to 'event section' to take possibilities of other kinds of
events into consideration. But currently we only store exception info in
this section.)
The event section is added between the global section and the export
section. This is for ease of validation per request of the V8 team.
This patch:
- Creates the event symbol type, which is a weak symbol
- Makes 'throw' instruction take the event symbol '__cpp_exception'
- Adds relocation support for events
- Adds WasmObjectWriter / WasmObjectFile (Reader) support
- Adds obj2yaml / yaml2obj support
- Adds '.eventtype' printing support
Reviewers: dschuff, sbc100, aardappel
Subscribers: jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D54096
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346825
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Zi Xuan Wu [Wed, 14 Nov 2018 02:34:45 +0000 (02:34 +0000)]
[PowerPC] Enhance the selection(ISD::VSELECT) of vector type
To make ISD::VSELECT available(legal) so long as there are altivec instruction, otherwise it's default behavior is expanding,
which is legalized at type-legalization phase. Use xxsel to match vselect if vsx is open, or use vsel.
Differential Revision: https://reviews.llvm.org/D49531
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346824
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Reid Kleckner [Wed, 14 Nov 2018 01:47:32 +0000 (01:47 +0000)]
Revert r346810 "Preserve loop metadata when splitting exit blocks"
It broke the Windows self-host:
http://lab.llvm.org:8011/builders/clang-x64-windows-msvc/builds/1457
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346823
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Eli Friedman [Wed, 14 Nov 2018 00:39:29 +0000 (00:39 +0000)]
[CodeGen] Fix forward scan in MachineBasicBlock::computeRegisterLiveness.
The scan was incorrectly skipping the first instruction, so a register
could appear to be dead when it was actually live. This eventually leads
to a machine verifier failure and miscompile in arm-ldst-opt.
Differential Revision: https://reviews.llvm.org/D54491
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346821
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Jessica Paquette [Tue, 13 Nov 2018 23:41:31 +0000 (23:41 +0000)]
[MachineOutliner][NFC] Use flags set in all candidates to check for calls
If we keep track of if the ContainsCalls bit is set in the MBB flags for each
candidate, then we have a better chance of not checking the candidate for calls
at all.
This saves quite a few checks in some CTMark tests (~200 in Bullet, for
example.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346816
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Adrian Prantl [Tue, 13 Nov 2018 23:31:25 +0000 (23:31 +0000)]
Make dsymutil more robust when parsing load commands.
rdar://problem/
45883463
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346815
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Sanjay Patel [Tue, 13 Nov 2018 23:27:23 +0000 (23:27 +0000)]
[InstCombine] fold funnel shift amount based on demanded bits
The shift amount of a funnel shift is modulo the scalar bitwidth:
http://llvm.org/docs/LangRef.html#llvm-fshl-intrinsic
...so we can use demanded bits analysis on that operand to simplify it
when we have a power-of-2 bitwidth.
This is another step towards canonicalizing {shift/shift/or} to the
intrinsics in IR.
Differential Revision: https://reviews.llvm.org/D54478
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346814
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Matthew Voss [Tue, 13 Nov 2018 23:21:00 +0000 (23:21 +0000)]
Make the ExpandTilde unit test expect "\" (not "/") on Win32
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346813
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Craig Topper [Tue, 13 Nov 2018 23:06:49 +0000 (23:06 +0000)]
Preserve loop metadata when splitting exit blocks
LoopUtils.cpp contains a utility that splits an loop exit block, so that the new block contains only edges coming from the loop. In the case of nested loops, the exit path for the inner loop might also be the back-edge of the outer loop. The new block which is inserted on this path, is now a latch for the outer loop, and it needs to hold the loop metadata for the outer loop. (The test case gives a more concrete view of the situation.)
Patch by Chang Lin (clin1)
Differential Revision: https://reviews.llvm.org/D53876
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346810
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Jessica Paquette [Tue, 13 Nov 2018 23:01:34 +0000 (23:01 +0000)]
[MachineOutliner][NFC] Use MBB flags to avoid call checks in getOutliningInfo
We already determine a bunch of information about an MBB in
getMachineOutlinerMBBFlags. We can reuse that information to avoid calculating
things that must be false/true.
The first thing we can easily check is if an outlined sequence could ever
contain calls. There's no reason to walk over the outlined range, checking for
calls, if we already know that there are no calls in the block containing the
sequence.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346809
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Sanjay Patel [Tue, 13 Nov 2018 22:47:24 +0000 (22:47 +0000)]
[InstCombine] canonicalize rotate patterns with cmp/select
The cmp+branch variant of this pattern is shown in:
https://bugs.llvm.org/show_bug.cgi?id=34924
...and as discussed there, we probably can't transform
that without a rotate intrinsic. We do have that now
via funnel shift, but we're not quite ready to
canonicalize IR to that form yet. The case with 'select'
should already be transformed though, so that's this patch.
The sequence with negation followed by masking is what we
use in the backend and partly in clang (though that part
should be updated).
https://rise4fun.com/Alive/TplC
%cmp = icmp eq i32 %shamt, 0
%sub = sub i32 32, %shamt
%shr = lshr i32 %x, %shamt
%shl = shl i32 %x, %sub
%or = or i32 %shr, %shl
%r = select i1 %cmp, i32 %x, i32 %or
=>
%neg = sub i32 0, %shamt
%masked = and i32 %shamt, 31
%maskedneg = and i32 %neg, 31
%shl2 = lshr i32 %x, %masked
%shr2 = shl i32 %x, %maskedneg
%r = or i32 %shl2, %shr2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346807
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Jessica Paquette [Tue, 13 Nov 2018 22:16:27 +0000 (22:16 +0000)]
[MachineOutliner][NFC] Exit getOutliningType if there are < 2 candidates
Since we never outline anything with fewer than 2 occurrences, there's no
reason to compute cost model information if there's less than that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346803
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Stanislav Mekhanoshin [Tue, 13 Nov 2018 21:18:21 +0000 (21:18 +0000)]
[AMDGPU] combine extractelement into several selects
An extractelement with non-constant index will be lowered either to
scratch or movrel loop in most cases. This patch converts such
instruction into a set of selects if vector size is not too big.
Differential Revision: https://reviews.llvm.org/D54351
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346800
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Alina Sbirlea [Tue, 13 Nov 2018 21:12:49 +0000 (21:12 +0000)]
[MemorySSA] Create query after checking if instruction is a fence.
The alternative is checking if I is a fence in the Query constructor, so
as to not attempt to get a non-existent MemoryLocation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346798
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Fangrui Song [Tue, 13 Nov 2018 20:59:25 +0000 (20:59 +0000)]
[AsmPrinter] Fix DebugInfo/X86/gnu-public-names.ll after rL346790
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346797
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Stanislav Mekhanoshin [Tue, 13 Nov 2018 20:26:27 +0000 (20:26 +0000)]
Fixed DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT i1 handling
Legalizer used to request an ext load from i8 to i1 when promoting
vector element type to i8. Fixed.
Differential Revision: https://reviews.llvm.org/D54440
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346795
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Nico Weber [Tue, 13 Nov 2018 20:18:26 +0000 (20:18 +0000)]
[MS Demangler] Print public:, protected:, private: if set in FunctionClass or a variable's StorageClass.
undname prints them, and the information is in the decorated name, so we probably shouldn't lose it when undecorating.
I spot-checked a few of the funnier-looking outputs, and undname has the same output.
Differential Revision: https://reviews.llvm.org/D54396
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346791
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Fangrui Song [Tue, 13 Nov 2018 20:18:08 +0000 (20:18 +0000)]
[AsmPrinter] Rename a comment of .debug_gnu_pubnames entry
Summary:
The comment refers to the field as "Kind:". However, in gdb,
https://sourceware.org/gdb//onlinedocs/gdb/Index-Section-Format.html names it "attributes",
gdb/dwarf2read.c:dw2_symtab_iter_next refers to the whole value as "cu_index_and_attrs"
Change it to `Attributes:` for consistency.
Reviewers: dblaikie
Reviewed By: dblaikie
Subscribers: aprantl, JDevlieghere, arphaman, llvm-commits
Differential Revision: https://reviews.llvm.org/D54480
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346790
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David Blaikie [Tue, 13 Nov 2018 20:08:10 +0000 (20:08 +0000)]
DebugInfo: Add a CU metadata attribute for use of DWARF ranges base address specifiers
Summary:
Ranges base address specifiers can save a lot of object size in
relocation records especially in optimized builds.
For an optimized self-host build of Clang with split DWARF and debug
info compression in object files, but uncompressed debug info in the
executable, this change produces about 18% smaller object files and 6%
larger executable.
While it would've been nice to turn this on by default, gold's 32 bit
gdb-index support crashes on this input & I don't think there's any
perfect heuristic to implement solely in LLVM that would suffice - so
we'll need a flag one way or another (also possible people might want to
aggressively optimized for executable size that contains debug info
(even with compression this would still come at some cost to executable
size)) - so let's plumb it through.
Differential Revision: https://reviews.llvm.org/D54242
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346788
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Zachary Turner [Tue, 13 Nov 2018 20:07:32 +0000 (20:07 +0000)]
[NativePDB] Improved support for nested type reconstruction.
In a previous patch, we pre-processed the TPI stream in order to build
the reverse mapping from nested type -> parent type so that we could
accurately reconstruct a DeclContext hierarchy.
However, there were some issues. An LF_NESTTYPE record is really just a
typedef, so although it happens to be used to indicate the name of the
nested type and referring to the global record which defines the type,
it is also used for every other kind of nested typedef. When we rebuild
the DeclContext hierarchy, we want it to be as accurate as possible,
which means that if we have something like:
struct A {
struct B {};
using C = B;
};
We don't want to create two CXXRecordDecls in the AST each with the
exact same definition. We just want to create one for B and then
define C as an alias to B. Previously, however, it would not be able
to distinguish between the two cases and it would treat A::B and
A::C as being two classes each with separate definitions. We address
the first half of improving the pre-processing logic so that only
actual definitions are treated this way.
Later, in a followup patch, we can handle the case of nested
typedefs since we're already going to be enumerating the field list
anyway and this patch introduces the general framework for
distinguishing between the two cases.
Differential Revision: https://reviews.llvm.org/D54357
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346786
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Matt Arsenault [Tue, 13 Nov 2018 19:50:38 +0000 (19:50 +0000)]
Add fneg instruction to syntax highlighting lists
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346785
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Craig Topper [Tue, 13 Nov 2018 19:45:21 +0000 (19:45 +0000)]
[SelectionDAG][X86] Relax restriction on the width of an input to *_EXTEND_VECTOR_INREG. Use them and regular *_EXTEND to replace the X86 specific VSEXT/VZEXT opcodes
Previously, the extend_vector_inreg opcode required their input register to be the same total width as their output. But this doesn't match up with how the X86 instructions are defined. For X86 the input just needs to be a legal type with at least enough elements to cover the output.
This patch weakens the check on these nodes and allows them to be used as long as they have more input elements than output elements. I haven't changed type legalization behavior so it will still create them with matching input and output sizes.
X86 will custom legalize these nodes by shrinking the input to be a 128 bit vector and once we've done that we treat them as legal operations. We still have one case during type legalization where we must custom handle v64i8 on avx512f targets without avx512bw where v64i8 isn't a legal type. In this case we will custom type legalize to a *extend_vector_inreg with a v16i8 input. After that the input is a legal type so type legalization should ignore the node and doesn't need to know about the relaxed restriction. We are no longer allowed to use the default expansion for these nodes during vector op legalization since the default expansion uses a shuffle which required the widths to match. Custom legalization for all types will prevent us from reaching the default expansion code.
I believe DAG combine works correctly with the released restriction because it doesn't check the number of input elements.
The rest of the patch is changing X86 to use either the vector_inreg nodes or the regular zero_extend/sign_extend nodes. I had to add additional isel patterns to handle any_extend during isel since simplifydemandedbits can create them at any time so we can't legalize to zero_extend before isel. We don't yet create any_extend_vector_inreg in simplifydemandedbits.
Differential Revision: https://reviews.llvm.org/D54346
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346784
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Jordan Rupprecht [Tue, 13 Nov 2018 19:32:27 +0000 (19:32 +0000)]
[llvm-objcopy] Rename --keep to --keep-section.
Summary:
llvm-objcopy/strip support `--keep` (for sections) and `--keep-symbols` (for symbols). For consistency and clarity, rename `--keep` to `--keep-section`.
In fact, for GNU compatability, -K is --keep-symbol, so it's weird that the alias `-K` is not the same as the short-ish `--keep`.
Reviewers: jakehehrlich, jhenderson, alexshap, MaskRay, espindola
Reviewed By: jakehehrlich, MaskRay
Subscribers: emaste, arichardson, llvm-commits
Differential Revision: https://reviews.llvm.org/D54477
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346782
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Sam Clegg [Tue, 13 Nov 2018 19:14:02 +0000 (19:14 +0000)]
[WebAssembly] Fix broken assumption that all bitcasts are to functions types
Specifically, we can bitcast to void.
Fixes PR39591
Differential Revision: https://reviews.llvm.org/D54447
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346778
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Jonas Devlieghere [Tue, 13 Nov 2018 18:23:32 +0000 (18:23 +0000)]
[FileSystem] Add expand_tilde function
In D54435 there was some discussion about the expand_tilde flag for
real_path that I wanted to expose through the VFS. The consensus is that
these two things should be separate functions. Since we already have the
code for this I went ahead and added a function expand_tilde that does
just that.
Differential revision: https://reviews.llvm.org/D54448
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346776
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Cameron McInally [Tue, 13 Nov 2018 18:15:47 +0000 (18:15 +0000)]
[IR] Add a dedicated FNeg IR Instruction
The IEEE-754 Standard makes it clear that fneg(x) and
fsub(-0.0, x) are two different operations. The former is a bitwise
operation, while the latter is an arithmetic operation. This patch
creates a dedicated FNeg IR Instruction to model that behavior.
Differential Revision: https://reviews.llvm.org/D53877
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346774
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Simon Atanasyan [Tue, 13 Nov 2018 18:14:29 +0000 (18:14 +0000)]
[WebAssembly] Mark immediates.ll as XFAILed on MIPS hosts
Usually MIPS hosts uses a legacy (non IEEE 754-2008) encoding for NaNs.
Tests like `nan_f32` failed in attempt to compare hard-coded IEEE
754-2008 NaN value and a legacy NaN value provided by a system.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346773
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Florian Hahn [Tue, 13 Nov 2018 17:54:43 +0000 (17:54 +0000)]
[CSP, Cloning] Update DuplicateInstructionsInSplitBetween to use DomTreeUpdater.
This patch updates DuplicateInstructionsInSplitBetween to update a DTU
instead of applying updates to the DT directly.
Given that there only are 2 users, also updated them in this patch to
avoid churn.
I slightly moved the code in CallSiteSplitting around to reduce the
places where we have to pass in DTU. If necessary, I could split those
changes in a separate patch.
This fixes missing DT updates when dealing with musttail calls in
CallSiteSplitting, by using DTU->deleteBB.
Reviewers: junbuml, kuhar, NutshellySima, indutny, brzycki
Reviewed By: NutshellySima
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346769
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Steven Wu [Tue, 13 Nov 2018 17:35:04 +0000 (17:35 +0000)]
Revert "[ThinLTO] Internalize readonly globals"
This reverts commit
10c84a8f35cae4a9fc421648d9608fccda3925f2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346768
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Sanjay Patel [Tue, 13 Nov 2018 16:47:16 +0000 (16:47 +0000)]
[InstCombine] add tests for funnel shift demanded bits; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346762
91177308-0d34-0410-b5e6-
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Alexander Kornienko [Tue, 13 Nov 2018 16:41:05 +0000 (16:41 +0000)]
Fix uninitialized variable.
Flags variable was not initialized and later used (both isMBBSafeToOutlineFrom
implementations assume it's initialized), which breaks
test/CodeGen/AArch64/machine-outliner.mir. under memory sanitizer:
MemorySanitizer: use-of-uninitialized-value
#0 in llvm::AArch64InstrInfo::getOutliningType(llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>&, unsigned int) const llvm/lib/Target/AArch64/AArch64InstrInfo.cpp:5494:9
#1 in (anonymous namespace)::InstructionMapper::convertToUnsignedVec(llvm::MachineBasicBlock&, llvm::TargetInstrInfo const&) llvm/lib/CodeGen/MachineOutliner.cpp:772:19
#2 in (anonymous namespace)::MachineOutliner::populateMapper((anonymous namespace)::InstructionMapper&, llvm::Module&, llvm::MachineModuleInfo&) llvm/lib/CodeGen/MachineOutliner.cpp:1543:14
#3 in (anonymous namespace)::MachineOutliner::runOnModule(llvm::Module&) llvm/lib/CodeGen/MachineOutliner.cpp:1645:3
#4 in (anonymous namespace)::MPPassManager::runOnModule(llvm::Module&) llvm/lib/IR/LegacyPassManager.cpp:1744:27
#5 in llvm::legacy::PassManagerImpl::run(llvm::Module&) llvm/lib/IR/LegacyPassManager.cpp:1857:44
#6 in compileModule(char**, llvm::LLVMContext&) llvm/tools/llc/llc.cpp:597:8
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346761
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Simon Pilgrim [Tue, 13 Nov 2018 16:40:10 +0000 (16:40 +0000)]
[CostModel][X86] Fix constant vector XOP rights shifts
We'll constant fold these cases so they are as cheap as vector left shift cases.
Noticed while improving funnel shift costs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346760
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Florian Hahn [Tue, 13 Nov 2018 16:26:34 +0000 (16:26 +0000)]
[VectorUtils] Use namespace for InterleaveGroup template specialization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346759
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Florian Hahn [Tue, 13 Nov 2018 15:58:18 +0000 (15:58 +0000)]
[VPlan] VPlan version of InterleavedAccessInfo.
This patch turns InterleaveGroup into a template with the instruction type
being a template parameter. It also adds a VPInterleavedAccessInfo class, which
only contains a mapping from VPInstructions to their respective InterleaveGroup.
As we do not have access to scalar evolution in VPlan, we can re-use
convert InterleavedAccessInfo to VPInterleavedAccess info.
Reviewers: Ayal, mssimpso, hfinkel, dcaballe, rengolin, mkuper, hsaito
Reviewed By: rengolin
Differential Revision: https://reviews.llvm.org/D49489
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346758
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Simon Pilgrim [Tue, 13 Nov 2018 13:45:10 +0000 (13:45 +0000)]
[TTI] Make TargetTransformInfo::getOperandInfo static. NFCI.
It has no member dependencies and this makes it easier to reuse in other cost analysis code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346755
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Simon Pilgrim [Tue, 13 Nov 2018 12:11:15 +0000 (12:11 +0000)]
[CostModel][X86] Add more cost tests for funnel shifts
Added full uniform/constant coverage for funnel shifts + rotates
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346754
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Simon Pilgrim [Tue, 13 Nov 2018 12:09:27 +0000 (12:09 +0000)]
Fix comment for XOP rotates. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346753
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Simon Pilgrim [Tue, 13 Nov 2018 11:28:46 +0000 (11:28 +0000)]
Add bracket that was lost in rL346727 and has been causing buildbot failures for some time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346752
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Alexander Richardson [Tue, 13 Nov 2018 10:54:49 +0000 (10:54 +0000)]
Fix .cfi_restore with register numbers > 64
Summary:
DW_CFA_restore can only encode register numbers up to 64 (6 bits unsigned
int). For regsiter numbers > 64 we have to use DW_CFA_restore_extended
instead which uses a ULEB128 value.
I discovered this problem in the out-of-tree CHERI target since we use
DWARF register number 89 for our return capability register.
Reviewers: probinson, dblaikie, aprantl, espindola
Reviewed By: dblaikie
Subscribers: JohnReagan, emaste, JDevlieghere, llvm-commits
Differential Revision: https://reviews.llvm.org/D54420
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346751
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Alexander Richardson [Tue, 13 Nov 2018 10:54:44 +0000 (10:54 +0000)]
Fix modules build of AVRAsmParser.cpp
Summary:
Without this change I get the following error:
lib/Target/AVR/AVRGenAsmMatcher.inc:1135:1: error: redundant #include of module 'LLVM_Utils.Support.Format' appears within namespace 'llvm' [-Wmodules-import-nested-redundant]
Reviewers: dylanmckay
Reviewed By: dylanmckay
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D53425
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346750
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Jonas Paulsson [Tue, 13 Nov 2018 08:37:09 +0000 (08:37 +0000)]
[SystemZ] Increase the number of VLREPs
If a loaded value is replicated it is best to combine these two operations
into a VLREP (load and replicate), but isel will not produce this if the load
has other users as well.
This patch handles this by putting the other users of the load to use the
REPLICATE 0-element instead of the load. This way the load has only the
REPLICATE node as user, and we get a VLREP.
Review: Ulrich Weigand
https://reviews.llvm.org/D54264
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346746
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Craig Topper [Tue, 13 Nov 2018 07:47:52 +0000 (07:47 +0000)]
[X86] Add more tests for -x86-experimental-vector-widening-legalization
I'm looking into whether we can make this the default legalization strategy. Adding these tests to help cover the changes that will be necessary.
This patch adds copies of some tests with the command line switch enabled. By making copies its easier to compare the two legalization strategies.
I've also removed RUN lines from some of these tests that already had -x86-experimental-vector-widening-legalization
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346745
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Fedor Sergeev [Tue, 13 Nov 2018 05:47:01 +0000 (05:47 +0000)]
[FileCheck] fixing docs buildbot - use proper code-block type
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346740
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George Karpenkov [Tue, 13 Nov 2018 02:59:27 +0000 (02:59 +0000)]
[BuildingAJIT] Fixing the build by inserting a forgotten paren.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346730
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Xing GUO [Tue, 13 Nov 2018 02:14:38 +0000 (02:14 +0000)]
[commit test] Add blank line to test/tools/llvm-objdump/full-contents.test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346729
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Craig Topper [Tue, 13 Nov 2018 01:59:32 +0000 (01:59 +0000)]
[DAGCombiner] Enable tryToFoldExtendOfConstant to run after legalize vector ops
It should be ok to create a new build_vector after legal operations so long as it doesn't cause an infinite loop in DAG combiner.
Unfortunately, X86's custom constant folding in combineVSZext is hiding any test changes from this. But I'm trying to get to a point where that X86 specific code isn't necessary at all.
Differential Revision: https://reviews.llvm.org/D54285
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346728
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Lang Hames [Tue, 13 Nov 2018 01:26:25 +0000 (01:26 +0000)]
[BuildingAJIT] Clang-format chapters 1 and 2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346727
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Lang Hames [Tue, 13 Nov 2018 01:25:34 +0000 (01:25 +0000)]
[BuildingAJIT] Update chapter 2 to use the ORCv2 APIs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346726
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Fedor Sergeev [Tue, 13 Nov 2018 01:12:19 +0000 (01:12 +0000)]
[FileCheck] fixing small formatting error in docs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346725
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Jake Ehrlich [Tue, 13 Nov 2018 01:10:35 +0000 (01:10 +0000)]
[libObject] Fix getDesc for Elf_Note_Impl
This change fixes a bug in Elf_Note_Impl in which Elf_Word was used
where uint8_t should have been used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346724
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Fedor Sergeev [Tue, 13 Nov 2018 01:09:53 +0000 (01:09 +0000)]
[FileCheck] fixing typo in assert
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346723
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Fedor Sergeev [Tue, 13 Nov 2018 00:46:13 +0000 (00:46 +0000)]
[FileCheck] introduce CHECK-COUNT-<num> repetition directive
In some cases it is desirable to match the same pattern repeatedly
many times. Currently the only way to do it is to copy the same
check pattern as many times as needed. And that gets pretty unwieldy
when its more than count is big.
Introducing CHECK-COUNT-<num> directive which acts like a plain CHECK
directive yet matches the same pattern exactly <num> times.
Extended FileCheckType to a struct to add Count there.
Changed some parsing routines to handle non-fixed length of directive
(all currently existing directives were fixed-length).
The code is generic enough to allow future support for COUNT in more
than just PlainCheck directives.
See motivating example for this feature in reviews.llvm.org/D54223.
Reviewed By: chandlerc, dblaikie
Differential Revision: https://reviews.llvm.org/D54336
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346722
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Jessica Paquette [Tue, 13 Nov 2018 00:32:09 +0000 (00:32 +0000)]
[MachineOutliner][NFC] Simplify isMBBSafeToOutlineFrom check in AArch64 outliner
Turns out it's way simpler to do this check with one LRU. Instead of
maintaining two, just keep one. Check if each of the registers is available,
and then check if it's a live out from the block. If it's a live out, but
available in the block, we know we're in an unsafe case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346721
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Zhizhou Yang [Tue, 13 Nov 2018 00:31:22 +0000 (00:31 +0000)]
Introduce DebugCounter into ConstProp pass
Summary:
This patch introduces DebugCounter into ConstProp pass at per-transformation level.
It will provide an option to skip first n or stop after n transformations for the whole ConstProp pass.
This will make debug easier for the pass, also providing chance to do transformation level bisecting.
Reviewers: davide, fhahn
Reviewed By: fhahn
Subscribers: llozano, george.burgess.iv, llvm-commits
Differential Revision: https://reviews.llvm.org/D50094
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346720
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Sanjay Patel [Mon, 12 Nov 2018 23:58:59 +0000 (23:58 +0000)]
[InstCombine] add rotate variants that include select; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346719
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Jessica Paquette [Mon, 12 Nov 2018 23:51:32 +0000 (23:51 +0000)]
[MachineOutliner][NFC] Change getMachineOutlinerMBBFlags to isMBBSafeToOutlineFrom
Instead of returning Flags, return true if the MBB is safe to outline from.
This lets us check for unsafe situations, like say, in AArch64, X17 is live
across a MBB without being defined in that MBB. In that case, there's no point
in performing an instruction mapping.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346718
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Fangrui Song [Mon, 12 Nov 2018 23:46:22 +0000 (23:46 +0000)]
[llvm-objcopy] Don't copy Config when processing --keep
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346717
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Sanjay Patel [Mon, 12 Nov 2018 22:52:25 +0000 (22:52 +0000)]
[InstCombine] narrow width of rotate patterns, part 3
This is a longer variant for the pattern handled in
rL346713
This one includes zexts.
Eventually, we should canonicalize all rotate patterns
to the funnel shift intrinsics, but we need a bit more
infrastructure to make sure the vectorizers handle those
intrinsics as well as the shift+logic ops.
https://rise4fun.com/Alive/FMn
Name: narrow rotateright
%neg = sub i8 0, %shamt
%rshamt = and i8 %shamt, 7
%rshamtconv = zext i8 %rshamt to i32
%lshamt = and i8 %neg, 7
%lshamtconv = zext i8 %lshamt to i32
%conv = zext i8 %x to i32
%shr = lshr i32 %conv, %rshamtconv
%shl = shl i32 %conv, %lshamtconv
%or = or i32 %shl, %shr
%r = trunc i32 %or to i8
=>
%maskedShAmt2 = and i8 %shamt, 7
%negShAmt2 = sub i8 0, %shamt
%maskedNegShAmt2 = and i8 %negShAmt2, 7
%shl2 = lshr i8 %x, %maskedShAmt2
%shr2 = shl i8 %x, %maskedNegShAmt2
%r = or i8 %shl2, %shr2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346716
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Simon Atanasyan [Mon, 12 Nov 2018 22:43:17 +0000 (22:43 +0000)]
[DWARF] Do not use PRIx32 for printing uint64_t values
The `DWARFDebugAddrTable::dump` routine prints 32/64-bits addresses.
These values are stored in a vector of `uint64_t` independently of their
original sizes. But `format` function gets format string with PRIx32
suffix in case of 32-bit address size. At least on MIPS 32-bit targets
that leads to incorrect output.
This patch changes formats strings and always use PRIx64 to print
`uint64_t` values.
Differential Revision: http://reviews.llvm.org/D54424
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346715
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Sanjay Patel [Mon, 12 Nov 2018 22:11:09 +0000 (22:11 +0000)]
[InstCombine] narrow width of rotate patterns, part 2 (PR39624)
The sub-pattern for the shift amount in a rotate can take on
several different forms, and there's apparently no way to
canonicalize those without seeing the entire rotate sequence.
This is the form noted in:
https://bugs.llvm.org/show_bug.cgi?id=39624
https://rise4fun.com/Alive/qnT
%zx = zext i8 %x to i32
%maskedShAmt = and i32 %shAmt, 7
%shl = shl i32 %zx, %maskedShAmt
%negShAmt = sub i32 0, %shAmt
%maskedNegShAmt = and i32 %negShAmt, 7
%shr = lshr i32 %zx, %maskedNegShAmt
%rot = or i32 %shl, %shr
%r = trunc i32 %rot to i8
=>
%truncShAmt = trunc i32 %shAmt to i8
%maskedShAmt2 = and i8 %truncShAmt, 7
%shl2 = shl i8 %x, %maskedShAmt2
%negShAmt2 = sub i8 0, %truncShAmt
%maskedNegShAmt2 = and i8 %negShAmt2, 7
%shr2 = lshr i8 %x, %maskedNegShAmt2
%r = or i8 %shl2, %shr2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346713
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Philip Reames [Mon, 12 Nov 2018 22:03:53 +0000 (22:03 +0000)]
[GC][NFC] Simplify code now that we only have one safepoint kind
This is the NFC follow up to exploit the semantic simplification from r346701
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346712
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Sanjay Patel [Mon, 12 Nov 2018 22:00:00 +0000 (22:00 +0000)]
[InstCombine] refactor code for matching shift amount of a rotate; NFC
As shown in existing test cases and with:
https://bugs.llvm.org/show_bug.cgi?id=39624
...we're missing at least 2 more patterns for rotate narrowing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346711
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Ali Tamur [Mon, 12 Nov 2018 21:43:43 +0000 (21:43 +0000)]
Use a data structure better suited for large sets in SimplificationTracker.
Summary:
D44571 changed SimplificationTracker to use SmallSetVector to keep phi nodes. As a result, when the number of phi nodes is large, the build time performance suffers badly. When building for power pc, we have a case where there are more than 600.000 nodes, and it takes too long to compile.
In this change, I partially revert D44571 to use SmallPtrSet, which does an acceptable job with any number of elements. In the original patch, having a deterministic iteration order was mentioned as a motivation, however I think it only applies to the nodes already matched in MatchPhiSet method, which I did not touch.
Reviewers: bjope, skatkov
Reviewed By: bjope, skatkov
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D54007
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346710
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Simon Pilgrim [Mon, 12 Nov 2018 21:12:38 +0000 (21:12 +0000)]
[X86][SSE] Add lowerVectorShuffleAsByteRotateAndPermute (PR39387)
This patch adds the ability to use a PALIGNR to rotate a pair of inputs to select a range containing all the referenced elements, followed by a single input permute to put them in the right location.
Differential Revision: https://reviews.llvm.org/D54267
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346706
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Aakanksha Patil [Mon, 12 Nov 2018 21:04:06 +0000 (21:04 +0000)]
AMDGPU: Adding more median3 patterns
min(max(a, b), max(min(a, b), c)) -> med3 a, b, c
Differential Revision: https://reviews.llvm.org/D54331
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346704
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Sanjay Patel [Mon, 12 Nov 2018 20:32:59 +0000 (20:32 +0000)]
[InstCombine] add more tests for rotate narrowing; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346703
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Philip Reames [Mon, 12 Nov 2018 20:30:50 +0000 (20:30 +0000)]
[GC docs] Update the gcroot documentation to reflect recent simplifcations to GCStrategy configurability
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346702
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Philip Reames [Mon, 12 Nov 2018 20:15:34 +0000 (20:15 +0000)]
[GC] Remove so called PreCall safepoints
Remove another bit of unused configuration potential from GCStrategy. It's not entirely clear what the intention here was, but from the docs, it sounds like this may have been subsumed by patchable call support.
Note: This change is deliberately small to make it clear that while implemented, there's nothing using the option. A following NFC will do most of the simplifications.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346701
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Wouter van Oortmerssen [Mon, 12 Nov 2018 20:15:01 +0000 (20:15 +0000)]
[WebAssembly] Added WasmAsmParser.
Summary:
This is to replace the ELFAsmParser that WebAssembly was using, which
so far was a stub that didn't do anything, and couldn't work correctly
with wasm.
This new class is there to implement generic directives related to
wasm as a binary format. Wasm target specific directives are still
parsed in WebAssemblyAsmParser as before. The two classes now
cooperate more correctly too.
Also implemented .result which was missing. Any unknown directives
will now result in errors.
Reviewers: dschuff, sbc100
Subscribers: mgorny, jgravelle-google, eraman, aheejin, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D54360
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346700
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Philip Reames [Mon, 12 Nov 2018 20:00:53 +0000 (20:00 +0000)]
[GC][InstCombine] Fix a potential iteration issue
Noticed via inspection. Appears to be largely innocious in practice, but slight code change could have resulted in either visit order dependent missed optimizations or infinite loops. May be a minor compile time problem today.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346698
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Craig Topper [Mon, 12 Nov 2018 19:37:29 +0000 (19:37 +0000)]
[X86] In LowerMULH, use generic truncate and vector shuffle nodes instead of directly emitting PACKUS.
Truncate and shuffle lowering are already capable of matching to PACKUS using known bits analysis.
This features one test change where we now prefer to extend v16i16->v16i32 then trunc v16i32->v16i8 over extract_subvector+packus when avx512f is available, but avx512bw is not.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346697
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David Blaikie [Mon, 12 Nov 2018 18:53:28 +0000 (18:53 +0000)]
NFC: DebugInfo: Reduce scope of DebugOffset to simplify code
This was being used as a sort of indirect out parameter from shouldDump
- seems simpler to use it as the actual result of the call. (this does
mean using a pointer to an Optional & actually using all 3 states (null,
None, and present) which is, admittedly, a tad subtle - but given the
limited scope, seems OK to me - open to discussion though, if others
feel strongly about it)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346691
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Stanislav Mekhanoshin [Mon, 12 Nov 2018 18:48:17 +0000 (18:48 +0000)]
[AMDGPU] Optimize S_CBRANCH_VCC[N]Z -> S_CBRANCH_EXEC[N]Z
Sometimes after basic block placement we end up with a code like:
sreg = s_mov_b64 -1
vcc = s_and_b64 exec, sreg
s_cbranch_vccz
This happens as a join of a block assigning -1 to a saved mask and
another block which consumes that saved mask with s_and_b64 and a
branch.
This is essentially a single s_cbranch_execz instruction when moved
into a single new basic block.
Differential Revision: https://reviews.llvm.org/D54164
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346690
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Sanjay Patel [Mon, 12 Nov 2018 18:41:08 +0000 (18:41 +0000)]
[InstCombine] regenerate checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346689
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Simon Pilgrim [Mon, 12 Nov 2018 18:27:54 +0000 (18:27 +0000)]
[CostModel][X86] Add funnel shift rotation special case costs
When we repeat the 2 shifting operands then this is a bit rotation - annoyingly this has to be done in the other getIntrinsicInstrCost than most intrinsics as we need to check the operands are the same.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346688
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Stanislav Mekhanoshin [Mon, 12 Nov 2018 18:12:28 +0000 (18:12 +0000)]
Fix MachineInstr::findRegisterUseOperandIdx subreg checks
The function only checks that instruction reads a super-register
containing requested physical register. In case if a sub-register
if being read that is also a use of a super-reg, so added the check.
In particular MI->readsRegister() is broken because of the missing
check. The resulting check is essentially regsOverlap().
Differential Revision: https://reviews.llvm.org/D54128
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346686
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Jordan Rupprecht [Mon, 12 Nov 2018 18:02:38 +0000 (18:02 +0000)]
[llvm-readelf] Make llvm-readelf more compatible with GNU readelf.
Summary:
This change adds a bunch of options that GNU readelf supports. There is one breaking change when invoked as `llvm-readobj`, and three breaking changes when invoked as `llvm-readelf`:
- Add --all (implies --file-header, --program-headers, etc.)
- [Breaking] -a is --all instead of --arm-attributes
- Add --file-header as an alias for --file-headers
- Replace --sections with --sections-headers, keeping --sections as an alias for it
- Add --relocs as an alias for --relocations
- Add --dynamic as an alias for --dynamic-table
- Add --segments as an alias for --program-headers
- Add --section-groups as an alias for --elf-section-groups
- Add --dyn-syms as an alias for --dyn-symbols
- Add --syms as an alias for --symbols
- Add --histogram as an alias for --elf-hash-histogram
- [Breaking] When invoked as `llvm-readelf`, -s is --symbols instead of --sections
- [Breaking] When invoked as `llvm-readelf`, -t is no longer an alias for --symbols
Reviewers: MaskRay, phosek, mcgrathr, jhenderson
Reviewed By: MaskRay, jhenderson
Subscribers: sbc100, aheejin, edd, jhenderson, silvas, echristo, compnerd, kristina, javed.absar, kristof.beyls, llvm-commits, Bigcheese
Differential Revision: https://reviews.llvm.org/D54124
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346685
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Simon Pilgrim [Mon, 12 Nov 2018 17:56:59 +0000 (17:56 +0000)]
[CostModel][X86] Add SHLD/SHRD scalar funnel shift costs
The costs match the typical reg-reg cases - the RMW case can be a lot slower but we don't model that at this level
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346683
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