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9 years agodrm/i915: Add ioctl to set per-context parameters
Chris Wilson [Wed, 24 Dec 2014 16:13:40 +0000 (08:13 -0800)]
drm/i915: Add ioctl to set per-context parameters

Sometimes we wish to tweak how an individual context behaves. Since we
always create a context for every filp, this means that individual
processes can fine tune their behaviour even if they do not explicitly
create a context.

The first example parameter here is to enable multi-process GPU testing,
but the interface should be able to cope with passing arbitrarily complex
parameters.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Testcase: igt/gem_reset_stats/ban-period-*
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Push vblank enable/disable past encoder->enable/disable
Daniel Vetter [Wed, 7 Jan 2015 12:54:39 +0000 (13:54 +0100)]
drm/i915: Push vblank enable/disable past encoder->enable/disable

It is platform/output depenedent when exactly the pipe will start
running. Sometimes we just need the (cpu) pipe enabled, in other cases
the pch transcoder is enough and in yet other cases the (DP) port is
sending the frame start signal.

In a perfect world we'd put the drm_crtc_vblank_on call exactly where
the pipe starts running, but due to cloning and similar things this
will get messy. And the current approach of picking the most
conservative place for all combinations also doesn't work since that
results in legit vblank waits (in encoder->enable hooks, e.g. the 2
vblank waits for sdvo) failing.

Completely going back to the old world before

commit 51e31d49c89055299e34b8f44d13f70e19aaaad1
Author: Daniel Vetter <daniel.vetter@ffwll.ch>
Date:   Mon Sep 15 12:36:02 2014 +0200

    drm/i915: Use generic vblank wait

isn't great either since screaming when the vblank wait work because
the pipe is off is kinda nice.

Pick a compromise and move the drm_crtc_vblank_on right before the
encoder->enable call. This is a lie on some outputs/platforms, but
after the ->enable callback the pipe is guaranteed to run everywhere.
So not that bad really. Suggested by Ville.

v2: Same treatment for drm_crtc_vblank_off and encoder->disable: I've
missed the ibx pipe B select w/a, which also has a vblank wait in the
disable function (while the pipe is obviously still running).

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
9 years agodrm/i915: Move the ban period onto the context
Chris Wilson [Wed, 24 Dec 2014 16:13:39 +0000 (08:13 -0800)]
drm/i915: Move the ban period onto the context

This will allow us to set per-file, or even per-context, periods in the
future.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agoRevert "drm/i915: Parsing LFP brightness control from VBT"
Rodrigo Vivi [Tue, 6 Jan 2015 19:48:15 +0000 (14:48 -0500)]
Revert "drm/i915: Parsing LFP brightness control from VBT"

This reverts commit 371abae844ede392066bfc21202b2e40f4a654d1.

This data seems unreliable and causing many issues and blocking other
teams and feature implementation. Safest way is to revert that for now.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88081
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88039
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=87671
Cc: Vandana Kannan <vandana.kannan@intel.com>
Cc: Deepak M <m.deepak@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ben Widawsky <ben@bwidawsk.net>
Cc: Kristian Høgsberg <hoegsberg@gmail.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Support creation of unbound wc user mappings for objects
Akash Goel [Fri, 2 Jan 2015 10:59:30 +0000 (16:29 +0530)]
drm/i915: Support creation of unbound wc user mappings for objects

This patch provides support to create write-combining virtual mappings of
GEM object. It intends to provide the same funtionality of 'mmap_gtt'
interface without the constraints and contention of a limited aperture
space, but requires clients handles the linear to tile conversion on their
own. This is for improving the CPU write operation performance, as with such
mapping, writes and reads are almost 50% faster than with mmap_gtt. Similar
to the GTT mmapping, unlike the regular CPU mmapping, it avoids the cache
flush after update from CPU side, when object is passed onto GPU.  This
type of mapping is specially useful in case of sub-region update,
i.e. when only a portion of the object is to be updated. Using a CPU mmap
in such cases would normally incur a clflush of the whole object, and
using a GTT mmapping would likely require eviction of an active object or
fence and thus stall. The write-combining CPU mmap avoids both.

To ensure the cache coherency, before using this mapping, the GTT domain
has been reused here. This provides the required cache flush if the object
is in CPU domain or synchronization against the concurrent rendering.
Although the access through an uncached mmap should automatically
invalidate the cache lines, this may not be true for non-temporal write
instructions and also not all pages of the object may be updated at any
given point of time through this mapping.  Having a call to get_pages in
set_to_gtt_domain function, as added in the earlier patch 'drm/i915:
Broaden application of set-domain(GTT)', would guarantee the clflush and
so there will be no cachelines holding the data for the object before it
is accessed through this map.

The drm_i915_gem_mmap structure (for the DRM_I915_GEM_MMAP_IOCTL) has been
extended with a new flags field (defaulting to 0 for existent users). In
order for userspace to detect the extended ioctl, a new parameter
I915_PARAM_MMAP_VERSION has been added for versioning the ioctl interface.

v2: Fix error handling, invalid flag detection, renaming (ickle)

v3: Rebase to latest drm-intel-nightly codebase

The new mmapping is exercised by igt/gem_mmap_wc,
igt/gem_concurrent_blit and igt/gem_gtt_speed.

Change-Id: Ie883942f9e689525f72fe9a8d3780c3a9faa769a
Signed-off-by: Akash Goel <akash.goel@intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Broaden application of set-domain(GTT)
Chris Wilson [Fri, 2 Jan 2015 10:59:29 +0000 (16:29 +0530)]
drm/i915: Broaden application of set-domain(GTT)

Previously, this was restricted to only operate on bound objects - to
make pointer access through the GTT to the object coherent with writes
to and from the GPU. A second usecase is drm_intel_bo_wait_rendering()
which at present does not function unless the object also happens to
be bound into the GGTT (on current systems that is becoming increasingly
rare, especially for the typical requests from mesa). A third usecase is
a future patch wishing to extend the coverage of the GTT domain to
include objects not bound into the GGTT but still in its coherent cache
domain. For the latter pair of requests, we need to operate on the
object regardless of its bind state.

v2: After discussion with Akash, we came to the conclusion that the
get-pages was required in order for accurate domain tracking in the
corner cases (like the shrinker) and also useful for ensuring memory
coherency with earlier cached CPU mmaps in case userspace uses exotic
cache bypass (non-temporal) instructions.

v3: Fix the inactive object check.

v4: Rebase to latest drm-intel-nightly codebase

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Akash Goel <akash.goel@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Add some extra guards in evict_vm
Ben Widawsky [Tue, 23 Dec 2014 17:16:04 +0000 (17:16 +0000)]
drm/i915: Add some extra guards in evict_vm

v2: Use WARN_ONs (Daniel)

Cc: Daniel Vetter <daniel@ffwll.ch>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Include i915_gem_evict.c kerneldoc into the drm docbook
Daniel Vetter [Mon, 5 Jan 2015 13:36:59 +0000 (14:36 +0100)]
drm/i915: Include i915_gem_evict.c kerneldoc into the drm docbook

I've written these long before we've had a reasonable docbook
structure, and naturally they've gone stale. Fix this up asap.

Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
9 years agodrm/i915: Make sample_c messages go faster on Haswell.
Kenneth Graunke [Thu, 1 Jan 2015 00:23:00 +0000 (16:23 -0800)]
drm/i915: Make sample_c messages go faster on Haswell.

Haswell significantly improved the performance of sampler_c messages,
but the optimization appears to be off by default.  Later platforms
remove this bit, and apparently always enable the optimization.

Improves performance in "Counter Strike: Global Offensive" by 18%
at default settings on Iris Pro.

This may break sampling of paletted formats (P8/A8P8/P8A8).  It's
unclear whether it affects sampling of paletted formats in general,
or just the sample_c message (which is never used).

While libva does have support for using paletted formats (primarily
for OSDs), that support appears to have been broken for at least a
year, so I couldn't observe a regression from this:

I tried to get libva-intel to use paletted formats, and observe a
regression...but the only thing I found that used it was mplayer's OSD
(on screen display).  Even without my patch, the colors were totally
wrong with that, and it's according to a few distro wikis, that's been
the case for over a year.

If libva's code for paletted formats /is/ broken, they could always
add code to disable this bit using the command validator when fixing
it.

Further investigation from Haihao shows that libva mplayer OSD seems
to work at least on his setup (still unclear what's wron with Ken's),
and that it's not affected by this patch. Quoting the discussion
between Haihao and Ken:

> > > If you use "-vo gl" or "-vo xv", the OSD is solid white text with a black
> > > border around it.  I presume that it's supposed to be white with vaapi as
> > > well, but I guess I'm not entirely sure.
> > >
> > > It's possible that the optimization doesn't affect the palette as long as
> > > you never use sample_c with the paletted textures.
> >
> > I verified the palette takes effect in the following way:
> >
> > 1. Only support P8A8 format in the driver
> >
> > 2. ran the above command and I saw white OSD text
> >
> > 3. Only support P4A4 format in the driver and don't use
> > 3DSTATE_SAMPLER_PALETTE_LOAD0 to load the value to the texture palette,
> > so the palette keeps unchanged.
> >
> > 4. ran the above command and I saw black OSD text.
> >
> > 5. Load the right value to the texture palette and ran the above command
> > again, I saw white OSD text.
> >
> > Hence I think sample_c with the paletted textures is used in the driver.
>
> That sounds like the palette is actually working, then.  Great :)
>
> I doubt that libva would use sample_c - sampling with a shadow comparison?
> It looks like it just uses sample and sample+killpix.

You are right, libva driver doesn't use sample_c message.

> I'm pretty sure the sample_c optimization just uses the palette memory as
> storage for some stuff, so it's quite possible it just works if you're
> only using sample and sample+killpix.

Thanks for the explanation, it makes sense to me.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
[danvet: Add wa name from Ville's review to the comment and copypaste
the explanation why we don't care about libva (already broken) from
Ken. Also add conclusion from libva devs that&why this is all fine.]
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: "Xiang, Haihao" <haihao.xiang@intel.com>
Cc: libva@lists.freedesktop.org
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Update DRIVER_DATE to 20141219
Daniel Vetter [Fri, 19 Dec 2014 15:21:42 +0000 (16:21 +0100)]
drm/i915: Update DRIVER_DATE to 20141219

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Hold runtime PM during plane commit
Matt Roper [Mon, 15 Dec 2014 18:11:53 +0000 (10:11 -0800)]
drm/i915: Hold runtime PM during plane commit

During plane operations, we read/write some registers that only operate
properly if we're not runtime suspended.  At the moment we're not
holding the runtime PM reference across the whole plane operation, so
there's a potential for problems.

This issue was already partially addressed by commit

        commit d6dd6843ff4a57c662dbc378b9f99a9c034b0956
        Author: Paulo Zanoni <paulo.r.zanoni@intel.com>
        Date:   Fri Aug 15 15:59:32 2014 -0300

            drm/i915: fix plane/cursor handling when runtime suspended

which took care of holding the runtime PM reference during the pin and
fence operations for plane updates.  However there are still a few
actual plane registers that we also need to hold the runtime PM
reference for.  Recent refactoring patches in preparation for atomic
have rearranged the code and made it increasingly likely that the
hardware will have time to suspend between the pin/fence operation and
the actual register writes. Examples of such registers are the stuff
touched by ivb_get_colorkey.

The solution here grabs the runtime PM reference around the 'commit'
operation for planes, which should cover all the relevant register
reads/writes.

Note that this has only been exposed with

commit 6beb8c23ebcc3d3287d8a247d11b73d7d0eaa475
Author: Matt Roper <matthew.d.roper@intel.com>
Date:   Mon Dec 1 15:40:14 2014 -0800

    drm/i915: Consolidate plane 'prepare' functions (v2)

so doesn't need to be ported to 3.19.

Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=87180
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Testcase: igt/pm-rpm/legacy-planes
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
[danvet: Augment commit message with information Paulo supplied.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Organize bind_vma funcs
Rodrigo Vivi [Wed, 3 Dec 2014 12:55:29 +0000 (04:55 -0800)]
drm/i915: Organize bind_vma funcs

Let's be optimistic that for future platforms this will remain the same
and reorg a bit.
This reorg in if blocks instead of switch make life easier for future
platform support addition.

Cc: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Organize INSTDONE report for future.
Rodrigo Vivi [Wed, 3 Dec 2014 12:55:28 +0000 (04:55 -0800)]
drm/i915: Organize INSTDONE report for future.

Let's be optimistic that for future platforms this will remain the same
and reorg a bit.
This reorg in if blocks instead of switch make life easier for future
platform support addition.

Cc: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Organize PDP regs report for future.
Rodrigo Vivi [Wed, 3 Dec 2014 12:55:27 +0000 (04:55 -0800)]
drm/i915: Organize PDP regs report for future.

Let's be optimistic that for future platforms this will remain the same
and reorg a bit.
This reorg in if blocks instead of switch make life easier for future
platform support addition.

Cc: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Organize PPGTT init
Rodrigo Vivi [Wed, 3 Dec 2014 12:55:26 +0000 (04:55 -0800)]
drm/i915: Organize PPGTT init

Let's be optimistic that for future platforms memory management doesn't change
that much and reuse gen8 function for PPGTT init.

Cc: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Organize Fence registers for future enablement.
Rodrigo Vivi [Thu, 4 Dec 2014 14:48:10 +0000 (06:48 -0800)]
drm/i915: Organize Fence registers for future enablement.

Let's be optimistic that for future platforms this will remain the same
and reorg a bit.
This reorg in if blocks instead of switch make life easier for future
platform support addition.

v2: Jani pointed out I was missing reg_830 for some gen3 platforms. So let's make
    this platforms subcases of Gen checks.

Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: tame the chattermouth (v2)
Rob Clark [Mon, 15 Dec 2014 18:56:32 +0000 (13:56 -0500)]
drm/i915: tame the chattermouth (v2)

Many distro's have mechanism in place to collect and automatically file
bugs for failed WARN()s.  And since i915 has a lot of hw state sanity
checks which result in WARN(), it generates quite a lot of noise which
is somewhat disconcerting to the end user.

Separate out the internal hw-is-in-the-state-I-expected checks into
I915_STATE_WARN()s and allow configuration via i915.verbose_checks module
param about whether this will generate a full blown stacktrace or just
DRM_ERROR().  The new moduleparam defaults to true, so by default there
is no change in behavior.  And even when disabled, you will still get
an error message logged.

v2: paint the macro names blue, clarify that the default behavior
    remains the same as before

Signed-off-by: Rob Clark <robdclark@gmail.com>
Acked-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Warn about missing context state workarounds only once
Michel Thierry [Wed, 26 Nov 2014 14:21:02 +0000 (14:21 +0000)]
drm/i915: Warn about missing context state workarounds only once

Otherwise, new platforms without workarounds will hit this warning for
every new context created.

Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Use true PPGTT in Gen8+ when execlists are enabled
Michel Thierry [Mon, 15 Dec 2014 14:58:00 +0000 (14:58 +0000)]
drm/i915: Use true PPGTT in Gen8+ when execlists are enabled

In Gen8+, full ppgtt needs execlist, otherwise the ctx switch can hang.

Also remove the current restriction, a user should be able to explicitly set
ppgtt=2.

Note, this patch considers that execlist support has been enabled by
default on Gen8.

v2: Remove non-default restriction and clarify commit message (Daniel)

Cc: Daniel Vetter <daniel@ffwll.ch>
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
[danvet: s/comment/commit message/ in the commit message since that's
what Michel meant as per our irc discussion.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Skip gunit save/restore for cherryview
Deepak S [Fri, 12 Dec 2014 08:48:16 +0000 (14:18 +0530)]
drm/i915: Skip gunit save/restore for cherryview

With cherryview onwards, Gunit hardware itself save and restore all the
Gunit registers. Skipping the "vlv_save_gunit_s0ix_state" &
"vlv_restore_gunit_s0ix_state" for cherryview in S3/S0ix sequence.

Signed-off-by: Deepak S <deepak.s@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915/chv: Use timeout mode for RC6 on chv
Deepak S [Sat, 13 Dec 2014 06:13:27 +0000 (11:43 +0530)]
drm/i915/chv: Use timeout mode for RC6 on chv

Higher RC6 residency is observed using timeout mode
instead of EI mode. It's Recommended to use TO Method for RC6.

v2: Add comment about timeout threshold. (Tom)

Signed-off-by: Deepak S <deepak.s@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Add GPGPU_THREADS_DISPATCHED to the register whitelist
Jordan Justen [Thu, 11 Dec 2014 21:28:09 +0000 (13:28 -0800)]
drm/i915: Add GPGPU_THREADS_DISPATCHED to the register whitelist

This will allow us to read the number of dispatched compute threads
for GL_ARB_pipeline_statistics_query.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Cc: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Tidy up execbuffer command parsing code
Brad Volkin [Thu, 11 Dec 2014 20:13:12 +0000 (12:13 -0800)]
drm/i915: Tidy up execbuffer command parsing code

Move it to a separate function since the main do_execbuffer function
already has so much going on.

v2:
- Move pin/unpin calls inside i915_parse_cmds() (Chris W, v4 7/7
  feedback)

Issue: VIZ-4719
Signed-off-by: Brad Volkin <bradley.d.volkin@intel.com>
Reviewed-By: Jon Bloomfield <jon.bloomfield@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Mark shadow batch buffers as purgeable
Brad Volkin [Thu, 11 Dec 2014 20:13:11 +0000 (12:13 -0800)]
drm/i915: Mark shadow batch buffers as purgeable

By adding a new exec_entry flag, we cleanly mark the shadow objects
as purgeable after they are on the active list.

v2:
- Move 'shadow_batch_obj->madv = I915_MADV_WILLNEED' inside _get
  fnc (danvet, from v4 6/7 feedback)

v3:
- Remove duplicate 'madv = I915_MADV_WILLNEED' (danvet, from v6 4/5)

Issue: VIZ-4719
Signed-off-by: Brad Volkin <bradley.d.volkin@intel.com>
Reviewed-By: Jon Bloomfield <jon.bloomfield@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Use batch length instead of object size in command parser
Brad Volkin [Thu, 11 Dec 2014 20:13:10 +0000 (12:13 -0800)]
drm/i915: Use batch length instead of object size in command parser

Previously we couldn't trust the user-supplied batch length because
it came directly from userspace (i.e. untrusted code). It would have
affected what commands software parsed without regard to what hardware
would actually execute, leaving a potential hole.

With the parser now copying the user supplied batch buffer and writing
MI_NOP commands to any space after the copied region, we can safely use
the batch length input. This should be a performance win as the actual
batch length is frequently much smaller than the allocated object size.

v2: Fix handling of non-zero batch_start_offset

Issue: VIZ-4719
Signed-off-by: Brad Volkin <bradley.d.volkin@intel.com>
Reviewed-By: Jon Bloomfield <jon.bloomfield@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Use batch pools with the command parser
Brad Volkin [Thu, 11 Dec 2014 20:13:09 +0000 (12:13 -0800)]
drm/i915: Use batch pools with the command parser

This patch sets up all of the tracking and copying necessary to
use batch pools with the command parser and dispatches the copied
(shadow) batch to the hardware.

After this patch, the parser is in 'enabling' mode.

Note that performance takes a hit from the copy in some cases
and will likely need some work. At a rough pass, the memcpy
appears to be the bottleneck. Without having done a deeper
analysis, two ideas that come to mind are:
1) Copy sections of the batch at a time, as they are reached
   by parsing. Might improve cache locality.
2) Copy only up to the userspace-supplied batch length and
   memset the rest of the buffer. Reduces the number of reads.

v2:
- Remove setting the capacity of the pool
- One global pool instead of per-ring pools
- Replace batch_obj with shadow_batch_obj and hook into eb->vmas
- Memset any space in the shadow batch beyond what gets copied
- Rebased on execlist prep refactoring

v3:
- Rebase on chained batch handling
- Squash in setting the secure dispatch flag
- Add a note about the interaction w/secure dispatch pinning
- Check for request->batch_obj == NULL in i915_gem_free_request

v4:
- Fix read domains for shadow_batch_obj
- Remove the set_to_gtt_domain call from i915_parse_cmds
- ggtt_pin/unpin in the parser block to simplify error handling
- Check USES_FULL_PPGTT before setting DISPATCH_SECURE flag
- Remove i915_gem_batch_pool_put calls

v5:
- Move 'pending_read_domains |= I915_GEM_DOMAIN_COMMAND' after
  the parser (danvet, from v4 0/7 feedback)

Issue: VIZ-4719
Signed-off-by: Brad Volkin <bradley.d.volkin@intel.com>
Reviewed-By: Jon Bloomfield <jon.bloomfield@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Implement a framework for batch buffer pools
Brad Volkin [Thu, 11 Dec 2014 20:13:08 +0000 (12:13 -0800)]
drm/i915: Implement a framework for batch buffer pools

This adds a small module for managing a pool of batch buffers.
The only current use case is for the command parser, as described
in the kerneldoc in the patch. The code is simple, but separating
it out makes it easier to change the underlying algorithms and to
extend to future use cases should they arise.

The interface is simple: init to create an empty pool, fini to
clean it up, get to obtain a new buffer. Note that all buffers are
expected to be inactive before cleaning up the pool.

Locking is currently based on the caller holding the struct_mutex.
We already do that in the places where we will use the batch pool
for the command parser.

v2:
- s/BUG_ON/WARN_ON/ for locking assertions
- Remove the cap on pool size
- Switch from alloc/free to init/fini

v3:
- Idiomatic looping structure in _fini
- Correct handling of purged objects
- Don't return a buffer that's too much larger than needed

v4:
- Rebased to latest -nightly

v5:
- Remove _put() function and clean up comments to match

v6:
- Move purged check inside the loop (danvet, from v4 1/7 feedback)

v7:
- Use single list instead of two. (Chris W)
- s/active_list/cache_list
- Squashed in debug patches (Chris W)
  drm/i915: Add a batch pool debugfs file

  It provides some useful information about the buffers in
  the global command parser batch pool.

  v2: rebase on global pool instead of per-ring pools
  v3: rebase

  drm/i915: Add batch pool details to i915_gem_objects debugfs

  To better account for the potentially large memory consumption
  of the batch pool.

v8:
- Keep cache in LRU order (danvet, from v6 1/5 feedback)

Issue: VIZ-4719
Signed-off-by: Brad Volkin <bradley.d.volkin@intel.com>
Reviewed-By: Jon Bloomfield <jon.bloomfield@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: fix use after free during eDP encoder destroying
Imre Deak [Fri, 12 Dec 2014 15:57:38 +0000 (17:57 +0200)]
drm/i915: fix use after free during eDP encoder destroying

After

commit a18c0af171bfb875012da26f23df051004726973
uthor: Thierry Reding <treding@nvidia.com>
Date:   Wed Dec 10 11:38:49 2014 +0100

    drm: Zero out DRM object memory upon cleanup

we will use the eDP encoder during destroying it. Fix this by calling
drm_encoder_cleanup() at a point when the encoder is not used any more.
This caused a NULL pointer dereference in pps_lock(), I can't see that
it caused any other problem.

All the other encoders seem to call drm_encoder_cleanup() at a safe
place.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915/skl: Skylake also supports DP MST
Damien Lespiau [Fri, 12 Dec 2014 14:26:58 +0000 (14:26 +0000)]
drm/i915/skl: Skylake also supports DP MST

I've checked that TRANS_DDI_MODE, DP_TP_CTL MST bits are identical to
HSW/BDW on SKL, as well as the long vs short HPD bits. So we have a good
chance to be working as well as prevous platforms.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Consolidate DDI clock reading out in a single function
Damien Lespiau [Fri, 12 Dec 2014 14:26:57 +0000 (14:26 +0000)]
drm/i915: Consolidate DDI clock reading out in a single function

2 pieces of code need to read out the DDI clock: the DDI encoder and the
MST encoder .get_config() vfuncs.

Until now the SKL read out code was only in the former, so let's move
the pre and post SKL logic in intel_ddi_clock_get() and this this one
everywhere.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Parsing LFP brightness control from VBT
Deepak M [Mon, 15 Dec 2014 10:28:21 +0000 (15:58 +0530)]
drm/i915: Parsing LFP brightness control from VBT

LFP brighness control from the VBT block 43 indicates which
controller is used for brightness.
LFP1 brightness control method:
Bit 7-4 = This field controller number of the brightnes controller.
0 = Controller 0
1 = Controller 1
2 = Controller 2
3 = Controller 3
Others = Reserved
Bits 3-0 = This field specifies the brightness control pin to be used on the
platform.
0 = PMIC pin is used for brightness control
1 = LPSS PWM is used for brightness control
2 = Display DDI is used for brightness control
3 = CABC method to control brightness
Others = Reserved

Adding the above fields in dev_priv->vbt and corresponding changes in
parse_backlight()

v2: Jani's review comments addressed
- Move PWM definitions to intel_bios.h
- Moving vbt_version to intel_vbt_data
- Rename brightness to bl_ctrl_data
- Logging just control_pin instead of string
- Avoid adding vbt_version in dev_priv
- Since only DDI option is available as of now, let control pin DDI
affect dev_priv->vbt.backlight.present

v3: Jani's review comments addressed
- Drop control_pin
- Use bdb->version
- set controller to 0 instead of using control pin define
- check controller bounds
- remove superfluous changes in intel_parse_bios

Signed-off-by: Deepak M <m.deepak@intel.com>
Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915/skl: Correcting the flushing of pipe
Sonika Jindal [Thu, 11 Dec 2014 12:28:15 +0000 (17:58 +0530)]
drm/i915/skl: Correcting the flushing of pipe

We were incorreectly bypassing the flush everytime which led to fifo
underrun when more than one plane is enabled.

Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Satheeshakrishna M<satheeshakrishna.m@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915/bdw: Enable execlists by default where supported
Thomas Daniel [Thu, 11 Dec 2014 12:48:35 +0000 (12:48 +0000)]
drm/i915/bdw: Enable execlists by default where supported

Execlist support in the i915 driver is now considered good enough for the
feature to be enabled by default on Gen8 and later and routinely tested.
Adjusted i915 parameters structure initialization to reflect this and updated
the comment in intel_sanitize_enable_execlists().

There's still work to do before we can let the wider massive onto it,
but there's still time left before the 3.20 cutoff.

v2: Update the MODULE_PARM_DESC too.

Issue: VIZ-2020
Signed-off-by: Thomas Daniel <thomas.daniel@intel.com>
[danvet: Add note that there's still some work left to do.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915/skl: Correctly updating sprite wm parameter
Sonika Jindal [Tue, 9 Dec 2014 05:29:15 +0000 (10:59 +0530)]
drm/i915/skl: Correctly updating sprite wm parameter

The pipe wm parameters is not correctly updated with sprite parameters
because it copies them for each plane from plane_list to the sprite
offset in pipe wm parameters. Since plane_list also contains primary and
cursor planes, we end up updating wrong params for sprites.

Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Documentation for multiple GGTT views
Tvrtko Ursulin [Wed, 10 Dec 2014 17:27:59 +0000 (17:27 +0000)]
drm/i915: Documentation for multiple GGTT views

A short section describing background, implementation and intended usage.

v2:
    * Align section name between template and DOC comment. (Michel Thierry)

For: VIZ-4544
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Michel Thierry <michel.thierry@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Infrastructure for supporting different GGTT views per object
Tvrtko Ursulin [Wed, 10 Dec 2014 17:27:58 +0000 (17:27 +0000)]
drm/i915: Infrastructure for supporting different GGTT views per object

Things like reliable GGTT mappings and mirrored 2d-on-3d display will need
to map objects into the same address space multiple times.

Added a GGTT view concept and linked it with the VMA to distinguish between
multiple instances per address space.

New objects and GEM functions which do not take this new view as a parameter
assume the default of zero (I915_GGTT_VIEW_NORMAL) which preserves the
previous behaviour.

This now means that objects can have multiple VMA entries so the code which
assumed there will only be one also had to be modified.

Alternative GGTT views are supposed to borrow DMA addresses from obj->pages
which is DMA mapped on first VMA instantiation and unmapped on the last one
going away.

v2:
    * Removed per view special casing in i915_gem_ggtt_prepare /
      finish_object in favour of creating and destroying DMA mappings
      on first VMA instantiation and last VMA destruction. (Daniel Vetter)
    * Simplified i915_vma_unbind which does not need to count the GGTT views.
      (Daniel Vetter)
    * Also moved obj->map_and_fenceable reset under the same check.
    * Checkpatch cleanups.

v3:
    * Only retire objects once the last VMA is unbound.

v4:
    * Keep scatter-gather table for alternative views persistent for the
      lifetime of the VMA.
    * Propagate binding errors to callers and handle appropriately.

v5:
    * Explicitly look for normal GGTT view in i915_gem_obj_bound to align
      usage in i915_gem_object_ggtt_unpin. (Michel Thierry)
    * Change to single if statement in i915_gem_obj_to_ggtt. (Michel Thierry)
    * Removed stray semi-colon in i915_gem_object_set_cache_level.

For: VIZ-4544
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Michel Thierry <michel.thierry@intel.com>
[danvet: Drop hunk from i915_gem_shrink since it's just prettification
but upsets a __must_check warning.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Forcewake Register Range changes for CHV
Deepak S [Thu, 11 Dec 2014 16:12:49 +0000 (21:42 +0530)]
drm/i915: Forcewake Register Range changes for CHV

According to updated BSpec, Render/Common/media Wells register range changed.
Updating the same to match the spec and avoid extra forcewake for none
forcewake range.

v2: Update media forcewake range (Ville)

Signed-off-by: Deepak S <deepak.s@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Changes related to the sequence port no for
Gaurav K Singh [Wed, 10 Dec 2014 16:37:40 +0000 (22:07 +0530)]
drm/i915: Changes related to the sequence port no for

From now on for both DSI Ports A & C, the seq_port value has been
set to 0. seq_port value is parsed from Sequence block#53 of VBT.
So, for packets that needs to be read/write for DSI single link on
Port A and Port C will now be based on the DVO port from VBT block 2,
instead of seq_port.

Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Use BUILD_BUG if possible in the i915 WARN_ON
Daniel Vetter [Mon, 8 Dec 2014 15:40:10 +0000 (16:40 +0100)]
drm/i915: Use BUILD_BUG if possible in the i915 WARN_ON

Faster feedback to errors is always better. This is inspired by the
addition to WARN_ONs to mask/enable helpers for registers to make sure
callers have the arguments ordered correctly: Pretty much always the
arguments are static.

We use WARN_ON(1) a lot in default switch statements though where we
should always handle all cases. So add a new macro specifically for
that.

The idea to use __builtin_constant_p is from Chris Wilson.

v2: Use the ({}) gcc-ism to avoid the static inline, suggested by
Dave. My first attempt used __cond as the temp var, which is the same
used by BUILD_BUG_ON, but with inverted sense. Hilarity ensued, so
sprinkle i915 into the name.

Also use a temporary variable to only evaluate the condition once,
suggested by Damien.

v3: It's crazy but apparently 32bit gcc can't compile out the
BUILD_BUG_ON in a lot of cases and just falls over. I have no idea
why, but until clue grows just disable this nifty idea on 32bit
builds. Reported by 0-day builder.

v4: Got it all wrong, apparently its the gcc version. We need 4.9+.
Now reported by Imre.

v5: Chris suggested to add the case to MISSING_CASE for speedier
debug.

v6: Even some gcc 4.9 versions don't see through the maze, so give up
for now. Keep the skeleton and MISSING_CASE stuff though.

Cc: Imre Deak <imre.deak@intel.com>
Cc: Damien Lespiau <damien.lespiau@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Dave Gordon <david.s.gordon@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
9 years agodrm/i915: Name the lrc irq handler correctly
Daniel Vetter [Wed, 10 Dec 2014 16:41:43 +0000 (17:41 +0100)]
drm/i915: Name the lrc irq handler correctly

We consistently use the _irq_handler postfix for functions called in
hardirq context. Especially when it's a non-static function hardirq is
a crazy enough calling context to warrant this level of ocd. So rename
it.

Cc: Thomas Daniel <thomas.daniel@intel.com>
Reviewed-by: Thomas Daniel <thomas.daniel@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
9 years agodrm/i915/bdw: Add WaForceEnableNonCoherent label
Michel Thierry [Wed, 10 Dec 2014 09:43:37 +0000 (09:43 +0000)]
drm/i915/bdw: Add WaForceEnableNonCoherent label

We already implement this workaround, but it was missing its name.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Protect against leaks in pipe_crc_set_source
Daniel Vetter [Wed, 10 Dec 2014 10:00:29 +0000 (11:00 +0100)]
drm/i915: Protect against leaks in pipe_crc_set_source

Stupid userspace (there is no evil userspace in debugfs by assumption)
might provoke a leak since we allocate the new array without holding
any locks. Drop in an unconditional kfree to deal with this - kfree
can handle NULL.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
9 years agodrm/i915: Make i915_pipe_crc_read() oops proof
Ville Syrjälä [Tue, 9 Dec 2014 19:28:32 +0000 (21:28 +0200)]
drm/i915: Make i915_pipe_crc_read() oops proof

Currently i915_pipe_crc_read() will drop pipe_crc->lock for the entire
duration of the copy_to_user() loop, which means it'll access
pipe_crc->entries without any protection. If another thread sneaks in
and frees pipe_crc->entries the code will oops.

Reorganize the code to hold the lock around everything except
copy_to_user(). After the copy the lock is reacquired and the the number
of available entries is rechecked.

Since this is a debug feature simplify the error handling a bit by
consuming the crc entry even if copy_to_user() would fail.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Allocate the pipe_crc->entires with kcalloc()
Ville Syrjälä [Tue, 9 Dec 2014 19:28:31 +0000 (21:28 +0200)]
drm/i915: Allocate the pipe_crc->entires with kcalloc()

pipe_crc->entries[] is an array so allocate with kcalloc() instead of
kzalloc().

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Protect pipe_crc->entries update
Ville Syrjälä [Tue, 9 Dec 2014 19:28:30 +0000 (21:28 +0200)]
drm/i915: Protect pipe_crc->entries update

Set the pipe_crc->entries pointer while holding the relevant spinlock.
Doesn't matter too much since a spurious pipe crc interrupt would then
just update one entry but later that entry would get cleared when head
and tail are both set to 0. But being a bit more paranoid doesn't hurt.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Fix CRC support for DP port D on CHV
Ville Syrjälä [Tue, 9 Dec 2014 19:28:29 +0000 (21:28 +0200)]
drm/i915: Fix CRC support for DP port D on CHV

Add the missing CRC control register value for DP port D on CHV.
Untested as I don't have a CHV machine with DP on port D.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
[danvet: Add a check to only allow DP D on chv, not vlv.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Engage the DP scramble reset for pipe C on CHV
Ville Syrjälä [Tue, 9 Dec 2014 19:28:28 +0000 (21:28 +0200)]
drm/i915: Engage the DP scramble reset for pipe C on CHV

To get stable CRCs from the DP CRC source we need to reset the
scrambler for each frame. Enable the reset feature when grabbing
CRCs for pipe C on CHV. Pipes A and B were already covered due
sharing the code with VLV.

We can safely extend PIPE_SCRAMBLE_RESET_MASK to deal with CHV since
the extra bit was MBZ on the older platforms.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Add headers to the various render state
Damien Lespiau [Tue, 9 Dec 2014 17:23:22 +0000 (17:23 +0000)]
drm/i915: Add headers to the various render state

intel-gpu-tools now generates the render state with license headers and
the version of i-g-t that generated the files.

A similar patch was previously sent but wasn't actually generated with
the make target so was lacking the i-g-t revision. So here another
version before we totally forget about this.

Cc: Armin Reese <armin.c.reese@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Introduce FBC DocBook.
Rodrigo Vivi [Mon, 8 Dec 2014 14:46:31 +0000 (06:46 -0800)]
drm/i915: Introduce FBC DocBook.

No functional changes.

v2 (Paulo): Rebase.
v3: Accept Daniel's suggestions:
    * remove unclear and duplicated explanation.
    * remove marketing like doc and replace by a simple one.
    * remove bdw_fbc_sw_flush documentation.

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Software workaround for getting the HW status of DSI Port C on BYT
Gaurav K Singh [Tue, 9 Dec 2014 05:29:20 +0000 (10:59 +0530)]
drm/i915: Software workaround for getting the HW status of DSI Port C on BYT

Due to hardware limitations on BYT, MIPI Port C DPI Enable bit
does not get set. To check whether DSI Port C was enabled in BIOS,
check the Pipe B enable bit for DSI Port C. In hardware, DSI Port C
is linked with Pipe B.

v2: Addressed review comments of Jani, Nikula
    - Used platform checks for this software workaround for BYT

Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Enable MIPI PHY transparent latch for DSI Port C
Gaurav K Singh [Sun, 7 Dec 2014 10:43:54 +0000 (16:13 +0530)]
drm/i915: Enable MIPI PHY transparent latch for DSI Port C

Common bit to be used for both DSI Port A & DSI Port C.

Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Use DSI Pll1 for enabling MIPI DSI on Port C
Gaurav K Singh [Tue, 9 Dec 2014 05:27:00 +0000 (10:57 +0530)]
drm/i915: Use DSI Pll1 for enabling MIPI DSI on Port C

DSI Pll1 is used for enabling DSI on Port C.

v2: Addressed review comments of Jani
    - Used & operator instead of == for intel_dsi->ports

Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Add MI_SET_APPID cmd to cmd parser tables
Michael H. Nguyen [Fri, 21 Nov 2014 17:35:36 +0000 (09:35 -0800)]
drm/i915: Add MI_SET_APPID cmd to cmd parser tables

Was missing.

Issue: VIZ-4701
Signed-off-by: Michael H. Nguyen <michael.h.nguyen@intel.com>
Reviewed-by: Jon Bloomfield <jon.bloomfield@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Move FBC stuff to intel_fbc.c
Rodrigo Vivi [Mon, 8 Dec 2014 16:09:10 +0000 (14:09 -0200)]
drm/i915: Move FBC stuff to intel_fbc.c

No functional changes. This is just the begin of a FBC rework.

v2 (Paulo):
  - Revert intel_fbc_init() changed parameter.
  - Revert set_no_fbc_reason() rename.
  - Rebase.

Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Check mask/bit helper functions
Daniel Vetter [Mon, 8 Dec 2014 15:30:00 +0000 (16:30 +0100)]
drm/i915: Check mask/bit helper functions

After a bit of irc discussion we've concluded that it would be prudent
to check that callers use the mask/enable paramters correctly. So add
a WARN_ON.

Spurred by Damien's bugfix which added _MASKED_FIELD.

v2: We use WARN_ON(1) a lot to catch default cases in switch blocks
which should always be extended. So this doesn't work really. Dunno
why gcc only started complaining when I've moved the WARN out of the
static inline helper to address a feedback from Jani.

Cc: Damien Lespiau <damien.lespiau@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
9 years agodrm/i915: Move golden context init into ->init_context
Daniel Vetter [Tue, 2 Dec 2014 15:19:07 +0000 (16:19 +0100)]
drm/i915: Move golden context init into ->init_context

Similar to a patch from Thomas Daniel for lrc contexts. This keeps
both sides somewhat in sync and should make Dave Gordon happy.

Note that both the wa and the golden context init code suffer a bit
from an inssuficient split into driver load and hw init code. Which
means we have a bunch of tests all over the place to check whether the
one-time initialization has been done already or not.

All that one-tim code should be moved into the one-time ring setup
code, but that's work for later.

Cc: Dave Gordon <david.s.gordon@intel.com>
Cc: Thomas Daniel <thomas.daniel@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
Reviewed-by: Dave Gordon <david.s.gordon@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agogpu: drm: i915: intel_display.c: Remove unused function
Rickard Strandqvist [Sun, 7 Dec 2014 18:29:17 +0000 (19:29 +0100)]
gpu: drm: i915: intel_display.c: Remove unused function

Remove the function intel_output_name() that is not used anywhere.

This was partially found by using a static code analysis program called cppcheck.

Signed-off-by: Rickard Strandqvist <rickard_strandqvist@spectrumdigital.se>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Additional request structure tracing
John Harrison [Fri, 5 Dec 2014 13:49:36 +0000 (13:49 +0000)]
drm/i915: Additional request structure tracing

Added the request structure's 'uniq' identifier to the trace information. Also
renamed the '_complete' trace event to '_notify' as it actually happens in the
IRQ 'notify_ring()' function. The intention is to add a new '_complete' trace
event which occurs when a request structure is actually marked as complete.
However, at the moment the completion status is re-tested every time the query
is made so there isn't a completion event as such.

v2: New patch added to series.

v3: Rebased to remove completion caching as that is apparently contentious.

Change-Id: Ic9bcde67d175c6c03b96217cdcb6e4cc4aa45d67
For: VIZ-4377
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Reviewed-by: Thomas Daniel <Thomas.Daniel@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Add unique id to the request structure for debugging
John Harrison [Fri, 5 Dec 2014 13:49:35 +0000 (13:49 +0000)]
drm/i915: Add unique id to the request structure for debugging

For debugging purposes, it is useful to be able to uniquely identify a given
request structure as it works its way through the system. This becomes
especially tricky once the seqno value is lazily allocated as then the request
has nothing but its pointer to identify it for much of its life.

Change-Id: Ie76b2268b940467f4cdf5a4ba6f5a54cbb96445d
For: VIZ-4377
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Reviewed-by: Thomas Daniel <Thomas.Daniel@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Zero fill the request structure
John Harrison [Fri, 5 Dec 2014 13:49:34 +0000 (13:49 +0000)]
drm/i915: Zero fill the request structure

There is a general theory that kzmalloc is better/safer than kmalloc, especially
for interesting data structures. This change updates the request structure
allocation to be zero filled.

This also fixes crashes in the reset code. Quoting Mika's patch:

"Clean the request structure on alloc. Otherwise we might end up
referencing uninitialized fields.  This is apparent when we try to
cleanup the preallocated request on ring reset, before any request has
been submitted to the ring.  The request->ctx is foobar and we end up
freeing the foobarness."

Note that this fixes a regression introduced in

commit 9eba5d4a1d79d5094321469479b4dbe418f60110
Author: John Harrison <John.C.Harrison@Intel.com>
Date:   Mon Nov 24 18:49:23 2014 +0000

    drm/i915: Ensure OLS & PLR are always in sync

References: https://bugs.freedesktop.org/show_bug.cgi?id=86959
References: https://bugs.freedesktop.org/show_bug.cgi?id=86962
References: https://bugs.freedesktop.org/show_bug.cgi?id=86992
Change-Id: I68715ef758025fab8db763941ef63bf60d7031e2
For: VIZ-4377
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Reviewed-by: Thomas Daniel <Thomas.Daniel@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Fix up seqno -> request merge issues
John Harrison [Fri, 5 Dec 2014 13:49:33 +0000 (13:49 +0000)]
drm/i915: Fix up seqno -> request merge issues

The display related patches earlier in this series were edited during merge to
improve the request unreferencing. Specifically, the need for de-referencing at
interrupt time was removed. However, the resulting code did a 'deref(req) ; req
= NULL' sequence rather than using the 'req_assign(req, NULL)' wrapper. The two
are functionally equivalent, but using the wrapper is more consistent with all
the other places where requests are assigned.

Note that the whole point of the wrapper is that using it everywhere that
request pointers are assigned means that the reference counting is done
automatically and can't be accidentally forgotten about. Plus it allows simpler
future maintainance if the reference counting mechanisms ever need to change.

For: VIZ-4377
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Make all plane disables use 'update_plane' (v5)
Matt Roper [Thu, 4 Dec 2014 18:27:42 +0000 (10:27 -0800)]
drm/i915: Make all plane disables use 'update_plane' (v5)

If we extend the commit_plane handlers for each plane type to be able to
handle fb=0, then we can easily implement plane disable via the
update_plane handler.  The cursor plane already works this way, and this
is the direction we need to go to integrate with the atomic plane
handler.  We can now kill off the type-specific disable functions, as
well as the redundant intel_plane_disable() (not to be confused with
intel_disable_plane()).

Note that prepare_plane_fb() only gets called as part of update_plane
when fb!=NULL (by design, to match the semantics of the atomic plane
helpers); this means that our commit_plane handlers need to handle the
frontbuffer tracking for the disable case, even though they don't handle
it for normal updates.

v2:
 - Change BUG_ON to WARN_ON (Ander/Daniel)

v3:
 - Drop unnecessary plane->crtc check since a previous patch to plane
   update ensures that plane->crtc will always be non-NULL, even for
   disable calls that might pass NULL from userspace.  (Ander)
 - Drop a s/crtc/plane->crtc/ hunk that was unnecessary.  (Ander)

v4:
 - Fix missing whitespace (Ander)

v5:
 - Use state's crtc rather than plane's crtc in
   intel_check_primary_plane().  plane->crtc could be NULL, but we've
   already fixed up state->crtc to ensure it's non-NULL (even if
   userspace passed it as NULL during a disable call).  (Ander)

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Ensure state->crtc is non-NULL for plane updates
Matt Roper [Mon, 1 Dec 2014 23:40:17 +0000 (15:40 -0800)]
drm/i915: Ensure state->crtc is non-NULL for plane updates

When disabling a plane, it is legal to pass crtc = NULL.  Since planes
on Intel hardware are tied to a fixed CRTC, go ahead and set state->crtc
to the appropriate crtc in cases where it is passed to us as NULL.

In a future patch, we will start using the update handler for plane
disables, so this will help ensure we always have a non-NULL crtc
pointer to work with.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Consolidate top-level .update_plane() handlers
Matt Roper [Mon, 1 Dec 2014 23:40:16 +0000 (15:40 -0800)]
drm/i915: Consolidate top-level .update_plane() handlers

Our .update_plane() handlers do the same check/prepare/commit/cleanup
steps regardless of plane type.  Consolidate them all into a single
function that calls check/commit through a vtable.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Consolidate plane 'cleanup' operations (v3)
Matt Roper [Tue, 2 Dec 2014 15:45:25 +0000 (07:45 -0800)]
drm/i915: Consolidate plane 'cleanup' operations (v3)

All plane update functions need to unpin the old framebuffer when
flipping to a new one.  Pull this logic into a separate function to ease
the integration with atomic plane helpers.

v2: Don't wait for vblank if we don't have an old fb to cleanup (Ander)

v3: Really don't wait for vblank if we don't have an old fb to cleanup.
    Previous version only handled this for primary planes; we need the
    same change on cursors/sprites too!  (Ander)

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Consolidate plane 'prepare' functions (v2)
Matt Roper [Mon, 1 Dec 2014 23:40:14 +0000 (15:40 -0800)]
drm/i915: Consolidate plane 'prepare' functions (v2)

The 'prepare' step for all types of planes are pretty similar;
consolidate the three 'prepare' functions into a single function.  This
paves the way for future integration with the atomic plane handlers.

Note that we pull the 'wait for pending flips' functionality out of the
primary plane's prepare step and place it directly in the 'setplane'
code.  When we move to the atomic plane handlers, this code will be in
the 'atomic begin' step.

v2: Update GEM fb tracking for physical cursors also (Ander)

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Make intel_plane_state subclass drm_plane_state
Matt Roper [Mon, 1 Dec 2014 23:40:13 +0000 (15:40 -0800)]
drm/i915: Make intel_plane_state subclass drm_plane_state

Reviewed-by: Bob Paauwe <bob.j.paauwe@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Introduce intel_prepare_cursor_plane() (v2)
Matt Roper [Mon, 1 Dec 2014 23:40:12 +0000 (15:40 -0800)]
drm/i915: Introduce intel_prepare_cursor_plane() (v2)

Primary and sprite planes have already been refactored to include a
'prepare' step which handles all the commit-time operations that could
fail (i.e., pinning buffers and such).  Refactor the cursor commit in a
similar manner.

For simplicity and consistency with other plane types, we also switch to
using intel_pin_and_fence_fb_obj() to perform our pinning for
non-physical cursors.  This will allow us to more easily migrate the
code into the atomic 'begin' handler in a plane-agnostic manner in a
future patchset.

v2:
 - Update GEM fb tracking for physical cursors too. (Ander)
 - Use intel_unpin_fb_obj() rather than
   i915_gem_object_unpin_from_display_plane() and do so while holding
   struct_mutex.  (Ander)
 - Update plane->fb in commit_cursor_plane.  This isn't really necessary
   since the DRM core does this for us in __setplane_internal(), but
   doing it in our driver once we know we're going to succeed helps
   avoid confusion. (Ander)

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: remove intel_pipe_set_base() (v4)
Gustavo Padovan [Mon, 1 Dec 2014 23:40:11 +0000 (15:40 -0800)]
drm/i915: remove intel_pipe_set_base() (v4)

After some refactor intel_primary_plane_setplane() does the same
as intel_pipe_set_base() so we can get rid of it and replace the calls
with intel_primary_plane_setplane().

v2: take Ville's comments:
- get the right arguments for update_plane()
- use drm_crtc_get_hv_timing()

v3 (by Matt):
 - Rebase to latest di-nightly codebase
 - Use primary->funcs->update_plane() in __intel_set_mode()
 - Use primary->funcs->disable_plane() in intel_crtc_disable()

v4 (by Matt):
 - Drop redundant calls to intel_crtc_wait_for_pending_flips() before
   calling update_plane() (Ville)

Signed-off-by: Gustavo Padovan <gustavo.padovan@collabora.co.uk>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Acked-and-mourned-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: remove intel_crtc_cursor_set_obj() (v5)
Gustavo Padovan [Mon, 1 Dec 2014 23:40:10 +0000 (15:40 -0800)]
drm/i915: remove intel_crtc_cursor_set_obj() (v5)

Merge it into the plane update_plane() callback and make other
users use the update_plane() functions instead.

The fb != crtc->cursor->fb was already inside intel_crtc_cursor_set_obj()
so we fold intel_crtc_cursor_set_obj() inside intel_commit_cursor_plane()
and merge both paths into one.

v5 (by Matt):
 - Rebase onto latest di-nightly codebase
 - Drop extra unreference call when we fail to pin (Ville)

Reviewed-by(v4): Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Gustavo Padovan <gustavo.padovan@collabora.co.uk>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm: add helper to get crtc timings (v5)
Gustavo Padovan [Mon, 1 Dec 2014 23:40:09 +0000 (15:40 -0800)]
drm: add helper to get crtc timings (v5)

We need to get hdisplay and vdisplay in a few places so create a
helper to make our job easier.

Note that drm_crtc_check_viewport() and intel_modeset_pipe_config() were
previously making adjustments for doublescan modes and vscan > 1 modes,
which was incorrect.  Using our new helper fixes this mistake.

v2 (by Matt): Use new stereo doubling function (suggested by Ville)

v3 (by Matt):
 - Add missing kerneldoc (Daniel)
 - Use drm_mode_copy() (Jani)

v4 (by Matt):
 - Drop stereo doubling function again; add 'stereo only' flag
   to drm_mode_set_crtcinfo() instead (Ville)

v5 (by Matt):
 - Note behavioral change in drm_crtc_check_viewport() and
   intel_modeset_pipe_config(). (Ander)
 - Describe new adjustment flags in drm_mode_set_crtcinfo()'s
   kerneldoc. (Ander)

Cc: dri-devel@lists.freedesktop.org
Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Gustavo Padovan <gustavo.padovan@collabora.co.uk>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Acked-by: Dave Airlie <airlied@gmail.com>
Reviewed-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Update DRIVER_DATE to 20141205
Daniel Vetter [Fri, 5 Dec 2014 14:59:16 +0000 (15:59 +0100)]
drm/i915: Update DRIVER_DATE to 20141205

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915/bdw: Add WaHdcDisableFetchWhenMasked
Michel Thierry [Thu, 4 Dec 2014 15:07:52 +0000 (15:07 +0000)]
drm/i915/bdw: Add WaHdcDisableFetchWhenMasked

We already have it for chv, but was missing for bdw.

Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Update the DSI enable path to support dual
Gaurav K Singh [Fri, 5 Dec 2014 08:54:21 +0000 (14:24 +0530)]
drm/i915: Update the DSI enable path to support dual

We need to program both port registers during dual link enable path.

v2: Address review comments by Jani
    - Used a for loop instead of do-while loop.

v3: Used for_each_dsi_port macro instead of for loop

v4: Renamed mode_hactive variable to mode_hdisplay

Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Update the DSI disable path to support dual link panel disabling
Gaurav K Singh [Fri, 5 Dec 2014 08:52:44 +0000 (14:22 +0530)]
drm/i915: Update the DSI disable path to support dual link panel disabling

We need to program both port registers during dual link disable path.

v2: Address review comments by Jani
    - Used a for loop instead of do-while loop.

v3: Used for_each_dsi_port macro instead of for loop

v4: Added comments for the usage of AFE latchout bit

Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: MIPI Timings related changes for dual link
Gaurav K Singh [Thu, 4 Dec 2014 05:28:54 +0000 (10:58 +0530)]
drm/i915: MIPI Timings related changes for dual link

hactive, hfp, hbp, hsync needs to be halved for dual link MIPI Panels.
Accordingly timing related mmio regs needs to be programmed for both MIPI Ports.

v2: Address review comments by Jani
    - Used a for loop instead of do-while loop

v3: Used for_each_dsi_port macro instead of for loop

Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: cck reg used for checking DSI Pll locked
Gaurav K Singh [Fri, 5 Dec 2014 08:46:58 +0000 (14:16 +0530)]
drm/i915: cck reg used for checking DSI Pll locked

Instead of pipe configuration reg, cck reg to be used for checking whether
DSI Pll is getting locked or not.

v2: dpio_lock unlocked now in case DSI PLL lock fails

Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Enable DSI PLL for both DSI0 and DSI1 in case of dual link
Gaurav K Singh [Thu, 4 Dec 2014 05:28:52 +0000 (10:58 +0530)]
drm/i915: Enable DSI PLL for both DSI0 and DSI1 in case of dual link

For Dual link MIPI Panels, dsipll clock for both DSI0 and DSI1 needs to be enabled.

v2: Address review comments by Jani
    - Added wait time for PLL to be locked.

v3: separate patch created for cck read for checking PLL to be locked

Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Dual link needs Shutdown and Turn on packet for both ports
Gaurav K Singh [Thu, 4 Dec 2014 05:28:51 +0000 (10:58 +0530)]
drm/i915: Dual link needs Shutdown and Turn on packet for both ports

For dual link MIPI panels, SHUTDOWN packet needs to send to both Ports
A & C during MIPI encoder disabling sequence. Similarly, TURN ON packet
to be sent to both Ports during MIPI encoder enabling sequence.

v2: Address review comments by Jani
    - Used a for loop instead of do-while loop.

v3: Used for_each_dsi_port macro instead of for loop

Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Pixel Clock changes for DSI dual link
Gaurav K Singh [Fri, 5 Dec 2014 08:43:41 +0000 (14:13 +0530)]
drm/i915: Pixel Clock changes for DSI dual link

For dual link MIPI Panels, each port needs half of pixel clock. Pixel overlap
can be enabled if needed by panel, then in that case, pixel clock will be
increased for extra pixels.

v2 : Address review comments by Jani
     - Removed the bit mask used for ->dual_link
     - Used DSI instead of MIPI for #define variables

v3: Added the VLV_DISPLAY_BASE to VLV_CHICKEN_3 register

Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Add support for port enable/disable for dual link configuration
Gaurav K Singh [Fri, 5 Dec 2014 08:39:28 +0000 (14:09 +0530)]
drm/i915: Add support for port enable/disable for dual link configuration

For Dual Link MIPI Panels, both Port A and Port C should be enabled
during the MIPI encoder enabling sequence. Similarly, during the
disabling sequence, both ports needs to be disabled.

v2: Used for_each_dsi_port macro instead of for loop

v3: Used intel_dsi->ports instead of dual_link var for dual link configuration check

v4: Masking of the required MIPI port bits before writing proper values

Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: s/MI_STORE_DWORD_IMM_GEN8/MI_STORE_DWORD_IMM_GEN4/
Ville Syrjälä [Fri, 14 Nov 2014 16:16:56 +0000 (18:16 +0200)]
drm/i915: s/MI_STORE_DWORD_IMM_GEN8/MI_STORE_DWORD_IMM_GEN4/

MI_STORE_DWORD_IMM length has been the same ever since gen4. Rename
the define to avoid potential confusion if someone tries to use this
on pre-gen8.

Also correct the comment on MI_MEM_VIRTUAL bit. It's present on 945,g33
and 965 only.

Cc: Oscar Mateo <oscar.mateo@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
[danvet: Add USE_GGTT define for g4x+ too.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: release struct_mutex on the i915_gem_init_hw fail path
Jani Nikula [Fri, 5 Dec 2014 12:17:42 +0000 (14:17 +0200)]
drm/i915: release struct_mutex on the i915_gem_init_hw fail path

Release struct_mutex if init_rings() fails.

This is a regression introduced in
commit 35a57ffbb10840af219eeaf64718434242bb7c76
Author: Daniel Vetter <daniel.vetter@ffwll.ch>
Date:   Thu Nov 20 00:33:07 2014 +0100

    drm/i915: Only init engines once

Reported-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Added port as parameter to the functions which does read/write of DSI Contr...
Gaurav K Singh [Thu, 4 Dec 2014 05:28:48 +0000 (10:58 +0530)]
drm/i915: Added port as parameter to the functions which does read/write of DSI Controller

This patch is in preparation of DSI dual link panels. For dual link
panels, few packets needs to be sent to Port A or Port C or both. Based
on the portno from MIPI Sequence Block#53, these sequences needs to be
sent accordingly.

v2: Addressed review comments by Jani
    - port variables named properly

Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: New functions added for enabling & disabling MIPI Port Ctrl reg
Gaurav K Singh [Thu, 4 Dec 2014 05:28:47 +0000 (10:58 +0530)]
drm/i915: New functions added for enabling & disabling MIPI Port Ctrl reg

This patch is in preparation for the DSI dual link
port enable and disable related changes.

Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Don't display nonsensical values in i915_ddb_info on gen < 9
Damien Lespiau [Wed, 3 Dec 2014 17:33:24 +0000 (17:33 +0000)]
drm/i915: Don't display nonsensical values in i915_ddb_info on gen < 9

When playing around with debugfs and a HSW machine I noticed that we
were displaying some garbled value in i915_ddb_info. This debugfs file
is only meaningful for gen9+, so don't display anything on earlier
platforms.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Stop putting GGTT VMA at the head of the list
Tvrtko Ursulin [Wed, 3 Dec 2014 14:59:24 +0000 (14:59 +0000)]
drm/i915: Stop putting GGTT VMA at the head of the list

Multiple GGTT VMAs per object will be introduced in the near future which will
make it impossible to guarantee normal GGTT view is at the head of the list.

Purpose of this patch is to break this assumption straight away so any
potential hidden assumptions in the code base can be bisected to this
simple patch.

For: VIZ-4544
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Suggested-by: Daniel Vetter <daniel@ffwll.ch>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915/skl: Update the DDI translation values for DP/eDP 1.3
Damien Lespiau [Wed, 26 Nov 2014 13:37:26 +0000 (13:37 +0000)]
drm/i915/skl: Update the DDI translation values for DP/eDP 1.3

Hardware team updated the recommended translation values for DP/eDP 1.3.
This should help with some stability and HBR2 issues.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Satheeshakrishna M<satheeshakrishna.m@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Move init_unused_rings to gem_init_hw
Daniel Vetter [Thu, 20 Nov 2014 08:45:19 +0000 (09:45 +0100)]
drm/i915: Move init_unused_rings to gem_init_hw

We need to do that every time we resume the rings, not just at load.
I've overlooked this in my untangling of the ring init code.

Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
Reviewed-by: Dave Gordon <david.s.gordon@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Fix startup failure in LRC mode after recent init changes
Thomas Daniel [Tue, 2 Dec 2014 12:50:48 +0000 (12:50 +0000)]
drm/i915: Fix startup failure in LRC mode after recent init changes

A previous commit introduced engine init changes:

    commit 372ee59699d9 ("drm/i915: Only init engines once")

This broke execlists as intel_lr_context_render_state_init was trying to emit
commands to the RCS for the default context before the ring->init_hw was called.

Made a new gen8_init_rcs_context function and assign in to render ring
init_context.  Moved call to intel_logical_ring_workarounds_emit into
gen8_init_rcs_context to maintain previous functionality.

Moved call to render_state_init from lr_context_deferred_create into
gen8_init_rcs_context, and modified deferred_create to call ring->init_context
for non-default contexts.

Modified i915_gem_context_enable to call ring->init_context for the default
context.

So init_context will now always be called when the hw is ready - in
i915_gem_context_enable for the default context and in lr_context_deferred_create
for other contexts.

Signed-off-by: Thomas Daniel <thomas.daniel@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Convert pxvid to extvid lookup table to a function
Mika Kuoppala [Mon, 1 Dec 2014 16:01:05 +0000 (18:01 +0200)]
drm/i915: Convert pxvid to extvid lookup table to a function

The conversion table can be replaced with simple enough function.

   text    data     bss     dec     hex filename
 839688   10987      24  850699   cfb0b drivers/gpu/drm/i915/i915.ko
 839224   10987      24  850235   cf93b drivers/gpu/drm/i915/i915.ko

Result is 494 saved bytes (.05525%).

v2: - no run on sentences from subject (Chris, Jani)
    - be verbose about the savings (Chris, Daniel)

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> (v1)
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Flatten engine init control flow
Daniel Vetter [Wed, 19 Nov 2014 23:33:08 +0000 (00:33 +0100)]
drm/i915: Flatten engine init control flow

Now that sanity prevails and we have the clean split between software
init and starting the engines we can drop all the "have we allocate
this struct already?" nonsense.

Execlist code could benefit quite a bit more still, but that's for
another patch.

Reviewed-by: Dave Gordon <david.s.gordon@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
9 years agodrm/i915: Remove unnecessary goto in intel_primary_plane_disable()
Ander Conselvan de Oliveira [Thu, 27 Nov 2014 13:32:34 +0000 (15:32 +0200)]
drm/i915: Remove unnecessary goto in intel_primary_plane_disable()

The same logic can be implemented without it, and it even saves a line
of code.

Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Only init engines once
Daniel Vetter [Wed, 19 Nov 2014 23:33:07 +0000 (00:33 +0100)]
drm/i915: Only init engines once

We can do this.

And now there's finally the clean split between software setup and
hardware setup I kinda wanted since multi-ring support was merged
aeons ago. It only took almost 5 years.

Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
Reviewed-by: Dave Gordon <david.s.gordon@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Move intel_init_pipe_control out of engine->init_hw
Daniel Vetter [Wed, 19 Nov 2014 23:33:06 +0000 (00:33 +0100)]
drm/i915: Move intel_init_pipe_control out of engine->init_hw

With this all the ->init_hw hooks really only set up hw state needed
to start the ring, all the software state setup and memory/buffer
allocations happen beforehand.

v2: We need to call intel_init_pipe_control after the ring init since
otherwise engine->dev is NULL and it falls over. Currently that's
now after the hw ring is enabled but a) we'll be fine as long as no
one submits a batch b) this will change soon.

Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
Reviewed-by: Dave Gordon <david.s.gordon@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: s/init()/init_hw()/ in intel_engine_cs
Daniel Vetter [Wed, 19 Nov 2014 23:33:04 +0000 (00:33 +0100)]
drm/i915: s/init()/init_hw()/ in intel_engine_cs

This is (mostly, some exceptions that need fixing) the hw setup
function which starts the ring. And not the function which allocates
all the resources.

Make this clear by giving it a better name.

Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
Reviewed-by: Dave Gordon <david.s.gordon@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Consolidate ring freespace calculations
Dave Gordon [Thu, 27 Nov 2014 11:22:49 +0000 (11:22 +0000)]
drm/i915: Consolidate ring freespace calculations

There are numerous places in the code where the driver's idea of
how much space is left in a ring is updated using the driver's
latest notions of the positions of 'head' and 'tail' for the ring.
Among them are some that update one or both of these values before
(re)doing the calculation. In particular, there are four different
places in the code where 'last_retired_head' is copied to 'head'
and then set to -1; and two of these do not have a guard to check
that it has actually been updated since last time it was consumed,
leaving the possibility that the dummy -1 can be transferred from
'last_retired_head' to 'head', causing the space calculation to
produce 'impossible' results (previously seen on Android/VLV).

This code therefore consolidates all the calculation and updating of
these values, such that there is only one place where the ring space
is updated, and it ALWAYS uses (and consumes) 'last_retired_head' if
(and ONLY if) it has been updated since the last call.

Signed-off-by: Dave Gordon <david.s.gordon@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915: Make ring freespace calculation more robust
Dave Gordon [Thu, 27 Nov 2014 11:22:48 +0000 (11:22 +0000)]
drm/i915: Make ring freespace calculation more robust

The used space in a ring is given by the cyclic distance from the
consumer (HEAD) to the producer (TAIL), i.e. ((tail-head) MOD size);
conversely, the available space in a ring is the cyclic distance
from the producer to the consumer, MINUS the amount reserved for a
"gap" that is supposed to guarantee that the producer never catches
up with or overruns the consumer. Note that some GEN h/w requires
that TAIL never approach to within one cacheline of HEAD, so the gap
is usually set to twice the cacheline size to ensure this.

While the existing code gives the correct answer for correct inputs,
if the producer HAS overrun into the reserved space, the result can
be a value larger than the maximum valid value (size-reserved). We
can improve this by reorganising the calculation, so that in the
event of overrun the result will be negative rather than over-large.

This means that the commonly-used test (available >= required)
will then reject further writes into the ring after an overrun,
giving some chance that we can recover from or at least diagnose
the original problem; whereas allowing more writes would likely both
confuse the h/w and destroy the evidence of what went wrong.

Signed-off-by: Dave Gordon <david.s.gordon@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915/dsi: add ports to intel_dsi to describe the ports being driven
Jani Nikula [Fri, 14 Nov 2014 14:54:22 +0000 (16:54 +0200)]
drm/i915/dsi: add ports to intel_dsi to describe the ports being driven

Later on this can include multiple ports (e.g. (1 << PORT_A) | (1 <<
PORT_C)) to describe dual link DSI.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
9 years agodrm/i915/dsi: clean up MIPI DSI pipe vs. port usage
Jani Nikula [Fri, 14 Nov 2014 14:54:21 +0000 (16:54 +0200)]
drm/i915/dsi: clean up MIPI DSI pipe vs. port usage

MIPI DSI works on ports A and C, which map to pipes A and B,
respectively. Things are going to get more complicated with the
introduction of dual link DSI support, so clean up the register defines
and code to match reality.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>