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Kevin Wang [Thu, 25 Jul 2019 03:08:42 +0000 (11:08 +0800)]
drm/amd/powerplay: add smu feature name support
add smu_get_feature_name support in smu.
Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kevin Wang [Thu, 25 Jul 2019 02:32:48 +0000 (10:32 +0800)]
drm/amd/powerplay: add smu message name support
add smu_get_message_name support in smu.
Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kevin Wang [Thu, 25 Jul 2019 01:59:46 +0000 (09:59 +0800)]
drm/amd/powerplay: move smu types to smu_types.h
move some enum type (message, feature, clock) to smu_types.h.
these types is too long in amdgpu_smu.h, and not clearly.
Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Joseph Greathouse [Fri, 26 Jul 2019 20:52:05 +0000 (15:52 -0500)]
drm/amdgpu: Default disable GDS for compute+gfx
Units in the GDS block default to allowing all VMIDs access to all
entries. Disable shader access to the GDS, GWS, and OA blocks from all
compute and gfx VMIDs by default. For compute, HWS firmware will set
up the access bits for the appropriate VMID when a compute queue
requires access to these blocks.
The driver will handle enabling access on-demand for graphics VMIDs.
Leaving VMID0 with full access because otherwise HWS cannot save or
restore values during task switch.
v2: Fixed code and comment styling.
Signed-off-by: Joseph Greathouse <Joseph.Greathouse@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Thong Thai [Thu, 25 Jul 2019 15:21:58 +0000 (11:21 -0400)]
drm/amd/amdgpu/vcn_v2_0: Mark RB commands as KMD commands
Sets the CMD_SOURCE bit for VCN 2.0 Decoder Ring Buffer commands. This
bit was previously set by the RBC HW on older firmware. Newer firmware
uses a SW RBC and this bit has to be set by the driver.
Signed-off-by: Thong Thai <thong.thai@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Fri, 26 Jul 2019 16:04:39 +0000 (11:04 -0500)]
drm/amdgpu/display: fix the build without CONFIG_DRM_AMD_DC_DSC_SUPPORT
Some code was missing the CONFIG_DRM_AMD_DC_DSC_SUPPORT guard.
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Andrey Grodzovsky [Fri, 26 Jul 2019 13:24:35 +0000 (09:24 -0400)]
drm/amdgpu: Fix amdgpu_display_supported_domains logic.
Add restriction to dissallow GTT domain if the relevant BO
doesn't have USWC flag set to avoid the APU hang scenario.
Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Fri, 26 Jul 2019 03:28:58 +0000 (22:28 -0500)]
drm/amdgpu/powerplay: use proper revision id for navi
The PCI revision id determines the sku.
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 25 Jul 2019 16:44:59 +0000 (11:44 -0500)]
drm/amdgpu: put the SMC into the proper state on reset/unload
When doing a GPU reset or unloading the driver, we need to
put the SMU into the apprpriate state for the re-init after
the reset or unload to reliably work.
I don't think this is necessary for BACO because the SMU actually
controls the BACO state to it needs to be active.
For suspend (S3), the asic is put into D3 so the SMU would be
powered down so I don't think we need to put the SMU into
any special state.
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 25 Jul 2019 15:55:57 +0000 (10:55 -0500)]
drm/amdgpu/powerplay: add set_mp1_state for vega12
This sets the SMU into the proper state for various
operations (shutdown, unload, GPU reset, etc.).
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 25 Jul 2019 15:55:25 +0000 (10:55 -0500)]
drm/amdgpu/powerplay: add set_mp1_state for vega10
This sets the SMU into the proper state for various
operations (shutdown, unload, GPU reset, etc.).
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 25 Jul 2019 15:43:28 +0000 (10:43 -0500)]
drm/amdgpu/powerplay: add set_mp1_state for vega20
This sets the SMU into the proper state for various
operations (shutdown, unload, GPU reset, etc.).
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Wed, 31 Jul 2019 02:27:03 +0000 (21:27 -0500)]
drm/amdgpu/powerplay: return success if set_mp1_state is not set
Some asics (APUs) don't have this callback so we want to return
success. Avoids spurious error messages on APUs.
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 25 Jul 2019 14:41:53 +0000 (09:41 -0500)]
drm/amdgpu/powerplay: add a new interface to set the mp1 state
This is required for certain cases such as various GPU resets
(mode1, mode2), BACO, shutdown, unload, etc. to put the SMU into
the appropriate state for when the hw is re-initialized.
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Wed, 24 Jul 2019 04:48:21 +0000 (23:48 -0500)]
drm/amdgpu: add reset_method asic callback for navi
Navi uses either mode1 or baco depending on various
conditions.
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Wed, 24 Jul 2019 04:47:06 +0000 (23:47 -0500)]
drm/amdgpu: add reset_method asic callback for soc15
APUs only support mode2 reset. dGPUs use either mode1 or
baco depending on various conditions.
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Wed, 24 Jul 2019 04:46:12 +0000 (23:46 -0500)]
drm/amdgpu: add reset_method asic callback for vi
VI always uses the legacy pci based reset.
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Wed, 24 Jul 2019 04:45:39 +0000 (23:45 -0500)]
drm/amdgpu: add reset_method asic callback for cik
CIK always uses the legacy pci based reset.
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Wed, 24 Jul 2019 04:44:54 +0000 (23:44 -0500)]
drm/amdgpu: add reset_method asic callback for si
SI always uses the legacy pci based reset.
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Wed, 24 Jul 2019 04:27:21 +0000 (23:27 -0500)]
drm/amdgpu: add an asic callback to determine the reset method
Sometimes the driver may have to behave differently depending
on the method we are using to reset the GPU.
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Thu, 25 Jul 2019 02:12:42 +0000 (10:12 +0800)]
drm/amd/powerplay: enable SW SMU reset functionality
Move SMU irq handler register to sw_init as that's totally
software related. Otherwise, it will prevent SMU reset working.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Thu, 25 Jul 2019 04:10:34 +0000 (12:10 +0800)]
drm/amd/powerplay: fix null pointer dereference around dpm state relates
DPM state relates are not supported on the new SW SMU ASICs. But still
it's not OK to trigger null pointer dereference on accessing them.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Wed, 24 Jul 2019 06:06:09 +0000 (14:06 +0800)]
drm/amd/powerplay: minor fixes around SW SMU power and fan setting
Add checking for possible invalid input and null pointer. And
drop redundant code.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Shirish S [Tue, 16 Jul 2019 09:19:48 +0000 (14:49 +0530)]
drm/amd/display: enable S/G for RAVEN chip
enables gpu_vm_support in dm and adds
AMDGPU_GEM_DOMAIN_GTT as supported domain
v2:
Move BO placement logic into amdgpu_display_supported_domains
v3:
Use amdgpu_bo_validate_uswc in amdgpu_display_supported_domains.
v4:
amdgpu_bo_validate_uswc moved to sepperate patch.
Signed-off-by: Shirish S <shirish.s@amd.com>
Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Andrey Grodzovsky [Wed, 24 Jul 2019 15:09:03 +0000 (11:09 -0400)]
drm/amdgpu: Add check for USWC support for amdgpu_display_supported_domains
This verifies we don't add GTT as allowed domain for APUs when USWC
is disabled.
Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Acked-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Andrey Grodzovsky [Wed, 24 Jul 2019 14:04:27 +0000 (10:04 -0400)]
drm/amdgpu: Create helper to clear AMDGPU_GEM_CREATE_CPU_GTT_USWC
Move the logic to clear AMDGPU_GEM_CREATE_CPU_GTT_USWC in
amdgpu_bo_do_create into standalone helper so it can be reused
in other functions.
v4:
Switch to return bool.
v5: Fix typos.
Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Acked-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Andrey Grodzovsky [Mon, 15 Jul 2019 22:04:08 +0000 (18:04 -0400)]
drm/amdgpu: Fix hard hang for S/G display BOs.
HW requires for caching to be unset for scanout BO
mappings when the BO placement is in GTT memory.
Usually the flag to unset is passed from user mode
but for FB mode this was missing.
v2:
Keep all BO placement logic in amdgpu_display_supported_domains
Suggested-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Tested-by: Shirish S <shirish.s@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jonathan Kim [Thu, 11 Jul 2019 17:14:02 +0000 (13:14 -0400)]
drm/amdgpu: adding xgmi error monitoring
monitor xgmi errors via mc pie status through fica registers.
Signed-off-by: Jonathan Kim <Jonathan.Kim@amd.com>
Reviewed-by: Kent Russell <Kent.Russell@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jonathan Kim [Tue, 9 Jul 2019 19:47:57 +0000 (15:47 -0400)]
drm/amdgpu: add perfmon and fica atomics for df
adding perfmon and fica atomic operations to adhere to data fabrics finite
state machine requirements for indirect register access.
Signed-off-by: Jonathan Kim <Jonathan.Kim@amd.com>
Reviewed-by: Kent Russell <Kent.Russell@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jay Cornwall [Wed, 24 Jul 2019 17:26:08 +0000 (12:26 -0500)]
drm/amdkfd: Remove dead code from gfx8/gfx9 trap handlers
Signed-off-by: Jay Cornwall <jay.cornwall@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jay Cornwall [Wed, 24 Jul 2019 17:23:42 +0000 (12:23 -0500)]
drm/amdkfd: Replace gfx10 trap handler with correct branch
Previously submitted code was taken from an incorrect branch and
was non-functional.
Cc: Oak Zeng <oak.zeng@amd.com>
Signed-off-by: Jay Cornwall <jay.cornwall@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-By: Oak Zeng <oak.zeng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jay Cornwall [Tue, 23 Jul 2019 00:21:13 +0000 (19:21 -0500)]
drm/amdkfd: Fix lost single step exceptions in gfx9 trap handler
If the trap is entered due to MODE.DEBUG_EN=1 and SAVECTX is raised
concurrently the handler cannot identify the source of the exception.
This causes the debugger to lose single step exception notification
when a context save request arrives at the same time.
When MODE.DEBUG_EN=1 and STATUS.HALT=0 (exception not already handled)
jump to the second-level trap handler upon entering the trap. The
second-level trap will set STATUS.HALT=1 and return to the shader.
If SAVECTX was raised then control flow will return to the trap, which
will then handle the context save request.
Cc: Tony Tye <tony.tye@amd.com>
Cc: Laurent Morichetti <laurent.morichetti@amd.com>
Cc: Qingchuan Shi <qingchuan.shi@amd.com>
Signed-off-by: Jay Cornwall <jay.cornwall@amd.com>
Reviewed-by: Laurent Morichetti <laurent.morichetti@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jay Cornwall [Tue, 23 Jul 2019 19:40:07 +0000 (14:40 -0500)]
drm/amdkfd: Use SQC when TCP would fail in gfx9 context save.
When a wavefront raises TRAPSTS.XNACK_ERROR with STATUS.ALLOW_REPLAY=0
subsequent memory instructions have undefined behavior. In practice
SQC stores continue to work but TCP stores do not.
Context save is permitted to fail after XNACK error because the
wavefront will be halted and subsequently terminated. However the
debugger has an interest in retrieving the wavefront VGPR/LDS state.
Detect the out-of-spec case and use SQC stores during context save
in place of TCP stores.
Signed-off-by: Jay Cornwall <jay.cornwall@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
tiancyin [Tue, 16 Jul 2019 10:25:01 +0000 (18:25 +0800)]
drm/amdgpu/gmc10: fix pte mytpe field error for navi14
navi14 share same PTE format with navi10.
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: tiancyin <tianci.yin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
James Zhu [Tue, 23 Jul 2019 20:45:19 +0000 (16:45 -0400)]
drm/amdgpu: use VCN firmware offset for cache window
Since we are using the signed FW now, and also using PSP firmware loading,
but it's still potential to break driver when loading FW directly
instead of PSP, so we should add offset.
Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kevin Wang [Tue, 23 Jul 2019 11:56:52 +0000 (19:56 +0800)]
drm/amd/powerplay: fix temperature granularity error in smu11
in this patch,
drm/amd/powerplay: add callback function of get_thermal_temperature_range
the driver missed temperature granularity change on other temperature.
Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Tue, 23 Jul 2019 08:23:28 +0000 (16:23 +0800)]
drm/amd/powerplay: some cosmetic fixes
Drop redundant check, duplicate check, duplicate setting
and fix the return value.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Tue, 23 Jul 2019 06:27:20 +0000 (14:27 +0800)]
drm/amd/powerplay: no pptable transfer and dpms enabled with "dpm=0"
Honor the 'dpm' module parameter setting on SW SMU routine as what
we did on previous ASICs. SMU FW loading is still proceeded even
with "dpm=0".
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Colin Ian King [Tue, 23 Jul 2019 14:23:12 +0000 (15:23 +0100)]
drm/amd/display: fix a missing null check on a failed kzalloc
Currently the allocation of config may fail and a null pointer
dereference on config can occur. Fix this by added a null
check on a failed allocation of config.
Addresses-Coverity: ("Dereference null return")
Fixes:
c2cd9d04ecf0 ("drm/amd/display: Hook up calls to do stereo mux and dig programming to stereo control interface")
Signed-off-by: Colin Ian King <colin.king@canonical.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chuhong Yuan [Tue, 23 Jul 2019 11:10:08 +0000 (19:10 +0800)]
drm/radeon: Use dev_get_drvdata where possible
Instead of using to_pci_dev + pci_get_drvdata,
use dev_get_drvdata to make code simpler.
Signed-off-by: Chuhong Yuan <hslester96@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chuhong Yuan [Tue, 23 Jul 2019 09:04:22 +0000 (17:04 +0800)]
drm/amd/display: Use dev_get_drvdata
Instead of using to_pci_dev + pci_get_drvdata,
use dev_get_drvdata to make code simpler.
Signed-off-by: Chuhong Yuan <hslester96@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chuhong Yuan [Tue, 23 Jul 2019 09:04:50 +0000 (17:04 +0800)]
drm/amdgpu: Use dev_get_drvdata where possible
Instead of using to_pci_dev + pci_get_drvdata,
use dev_get_drvdata to make code simpler.
Signed-off-by: Chuhong Yuan <hslester96@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nick Desaulniers [Mon, 22 Jul 2019 22:31:05 +0000 (15:31 -0700)]
drm/amd/display: readd -msse2 to prevent Clang from emitting libcalls to undefined SW FP routines
arch/x86/Makefile disables SSE and SSE2 for the whole kernel. The
AMDGPU drivers modified in this patch re-enable SSE but not SSE2. Turn
on SSE2 to support emitting double precision floating point instructions
rather than calls to non-existent (usually available from gcc_s or
compiler_rt) floating point helper routines for Clang.
This was originally landed in:
commit
10117450735c ("drm/amd/display: add -msse2 to prevent Clang from emitting libcalls to undefined SW FP routines")
but reverted in:
commit
193392ed9f69 ("Revert "drm/amd/display: add -msse2 to prevent Clang from emitting libcalls to undefined SW FP routines"")
due to bugreports from GCC builds. Add guards to only do so for Clang.
Link: https://bugs.freedesktop.org/show_bug.cgi?id=109487
Link: https://github.com/ClangBuiltLinux/linux/issues/327
Suggested-by: Sedat Dilek <sedat.dilek@gmail.com>
Suggested-by: Sami Tolvanen <samitolvanen@google.com>
Signed-off-by: Nick Desaulniers <ndesaulniers@google.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kent Russell [Tue, 23 Jul 2019 14:18:01 +0000 (10:18 -0400)]
drm/amdkfd: Fix byte align on VegaM
This was missed during the addition of VegaM support
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Kent Russell <kent.russell@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kevin Wang [Mon, 3 Jun 2019 07:58:31 +0000 (15:58 +0800)]
drm/amd/powerplay: add callback function of get_thermal_temperature_range
1. the thermal temperature is asic related data, move the code logic to
xxx_ppt.c.
2. replace data structure PP_TemperatureRange with
smu_temperature_range.
3. change temperature uint from temp*1000 to temp (temperature uint).
Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 18 Jul 2019 20:25:04 +0000 (15:25 -0500)]
drm/amdgpu/smu: move fan rpm query into the asic specific code
On vega20, there is an SMU message to query it. On navi, it's fetched
from the metrics table.
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Fri, 19 Jul 2019 11:09:38 +0000 (19:09 +0800)]
drm/amdgpu: set sdma irq src num according to sdma instances
Otherwise, it will cause driver access non-existing sdma registers
in gpu reset code path
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kevin Wang [Fri, 19 Jul 2019 08:06:29 +0000 (16:06 +0800)]
drm/amd/powerplay: remove redundancy debug log in smu
remove redundacy debug log in smu.
eg:
[ 6897.969447] amdgpu: [powerplay] smu 11 clk dpm feature 1 is not enabled
[ 6897.969448] amdgpu: [powerplay] smu 11 clk dpm feature 1 is not enabled
[ 6897.969448] amdgpu: [powerplay] smu 11 clk dpm feature 1 is not enabled
[ 6899.024114] amdgpu: [powerplay] Unsupported SMU message: 38
[ 6899.024151] amdgpu: [powerplay] smu 11 clk dpm feature 1 is not enabled
[ 6899.024151] amdgpu: [powerplay] smu 11 clk dpm feature 1 is not enabled
[ 6899.024152] amdgpu: [powerplay] smu 11 clk dpm feature 1 is not enabled
[ 6900.078296] amdgpu: [powerplay] Unsupported SMU message: 38
[ 6900.078332] amdgpu: [powerplay] smu 11 clk dpm feature 1 is not enabled
[ 6900.078332] amdgpu: [powerplay] smu 11 clk dpm feature 1 is not enabled
[ 6900.078333] amdgpu: [powerplay] smu 11 clk dpm feature 1 is not enabled
[ 6901.133230] amdgpu: [powerplay] Unsupported SMU message: 38
Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kevin Wang [Fri, 19 Jul 2019 03:39:21 +0000 (11:39 +0800)]
drm/amd/powerplay: custom peak clock freq for navi10
v2:
add function smu_default_set_performance_level as default dpm level handler.
change function name smu_set_performance_level to smu_asic_set_performance_level
v1:
1.NAVI10_PEAK_SCLK_XTX 1830 Mhz
2.NAVI10_PEAK_SCLK_XT 1755 Mhz
3.NAVI10_PEAK_SCLK_XL 1625 Mhz
Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Jack Gui <Jack.Gui@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dale Zhao [Wed, 10 Jul 2019 09:36:53 +0000 (17:36 +0800)]
drm/amd/display: handle active dongle port type is DP++ or DP case
[Why]:
Some active dongles have DP++ port and DP port at the same time. Current
code doesn't cover DP++ case and processes as default DVI case, in which
audio is disabled. Because of dual mode, DP case is also treat as DVI case
for the other port.
[How]:
According DP 1.4 spec, add DP++ procedure similar with HDMI case. Also
add None dongle type for DP case.
Signed-off-by: Dale Zhao <dale.zhao@amd.com>
Reviewed-by: Wenjing Liu <wenjing.liu@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nicholas Kazlauskas [Thu, 11 Jul 2019 16:32:43 +0000 (12:32 -0400)]
drm/amd/display: Copy GSL groups when committing a new context
[Why]
DC configures the GSL group for the pipe when pipe_split is enabled
and we're switching flip types (buffered <-> immediate flip) on DCN2.
In order to record what GSL group the pipe is using DC stores it in
the pipe's stream_res. DM is not aware of this internal grouping, nor
is DC resource.
So when DM creates a dc_state context and passes it to DC the current
GSL group is lost - DM never knew about it in the first place.
After 3 immediate flips we run out of GSL groups and we're no longer
able to correctly perform *any* flip for multi-pipe scenarios.
[How]
The gsl_group needs to be copied to the new context.
DM has no insight into GSL grouping and could even potentially create
a brand new context without referencing current hardware state. So this
makes the most sense to have happen in DC.
There are two places where DC can apply a new context:
- dc_commit_state
- dc_commit_updates_for_stream
But what's shared between both of these is apply_ctx_for_surface.
This logic only matters for DCN2, so it can be placed in
dcn20_apply_ctx_for_surface. Before doing any locking (where the GSL
group is setup) we can copy over the GSL groups before committing the
new context.
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Hersen Wu <hersen.wu@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Lewis Huang [Wed, 3 Jul 2019 03:33:34 +0000 (22:33 -0500)]
drm/amd/display: Add debug entry to destroy disconnected edp link
Add a flag to dc_debug_options to determine if a disconnected edp link
should be destroyed.
Signed-off-by: Lewis Huang <Lewis.Huang@amd.com>
Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tony Cheng [Sun, 23 Jun 2019 17:07:02 +0000 (12:07 -0500)]
drm/amd/display: avoid power gate domains that doesn't exist
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Fatemeh Darbehani [Wed, 10 Jul 2019 14:34:31 +0000 (10:34 -0400)]
drm/amd/display: Add SMU version field to clk_mgr_internal
For some platforms, we need to know SMU version for driver/SMU
compatibility. This change adds that field.
Signed-off-by: Fatemeh Darbehani <fatemeh.darbehani@amd.com>
Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jun Lei [Mon, 8 Jul 2019 19:15:42 +0000 (15:15 -0400)]
drm/amd/display: support "dummy pstate"
[why]
Existing support in DC for pstate only accounts for a single latency. This is sufficient when the
variance of latency is small, or that pstate support isn't necessary for correct ASIC functionality.
Newer ASICs violate both existing assumptions. PState support is mandatory of correct ASIC
functionality, but not all latencies have to be supported. Existing code supports a "full p state" which
allows memory clock to change, but is hard for DCN to support (as it requires very large buffers).
New code will now fall back to a "dummy p state" support when "full p state" cannot be support.
This easy p state support should always be allowed.
[how]
Define a new latency in socBB. Add fallback logic to support it. Note DML is also updated to ensure
that fallback will always work.
Signed-off-by: Jun Lei <Jun.Lei@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Eric Yang [Sat, 29 Jun 2019 20:02:37 +0000 (16:02 -0400)]
drm/amd/display: fix mpcc assert condition
[Why]
In DCN2x asic, the MPCC status register definition changed, and
our logic for assert is incorrect. disabled is valid state,
where we should see idle and not busy, where as in not
disabled state, we should see not idle.
[How]
Change assert condition to be more sensible.
Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Eric Yang [Sat, 29 Jun 2019 18:38:04 +0000 (14:38 -0400)]
drm/amd/display: do not read link setting if edp not connected
[Why]
Previously assume eDP sink present if connector present. Do not
need to enforce this restriction. Fix issue where driver attempt
to read link setting even though no edp connected.
{How]
Only read link setting after reading connection status.
Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tai Man [Fri, 28 Jun 2019 15:40:38 +0000 (11:40 -0400)]
drm/amd/display: Increase size of audios array
[Why]
The audios array defined in "struct resource_pool" is only 6 (MAX_PIPES)
but the max number of audio devices (num_audio) is 7. In some projects,
it will run out of audios array.
[How]
Incraese the audios array size to 7.
Signed-off-by: Tai Man <taiman.wong@amd.com>
Reviewed-by: Joshua Aberback <Joshua.Aberback@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aric Cyr [Mon, 8 Jul 2019 01:25:35 +0000 (21:25 -0400)]
drm/amd/display: 3.2.42
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Zhan Liu [Tue, 2 Jul 2019 19:17:07 +0000 (15:17 -0400)]
drm/amd/display: drop ASSERT() if eDP panel is not connected
[Why]
For boards that support eDP but do not have a physical eDP
display connected an ASSERT will be thrown. This is not a
critical failure and shouldn't be treated as such.
[How]
Drop the assertion.
Signed-off-by: Zhan Liu <zhan.liu@amd.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nicholas Kazlauskas [Wed, 3 Jul 2019 14:02:39 +0000 (10:02 -0400)]
drm/amd/display: Set enabled to false at start of audio disable
[Why]
In an effort to stop redundant calls to dce110_disable_audio_stream
the audio->enabled flag was added to the audio resource struct. While
this state probably shouldn't have been tracked on the audio struct
itself it still works fine for some sequences.
However, it does not work for cases where we're freeing the audio
resource (such as hotplugs) or when dynamic audio is enabled.
In these cases the pipe_ctx->stream_res.audio = NULL before we can
set audio->enabled = false. The next time we acquire the audio resource
such as on hotplug the audio will not be enabled for the stream since
DC thinks it's still enabled.
Audio state tracking should cover this sequence.
[How]
Set audio->enabled = false at the start as long as we have
pipe_ctx->stream_res.audio.
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Zhan Liu <Zhan.Liu@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Julian Parkin [Wed, 3 Jul 2019 17:59:26 +0000 (13:59 -0400)]
drm/amd/display: Clean up dynamic metadata logic
[Why]
Code to enable DCN20 dynamic metadata feature is duplicated in two places
and was added to DCE110 enable stream.
[How]
Create DCN20 specific enable stream function for clarity, and add a hardware
sequencer function to program dynamic metadata to avoid the duplicate
code.
Signed-off-by: Julian Parkin <julian.parkin@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alvin Lee [Thu, 4 Jul 2019 19:17:42 +0000 (15:17 -0400)]
drm/amd/display: Only enable audio if speaker allocation exists
[Why]
In dm_helpers_parse_edid_caps, there is a corner case where no speakers
can be allocated even though the audio mode count is greater than 0.
Enabling audio when no speaker allocations exists can cause issues in
the video stream.
[How]
Add a check to not enable audio unless one or more speaker allocations
exist (since doing this can cause issues in the video stream).
Signed-off-by: Alvin Lee <alvin.lee2@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Julian Parkin [Tue, 25 Jun 2019 18:55:53 +0000 (14:55 -0400)]
drm/amd/display: Fix dc_create failure handling and 666 color depths
[Why]
It is possible (but very unlikely) that constructing dc fails
before current_state is created.
We support 666 color depth in some scenarios, but this
isn't handled in get_norm_pix_clk. It uses exactly the
same pixel clock as the 888 case.
[How]
Check for non null current_state before destructing.
Add case for 666 color depth to get_norm_pix_clk to
avoid assertion.
Signed-off-by: Julian Parkin <julian.parkin@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jun Lei [Wed, 3 Jul 2019 20:52:38 +0000 (16:52 -0400)]
drm/amd/display: populate last calculated bb state with max clocks
[why]
update_bounding_box calculates intermediate bb states based on clock relationship
however, the last state doesn't need to maintain a minimum relationship, but should
actually contain maximum of every clock. otherwise maximum clocks are not usable
[how]
once the calculated bb is built, override the last state with max values
Signed-off-by: Jun Lei <Jun.Lei@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dmytro Laktyushkin [Wed, 3 Jul 2019 20:20:42 +0000 (16:20 -0400)]
drm/amd/display: add dcc programming for dual plane
Add dual plane dcc programming support for
surfaces.
Removes unions from plane size and dcc params as they
serve no practical purpose only making our code
more convoluted. This results in easy dual plane
dcc and surface size programming.
Temporary diags_dm code is used to handle the interface
change without breaking functionality as a diags change
needs to be applied after this one.
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reza Amini [Mon, 10 Jun 2019 20:45:50 +0000 (16:45 -0400)]
drm/amd/display: Implement DAL3 GPU Integer Scaling
[WHY]
Users want to not have filtering when scaling by integer
multiples to native timing.
[HOW]
If timing is a multiple integer of view, we set number of taps
to 1 (effectivly closest neighbour).
Signed-off-by: Reza Amini <Reza.Amini@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Acked-by: Tony Cheng <Tony.Cheng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dingchen Zhang [Fri, 28 Jun 2019 21:23:24 +0000 (17:23 -0400)]
drm/amd/display: add pipe CRC sources without disabling dithering.
[Why]
need to verify the impact of spatial dithering on 8bpc bypass mode.
[How]
added CRC sources and configure dihter option from dc stream.
Signed-off-by: Dingchen Zhang <dingchen.zhang@amd.com>
Reviewed-by: Hanghong Ma <Hanghong.Ma@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dmytro Laktyushkin [Tue, 2 Jul 2019 18:51:01 +0000 (14:51 -0400)]
drm/amd/display: use min disp and dpp clk debug option for dcn2
This allows to set a minimum display and dpp clock on dcn2+ HW
by adjusting clocks used for dml calculations.
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Charlene Liu [Tue, 2 Jul 2019 18:04:35 +0000 (14:04 -0400)]
drm/amd/display: add a option to force the clock at every mode change.
[Description]
This is for HW negative stress testing use.
force reset the dispclk and dppclk even the same clock already set in HW.
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Murton Liu [Tue, 2 Jul 2019 15:32:19 +0000 (11:32 -0400)]
drm/amd/display: Change offset_to_id to reflect what id_to_offset returns
id_to_offset does not point to the same reg offset that offset_to_id checks for,
causing unintended asserts
Signed-off-by: Murton Liu <murton.liu@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Charlene Liu [Thu, 27 Jun 2019 22:16:21 +0000 (18:16 -0400)]
drm/amd/display: add set and get clock for testing purposes
add dc_set_clock
add dc_get_clock
this is for testing and diagnostics to get/set DPPCLK and DISPCLK.
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Derek Lai [Tue, 2 Jul 2019 09:50:41 +0000 (17:50 +0800)]
drm/amd/display: allocate 4 ddc engines for RV2
[Why]
Driver will create 0, 1, and 2 ddc engines for RV2,
but some platforms used 0, 1, and 3.
[How]
Still allocate 4 ddc engines for RV2.
Signed-off-by: Derek Lai <Derek.Lai@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Murton Liu [Tue, 25 Jun 2019 15:15:09 +0000 (11:15 -0400)]
drm/amd/display: Hook up calls to do stereo mux and dig programming to stereo control interface
[Why]
Implementation of stereo mux register is complete, but unused. Need to
call functions to write relevant configs.
[How]
Add function to write stereo config for enable/disable case and call in
stereo control interface.
Signed-off-by: Murton Liu <murton.liu@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aric Cyr [Tue, 2 Jul 2019 03:15:42 +0000 (23:15 -0400)]
drm/amd/display: 3.2.41
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Ilya Bakoulin [Wed, 26 Jun 2019 18:52:46 +0000 (14:52 -0400)]
drm/amd/display: Fixes for some MPO cases
[Why]
Alpha could be improperly applied (only affecting half the
frame) for some source pixel formats.
[How]
Change how alpha is enabled in MPC/DPP LB and change the
bottom plane blend mode in MPC.
Signed-off-by: Ilya Bakoulin <Ilya.Bakoulin@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Ilya Bakoulin [Wed, 19 Jun 2019 21:33:02 +0000 (17:33 -0400)]
drm/amd/display: Cache the use_pitch_c conditional
For clarity, save the use_pitch_c logic to a bool
Signed-off-by: Ilya Bakoulin <Ilya.Bakoulin@amd.com>
Reviewed-by: Eric Bernstein <eric.bernstein@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nevenko Stupar [Fri, 28 Jun 2019 16:12:13 +0000 (12:12 -0400)]
drm/amd/display: Add DIG_CLOCK_PATTERN register
Add this register for future use
Signed-off-by: Nevenko Stupar <Nevenko.Stupar@amd.com>
Reviewed-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Qingqing Zhuo [Thu, 27 Jun 2019 23:17:23 +0000 (19:17 -0400)]
drm/amd/display: Add CM_BYPASS via debug option
[Why]
bypass CM block and MPC ogam for debug or triage use.
[How]
create a new flag cm_bypass_mode, which will set both CM_CONTROL
and MPCC_OGAM_MODE to bypass when set to 1.
Signed-off-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Vitaly Prosyak [Fri, 21 Jun 2019 15:13:16 +0000 (10:13 -0500)]
drm/amd/display: Add MPC 3DLUT resource management
[Why & How]
Number of 3DLUT's in MPC are not equal to number of pipes.
Resource management is required.
Activate on FPGA entire tm solution which includes
the following :hdr multiplier, shaper, 3dlut.
Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Gary Kattan <Gary.Kattan@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Joshua Aberback [Fri, 17 May 2019 18:43:10 +0000 (14:43 -0400)]
drm/amd/display: Add debug option to disable timing sync
[Why]
We want a debug option to disable timing sync for testing.
[How]
New dc debug option that must be false to call program_timing_sync
Signed-off-by: Joshua Aberback <joshua.aberback@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nikola Cornij [Tue, 25 Jun 2019 21:19:25 +0000 (17:19 -0400)]
drm/amd/display: Clear FEC_READY shadow register if DPCD write fails
[why]
As a fail-safe, in case 'set FEC_READY' DPCD write fails, a HW shadow
register should be cleared and the internal FEC stat should be set to
'not ready'. This is to make sure HW settings will be consistent with
FEC_READY state on the RX.
Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
Reviewed-by: Joshua Aberback <Joshua.Aberback@amd.com>
Acked-by: Chris Park <Chris.Park@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Krunoslav Kovac [Tue, 18 Jun 2019 21:38:43 +0000 (17:38 -0400)]
drm/amd/display: Optimize gamma calculations
[Why&How]
1. Stack usage is pretty high as fixed31_32 struct is 8 bytes and we
have functions with >30 vars on the stack.
2. Optimize gamma calculation by reducing number of calls to
dc_fixpt_pow Our X points are divided into 32 regions wth 16 pts each.
Each region is 2x the previous, meaning x[i] = 2*x[i-16] for i>=16.
Using (2x)^gamma = 2^gamma * x^gamma, we can recursively compute powers
of gamma, we just need first 16 pts to start it up. dc_fixpt_pow() is
expensive, it computes x^y by doing exp(y*logx) Exp is done by Taylor
series approximation, and log by Newton-like approximation that also
uses exp internally. In short, it's significantly heavier than
run-of-the-mill addition/subtraction/multiply.
Signed-off-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Eric Yang [Mon, 24 Jun 2019 22:18:58 +0000 (18:18 -0400)]
drm/amd/display: put back front end initialization sequence
[Why]
Seamless boot optimization removed proper front end power off sequence.
In driver disable enable case, this causes driver to power gate hubp
and dpp while there is still memory fetching going on, this can cause
invalid memory requests to be generated which will hang data fabric.
[How]
Put back proper front end power off sequence
Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Acked-by: Tony Cheng <Tony.Cheng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nikola Cornij [Mon, 24 Jun 2019 19:44:42 +0000 (15:44 -0400)]
drm/amd/display: Set FEC_READY always before link training
[why]
Right now we FEC_READY is set only before the final link training,
i.e. at mode set time. This means FEC_READY won't be set when doing
link training as a response to HPD. It also fails UCD400 FEC test in
DP compliance.
[how]
Move FEC_READY setup to link training.
Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Abdoulaye Berthe <Abdoulaye.Berthe@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Eric Bernstein [Mon, 24 Jun 2019 18:11:55 +0000 (14:11 -0400)]
drm/amd/display: Use helper for determining HDMI signal
Use helper to determine if HDMI signal when processing avmute.
Signed-off-by: Eric Bernstein <eric.bernstein@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Murton Liu [Mon, 24 Jun 2019 15:28:06 +0000 (11:28 -0400)]
drm/amd/display: Implement generic MUX registers (v2)
[Why]
Logic & structures for generic regs does not exist in DC currently.
[How]
Implement register masks/shifts and relevant functions for generic mux,
similar to existing HPD and DDC objects.
V2: fix includes for kalloc/free (Alex)
Signed-off-by: Murton Liu <murton.liu@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Joshua Aberback <Joshua.Aberback@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alvin Lee [Mon, 24 Jun 2019 13:49:44 +0000 (09:49 -0400)]
drm/amd/display: Wait for flip to complete
[why]
In pipe split issue occurs when we program immediate flip while vsync flip is pending
[how]
Don't program immediate flip until flip is no longer pending
Signed-off-by: Alvin Lee <alvin.lee2@amd.com>
Reviewed-by: Jaehyun Chung <Jaehyun.Chung@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aric Cyr [Sun, 23 Jun 2019 21:27:43 +0000 (17:27 -0400)]
drm/amd/display: 3.2.40
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Fatemeh Darbehani [Fri, 21 Jun 2019 21:44:50 +0000 (17:44 -0400)]
drm/amd/display: Change min_h_sync_width from 8 to 4
[Why]
Some display's hsync width is lower than the minimum dcn20 is set
to support right now. This will cause optc1_validate_timing to fail which
eventually will result in wrong set mode. This was set to 8 as per
HW team's request for no valid reason.
[How]
Changing min_h_sync_width to 4 will let us validate timing for
preffered mode and light up the headset. This change was made
to Vega 10 before for a similar issue.
Signed-off-by: Fatemeh Darbehani <fatemeh.darbehani@amd.com>
Reviewed-by: Joshua Aberback <Joshua.Aberback@amd.com>
Acked-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alvin Lee [Fri, 21 Jun 2019 21:58:41 +0000 (17:58 -0400)]
drm/amd/display: Remove second initialization of pp_smu
[why]
We initialize pp_smu twice
[how]
Remove second initialization of pp_smu
Signed-off-by: Alvin Lee <alvin.lee2@amd.com>
Reviewed-by: Jaehyun Chung <Jaehyun.Chung@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Su Sung Chung [Fri, 21 Jun 2019 20:14:36 +0000 (16:14 -0400)]
drm/amd/display: fix not calling ppsmu to trigger PME
[why]
dcn20_clk_mgr_construct was not initializing pp_smu, and PME call gets
filtered out by the null check
[how]
initialize pp_smu dcn20_clk_mgr_construct
Signed-off-by: Su Sung Chung <Su.Chung@amd.com>
Reviewed-by: Eric Yang <eric.yang2@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tai Man [Fri, 7 Jun 2019 21:32:27 +0000 (17:32 -0400)]
drm/amd/display: use encoder's engine id to find matched free audio device
[Why]
On some platforms, the encoder id 3 is not populated. So the encoders
are not stored in right order as index (id: 0, 1, 2, 4, 5) at pool. This
would cause encoders id 4 & id 5 to fail when finding corresponding
audio device, defaulting to the first available audio device. As result,
we cannot stream audio into two DP ports with encoders id 4 & id 5.
[How]
It need to create enough audio device objects (0 - 5) to perform matching.
Then use encoder engine id to find matched audio device.
Signed-off-by: Tai Man <taiman.wong@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Harry Wentland [Fri, 31 May 2019 18:17:43 +0000 (14:17 -0400)]
drm/amd/display: Remove unnecessary NULL check in set_preferred_link_settings
[Why]
link_stream is never NULL here as we've dereferenced it a couple lines before
and have done so for a couple months now.
[How]
- Drop the NULL check.
- Initialize where we know link_stream is non-NULL
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Charlene Liu [Thu, 20 Jun 2019 01:35:35 +0000 (21:35 -0400)]
drm/amd/display: Do not fill Null packet in the blank period
[Description]
Do not fill Null packet in the blank period for new packet gen
This is based on HW IP team recommended default setting change.
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Zi Yu Liao [Thu, 20 Jun 2019 14:55:26 +0000 (10:55 -0400)]
drm/amd/display: fix DMCU hang when going into Modern Standby
[why]
When the system is going into suspend, set_backlight gets called
after the eDP got blanked. Since smooth brightness is enabled,
the driver will make a call into the DMCU to ramp the brightness.
The DMCU would try to enable ABM to do so. But since the display is
blanked, this ends up causing ABM1_ACE_DBUF_REG_UPDATE_PENDING to
get stuck at 1, which results in a dead lock in the DMCU firmware.
[how]
Disable brightness ramping when the eDP display is blanked.
Signed-off-by: Zi Yu Liao <ziyu.liao@amd.com>
Reviewed-by: Eric Yang <eric.yang2@amd.com>
Acked-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alvin Lee [Thu, 20 Jun 2019 17:03:25 +0000 (13:03 -0400)]
drm/amd/display: Disable Audio on reinitialize hardware
[Why]
When we recover from hang, we do not want to skip the audio enable call.
[How]
Disable audio in dc_reinitialize_hardware
Signed-off-by: Alvin Lee <alvin.lee2@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nikola Cornij [Wed, 19 Jun 2019 18:30:52 +0000 (14:30 -0400)]
drm/amd/display: Power-gate all DSCs at driver init time
[why]
DSC should be powered-on only on as-needed basis, i.e. if the mode
requires it
[how]
Loop over all the DSCs at driver init time and power-gate each
Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
Reviewed-by: Nevenko Stupar <Nevenko.Stupar@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dmytro Laktyushkin [Tue, 18 Jun 2019 19:57:03 +0000 (15:57 -0400)]
drm/amd/display: Remove dsc disable_ich flag programming.
Current default is sufficient for a flag that does not change.
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Derek Lai [Tue, 18 Jun 2019 06:55:57 +0000 (14:55 +0800)]
drm/amd/display: Read max down spread
[Why]
When launch D10.2, driver will write DPCD 0x107 with 0x00
[How]
Read MAX_DOWNSPREAD (0x0003h) then keep in current
link settings
Signed-off-by: Derek Lai <Derek.Lai@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>