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Bjorn Helgaas [Wed, 1 Oct 2014 18:30:58 +0000 (12:30 -0600)]
Merge branches 'pci/aer' and 'pci/virtualization' into next
* pci/aer:
PCI/AER: Rename PCI_ERR_UNC_TRAIN to PCI_ERR_UNC_UND
PCI/AER: Add additional PCIe AER error strings
trace, RAS: Add additional PCIe AER error strings
trace, RAS: Replace bare numbers with #defines for PCIe AER error strings
* pci/virtualization:
PCI: Add ACS quirk for Intel 10G NICs
Alex Williamson [Fri, 26 Sep 2014 23:07:59 +0000 (17:07 -0600)]
PCI: Add ACS quirk for Intel 10G NICs
Intel has verified there is no peer-to-peer between functions for the below
selection of 82598, 82599, and X520 10G NICs. These NICs lack an ACS
capability, so we're not able to determine this isolation without the help
of quirks.
Generalize the Solarflare quirk and add these Intel 10G NICs.
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: John Ronciak <John.ronciak@intel.com>
Bjorn Helgaas [Mon, 29 Sep 2014 19:24:24 +0000 (13:24 -0600)]
Merge branch 'pci/host-designware' into next
* pci/host-designware:
PCI: designware: Add get_msi_data() to pcie_host_ops
PCI: designware: Rename get_msi_data() to get_msi_addr()
PCI: designware: Fix IO resource end address calculation
PCI: designware: Fix configuration base address when using 'reg'
PCI: designware: Use NULL instead of false
[bhelgaas: Fixup keystone for "PCI: designware: Rename get_msi_data() to
get_msi_addr()"]
Bjorn Helgaas [Thu, 25 Sep 2014 19:52:02 +0000 (13:52 -0600)]
Merge branches 'pci/enumeration', 'pci/virtualization' and 'pci/cleanup' into next
* pci/enumeration:
PCI: Generate uppercase hex for modalias interface class
* pci/virtualization:
PCI: Add ACS quirk for Solarflare SFC9120 & SFC9140
PCI: Remove unused pci_get_dma_source()
PCI: Remove unused pci_find_upstream_pcie_bridge()
* pci/cleanup:
PCI: Remove assignment from complicated "if" conditions
PCI: Remove assignment from "if" conditions
PCI: Remove unnecessary curly braces
PCI: Add space before open parenthesis
Bjorn Helgaas [Thu, 25 Sep 2014 19:51:55 +0000 (13:51 -0600)]
Merge branches 'pci/host-mvebu' and 'pci/host-spear' into next
* pci/host-mvebu:
PCI: mvebu: Fix uninitialized variable in mvebu_get_tgt_attr()
* pci/host-spear:
PCI: spear: Pass config resource through reg property
Chen, Gong [Wed, 13 Aug 2014 06:22:40 +0000 (02:22 -0400)]
PCI/AER: Rename PCI_ERR_UNC_TRAIN to PCI_ERR_UNC_UND
In PCIe r1.0, sec 5.10.2, bit 0 of the Uncorrectable Error Status, Mask,
and Severity Registers was for "Training Error." In PCIe r1.1, sec 7.10.2,
bit 0 was redefined to be "Undefined."
Rename PCI_ERR_UNC_TRAIN to PCI_ERR_UNC_UND to reflect this change.
No functional change.
[bhelgaas: changelog]
Signed-off-by: Chen, Gong <gong.chen@linux.intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Chen, Gong [Thu, 25 Sep 2014 15:36:43 +0000 (09:36 -0600)]
PCI/AER: Add additional PCIe AER error strings
Add strings for all AER error bits defined in PCIe r3.0.
[bhelgaas: changelog, drop designated initializer change]
Signed-off-by: Chen, Gong <gong.chen@linux.intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Chen, Gong [Wed, 13 Aug 2014 06:22:39 +0000 (02:22 -0400)]
trace, RAS: Add additional PCIe AER error strings
Add all AER error bits defined in PCIe r3.0.
[bhelgaas: changelog]
Signed-off-by: Chen, Gong <gong.chen@linux.intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Chen, Gong [Wed, 13 Aug 2014 06:22:37 +0000 (02:22 -0400)]
trace, RAS: Replace bare numbers with #defines for PCIe AER error strings
Replace bare numbers like "BIT(0)" with the existing #defines, e.g.,
PCI_ERR_COR_RCVR, to improve maintainability. This way grep will find more
uses of the #defines.
No functional change.
[bhelgaas: changelog]
Signed-off-by: Chen, Gong <gong.chen@linux.intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Bjorn Helgaas [Wed, 24 Sep 2014 20:36:11 +0000 (14:36 -0600)]
Merge branches 'pci/hotplug', 'pci/initdata' and 'pci/misc' into next
* pci/hotplug:
PCI: pciehp: Stop disabling notifications during init
PCI: pciehp: Add more Slot Control debug output
PCI: pciehp: Fix wait time in timeout message
* pci/initdata:
x86/PCI: Mark PCI BIOS initialization code as such
x86/PCI: Constify pci_mmcfg_probes[] array
x86/PCI: Mark constants of pci_mmcfg_nvidia_mcp55() as __initconst
x86/PCI: Move __init annotation to the correct place
x86/PCI: Mark DMI tables as initialization data
* pci/misc:
PCI: Move PCI_VENDOR_ID_VMWARE to pci_ids.h
Francesco Ruggeri [Wed, 24 Sep 2014 17:12:41 +0000 (10:12 -0700)]
PCI: Move PCI_VENDOR_ID_VMWARE to pci_ids.h
Move PCI_VENDOR_ID_VMWARE from device-specific files to pci_ids.h.
It is useful to always have access to it, especially when accessing
subsystem_vendor_id on emulated devices.
[bhelgaas: keep pci_ids.h sorted and use lower-case hex]
Signed-off-by: Francesco Ruggeri <fruggeri@arista.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Quentin Lambert [Sun, 7 Sep 2014 18:04:28 +0000 (20:04 +0200)]
PCI: Remove assignment from complicated "if" conditions
The modifications effectively change the value of len_tmp
in the case where the first condition is not met.
Signed-off-by: Quentin Lambert <lambert.quentin@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Quentin Lambert [Sun, 7 Sep 2014 18:03:32 +0000 (20:03 +0200)]
PCI: Remove assignment from "if" conditions
The following Coccinelle semantic patch was used to find and correct cases
of assignments in "if" conditions:
@@
expression var, expr;
statement S;
@@
+ var = expr;
if(
- (var = expr)
+ var
) S
Signed-off-by: Quentin Lambert <lambert.quentin@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Quentin Lambert [Sun, 7 Sep 2014 18:02:47 +0000 (20:02 +0200)]
PCI: Remove unnecessary curly braces
Remove curly braces in simple "if" cases.
No functional change.
Signed-off-by: Quentin Lambert <lambert.quentin@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Quentin Lambert [Sun, 7 Sep 2014 18:02:04 +0000 (20:02 +0200)]
PCI: Add space before open parenthesis
Add space before open parenthesis as is conventional.
No functional change.
[bhelgaas: fix a few more in ibmphp, shpchp]
Signed-off-by: Quentin Lambert <lambert.quentin@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Minghuan Lian [Tue, 23 Sep 2014 14:28:59 +0000 (22:28 +0800)]
PCI: designware: Add get_msi_data() to pcie_host_ops
Add a struct pcie_host_ops .get_msi_data() method for platforms to return
their special MSI message data.
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Mohit KUMAR <mohit.kumar@st.com>
Minghuan Lian [Tue, 23 Sep 2014 14:28:58 +0000 (22:28 +0800)]
PCI: designware: Rename get_msi_data() to get_msi_addr()
The struct pcie_host_ops .get_msi_data() method returns the MSI message
address. To accurately express its purpose, rename it to .get_msi_addr().
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Mohit KUMAR <mohit.kumar@st.com>
Minghuan Lian [Tue, 23 Sep 2014 14:28:57 +0000 (22:28 +0800)]
PCI: designware: Fix IO resource end address calculation
End address should be equal to start_addr + size - 1. Fix PCI IO resource
end address calculation.
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Mohit KUMAR <mohit.kumar@st.com>
Minghuan Lian [Tue, 23 Sep 2014 14:28:56 +0000 (22:28 +0800)]
PCI: designware: Fix configuration base address when using 'reg'
The code has calculated cfg0_base and cfg1_base when parsing 'reg' or
'ranges' property of PCI DTS node, so remove duplicate calculation. When
using 'reg', resource cfg is not used, so this code computed an incorrect
configuration base.
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Mohit KUMAR <mohit.kumar@st.com>
Mathias Krause [Mon, 25 Aug 2014 21:26:39 +0000 (23:26 +0200)]
x86/PCI: Mark PCI BIOS initialization code as such
The pci_find_bios() function is only ever called from initialization code,
therefore can be marked as such, too. This, in turn, allows marking other
functions called only in this context as well.
The bios32_indirect variable can be marked as __initdata as it is only
referenced from __init functions now.
Signed-off-by: Mathias Krause <minipli@googlemail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Ingo Molnar <mingo@kernel.org>
Mathias Krause [Mon, 25 Aug 2014 21:26:38 +0000 (23:26 +0200)]
x86/PCI: Constify pci_mmcfg_probes[] array
The pci_mmcfg_probes[] array is only ever read, therefore make it const.
Signed-off-by: Mathias Krause <minipli@googlemail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Ingo Molnar <mingo@kernel.org>
Mathias Krause [Mon, 25 Aug 2014 21:26:37 +0000 (23:26 +0200)]
x86/PCI: Mark constants of pci_mmcfg_nvidia_mcp55() as __initconst
The constants in pci_mmcfg_nvidia_mcp55() need to be marked as __initconst
or they will remain in memory after init memory was released.
Signed-off-by: Mathias Krause <minipli@googlemail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Ingo Molnar <mingo@kernel.org>
Mathias Krause [Mon, 25 Aug 2014 21:26:36 +0000 (23:26 +0200)]
x86/PCI: Move __init annotation to the correct place
According to include/linux/init.h, the __init annotation should be added
immediately before the function name. However, for quite a few functions
in mmconfig-shared.c this is not the case. It's either before the return
type or even in the middle of it. Beside gcc still getting it right, we
should change them to comply to the rules of include/linux/init.h.
Signed-off-by: Mathias Krause <minipli@googlemail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Ingo Molnar <mingo@kernel.org>
Yinghai Lu [Sat, 23 Aug 2014 01:15:12 +0000 (18:15 -0700)]
PCI: pciehp: Stop disabling notifications during init
During pciehp initialization, we previously wrote two hotplug commands:
pciehp_probe
pcie_init
pcie_disable_notification
pcie_write_cmd # command 1
pcie_init_notification
pcie_enable_notification
pcie_write_cmd # command 2
For controllers with errata like Intel CF118, we previously waited for a
timeout before issuing the second hotplug command because the first command
only updates interrupt enable bits and is not a "real" hotplug command, so
the controller doesn't report Command Completed for it.
But there's no need to disable notifications in the first place. If BIOS
left them enabled, we could easily take an interrupt before disabling them,
so there's no benefit in disabling them for the tiny window before we
enable them.
Drop the unnecessary pcie_disable_notification() call.
[bhelgaas: changelog]
Link: http://www.intel.com/content/www/us/en/processors/xeon/xeon-e7-v2-spec-update.html
Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Yinghai Lu [Tue, 23 Sep 2014 02:36:09 +0000 (20:36 -0600)]
PCI: pciehp: Add more Slot Control debug output
Add more Slot Control debug output and move one print after
pcie_write_cmd() to be consistent with other debug output.
Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Yinghai Lu [Tue, 23 Sep 2014 02:07:35 +0000 (20:07 -0600)]
PCI: pciehp: Fix wait time in timeout message
When we warned about a timeout on a hotplug command, we previously printed
the time between calls to pcie_write_cmd(), without accounting for any time
spent actually waiting. Consider this sequence:
pcie_write_cmd
write SLTCTL
cmd_started = jiffies # T1
pcie_write_cmd
pcie_wait_cmd
now = jiffies # T2
wait_event_timeout # we may wait here
if (timeout)
ctrl_info("Timeout on command issued %u msec ago",
jiffies_to_msecs(now - cmd_started))
We previously printed (T2 - T1), but that doesn't include the time spent in
wait_event_timeout().
Fix this by using the current jiffies value, not the one cached before
calling wait_event_timeout().
[bhelgaas: changelog, use current jiffies instead of adding timeout]
Fixes:
40b960831cfa ("PCI: pciehp: Compute timeout from hotplug command start time")
Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Bjorn Helgaas [Tue, 23 Sep 2014 16:03:18 +0000 (10:03 -0600)]
Merge branch 'pci/hotplug' into next
* pci/hotplug:
PCI: pciehp: Prevent NULL dereference during probe
PCI: pciehp: Reduce PCIe slot_ctrl to 16 bits
PCI: Configure *all* devices, not just hot-added ones
PCI: Preserve MPS and MRRS when applying _HPX settings
PCI: Apply _HPP settings to all hot-added PCI devices
PCI: Preserve BIOS PCI_COMMAND_SERR and PCI_COMMAND_PARITY settings
PCI: Apply _HPP settings to PCIe devices as well as PCI and PCI-X
PCI: Remove unused pci_configure_slot()
ACPI / hotplug / PCI: Remove pci_configure_slot() usage
PCI: shpchp: Remove pci_configure_slot() usage
PCI: pciehp: Remove pci_configure_slot() usage
PCI: Add pci_configure_device() during enumeration
PCI: Move pci_configure_slot() to drivers/pci/probe.c
PCI: Shuffle pci-acpi.c functions to group them logically
PCI: Whitespace cleanup in pci-acpi.c
PCI: Move pci_get_hp_params() to drivers/pci/pci-acpi.c
PCI: pciehp: Configure hot-added display devices
PCI: Remove "no hotplug settings from platform" warning
Alex Williamson [Wed, 17 Sep 2014 14:59:36 +0000 (08:59 -0600)]
PCI: Add ACS quirk for Solarflare SFC9120 & SFC9140
Solarflare confirms that these devices do not allow peer-to-peer between
functions. Quirk them to allow IOMMU grouping to expose this isolation.
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Robert Stonehouse <rstonehouse@solarflare.com>
Fabio Estevam [Mon, 22 Sep 2014 20:52:07 +0000 (14:52 -0600)]
PCI: designware: Use NULL instead of false
of_get_address() expects pointers in the third and fourth parameters.
Pass NULL in order to fix the following sparse warnings:
drivers/pci/host/pcie-designware.c:433:51: warning: Using plain integer as NULL pointer
drivers/pci/host/pcie-designware.c:433:58: warning: Using plain integer as NULL pointer
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Lucas Stach <l.stach@pengutronix.de>
Acked-by: Jingoo Han <jg1.han@samsung.com>
Alex Williamson [Wed, 17 Sep 2014 16:41:13 +0000 (10:41 -0600)]
PCI: Remove unused pci_get_dma_source()
pci_get_dma_source() is unused, so remove it. We now have
dma_alias_devfn() to describe this.
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Alex Williamson [Mon, 22 Sep 2014 20:46:13 +0000 (14:46 -0600)]
PCI: Remove unused pci_find_upstream_pcie_bridge()
pci_find_upstream_pcie_bridge() is unused, so remove it.
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Thomas Petazzoni [Wed, 17 Sep 2014 15:58:27 +0000 (17:58 +0200)]
PCI: mvebu: Fix uninitialized variable in mvebu_get_tgt_attr()
Geert Uytterhoeven reported a warning when building pci-mvebu:
drivers/pci/host/pci-mvebu.c: In function 'mvebu_get_tgt_attr':
drivers/pci/host/pci-mvebu.c:887:39: warning: 'rtype' may be used uninitialized in this function [-Wmaybe-uninitialized]
if (slot == PCI_SLOT(devfn) && type == rtype) {
^
And indeed, the code of mvebu_get_tgt_attr() may lead to the usage of rtype
when being uninitialized, even though it would only happen if we had
entries other than I/O space and 32 bits memory space.
This commit fixes that by simply skipping the current DT range being
considered, if it doesn't match the resource type we're looking for.
Reported-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
CC: stable@vger.kernel.org # v3.12+
Mathias Krause [Mon, 25 Aug 2014 21:26:35 +0000 (23:26 +0200)]
x86/PCI: Mark DMI tables as initialization data
The DMI tables are only used in __init code, thereby can be marked as
initialization data, too. The same is true for the callback functions
referenced from the DMI tables.
This moves ~9.6 kB of code and r/o data to the init sections, marking the
memory for release after initialization.
Signed-off-by: Mathias Krause <minipli@googlemail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Ingo Molnar <mingo@kernel.org>
Pratyush Anand [Wed, 3 Sep 2014 05:20:49 +0000 (10:50 +0530)]
PCI: spear: Pass config resource through reg property
PCIe configuration space should be passed through reg property, rather than
through ranges property. This patch does the correction for SPEAr13XX
SOCs.
Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Mohit Kumar <mohit.kumar@st.com>
Ricardo Ribalda Delgado [Wed, 27 Aug 2014 12:57:57 +0000 (14:57 +0200)]
PCI: Generate uppercase hex for modalias interface class
Some implementations of modprobe fail to load the driver for a PCI device
automatically because the "interface" part of the modalias from the kernel
is lowercase, and the modalias from file2alias is uppercase.
The "interface" is the low-order byte of the Class Code, defined in PCI
r3.0, Appendix D. Most interface types defined in the spec do not use
alpha characters, so they won't be affected. For example, 00h, 01h, 10h,
20h, etc. are unaffected.
Print the "interface" byte of the Class Code in uppercase hex, as we
already do for the Vendor ID, Device ID, Class, etc.
[bhelgaas: changelog]
Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
CC: stable@vger.kernel.org
Bjorn Helgaas [Mon, 22 Sep 2014 18:31:10 +0000 (12:31 -0600)]
Merge branches 'pci/host-designware', 'pci/host-imx6', 'pci/host-keystone', 'pci/host-tegra' and 'pci/host-xilinx' into next
* pci/host-designware:
PCI: designware: Fold struct pcie_port_info into struct pcie_port
* pci/host-imx6:
PCI: imx6: Delay enabling reference clock for SS until it stabilizes
* pci/host-keystone:
PCI: keystone: Set device ID based on SoC to support multiple ports
PCI: keystone: Assume controller is already in RC mode
PCI: keystone: Limit MRSS for all downstream devices
* pci/host-tegra:
PCI: tegra: Add Tegra124 support
PCI: tegra: Make sure the PCIe PLL is really reset
PCI: tegra: Fix extended configuration space mapping
PCI: tegra: Clear CLKREQ# enable on port disable
* pci/host-xilinx:
PCI: xilinx: Fix xilinx_pcie_assign_msi() return value test
Bjorn Helgaas [Mon, 22 Sep 2014 18:31:01 +0000 (12:31 -0600)]
Merge branches 'pci/enumeration', 'pci/misc' and 'pci/virtualization' into next
* pci/enumeration:
PCI: Enable CRS Software Visibility for root port if it is supported
PCI: Check only the Vendor ID to identify Configuration Request Retry
* pci/misc:
PCI: Parenthesize PCI_DEVID and PCI_VPD_LRDT_ID parameters
PCI: Increase IBM ipr SAS Crocodile BARs to at least system page size
PCI/AER: Make <linux/aer.h> standalone includable
* pci/virtualization:
PCI: Use device flag helper functions
xen/pciback: Use PCI device flag helper functions
KVM: Use PCI device flag helper functions
PCI: Add device flag helper functions
PCI: Assume all Mellanox devices have broken INTx masking
Dan Carpenter [Tue, 9 Sep 2014 12:11:50 +0000 (15:11 +0300)]
PCI: xilinx: Fix xilinx_pcie_assign_msi() return value test
We should be testing "hwirq" instead of "irq". "irq" is unsigned so it's
never less than zero. Also it's uninitialized.
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Srikanth Thokala <sthokal@xilinx.com>
Megan Kamiya [Sat, 6 Sep 2014 03:19:10 +0000 (20:19 -0700)]
PCI: Parenthesize PCI_DEVID and PCI_VPD_LRDT_ID parameters
Add parentheses around parameters in PCI_DEVID and PCI_VPD_LRDT_ID macros
to prevent possible expansion errors as described by the CERT Secure Coding
Standard: PRE01-C: Use parentheses within macros around parameter names
Tested-by: Aaron Brown <aaron.f.brown@intel.com>
Signed-off-by: Megan Kamiya <megan.a.kamiya@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Thierry Reding [Tue, 26 Aug 2014 15:11:38 +0000 (17:11 +0200)]
PCI: tegra: Add Tegra124 support
The PCIe controller on Tegra124 has two root ports that can be used in a
x4/x1 or x2/x1 configuration and can run at PCIe 2.0 link speeds (up to
5 GT/s). The PHY programming has been moved into a separate controller, so
the driver now needs to request an external PHY referenced using the device
tree.
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Eric Yuen [Tue, 26 Aug 2014 15:11:37 +0000 (17:11 +0200)]
PCI: tegra: Make sure the PCIe PLL is really reset
Depending on the prior state of the controller, the PLL reset may not be
pulsed. Clear the register bit and set it after a small delay to ensure
that the PLL is really reset.
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Eric Yuen <eyuen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Peter Daifuku [Tue, 26 Aug 2014 15:11:36 +0000 (17:11 +0200)]
PCI: tegra: Fix extended configuration space mapping
The 16 chunks of 64 KiB that need to be stitched together to make up the
configuration space for one bus (1 MiB) are located 24 bits (== 16 MiB)
apart in physical address space. This is determined by the start of the
extended register field (bits 24-27) in the physical mapping.
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Thierry Reding [Tue, 26 Aug 2014 15:11:35 +0000 (17:11 +0200)]
PCI: tegra: Clear CLKREQ# enable on port disable
When a root port is disabled, disable the CLKREQ# signal if available.
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Douglas Lehr [Wed, 20 Aug 2014 23:26:52 +0000 (09:26 +1000)]
PCI: Increase IBM ipr SAS Crocodile BARs to at least system page size
The Crocodile chip occasionally comes up with 4k and 8k BAR sizes. Due to
an erratum, setting the SR-IOV page size causes the physical function BARs
to expand to the system page size. Since ppc64 uses 64k pages, when Linux
tries to assign the smaller resource sizes to the now 64k BARs the address
will be truncated and the BARs will overlap.
Force Linux to allocate the resource as a full page, which avoids the
overlap.
[bhelgaas: print expanded resource, too]
Signed-off-by: Douglas Lehr <dllehr@us.ibm.com>
Signed-off-by: Anton Blanchard <anton@samba.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Milton Miller <miltonm@us.ibm.com>
CC: stable@vger.kernel.org
Thierry Reding [Tue, 5 Aug 2014 12:08:55 +0000 (14:08 +0200)]
PCI/AER: Make <linux/aer.h> standalone includable
The header file references u16 and u32 types, but they are not defined in
the header nor does the header pull in the necessary includes for them.
This causes build breakage when the file is included without any of the
dependencies being satisfied from somewhere else.
Fix this by including linux/types.h (for u16 and u32).
[bhelgaas: removed pci_dev declaration (already added by
5ccb8225abf2)]
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Ethan Zhao [Tue, 9 Sep 2014 02:21:28 +0000 (10:21 +0800)]
PCI: Use device flag helper functions
Use PCI device flag helper functions when checking whether a device is
assigned. No functional change.
Signed-off-by: Ethan Zhao <ethan.zhao@oracle.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Ethan Zhao [Tue, 9 Sep 2014 02:21:27 +0000 (10:21 +0800)]
xen/pciback: Use PCI device flag helper functions
Use PCI device flag helper functions when assigning or releasing device.
No functional change.
Signed-off-by: Ethan Zhao <ethan.zhao@oracle.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Acked-by: David Vrabel <david.vrabel@citrix.com>
Ethan Zhao [Tue, 9 Sep 2014 02:21:26 +0000 (10:21 +0800)]
KVM: Use PCI device flag helper functions
Use PCI device flag helper functions when assigning or releasing device.
No functional change.
Signed-off-by: Ethan Zhao <ethan.zhao@oracle.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Ethan Zhao [Tue, 9 Sep 2014 02:21:25 +0000 (10:21 +0800)]
PCI: Add device flag helper functions
Add helper functions to hide direct device flag operations:
void pci_set_dev_assigned(struct pci_dev *dev);
void pci_clear_dev_assigned(struct pci_dev *dev);
bool pci_is_dev_assigned(struct pci_dev *dev);
Signed-off-by: Ethan Zhao <ethan.zhao@oracle.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Murali Karicheri [Wed, 10 Sep 2014 17:12:39 +0000 (13:12 -0400)]
PCI: keystone: Set device ID based on SoC to support multiple ports
K2E SoC has two PCI ports. The SATA controller is connected to second PCI
port (port 1). To support multiple port handling in Keystone PCI driver,
read the PCI device ID dynamically by iomap/read/unmap during probe and
save it in driver's private data and update it in host init code. The PCI
device ID field in the RC's config space is not filled by default by the
hardware and has to be updated by the PCI driver by reading the same from
the SoC register indicated by reg index #2 in DT bindings.
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Murali Karicheri [Wed, 10 Sep 2014 17:12:38 +0000 (13:12 -0400)]
PCI: keystone: Assume controller is already in RC mode
Keystone PCI hardware supports both RC and EP modes and devcfg register has
bits to boot strap the device to either of these modes. It seems proper to
add this functionality to the boot loader rather than in the driver as
device will be operating in either mode, not both any time. Currently the
driver supports only RC mode and hence register configuration in the driver
is not needed and the driver can assume the hardware is in RC mode.
Also update the DT documentation accordingly.
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Murali Karicheri [Mon, 8 Sep 2014 17:03:34 +0000 (13:03 -0400)]
PCI: keystone: Limit MRSS for all downstream devices
Keystone PCIe controller has a limitation that memory read request size
must not exceed 256 bytes. This is a hardware limitation. Add a quirk to
force this limit on all downstream devices by updating MRRS.
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Andreas Noever [Tue, 16 Sep 2014 21:16:02 +0000 (15:16 -0600)]
PCI: pciehp: Prevent NULL dereference during probe
pciehp assumes that dev->subordinate, the struct pci_bus for a bridge's
secondary bus, exists. But we do not create that bus if we run out of bus
numbers during enumeration. This leads to a NULL dereference in
init_slot() (and other places).
Change pciehp_probe() to return -ENODEV when no secondary bus is present.
Signed-off-by: Andreas Noever <andreas.noever@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
CC: stable@vger.kernel.org # v3.2+
Bjorn Helgaas [Fri, 15 Aug 2014 23:18:44 +0000 (17:18 -0600)]
PCI: pciehp: Reduce PCIe slot_ctrl to 16 bits
4283c70e91dc ("PCI: pciehp: Make pcie_wait_cmd() self-contained") added
a cache of the most recent command written to the Slot Control register.
This register is only 16 bits wide, but the cache ("slot_ctrl") is 32 bits.
Reduce slot_ctrl to a u16 so it matches the register size. No functional
change.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Bjorn Helgaas [Sat, 30 Aug 2014 13:23:01 +0000 (07:23 -0600)]
PCI: Configure *all* devices, not just hot-added ones
There's not really a good way to determine whether firmware has already
configured a device with _HPP/_HPX settings. On legacy systems, the BIOS
has probably configured everything, but on UEFI systems it is not required
to do so.
Per the PCI Firmware Specification, rev 3.1, sec 3.5, if PCI_COMMAND_IO or
PCI_COMMAND_MEMORY is set, we can assume firmware has set the corresponding
BARs and maybe we can assume it has configured the rest of the device. And
if a bridge has PCI_COMMAND_PARITY or PCI_COMMAND_SERR set, we can assume
firmware has configured the bridge. But we can't tell much about devices
without BARs.
I think it should be safe to apply _HPP and _HPX settings anyway, even if
firmware has already configured the device, so configure everything we
find.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Yinghai Lu <yinghai@kernel.org>
Bjorn Helgaas [Wed, 3 Sep 2014 19:26:29 +0000 (13:26 -0600)]
PCI: Preserve MPS and MRRS when applying _HPX settings
Linux manages MPS and MRRS settings to keep them consistent across the PCIe
fabric. BIOS doesn't participate in this Linux management, so ignore that
part of any _HPX settings it supplies.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Yinghai Lu <yinghai@kernel.org>
Bjorn Helgaas [Sat, 30 Aug 2014 13:22:13 +0000 (07:22 -0600)]
PCI: Apply _HPP settings to all hot-added PCI devices
We currently apply _HPP settings only to:
- non-bridge devices, and
- PCI-to-PCI bridges
i.e., we do not apply them to PCI-to-ISA bridges and the like. It has been
that way since _HPP support was added by
40abb96c51bb ("pciehp: Fix
programming hotplug parameters"), but I don't think there's any reason to
exclude these other bridges.
Apply _HPP settings to hot-added PCI devices of any type.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Yinghai Lu <yinghai@kernel.org>
Bjorn Helgaas [Wed, 27 Aug 2014 20:38:14 +0000 (14:38 -0600)]
PCI: Preserve BIOS PCI_COMMAND_SERR and PCI_COMMAND_PARITY settings
Do not clear PCI_COMMAND_SERR or PCI_COMMAND_PARITY based on _HPP. The
spec (ACPI rev 5.0, sec 6.2.7) says that when "Enable SERR" is set to 1,
we should enable SERR in the command register. It says nothing about
*disabling* SERR or PERR; in fact, the example in 6.2.7.1 says we should
leave PERR alone unless "Enable PERR" is 1.
For hot-added devices, this probably doesn't matter because they power up
with these bits cleared. But in addition to hot-plugged devices, the spec
allows the platform to use _HPP for "configuration of PCI devices not
configured by the BIOS at system boot," and it may make a difference for
devices present at boot.
This change means that if BIOS enables SERR or PERR on a device, and it
supplies _HPP or _HPX with the SERR or PERR bits *cleared*, we will now
leave SERR or PERR reporting enabled on that device instead of disabling it
as we previously did.
See also
40abb96c51bb ("pciehp: Fix programming hotplug parameters"), where
this code was first added.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Yinghai Lu <yinghai@kernel.org>
Bjorn Helgaas [Sat, 30 Aug 2014 00:10:19 +0000 (18:10 -0600)]
PCI: Apply _HPP settings to PCIe devices as well as PCI and PCI-X
The ACPI _HPP method was defined before PCIe existed, so its documentation
only mentions PCI. The _HPX Type 0 setting record is essentially identical
to _HPP, but the spec (ACPI rev 5.0, sec 6.2.8.1) says it should be applied
to PCI, PCI-X, and PCIe devices, with settings being ignored if they are
not applicable.
Some platforms with both conventional PCI and PCIe devices provide only
_HPP (not _HPX), so treat _HPP the same way as an _HPX Type 0 record and
apply it to PCIe devices as well as PCI and PCI-X.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Yinghai Lu <yinghai@kernel.org>
Bjorn Helgaas [Thu, 28 Aug 2014 18:21:44 +0000 (12:21 -0600)]
PCI: Remove unused pci_configure_slot()
All pci_configure_slot() uses have been removed, so remove the definition
as well.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Yinghai Lu <yinghai@kernel.org>
Bjorn Helgaas [Thu, 28 Aug 2014 17:59:41 +0000 (11:59 -0600)]
ACPI / hotplug / PCI: Remove pci_configure_slot() usage
We now configure each PCI device as it is enumerated, in pci_device_add(),
so remove the configuration done in acpiphp.
That configuration, in pci_configure_device(), does not include the
MPS/MRRS configuration done by pcie_bus_configure_settings(), so keep
that here.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Yinghai Lu <yinghai@kernel.org>
Bjorn Helgaas [Thu, 28 Aug 2014 18:18:37 +0000 (12:18 -0600)]
PCI: shpchp: Remove pci_configure_slot() usage
We now configure each PCI device as it is enumerated, in pci_device_add(),
so remove the configuration done in shpchp.
That configuration, in pci_configure_device(), does not include the
MPS/MRRS configuration done by pcie_bus_configure_settings(), so keep
that here.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Yinghai Lu <yinghai@kernel.org>
Bjorn Helgaas [Thu, 28 Aug 2014 18:13:51 +0000 (12:13 -0600)]
PCI: pciehp: Remove pci_configure_slot() usage
We now configure each PCI device as it is enumerated, in pci_device_add(),
so remove the configuration done in pciehp.
That configuration, in pci_configure_device(), does not include the
MPS/MRRS configuration done by pcie_bus_configure_settings(), so keep
that here.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Yinghai Lu <yinghai@kernel.org>
Bjorn Helgaas [Wed, 27 Aug 2014 20:29:47 +0000 (14:29 -0600)]
PCI: Add pci_configure_device() during enumeration
Some platforms can tell the OS how to configure PCI devices, e.g., how to
set cache line size, error reporting enables, etc. ACPI defines _HPP and
_HPX methods for this purpose.
This configuration was previously done by some of the hotplug drivers using
pci_configure_slot(). But not all hotplug drivers did this, and per the
spec (ACPI rev 5.0, sec 6.2.7), we can also do it for "devices not
configured by the BIOS at system boot."
Move this configuration into the PCI core by adding pci_configure_device()
and calling it from pci_device_add(), so we do this for all devices as we
enumerate them.
This is based on pci_configure_slot(), which is used by hotplug drivers.
I omitted:
- pcie_bus_configure_settings() because it configures MPS and MRRS, which
requires global knowledge of the fabric and must be done later, and
- configuration of subordinate devices; that will happen when we call
pci_device_add() for those devices.
Because pci_configure_slot() was only done by hotplug drivers, this initial
version of pci_configure_device() only configures hot-added devices,
ignoring anything added during boot.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Yinghai Lu <yinghai@kernel.org>
Bjorn Helgaas [Sat, 13 Sep 2014 02:02:00 +0000 (20:02 -0600)]
PCI: Move pci_configure_slot() to drivers/pci/probe.c
Move pci_configure_slot() and related functions from
drivers/pci/hotplug/pcihp_slot to drivers/pci/probe.c.
This is to prepare for doing device configuration during the normal
enumeration process instead of just after hot-add.
No functional change.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Bjorn Helgaas [Fri, 12 Sep 2014 21:36:29 +0000 (15:36 -0600)]
PCI: Shuffle pci-acpi.c functions to group them logically
Move code around to put all the ACPI power management stuff together and
all the pieces related to ACPI methods (_CBA, _HPP, _HPX) together.
No functional change.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Bjorn Helgaas [Fri, 12 Sep 2014 21:29:55 +0000 (15:29 -0600)]
PCI: Whitespace cleanup in pci-acpi.c
Whitespace fixes only; no functional change.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Bjorn Helgaas [Fri, 12 Sep 2014 21:23:14 +0000 (15:23 -0600)]
PCI: Move pci_get_hp_params() to drivers/pci/pci-acpi.c
Move pci_get_hp_params() and related functions from
drivers/pci/hotplug/acpi_pcihp.c to drivers/pci/pci-acpi.c.
Previously, pci_get_hp_params() was used only by hotplug drivers. But
future changes will move this into the normal device enumeration process,
so it will be used even when CONFIG_HOTPLUG_PCI is not set.
No functional change.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Bjorn Helgaas [Thu, 28 Aug 2014 17:12:50 +0000 (11:12 -0600)]
PCI: pciehp: Configure hot-added display devices
We configure cache line size and other settings of hot-added devices, e.g.,
based on ACPI _HPP or _HPX methods. Previously we skipped this for display
devices, but ACPI rev 5.0, sec 6.2.7 and 6.2.8 have no requirement to skip
them.
Remove the check so we configure display devices the same way we configure
other devices.
See also
ac81860ea073 ("PCI: hotplug: pciehp: Removed check for hotplug of
display devices").
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Yinghai Lu <yinghai@kernel.org>
Bjorn Helgaas [Fri, 12 Sep 2014 14:50:10 +0000 (08:50 -0600)]
PCI: Remove "no hotplug settings from platform" warning
We print way too many messages like this:
pci 0000:00:00.0: no hotplug settings from platform
pci 0000:00:00.0: using default PCI settings
This usually happens when the platform doesn't supply an ACPI _HPP method,
but the method is optional, so there's no point in warning about it.
Not only are the messages useless, but we call pci_configure_slot() far too
many times, so they're repeated many times. I'll fix the overuse of
pci_configure_slot() too, but that will wait until the next merge window.
For now, just remove both log messages.
Link: https://bugzilla.kernel.org/show_bug.cgi?id=84391
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Yinghai Lu <yinghai@kernel.org>
Rajat Jain [Tue, 2 Sep 2014 23:26:00 +0000 (16:26 -0700)]
PCI: Enable CRS Software Visibility for root port if it is supported
Per PCIe r3.0, sec 2.3.2, an endpoint may respond to a Configuration
Request with a Completion with Configuration Request Retry Status (CRS).
This terminates the Configuration Request.
When the CRS Software Visibility feature is disabled (as it is by default),
a Root Complex must handle a CRS Completion by re-issuing the Configuration
Request. This is invisible to software. From the CPU's point of view, an
endpoint that always responds with CRS causes a hang because the Root
Complex never supplies data to complete the CPU read.
When CRS Software Visibility is enabled, a Root Complex that receives a CRS
Completion for a read of the Vendor ID must return data of 0x0001. The
Vendor ID of 0x0001 indicates to software that the endpoint is not ready.
We now have more devices that require CRS Software Visibility. For
example, a PLX 8713 NT bridge may respond with CRS until it has been
configured via I2C, and the I2C configuration is completely independent of
PCI enumeration.
Enable CRS Software Visibility if it is supported. This allows a system
with such a device to work (though the PCI core times out waiting for it to
become ready, and we have to rescan the bus after it is ready).
This essentially reverts
ad7edfe04908 ("[PCI] Do not enable CRS Software
Visibility by default"). The failures that led to
ad7edfe04908 should be
addressed by
89665a6a7140 ("PCI: Check only the Vendor ID to identify
Configuration Request Retry").
[bhelgaas: changelog]
Link: http://lkml.kernel.org/r/20071029061532.5d10dfc6@snowcone
Link: http://lkml.kernel.org/r/alpine.LFD.0.9999.0712271023090.21557@woody.linux-foundation.org
Signed-off-by: Rajat Jain <rajatxjain@gmail.com>
Signed-off-by: Rajat Jain <rajatjain@juniper.net>
Signed-off-by: Guenter Roeck <groeck@juniper.net>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Rajat Jain [Mon, 8 Sep 2014 21:19:49 +0000 (14:19 -0700)]
PCI: Check only the Vendor ID to identify Configuration Request Retry
Per PCIe r3.0, sec 2.3.2, if a Root Complex
- has Configuration Request Retry Status Software Visibility enabled,
- issues a Configuration Read of both bytes of the Vendor ID, and
- receives a Completion with Configuration Request Retry Status (CRS),
it must complete the request to the host by fabricating data of 0x0001 for
the Vendor ID and 0xff for any additional bytes in the request.
Linux issues a single config read for the four bytes containing the Vendor
ID and the Device ID. Previously we checked all four bytes for 0xffff0001
to identify CRS.
However, it is only the Vendor ID that really indicates CRS, because it's
sufficient to read only those two bytes. Checking the Device ID verifies
spec compliance but doesn't add any information.
Some Root Complexes appear to indicate CRS by returning 0x0001 for the
Vendor ID along with the actual the Device ID. Previously we interpreted
that as a valid Vendor/Device ID pair, although 0x0001 is reserved and
cannot be a valid Vendor ID.
[bhelgaas: changelog]
Link: http://lkml.kernel.org/r/4729FC36.3040000@gmail.com
Signed-off-by: Rajat Jain <rajatxjain@gmail.com>
Signed-off-by: Rajat Jain <rajatjain@juniper.net>
Signed-off-by: Guenter Roeck <groeck@juniper.net>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Gavin Shan [Fri, 5 Sep 2014 21:35:30 +0000 (15:35 -0600)]
PCI: Assume all Mellanox devices have broken INTx masking
The VFIO driver routes LSI interrupts by capturing, masking, and then
delivering. When passing though Mellanox adapters from host to guest,
interrupt storm are reported from host and guest. That's because the PCI
command register INTx Disable bit doesn't work on Mellanox devices.
# lspci | grep Mellanox
0001:05:00.0 Ethernet controller: Mellanox Technologies MT27500 Family [ConnectX-3]
0005:01:00.0 Ethernet controller: Mellanox Technologies MT26448 [ConnectX EN 10GigE, PCIe 2.0 5GT/s] (rev b0)
Amir Vadai confirmed that all Mellanox devices have same problem.
The patch marks broken INTx masking for all Mellanox adapters.
Suggested-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-By: Amir Vadai <amirv@mellanox.com>
Pratyush Anand [Fri, 5 Sep 2014 23:48:54 +0000 (17:48 -0600)]
PCI: designware: Fold struct pcie_port_info into struct pcie_port
The struct pcie_port_info doesn't contain any exclusive information
compared to other elements of struct pcie_port. So, keeping a separate
structure does not seem very logical. Therefore remove this struct and
embed its elements directly into struct pcie_port.
Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Mohit Kumar <mohit.kumar@st.com>
Tim Harvey [Fri, 8 Aug 2014 06:36:40 +0000 (23:36 -0700)]
PCI: imx6: Delay enabling reference clock for SS until it stabilizes
According to the IMX6 reference manuals, REF_SSP_EN (Reference clock enable
for SS function) must remain deasserted until the reference clock is
running at the appropriate frequency.
Delay enabling the reference clock for the SS function until it has
stabilized. This prevents a high link failure rate (>5%) on certain IMX6
boards at various temperatures.
[bhelgaas: reword changelog slightly]
Tested-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Lucas Stach <l.stach@pengutronix.de>
Bjorn Helgaas [Fri, 5 Sep 2014 16:57:20 +0000 (10:57 -0600)]
Merge branches 'pci/misc', 'pci/pm', 'pci/host-designware', 'pci/host-imx6', 'pci/host-keystone', 'pci/host-tegra' and 'pci/host-xilinx' into next
* pci/misc:
PCI/AER: Make <linux/aer.h> standalone includable
PCI: Remove unnecessary variable in pci_add_dynid()
* pci/pm:
PCI/PM: Allow PCI devices to be put into D3cold during system suspend
PCI/PM: Drop unused runtime PM support code for PCIe ports
* pci/host-designware:
PCI: designware: Check private_data validity in single place
PCI: designware: Remove pci_assign_unassigned_resources() from dw_pcie_host_init()
PCI: designware: Use pci_create_root_bus() instead of pci_scan_root_bus()
PCI: designware: Parse bus-range property from devicetree
PCI: designware: Add support for v3.65 hardware
* pci/host-imx6:
PCI: imx6: Probe in module_init(), not fs_initcall()
PCI: designware: Remove pci_assign_unassigned_resources() from dw_pcie_host_init()
PCI: designware: Use pci_create_root_bus() instead of pci_scan_root_bus()
PCI: designware: Parse bus-range property from devicetree
PCI: imx6: Put LTSSM in "Detect" state before disabling it
MAINTAINERS: Add Lucas Stach as co-maintainer for i.MX6 PCI driver
PCI: designware: Add support for v3.65 hardware
* pci/host-keystone:
PCI: keystone: Add TI Keystone PCIe driver
PCI: designware: Add support for v3.65 hardware
* pci/host-tegra:
PCI: tegra: Implement a proper resource hierarchy
PCI: tegra: Add missing cleanup in error path and tegra_msi_teardown_irq()
resources: Add device-managed request/release_resource()
* pci/host-xilinx:
PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver
Conflicts:
drivers/pci/host/Kconfig
drivers/pci/host/Makefile
Lucas Stach [Fri, 5 Sep 2014 15:37:55 +0000 (09:37 -0600)]
PCI: designware: Check private_data validity in single place
The driver had checks for this sprinkled all over. As we call
sys_to_pcie() before every instance of this check, we can move the
check to this single location to make things clear.
Removing the statements after BUG[_ON]() is safe as the kernel is halted at
this point anyway.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Jingoo Han <jg1.han@samsung.com>
Acked-by: Mohit Kumar <mohit.kumar@st.com>
Lucas Stach [Fri, 5 Sep 2014 15:36:48 +0000 (09:36 -0600)]
PCI: imx6: Probe in module_init(), not fs_initcall()
This effectively reverts
f216f57ffe6e ("PCI: imx6: Probe the PCIe in
fs_initcall()") as the resource allocation issue that prevented the driver
from working properly at module_initcall level is now fixed in
pcie-designware.c.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Richard Zhu <r65037@freescale.com>
Bjorn Helgaas [Fri, 5 Sep 2014 15:28:08 +0000 (09:28 -0600)]
Merge branch 'pci/host-designware' into pci/host-imx6
* pci/host-designware:
PCI: designware: Remove pci_assign_unassigned_resources() from dw_pcie_host_init()
PCI: designware: Use pci_create_root_bus() instead of pci_scan_root_bus()
PCI: designware: Parse bus-range property from devicetree
PCI: designware: Add support for v3.65 hardware
Thierry Reding [Tue, 5 Aug 2014 12:08:55 +0000 (14:08 +0200)]
PCI/AER: Make <linux/aer.h> standalone includable
The header file references u16 and u32 types, but they are not defined in
the header nor does the header pull in the necessary includes for them.
This causes build breakage when the file is included without any of the
dependencies being satisfied from somewhere else.
Fix this by including linux/types.h (for u16 and u32).
[bhelgaas: removed pci_dev declaration (already added by
5ccb8225abf2)]
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Lucas Stach [Wed, 23 Jul 2014 17:52:40 +0000 (19:52 +0200)]
PCI: designware: Remove pci_assign_unassigned_resources() from dw_pcie_host_init()
The pci_common_init_dev() call right before will already handle the device
resource allocation, so this call was a no-op.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Mohit Kumar <mohit.kumar@st.com>
Lucas Stach [Wed, 23 Jul 2014 17:52:39 +0000 (19:52 +0200)]
PCI: designware: Use pci_create_root_bus() instead of pci_scan_root_bus()
Use pci_create_root_bus() similar to other PCI host controller drivers.
The main problem with pci_scan_root_bus() is that it not only creates the
root bus, but also activates all devices on the bus. This triggers PCI
device driver probe routines, which fail because resources haven't been
allocated.
To work around this we made sure that the host controller driver is probed
early and finishes resource allocation before any other device drivers are
registered. Switching to pci_create_root_bus() allows us to get rid of
this special handling.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Pratyush Anand <pratyush.anand@st.com>
Acked-by: Mohit Kumar <mohit.kumar@st.com>
Lucas Stach [Wed, 23 Jul 2014 17:52:38 +0000 (19:52 +0200)]
PCI: designware: Parse bus-range property from devicetree
This allows to explicitly specify the covered bus numbers in the
devicetree, which will come in handy once we see a SoC with more than one
PCIe host controller instance.
Previously the driver relied on the behavior of pci_scan_root_bus() to fill
in a range of 0x00-0xff if no valid range was found. We fall back to the
same range if no valid DT entry was found to keep backwards compatibility,
but now do it explicitly.
[bhelgaas: use %pR in error message to avoid duplication]
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Pratyush Anand <pratyush.anand@st.com>
Acked-by: Mohit Kumar <mohit.kumar@st.com>
Murali Karicheri [Tue, 2 Sep 2014 23:26:19 +0000 (17:26 -0600)]
PCI: keystone: Add TI Keystone PCIe driver
The Keystone PCIe controller is based on v3.65 version of the Designware
h/w. Main differences are:
1. No ATU support
2. Legacy and MSI IRQ functions are implemented in application register
space
3. MSI interrupts are multiplexed over 8 IRQ lines to the Host side.
All of the application register space handing code is organized into
pci-keystone-dw.c and the functions are called from pci-keystone.c to
implement PCI controller driver. Also add necessary DT documentation and
update the MAINTAINERS file for the driver.
[bhelgaas: spelling and whitespace fixes]
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
CC: Russell King <linux@arm.linux.org.uk>
CC: Grant Likely <grant.likely@linaro.org>
CC: Rob Herring <robh+dt@kernel.org>
CC: Mohit Kumar <mohit.kumar@st.com>
CC: Pratyush Anand <pratyush.anand@st.com>
CC: Jingoo Han <jg1.han@samsung.com>
CC: Richard Zhu <r65037@freescale.com>
CC: Kishon Vijay Abraham I <kishon@ti.com>
CC: Marek Vasut <marex@denx.de>
CC: Arnd Bergmann <arnd@arndb.de>
CC: Pawel Moll <pawel.moll@arm.com>
CC: Mark Rutland <mark.rutland@arm.com>
CC: Ian Campbell <ijc+devicetree@hellion.org.uk>
CC: Kumar Gala <galak@codeaurora.org>
CC: Randy Dunlap <rdunlap@infradead.org>
CC: Grant Likely <grant.likely@linaro.org>
Thierry Reding [Fri, 1 Aug 2014 12:15:11 +0000 (14:15 +0200)]
PCI: tegra: Implement a proper resource hierarchy
Currently the resource hierarchy generated from the PCIe host bridge is
completely flat:
$ cat /proc/iomem
00000000-
00000fff : /pcie-controller@
00003000/pci@1,0
00003000-
000037ff : pads
00003800-
000039ff : afi
10000000-
1fffffff : cs
28000000-
28003fff : r8169
28004000-
28004fff : r8169
...
The host bridge driver doesn't request all the resources that are used.
Windows allocated to each of the root ports aren't tracked, so there is no
way for resources allocated to individual devices to be matched up with the
correct parent resource by the PCI core.
This patch addresses this in two steps. It first takes the union of all
regions associated with the PCIe host bridge (control registers, root port
registers, configuration space, I/O and prefetchable as well as non-
prefetchable memory regions) and uses it as the new root of the resource
hierarchy.
Subsequently, regions are allocated from within this new root resource so
that the resource tree looks much more like what's expected:
# cat /proc/iomem
00000000-
3fffffff : /pcie-controller@
00003000
00000000-
00000fff : /pcie-controller@
00003000/pci@1,0
00003000-
000037ff : pads
00003800-
000039ff : afi
10000000-
1fffffff : cs
20000000-
27ffffff : non-prefetchable
28000000-
3fffffff : prefetchable
28000000-
280fffff : PCI Bus 0000:01
28000000-
28003fff : 0000:01:00.0
28000000-
28003fff : r8169
28004000-
28004fff : 0000:01:00.0
28004000-
28004fff : r8169
...
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Jisheng Zhang [Tue, 29 Jul 2014 01:33:30 +0000 (09:33 +0800)]
PCI: tegra: Add missing cleanup in error path and tegra_msi_teardown_irq()
We should call tegra_msi_free() to free the MSI bit if irq_create_mapping()
fails. And we need to dispose the IRQ mapping during IRQ teardown.
[bhelgaas: made irqd_to_hwirq() change suggested by Thierry]
Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Fri, 1 Aug 2014 12:15:10 +0000 (14:15 +0200)]
resources: Add device-managed request/release_resource()
Provide device-managed implementations of the request_resource() and
release_resource() functions. Upon failure to request a resource, the new
devm_request_resource() function will output an error message for
consistent error reporting.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Tejun Heo <tj@kernel.org>
Lucas Stach [Thu, 31 Jul 2014 18:16:05 +0000 (20:16 +0200)]
PCI: imx6: Put LTSSM in "Detect" state before disabling it
This fixes a boot hang observed when the bootloader already enabled the
PCIe link for its own use. The fundamental problem is that Freescale
forgot to wire up the core reset, so software doesn't have a sane way to
get the core into a defined state.
According to the DW PCIe core reference manual, configuration of the core
may only happen when the LTSSM is disabled, so this is one of the first
things we need to do. Apparently this isn't safe to do when the LTSSM is in
any state other than "detect" as we observe an instant machine hang when
trying to do so while the link is already up.
As a workaround, force LTSSM into detect state right before hitting the
disable switch. There is still a race window because the LTSSM may
transition out of "detect" before we can disable it, but it's the best
we can do for now.
[bhelgaas: mention race window]
Link: http://lkml.kernel.org/r/1406830565-23450-3-git-send-email-l.stach@pengutronix.de
Reported-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Tim Harvey <tharvey@gateworks.com>
Lucas Stach [Thu, 31 Jul 2014 18:16:04 +0000 (20:16 +0200)]
MAINTAINERS: Add Lucas Stach as co-maintainer for i.MX6 PCI driver
Also drop Shawn Guo per his request.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Shawn Guo <shawn.guo@freescale.com>
Acked-by: Richard Zhu <r65037@freescale.com>
Acked-by: Jingoo Han <jg1.han@samsung.com>
Srikanth Thokala [Wed, 20 Aug 2014 16:26:02 +0000 (21:56 +0530)]
PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver
This is the driver for Xilinx AXI PCIe Host Bridge Soft IP.
[bhelgaas: minor whitespace fixes]
Signed-off-by: Srikanth Thokala <sthokal@xilinx.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Tobias Klauser [Fri, 25 Jul 2014 08:36:14 +0000 (10:36 +0200)]
PCI: Remove unnecessary variable in pci_add_dynid()
The variable "retval" in pci_add_dynid() is only used to store the return
value of driver_attach() and is then directly returned. Remove the
variable and directly pass on driver_attach()'s return value.
Signed-off-by: Tobias Klauser <tklauser@distanz.ch>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Murali Karicheri [Wed, 23 Jul 2014 18:54:51 +0000 (14:54 -0400)]
PCI: designware: Add support for v3.65 hardware
The Keystone PCI controller is based on v3.65 DesignWare hardware. This
version differs from newer versions of the hardware in functional areas
discussed below that make it necessary to change dw_pcie_host_init() to
support v3.65 based PCI controller.
1. No support for ATU port. Any ATU-specific resource handling code is
to be bypassed for v3.65 h/w.
2. MSI controller uses application space to implement MSI and 32 MSI
interrupts are multiplexed over 8 IRQs to the host. Hence the code
to process MSI IRQ needs to be different. This patch allows
platform driver to provide its own irq_domain_ops ptr to
irq_domain_add_linear() through an API callback from the DesignWare
core driver.
3. MSI interrupt generation requires EP to write to the RC's
application register. So enhance the driver to allow setup of
inbound access to MSI IRQ register as a post scan bus API callback.
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Pratyush Anand <pratyush.anand@st.com>
Acked-by: Mohit KUMAR <mohit.kumar@st.com>
Acked-by: Jingoo Han <jg1.han@samsung.com>
CC: Santosh Shilimkar <santosh.shilimkar@ti.com>
CC: Russell King <linux@arm.linux.org.uk>
CC: Grant Likely <grant.likely@linaro.org>
CC: Rob Herring <robh+dt@kernel.org>
CC: Jingoo Han <jg1.han@samsung.com>
CC: Richard Zhu <r65037@freescale.com>
CC: Kishon Vijay Abraham I <kishon@ti.com>
CC: Marek Vasut <marex@denx.de>
CC: Arnd Bergmann <arnd@arndb.de>
CC: Pawel Moll <pawel.moll@arm.com>
CC: Mark Rutland <mark.rutland@arm.com>
CC: Ian Campbell <ijc+devicetree@hellion.org.uk>
CC: Kumar Gala <galak@codeaurora.org>
CC: Randy Dunlap <rdunlap@infradead.org>
CC: Grant Likely <grant.likely@linaro.org>
Rafael J. Wysocki [Mon, 21 Jul 2014 01:18:24 +0000 (03:18 +0200)]
PCI/PM: Allow PCI devices to be put into D3cold during system suspend
Commit
448bd857d48e ("PCI/PM: add PCIe runtime D3cold support") added a
check to prevent PCI devices from being put into D3cold during system
suspend without giving any particular reason.
Also the check isn't really necessary, because acpi_pci_set_power_state()
maps PCI_D3hot to ACPI_STATE_D3_COLD anyway.
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Rafael J. Wysocki [Mon, 21 Jul 2014 00:02:23 +0000 (02:02 +0200)]
PCI/PM: Drop unused runtime PM support code for PCIe ports
Since commit
de7d5f729c72 ("PCI/PM: Disable runtime PM of PCIe ports") the
runtime PM support code for PCIe ports in portdrv_pci.c has never been
used, so drop it entirely.
If we are to support runtime PM of PCIe ports, it will have to be done in a
different way most likely anyway.
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Linus Torvalds [Mon, 25 Aug 2014 22:36:20 +0000 (15:36 -0700)]
Linux 3.17-rc2
Linus Torvalds [Mon, 25 Aug 2014 22:34:28 +0000 (15:34 -0700)]
Merge tag 'nfs-for-3.17-2' of git://git.linux-nfs.org/projects/trondmy/linux-nfs
Pull NFS client fixes from Trond Myklebust:
"Highlights:
- more fixes for read/write codepath regressions
* sleeping while holding the inode lock
* stricter enforcement of page contiguity when coalescing requests
* fix up error handling in the page coalescing code
- don't busy wait on SIGKILL in the file locking code"
* tag 'nfs-for-3.17-2' of git://git.linux-nfs.org/projects/trondmy/linux-nfs:
nfs: Don't busy-wait on SIGKILL in __nfs_iocounter_wait
nfs: can_coalesce_requests must enforce contiguity
nfs: disallow duplicate pages in pgio page vectors
nfs: don't sleep with inode lock in lock_and_join_requests
nfs: fix error handling in lock_and_join_requests
nfs: use blocking page_group_lock in add_request
nfs: fix nonblocking calls to nfs_page_group_lock
nfs: change nfs_page_group_lock argument
Linus Torvalds [Mon, 25 Aug 2014 22:29:33 +0000 (15:29 -0700)]
Merge tag 'renesas-sh-drivers-for-v3.17' of git://git./linux/kernel/git/horms/renesas
Pull SH driver fix from Simon Horman:
"Confine SH_INTC to platforms that need it"
* tag 'renesas-sh-drivers-for-v3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
sh: intc: Confine SH_INTC to platforms that need it
Linus Torvalds [Mon, 25 Aug 2014 22:28:57 +0000 (15:28 -0700)]
Merge branch 'upstream' of git://git.linux-mips.org/ralf/upstream-linus
Pull MIPS fixes from Ralf Baechle:
"Pretty much all across the field so with this we should be in
reasonable shape for the upcoming -rc2"
* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus:
MIPS: OCTEON: make get_system_type() thread-safe
MIPS: CPS: Initialize EVA before bringing up VPEs from secondary cores
MIPS: Malta: EVA: Rename 'eva_entry' to 'platform_eva_init'
MIPS: EVA: Add new EVA header
MIPS: scall64-o32: Fix indirect syscall detection
MIPS: syscall: Fix AUDIT value for O32 processes on MIPS64
MIPS: Loongson: Fix COP2 usage for preemptible kernel
MIPS: NL: Fix nlm_xlp_defconfig build error
MIPS: Remove race window in page fault handling
MIPS: Malta: Improve system memory detection for '{e, }memsize' >= 2G
MIPS: Alchemy: Fix db1200 PSC clock enablement
MIPS: BCM47XX: Fix reboot problem on BCM4705/BCM4785
MIPS: Remove duplicated include from numa.c
MIPS: Add common plat_irq_dispatch declaration
MIPS: MSP71xx: remove unused plat_irq_dispatch() argument
MIPS: GIC: Remove useless parens from GICBIS().
MIPS: perf: Mark pmu interupt IRQF_NO_THREAD
Linus Torvalds [Mon, 25 Aug 2014 22:11:53 +0000 (15:11 -0700)]
Merge tag 'trace-fixes-v3.17-rc1' of git://git./linux/kernel/git/rostedt/linux-trace
Pull fix for ftrace function tracer/profiler conflict from Steven Rostedt:
"The rewrite of the ftrace code that makes it possible to allow for
separate trampolines had a design flaw with the interaction between
the function and function_graph tracers.
The main flaw was the simplification of the use of multiple tracers
having the same filter (like function and function_graph, that use the
set_ftrace_filter file to filter their code). The design assumed that
the two tracers could never run simultaneously as only one tracer can
be used at a time. The problem with this assumption was that the
function profiler could be implemented on top of the function graph
tracer, and the function profiler could run at the same time as the
function tracer. This caused the assumption to be broken and when
ftrace detected this failed assumpiton it would spit out a nasty
warning and shut itself down.
Instead of using a single ftrace_ops that switches between the
function and function_graph callbacks, the two tracers can again use
their own ftrace_ops. But instead of having a complex hierarchy of
ftrace_ops, the filter fields are placed in its own structure and the
ftrace_ops can carefully use the same filter. This change took a bit
to be able to allow for this and currently only the global_ops can
share the same filter, but this new design can easily be modified to
allow for any ftrace_ops to share its filter with another ftrace_ops.
The first four patches deal with the change of allowing the ftrace_ops
to share the filter (and this needs to go to 3.16 as well).
The fifth patch fixes a bug that was also caused by the new changes
but only for archs other than x86, and only if those archs implement a
direct call to the function_graph tracer which they do not do yet but
will in the future. It does not need to go to stable, but needs to be
fixed before the other archs update their code to allow direct calls
to the function_graph trampoline"
* tag 'trace-fixes-v3.17-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rostedt/linux-trace:
ftrace: Use current addr when converting to nop in __ftrace_replace_code()
ftrace: Fix function_profiler and function tracer together
ftrace: Fix up trampoline accounting with looping on hash ops
ftrace: Update all ftrace_ops for a ftrace_hash_ops update
ftrace: Allow ftrace_ops to use the hashes from other ops
Linus Torvalds [Sun, 24 Aug 2014 23:17:41 +0000 (16:17 -0700)]
Merge branch 'x86-urgent-for-linus' of git://git./linux/kernel/git/tip/tip
Pull x86 fixes from Ingo Molnar:
"A couple of EFI fixes, plus misc fixes all around the map"
* 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
efi/arm64: Store Runtime Services revision
firmware: Do not use WARN_ON(!spin_is_locked())
x86_32, entry: Clean up sysenter_badsys declaration
x86/doc: Fix the 'tlb_single_page_flush_ceiling' sysconfig path
x86/mm: Fix sparse 'tlb_single_page_flush_ceiling' warning and make the variable read-mostly
x86/mm: Fix RCU splat from new TLB tracepoints