OSDN Git Service
Jinsong Ji [Tue, 9 Jul 2019 02:27:29 +0000 (02:27 +0000)]
[PowerPC][MachinePipeliner][NFC] Add a testcase for Phi bug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365427
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Heejin Ahn [Tue, 9 Jul 2019 02:10:33 +0000 (02:10 +0000)]
[WebAssembly] Make sret parameter work with AddMissingPrototypes
Summary:
Even with functions with `no-prototype` attribute, there can be an
argument `sret` (structure return) attribute, which is an optimization
when a function return type is a struct. Fixes PR42420.
Reviewers: sbc100
Subscribers: dschuff, jgravelle-google, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D64318
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365426
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Philip Reames [Tue, 9 Jul 2019 02:03:31 +0000 (02:03 +0000)]
[LoopPred] Stylistic improvement to recently added NE/EQ normalization [NFC]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365425
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Yonghong Song [Tue, 9 Jul 2019 01:51:36 +0000 (01:51 +0000)]
[BPF] add new intrinsics preserve_{array,union,struct}_access_index
For background of BPF CO-RE project, please refer to
http://vger.kernel.org/bpfconf2019.html
In summary, BPF CO-RE intends to compile bpf programs
adjustable on struct/union layout change so the same
program can run on multiple kernels with adjustment
before loading based on native kernel structures.
In order to do this, we need keep track of GEP(getelementptr)
instruction base and result debuginfo types, so we
can adjust on the host based on kernel BTF info.
Capturing such information as an IR optimization is hard
as various optimization may have tweaked GEP and also
union is replaced by structure it is impossible to track
fieldindex for union member accesses.
Three intrinsic functions, preserve_{array,union,struct}_access_index,
are introducted.
addr = preserve_array_access_index(base, index, dimension)
addr = preserve_union_access_index(base, di_index)
addr = preserve_struct_access_index(base, gep_index, di_index)
here,
base: the base pointer for the array/union/struct access.
index: the last access index for array, the same for IR/DebugInfo layout.
dimension: the array dimension.
gep_index: the access index based on IR layout.
di_index: the access index based on user/debuginfo types.
For example, for the following example,
$ cat test.c
struct sk_buff {
int i;
int b1:1;
int b2:2;
union {
struct {
int o1;
int o2;
} o;
struct {
char flags;
char dev_id;
} dev;
int netid;
} u[10];
};
static int (*bpf_probe_read)(void *dst, int size, const void *unsafe_ptr)
= (void *) 4;
#define _(x) (__builtin_preserve_access_index(x))
int bpf_prog(struct sk_buff *ctx) {
char dev_id;
bpf_probe_read(&dev_id, sizeof(char), _(&ctx->u[5].dev.dev_id));
return dev_id;
}
$ clang -target bpf -O2 -g -emit-llvm -S -mllvm -print-before-all \
test.c >& log
The generated IR looks like below:
...
define dso_local i32 @bpf_prog(%struct.sk_buff*) #0 !dbg !15 {
%2 = alloca %struct.sk_buff*, align 8
%3 = alloca i8, align 1
store %struct.sk_buff* %0, %struct.sk_buff** %2, align 8, !tbaa !45
call void @llvm.dbg.declare(metadata %struct.sk_buff** %2, metadata !43, metadata !DIExpression()), !dbg !49
call void @llvm.lifetime.start.p0i8(i64 1, i8* %3) #4, !dbg !50
call void @llvm.dbg.declare(metadata i8* %3, metadata !44, metadata !DIExpression()), !dbg !51
%4 = load i32 (i8*, i32, i8*)*, i32 (i8*, i32, i8*)** @bpf_probe_read, align 8, !dbg !52, !tbaa !45
%5 = load %struct.sk_buff*, %struct.sk_buff** %2, align 8, !dbg !53, !tbaa !45
%6 = call [10 x %union.anon]* @llvm.preserve.struct.access.index.p0a10s_union.anons.p0s_struct.sk_buffs(
%struct.sk_buff* %5, i32 2, i32 3), !dbg !53, !llvm.preserve.access.index !19
%7 = call %union.anon* @llvm.preserve.array.access.index.p0s_union.anons.p0a10s_union.anons(
[10 x %union.anon]* %6, i32 1, i32 5), !dbg !53
%8 = call %union.anon* @llvm.preserve.union.access.index.p0s_union.anons.p0s_union.anons(
%union.anon* %7, i32 1), !dbg !53, !llvm.preserve.access.index !26
%9 = bitcast %union.anon* %8 to %struct.anon.0*, !dbg !53
%10 = call i8* @llvm.preserve.struct.access.index.p0i8.p0s_struct.anon.0s(
%struct.anon.0* %9, i32 1, i32 1), !dbg !53, !llvm.preserve.access.index !34
%11 = call i32 %4(i8* %3, i32 1, i8* %10), !dbg !52
%12 = load i8, i8* %3, align 1, !dbg !54, !tbaa !55
%13 = sext i8 %12 to i32, !dbg !54
call void @llvm.lifetime.end.p0i8(i64 1, i8* %3) #4, !dbg !56
ret i32 %13, !dbg !57
}
!19 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "sk_buff", file: !3, line: 1, size: 704, elements: !20)
!26 = distinct !DICompositeType(tag: DW_TAG_union_type, scope: !19, file: !3, line: 5, size: 64, elements: !27)
!34 = distinct !DICompositeType(tag: DW_TAG_structure_type, scope: !26, file: !3, line: 10, size: 16, elements: !35)
Note that @llvm.preserve.{struct,union}.access.index calls have metadata llvm.preserve.access.index
attached to instructions to provide struct/union debuginfo type information.
For &ctx->u[5].dev.dev_id,
. The "%6 = ..." represents struct member "u" with index 2 for IR layout and index 3 for DI layout.
. The "%7 = ..." represents array subscript "5".
. The "%8 = ..." represents union member "dev" with index 1 for DI layout.
. The "%10 = ..." represents struct member "dev_id" with index 1 for both IR and DI layout.
Basically, traversing the use-def chain recursively for the 3rd argument of bpf_probe_read() and
examining all preserve_*_access_index calls, the debuginfo struct/union/array access index
can be achieved.
The intrinsics also contain enough information to regenerate codes for IR layout.
For array and structure intrinsics, the proper GEP can be constructed.
For union intrinsics, replacing all uses of "addr" with "base" should be enough.
The test case ThinLTO/X86/lazyload_metadata.ll is adjusted to reflect the
new addition of the metadata.
Signed-off-by: Yonghong Song <yhs@fb.com>
Differential Revision: https://reviews.llvm.org/D61810
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365423
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Philip Reames [Tue, 9 Jul 2019 01:27:45 +0000 (01:27 +0000)]
[LoopPred] Extend LFTR normalization to the inverse EQ case
A while back, I added support for NE latches formed by LFTR. I didn't think that quite through, as LFTR will also produce the inverse EQ form for some loops and I hadn't handled that. This change just adds handling for that case as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365419
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Heejin Ahn [Tue, 9 Jul 2019 01:21:04 +0000 (01:21 +0000)]
[WebAssembly] Fix a typo in a test file name
Reviewers: sbc100
Subscribers: dschuff, jgravelle-google, sunfish, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D64324
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365418
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Nilanjana Basu [Tue, 9 Jul 2019 01:11:02 +0000 (01:11 +0000)]
Changing CodeView debug info type record representation in assembly files to make it more human-readable & editable & fixing bug introduced in r364987
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365417
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Nico Weber [Tue, 9 Jul 2019 00:34:08 +0000 (00:34 +0000)]
Let unaliased Args track which Alias they were created from, and use that in Arg::getAsString() for diagnostics
With this, `clang-cl /source-charset:utf-16 test.cc` now prints `invalid
value 'utf-16' in '/source-charset:utf-16'` instead of `invalid value
'utf-16' in '-finput-charset=utf-16'` before, and several other clang-cl
flags produce much less confusing output as well.
Fixes PR29106.
Since an arg and its alias can have different arg types (joined vs not)
and different values (because of AliasArgs<>), I chose to give the Alias
its own Arg object. For convenience, I just store the alias directly in
the unaliased arg – there aren't many arg objects at runtime, so that
seems ok.
Finally, I changed Arg::getAsString() to use the alias's representation
if it's present – that function was already documented as being the
suitable function for diagnostics, and most callers already used it for
diagnostics.
Implementation-wise, Arg::accept() previously used to parse things as
the unaliased option. The core of that switch is now extracted into a
new function acceptInternal() which parses as the _aliased_ option, and
the previously-intermingled unaliasing is now done as an explicit step
afterwards.
(This also changes one place in lld that didn't use getAsString() for
diagnostics, so that that one place now also prints the flag as the user
wrote it, not as it looks after it went through unaliasing.)
Differential Revision: https://reviews.llvm.org/D64253
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365413
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Johannes Doerfert [Mon, 8 Jul 2019 23:27:20 +0000 (23:27 +0000)]
[Attributor] Deduce the "returned" argument attribute
Deduce the "returned" argument attribute by collecting all potentially
returned values.
Not only the unique return value, if any, can be used by subsequent
attributes but also the set of all potentially returned values as well
as the mapping from returned values to return instructions that they
originate from (see AAReturnedValues::checkForallReturnedValues).
Change in statistics (-stats) for LLVM-TS + Spec2006, totaling ~19% more "returned" arguments.
ADDED: attributor NumAttributesManifested n/a -> 637
ADDED: attributor NumAttributesValidFixpoint n/a -> 25545
ADDED: attributor NumFnArgumentReturned n/a -> 637
ADDED: attributor NumFnKnownReturns n/a -> 25545
ADDED: attributor NumFnUniqueReturned n/a -> 14118
CHANGED: deadargelim NumRetValsEliminated 470 -> 449 ( -4.468%)
REMOVED: functionattrs NumReturned 535 -> n/a
CHANGED: indvars NumElimIdentity 138 -> 164 ( +18.841%)
Reviewers: homerdin, hfinkel, fedor.sergeev, sanjoy, spatel, nlopes, nicholas, reames, efriedma, chandlerc
Subscribers: hiraditya, bollu, cfe-commits, llvm-commits
Tags: #clang, #llvm
Differential Revision: https://reviews.llvm.org/D59919
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365407
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Jessica Paquette [Mon, 8 Jul 2019 22:58:36 +0000 (22:58 +0000)]
[AArch64][GlobalISel] Use TST for comparisons when possible
Porting over the part of `emitComparison` in AArch64ISelLowering where we use
TST to represent a compare.
- Rename `tryOptCMN` to `tryFoldIntegerCompare`, since it now also emits TSTs
when possible.
- Add a utility function for emitting a TST with register operands.
- Rename opt-fold-cmn.mir to opt-fold-compare.mir, since it now also tests the
TST fold as well.
Differential Revision: https://reviews.llvm.org/D64371
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365404
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Rong Xu [Mon, 8 Jul 2019 22:17:55 +0000 (22:17 +0000)]
[llvm-profdata] Fix buildbot failure on llvm-clang-x86_64-expensive-checks-win
This fixes buildbot failure in LLVM on llvm-clang-x86_64-expensive-checks-win
from r365386.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365401
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Matt Arsenault [Mon, 8 Jul 2019 22:08:23 +0000 (22:08 +0000)]
AMDGPU: Split extload/zextload local load patterns
This will help removing the custom load predicates, allowing the
global isel emitter to handle them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365398
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Bill Wendling [Mon, 8 Jul 2019 22:00:33 +0000 (22:00 +0000)]
Add parentheses to silence warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365394
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Reid Kleckner [Mon, 8 Jul 2019 21:05:20 +0000 (21:05 +0000)]
Standardize on MSVC behavior for triples with no environment
Summary:
This makes it so that IR files using triples without an environment work
out of the box, without normalizing them.
Typically, the MSVC behavior is more desirable. For example, it tends to
enable things like constant merging, use of associative comdats, etc.
Addresses PR42491
Reviewers: compnerd
Subscribers: hiraditya, dexonsmith, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D64109
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365387
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Rong Xu [Mon, 8 Jul 2019 21:03:12 +0000 (21:03 +0000)]
llvm-profdata] Handle the cases of overlapping input file and output file
Currently llvm-profdata does not expect the same file name for the input profile
and the output profile.
>llvm-profdata merge A.profraw B.profraw -o B.profraw
The above command runs successfully but the resulted B.profraw is not correct.
This patch fixes the issue by moving the initialization of writer after loading
the profile.
For the show command, the following will report a confusing error of
"Empty raw profile file":
>llvm-profdata show B.profraw -o B.profraw
It's harder to fix as we need to output something before loading the input profile.
I don't think that a fix for this is worth the effort. I just make the error explicit for
the show command.
Differential Revision: https://reviews.llvm.org/D64360
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365386
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JF Bastien [Mon, 8 Jul 2019 20:06:36 +0000 (20:06 +0000)]
Revert "Reapply [llvm-ar][test] Increase llvm-ar test coverage"
llvm-ar.extract.test has been failing on greendragon and gone unfixed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365383
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Sanjay Patel [Mon, 8 Jul 2019 19:48:52 +0000 (19:48 +0000)]
[InstCombine] fold insertelement into splat of same scalar
Forming the canonical splat shuffle improves analysis and
may allow follow-on transforms (although some possibilities
are missing as shown in the test diffs).
The backend generically turns these patterns into build_vector,
so there should be no codegen regressions. All targets are
expected to be able to lower splats efficiently.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365379
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Matt Arsenault [Mon, 8 Jul 2019 19:47:42 +0000 (19:47 +0000)]
AMDGPU: Fix unused variable in release build
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365378
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Yuanfang Chen [Mon, 8 Jul 2019 19:28:57 +0000 (19:28 +0000)]
Teach the symbolizer lib symbolize objects directly.
Currently, the symbolizer lib can only symbolize a file on disk.
This patch teaches the symbolizer lib to symbolize objects.
llvm-objdump needs this to support archive disassembly with source info.
https://bugs.llvm.org/show_bug.cgi?id=41871
Reviewed by: jhenderson, grimar, MaskRay
Differential Revision: https://reviews.llvm.org/D63521
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365376
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Matt Arsenault [Mon, 8 Jul 2019 19:05:19 +0000 (19:05 +0000)]
AMDGPU: Fix stray typing
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365373
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Matt Arsenault [Mon, 8 Jul 2019 19:03:38 +0000 (19:03 +0000)]
AMDGPU: Make s34 the FP register
Make the FP register callee saved.
This is tricky because now the FP needs to be spilled in the prolog
relative to the incoming SP register, rather than the frame register
used throughout the rest of the function. I don't like how this
bypassess the standard mechanism for CSR spills just to get the
correct insert point. I may look for a better solution, since all CSR
VGPRs may also need to have all lanes activated. Another option might
be to make getFrameIndexReference change the base register if the
frame index is a CSR, and then try to figure out the right insertion
point in emitProlog.
If there is a free VGPR lane available for SGPR spilling, try to use
it for the FP. If that would require intrtoducing a new VGPR spill,
try to use a free call clobbered SGPR. Only fallback to introducing a
new VGPR spill as a last resort.
This also doesn't attempt to handle SGPR spilling with scalar stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365372
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Matt Arsenault [Mon, 8 Jul 2019 18:48:42 +0000 (18:48 +0000)]
RegUsageInfoCollector: Don't iterate all regs for every reg class
This is extremly slow on AMDGPU, which has a lot of physical register
and a lot of register classes.
determineCalleeSaves, via MachineRegisterInfo::isPhysRegUsed already
added all of the super registers to the saved set.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365370
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Matt Arsenault [Mon, 8 Jul 2019 18:48:39 +0000 (18:48 +0000)]
AMDGPU: Move DEBUG_TYPE definition below includes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365369
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Whitney Tsang [Mon, 8 Jul 2019 18:30:35 +0000 (18:30 +0000)]
Keep the order of the basic blocks in the cloned loop as the original
loop
Summary:
Do the cloning in two steps, first allocate all the new loops, then
clone the basic blocks in the same order as the original loop.
Reviewer: Meinersbur, fhahn, kbarton, hfinkel
Reviewed By: hfinkel
Subscribers: hfinkel, hiraditya, llvm-commits
Tag: https://reviews.llvm.org/D64224
Differential Revision:
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365366
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Chris Bieneman [Mon, 8 Jul 2019 18:29:29 +0000 (18:29 +0000)]
Fix issues building libraries as more than one type with Xcode
Summary:
CMake+Xcode doesn't seem to handle targets that only have object
sources. This patch works around that limitation by adding a dummy
soruce file to any library target that is generated by llvm_add_library
when object libraries are generated.
Object libraries are generated whenever llvm_add_library is passed more
than one library type, which is now the default case for clang static
libraries (which generate STATIC and OBJECT libraries).
Reviewers: zturner, compnerd, joanlluch
Reviewed By: joanlluch
Subscribers: joanlluch, xbolva00, mgorny, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D64300
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365365
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Denis Bakhvalov [Mon, 8 Jul 2019 18:03:43 +0000 (18:03 +0000)]
[SCEV] Fix for PR42397. SCEVExpander wrongly adds nsw to shl instruction.
Change-Id: I76c9f628c092ae3e6e78ebdaf55cec726e25d692
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365363
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Sanjay Patel [Mon, 8 Jul 2019 18:03:22 +0000 (18:03 +0000)]
[InstCombine] add tests for insert of same splatted scalar; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365362
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Vitaly Buka [Mon, 8 Jul 2019 17:50:22 +0000 (17:50 +0000)]
Update gn files
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365361
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Yonghong Song [Mon, 8 Jul 2019 17:47:43 +0000 (17:47 +0000)]
Revert "[BPF] add new intrinsics preserve_{array,union,struct}_access_index"
This reverts commit r365352.
Test ThinLTO/X86/lazyload_metadata.ll failed. Revert the commit
and at the same time to fix the issue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365360
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Vitaly Buka [Mon, 8 Jul 2019 17:15:57 +0000 (17:15 +0000)]
Update gn files
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365354
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Dmitry Preobrazhensky [Mon, 8 Jul 2019 17:09:09 +0000 (17:09 +0000)]
[AMDGPU][MC][DOC] Updated AMD GPU assembler syntax description.
Corrected a typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365353
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Yonghong Song [Mon, 8 Jul 2019 17:08:28 +0000 (17:08 +0000)]
[BPF] add new intrinsics preserve_{array,union,struct}_access_index
For background of BPF CO-RE project, please refer to
http://vger.kernel.org/bpfconf2019.html
In summary, BPF CO-RE intends to compile bpf programs
adjustable on struct/union layout change so the same
program can run on multiple kernels with adjustment
before loading based on native kernel structures.
In order to do this, we need keep track of GEP(getelementptr)
instruction base and result debuginfo types, so we
can adjust on the host based on kernel BTF info.
Capturing such information as an IR optimization is hard
as various optimization may have tweaked GEP and also
union is replaced by structure it is impossible to track
fieldindex for union member accesses.
Three intrinsic functions, preserve_{array,union,struct}_access_index,
are introducted.
addr = preserve_array_access_index(base, index, dimension)
addr = preserve_union_access_index(base, di_index)
addr = preserve_struct_access_index(base, gep_index, di_index)
here,
base: the base pointer for the array/union/struct access.
index: the last access index for array, the same for IR/DebugInfo layout.
dimension: the array dimension.
gep_index: the access index based on IR layout.
di_index: the access index based on user/debuginfo types.
For example, for the following example,
$ cat test.c
struct sk_buff {
int i;
int b1:1;
int b2:2;
union {
struct {
int o1;
int o2;
} o;
struct {
char flags;
char dev_id;
} dev;
int netid;
} u[10];
};
static int (*bpf_probe_read)(void *dst, int size, const void *unsafe_ptr)
= (void *) 4;
#define _(x) (__builtin_preserve_access_index(x))
int bpf_prog(struct sk_buff *ctx) {
char dev_id;
bpf_probe_read(&dev_id, sizeof(char), _(&ctx->u[5].dev.dev_id));
return dev_id;
}
$ clang -target bpf -O2 -g -emit-llvm -S -mllvm -print-before-all \
test.c >& log
The generated IR looks like below:
...
define dso_local i32 @bpf_prog(%struct.sk_buff*) #0 !dbg !15 {
%2 = alloca %struct.sk_buff*, align 8
%3 = alloca i8, align 1
store %struct.sk_buff* %0, %struct.sk_buff** %2, align 8, !tbaa !45
call void @llvm.dbg.declare(metadata %struct.sk_buff** %2, metadata !43, metadata !DIExpression()), !dbg !49
call void @llvm.lifetime.start.p0i8(i64 1, i8* %3) #4, !dbg !50
call void @llvm.dbg.declare(metadata i8* %3, metadata !44, metadata !DIExpression()), !dbg !51
%4 = load i32 (i8*, i32, i8*)*, i32 (i8*, i32, i8*)** @bpf_probe_read, align 8, !dbg !52, !tbaa !45
%5 = load %struct.sk_buff*, %struct.sk_buff** %2, align 8, !dbg !53, !tbaa !45
%6 = call [10 x %union.anon]* @llvm.preserve.struct.access.index.p0a10s_union.anons.p0s_struct.sk_buffs(
%struct.sk_buff* %5, i32 2, i32 3), !dbg !53, !llvm.preserve.access.index !19
%7 = call %union.anon* @llvm.preserve.array.access.index.p0s_union.anons.p0a10s_union.anons(
[10 x %union.anon]* %6, i32 1, i32 5), !dbg !53
%8 = call %union.anon* @llvm.preserve.union.access.index.p0s_union.anons.p0s_union.anons(
%union.anon* %7, i32 1), !dbg !53, !llvm.preserve.access.index !26
%9 = bitcast %union.anon* %8 to %struct.anon.0*, !dbg !53
%10 = call i8* @llvm.preserve.struct.access.index.p0i8.p0s_struct.anon.0s(
%struct.anon.0* %9, i32 1, i32 1), !dbg !53, !llvm.preserve.access.index !34
%11 = call i32 %4(i8* %3, i32 1, i8* %10), !dbg !52
%12 = load i8, i8* %3, align 1, !dbg !54, !tbaa !55
%13 = sext i8 %12 to i32, !dbg !54
call void @llvm.lifetime.end.p0i8(i64 1, i8* %3) #4, !dbg !56
ret i32 %13, !dbg !57
}
!19 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "sk_buff", file: !3, line: 1, size: 704, elements: !20)
!26 = distinct !DICompositeType(tag: DW_TAG_union_type, scope: !19, file: !3, line: 5, size: 64, elements: !27)
!34 = distinct !DICompositeType(tag: DW_TAG_structure_type, scope: !26, file: !3, line: 10, size: 16, elements: !35)
Note that @llvm.preserve.{struct,union}.access.index calls have metadata llvm.preserve.access.index
attached to instructions to provide struct/union debuginfo type information.
For &ctx->u[5].dev.dev_id,
. The "%6 = ..." represents struct member "u" with index 2 for IR layout and index 3 for DI layout.
. The "%7 = ..." represents array subscript "5".
. The "%8 = ..." represents union member "dev" with index 1 for DI layout.
. The "%10 = ..." represents struct member "dev_id" with index 1 for both IR and DI layout.
Basically, traversing the use-def chain recursively for the 3rd argument of bpf_probe_read() and
examining all preserve_*_access_index calls, the debuginfo struct/union/array access index
can be achieved.
The intrinsics also contain enough information to regenerate codes for IR layout.
For array and structure intrinsics, the proper GEP can be constructed.
For union intrinsics, replacing all uses of "addr" with "base" should be enough.
Signed-off-by: Yonghong Song <yhs@fb.com>
Differential Revision: https://reviews.llvm.org/D61810
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365352
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Wouter van Oortmerssen [Mon, 8 Jul 2019 16:58:37 +0000 (16:58 +0000)]
[WebAssembly] tablegen: distinguish float/int immediate operands.
Summary:
Before, they were one category of operands which could cause
crashes in non-sensical combinations, e.g. "f32.const symbol".
Now these are forced to be an error.
Reviewers: dschuff
Subscribers: sbc100, jgravelle-google, aheejin, sunfish, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D64039
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365351
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Matt Arsenault [Mon, 8 Jul 2019 16:53:53 +0000 (16:53 +0000)]
AMDGPU: Remove mubuf specific PatFrags
These are identical to the *_global PatFrag, and will only create more
work to get the GlobalISel importer to handle them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365350
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Matt Arsenault [Mon, 8 Jul 2019 16:53:48 +0000 (16:53 +0000)]
AMDGPU: Move waitcnt intrinsic to instruction definition pattern
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365349
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George Rimar [Mon, 8 Jul 2019 16:53:39 +0000 (16:53 +0000)]
[llvm\test\Object] - An initial step to cleanup the test cases.
This patch removes trivial-object-test.elf-i386,
trivial-object-test.elf-x86-64 and trivial-object-test2.elf-x86-64
precompiled objects from test/Object/Inputs folder.
I adjusted the existent test cases to use YAML instead.
Differential revision: https://reviews.llvm.org/D64206
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365348
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Dmitry Preobrazhensky [Mon, 8 Jul 2019 16:50:11 +0000 (16:50 +0000)]
[AMDGPU][MC][DOC] Updated AMD GPU assembler syntax description.
Summary of changes:
- added description of GFX10;
- added description of operands sccz, vccz, lds_direct, etc;
- minor bugfixing and improvements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365347
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Brian Homerding [Mon, 8 Jul 2019 16:33:32 +0000 (16:33 +0000)]
Add, and infer, a nofree function attribute
Removing dead code leftover from refactor.
Reviewers: jdoerfert
Differential Revision: https://reviews.llvm.org/D49165
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365345
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Matt Arsenault [Mon, 8 Jul 2019 16:27:47 +0000 (16:27 +0000)]
GlobalISel: Convert some build functions to using SrcOp/DstOp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365343
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Sanjay Patel [Mon, 8 Jul 2019 16:26:48 +0000 (16:26 +0000)]
[InstCombine] canonicalize insert+splat to/from element 0 of vector
We recognize a splat from element 0 in (VectorUtils) llvm::getSplatValue()
and also in ShuffleVectorInst::isZeroEltSplatMask(), so this converts
to that form for better matching.
The backend generically turns these patterns into build_vector,
so there should be no codegen difference.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365342
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Francis Visoiu Mistrih [Mon, 8 Jul 2019 16:19:45 +0000 (16:19 +0000)]
[Bitcode][NFC] Remove unused variable from BitcodeAnalyzer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365340
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Kevin P. Neal [Mon, 8 Jul 2019 16:18:18 +0000 (16:18 +0000)]
Teach the IRBuilder about fadd and friends.
The IRBuilder has calls to create floating point instructions like fadd.
It does not have calls to create constrained versions of them. This patch
adds support for constrained creation of fadd, fsub, fmul, fdiv, and frem.
Reviewed by: John McCall, Sanjay Patel
Approved by: John McCall
Differential Revision: https://reviews.llvm.org/D53157
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365339
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Brian Homerding [Mon, 8 Jul 2019 15:57:56 +0000 (15:57 +0000)]
Add, and infer, a nofree function attribute
This patch adds a function attribute, nofree, to indicate that a function does
not, directly or indirectly, call a memory-deallocation function (e.g., free,
C++'s operator delete).
Reviewers: jdoerfert
Differential Revision: https://reviews.llvm.org/D49165
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365336
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James Henderson [Mon, 8 Jul 2019 15:46:26 +0000 (15:46 +0000)]
[docs][llvm-readobj][llvm-readelf] Improve wording
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365335
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Sanjay Patel [Mon, 8 Jul 2019 15:38:03 +0000 (15:38 +0000)]
[InstCombine] fix typo in test; NFC
I added this test in rL365325, but didn't mean to create an undef insert.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365333
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Jinsong Ji [Mon, 8 Jul 2019 15:24:32 +0000 (15:24 +0000)]
[PowerPC][NFC]Update testcases using script.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365330
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Simon Pilgrim [Mon, 8 Jul 2019 14:52:56 +0000 (14:52 +0000)]
[X86] ISD::INSERT_SUBVECTOR - use uint64_t index. NFCI.
Keep the uint64_t type from getConstantOperandVal to stop truncation/extension overflow warnings in MSVC in subvector index math.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365328
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Alex Bradbury [Mon, 8 Jul 2019 14:52:36 +0000 (14:52 +0000)]
[Triple] Add isRISCV function
This matches isARM, isThumb, isAArch64 and similar helpers. Future commits
which clean-up code that currently checks for Triple::riscv32 ||
Triple::riscv64.
Differential Revision: https://reviews.llvm.org/D54215
Patch by Simon Cook.
Test case added by Alex Bradbury.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365327
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Sanjay Patel [Mon, 8 Jul 2019 14:49:21 +0000 (14:49 +0000)]
[InstCombine] add tests for splat shuffles; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365325
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Cameron McInally [Mon, 8 Jul 2019 14:46:07 +0000 (14:46 +0000)]
[Float2Int] Add support for unary FNeg to Float2Int
Differential Revision: https://reviews.llvm.org/D63941
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365324
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Petar Avramovic [Mon, 8 Jul 2019 14:45:52 +0000 (14:45 +0000)]
[MIPS GlobalISel] Register bank select for G_LOAD. Select i64 load
Select gprb or fprb when loaded value is used by either:
copy to physical register or
instruction with only one mapping available for that use operand.
Load of integer s64 is handled with narrowScalar when mapping is applied,
produced artifacts are combined away. Manually set gprb to all register
operands of instructions created during narrowScalar.
Differential Revision: https://reviews.llvm.org/D64269
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365323
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Petar Avramovic [Mon, 8 Jul 2019 14:36:36 +0000 (14:36 +0000)]
[MIPS GlobalISel] Register bank select for G_STORE. Select i64 store
Select gprb or fprb when stored value is defined by either:
copy from physical register or
instruction with only one mapping available for that def operand.
Store of integer s64 is handled with narrowScalar when mapping is applied,
produced artifacts are combined away. Manually set gprb to all register
operands of instructions created during narrowScalar.
Differential Revision: https://reviews.llvm.org/D64268
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365322
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Dmitry Preobrazhensky [Mon, 8 Jul 2019 14:27:37 +0000 (14:27 +0000)]
[AMDGPU][MC] Corrected parsing of FLAT offset modifier
Summary of changes:
- simplified handling of FLAT offset: offset_s13 and offset_u12 have been replaced with flat_offset;
- provided information about error position for pre-gfx9 targets;
- improved errors handling.
Reviewers: artem.tamazov, arsenm, rampitec
Differential Revision: https://reviews.llvm.org/D64244
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365321
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Matt Arsenault [Mon, 8 Jul 2019 13:48:06 +0000 (13:48 +0000)]
GlobalISel: widenScalar for G_BUILD_VECTOR
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365320
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Matt Arsenault [Mon, 8 Jul 2019 13:48:04 +0000 (13:48 +0000)]
GlobalISel: Check address space when looking up iPTR size
Fixes AMDGPU patterns for 32-bit address spaces always failing. Tests
will be included in future patches when additional issues are solved.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365319
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Owen Reynolds [Mon, 8 Jul 2019 13:41:52 +0000 (13:41 +0000)]
Reapply [llvm-ar][test] Increase llvm-ar test coverage
This change adds tests to cover existing llvm-ar functionality.
Differential Revision: https://reviews.llvm.org/D63935
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365318
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Owen Reynolds [Mon, 8 Jul 2019 13:08:25 +0000 (13:08 +0000)]
Revert [llvm-ar][test] Increase llvm-ar test coverage
Reverted due to test failures
Differential Revision: https://reviews.llvm.org/D63935
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365317
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Owen Reynolds [Mon, 8 Jul 2019 12:54:24 +0000 (12:54 +0000)]
[llvm-ar][test] Increase llvm-ar test coverage
This change adds tests to cover existing llvm-ar functionality.
Differential Revision: https://reviews.llvm.org/D63935
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365316
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Joel E. Denny [Mon, 8 Jul 2019 12:18:40 +0000 (12:18 +0000)]
[lit] Parse command-line options from LIT_OPTS
Similar to `FILECHECK_OPTS` for FileCheck, `LIT_OPTS` makes it easy to
adjust lit behavior when running the test suite via ninja. For
example:
```
$ LIT_OPTS='--time-tests -vv --filter=threadprivate' \
ninja check-clang-openmp
```
Reviewed By: probinson
Differential Revision: https://reviews.llvm.org/D64135
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365313
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James Henderson [Mon, 8 Jul 2019 11:41:54 +0000 (11:41 +0000)]
[docs][llvm-objcopy] Add description of binary input/output to doc
We briefly referred to being able to specify --target=binary without
explaining what binary input/output meant. This change adds a section on
this.
Reviewed by: MaskRay, abrachet
Differential Revision: https://reviews.llvm.org/D64245
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365312
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Simon Pilgrim [Mon, 8 Jul 2019 11:00:39 +0000 (11:00 +0000)]
[TargetLowering] SimplifyDemandedBits - just call computeKnownBits for BUILD_VECTOR cases.
Don't do this locally, computeKnownBits does this better (and can handle non-constant cases as well).
A next step would be to actually simplify non-constant elements - building on what we already do in SimplifyDemandedVectorElts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365309
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Mikhail Maltsev [Mon, 8 Jul 2019 09:44:52 +0000 (09:44 +0000)]
[ARM] Relax constraints on operands of VQxDMLxDH instructions
Summary:
According to a recently updated Armv8-M spec
(https://static.docs.arm.com/ddi0553/bh/DDI0553B_h_armv8m_arm.pdf) the
32-bit width versions of the following instructions:
* VQDMLADH
* VQDMLADHX
* VQRDMLADH
* VQRDMLADHX
* VQDMLSDH
* VQDMLSDHX
* VQRDMLSDH
* VQRDMLSDHX
are no longer unpredictable when their output register is the same as
one of the input registers.
This patch updates the assembler parser and the corresponding tests
and also removes @earlyclobber from the instruction constraints.
Reviewers: simon_tatham, ostannard, dmgreen, SjoerdMeijer, samparker
Reviewed By: simon_tatham
Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D64250
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365306
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Alex Bradbury [Mon, 8 Jul 2019 09:16:47 +0000 (09:16 +0000)]
[RISCV] Specify registers used in DWARF exception handling
Defines RISCV registers for getExceptionPointerRegister() and
getExceptionSelectorRegister().
Differential Revision: https://reviews.llvm.org/D63411
Patch by Edward Jones.
Modified by Alex Bradbury to add CHECK lines to exception-pointer-register.ll.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365301
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Fangrui Song [Mon, 8 Jul 2019 08:43:31 +0000 (08:43 +0000)]
[ARM] Fix null pointer dereference in CodeGen/ARM/Windows/stack-protector-msvc.ll.test after D64292/r365283
CLI.CS may not be set.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365299
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Alex Bradbury [Mon, 8 Jul 2019 08:34:16 +0000 (08:34 +0000)]
[UpdateTestChecks] Skip over .Lfunc_begin for RISC-V
This mirrors the change made for X86 in rL336987. Without this patch,
update_llc_test_checks will completely skip functions with personality
functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365297
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Jay Foad [Mon, 8 Jul 2019 07:04:58 +0000 (07:04 +0000)]
[AMDGPU] Use a named predicate instead of a magic number.
Reviewers: arsenm
Reviewed By: arsenm
Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D64201
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365294
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Craig Topper [Mon, 8 Jul 2019 06:52:49 +0000 (06:52 +0000)]
[X86] Allow execution domain fixing to turn SHUFPD into SHUFPS.
This can help with code size on SSE targets where SHUFPD requires
a 0x66 prefix and SHUFPS doesn't.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365293
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Craig Topper [Mon, 8 Jul 2019 06:52:43 +0000 (06:52 +0000)]
[X86] Make movsd commutable to shufpd with a 0x02 immediate on pre-SSE4.1 targets.
This can help avoid a copy or enable load folding.
On SSE4.1 targets we can commute it to blendi instead.
I had to make shufpd with a 0x02 immediate commutable as well
since we expect commuting to be reversible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365292
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Alex Bradbury [Mon, 8 Jul 2019 05:00:26 +0000 (05:00 +0000)]
[RISCV] Support z and i operand modifiers
Differential Revision: https://reviews.llvm.org/D57792
Patch by James Clarke.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365291
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Craig Topper [Mon, 8 Jul 2019 02:10:20 +0000 (02:10 +0000)]
[X86] Add MOVSDrr->MOVLPDrm entry to load folding table. Add custom handling to turn UNPCKLPDrr->MOVHPDrm when load is under aligned.
If the load is aligned we can turn UNPCKLPDrr into UNPCKLPDrm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365287
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Francis Visoiu Mistrih [Mon, 8 Jul 2019 02:06:34 +0000 (02:06 +0000)]
[llvm-bcanalyzer] Refactor and move to libLLVMBitReader
This allows us to use the analyzer from unit tests.
* Refactor the interface to use proper error handling for most functions
after JF's work.
* Move everything into a BitstreamAnalyzer class.
* Move that to Bitcode/BitcodeAnalyzer.h.
Differential Revision: https://reviews.llvm.org/D64116
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365286
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Kang Zhang [Mon, 8 Jul 2019 01:51:29 +0000 (01:51 +0000)]
[NFC][PowerPC] Add the test add_cmp.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365285
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Petr Hosek [Sun, 7 Jul 2019 22:12:01 +0000 (22:12 +0000)]
Revert "[IRBuilder] Fold consistently for or/and whether constant is LHS or RHS"
This reverts commit r365260 which broke the following tests:
Clang :: CodeGenCXX/cfi-mfcall.cpp
Clang :: CodeGenObjC/ubsan-nullability.m
LLVM :: Transforms/LoopVectorize/AArch64/pr36032.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365284
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Martin Storsjo [Sun, 7 Jul 2019 18:57:31 +0000 (18:57 +0000)]
[ARM] Add support for MSVC stack cookie checking
Heavily based on the same for AArch64, from SVN r346469.
Differential Revision: https://reviews.llvm.org/D64292
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365283
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Nico Weber [Sun, 7 Jul 2019 16:49:44 +0000 (16:49 +0000)]
gn build: Merge r355546
Found by inspection; the sync script doesn't sync .ipp files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365280
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Nico Weber [Sun, 7 Jul 2019 16:44:07 +0000 (16:44 +0000)]
gn build: Merge r365273
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365279
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Nico Weber [Sun, 7 Jul 2019 16:40:29 +0000 (16:40 +0000)]
gn build: Sort sync script output
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365278
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Nico Weber [Sun, 7 Jul 2019 16:36:11 +0000 (16:36 +0000)]
gn build: Sort cxx_sources in libcxx build file
Since these are in a custom list, `gn format` doesn't automatically sort
them.
Now their order matches the CMake build.
No additions or deletions, this just sorts the files that are there.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365277
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Nico Weber [Sun, 7 Jul 2019 15:43:32 +0000 (15:43 +0000)]
gn build: Merge r365258 and follow-ups r365263, r365264
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365276
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Craig Topper [Sun, 7 Jul 2019 05:33:20 +0000 (05:33 +0000)]
[X86] Make sure load isn't volatile before shrinking it in MOVDDUP isel patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365275
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David Majnemer [Sun, 7 Jul 2019 04:47:37 +0000 (04:47 +0000)]
[CodeGen] Add larger vector types for i32 and f32
Some out of tree backend require larger vector type. Since maintaining the changes out of tree is difficult due to the many manual changes needed when adding a new type we are adding it even if no backend currently use it.
Differential Revision: https://reviews.llvm.org/D64141
Patch by Thomas Raoux!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365274
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Simon Pilgrim [Sat, 6 Jul 2019 18:46:09 +0000 (18:46 +0000)]
[X86] SimplifyDemandedVectorEltsForTargetNode - fix shadow variable warning. NFCI.
Fixes cppcheck warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365271
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Simon Pilgrim [Sat, 6 Jul 2019 18:33:29 +0000 (18:33 +0000)]
[X86] LowerBuildVectorv16i8 - pull out repeated getOperand() call. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365270
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Simon Pilgrim [Sat, 6 Jul 2019 18:32:15 +0000 (18:32 +0000)]
[DAGCombine] convertBuildVecZextToZext - remove duplicate getOpcode() call. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365269
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Craig Topper [Sat, 6 Jul 2019 17:59:57 +0000 (17:59 +0000)]
[X86] Add PS<->PD domain changing support for MOVH/MOVL load instructions and MOVH store instructions.
These instructions don't have an integer domain equivalent, but
we can at least change between the two floating point domains.
This allows a smaller encoding on SSE targets if we can turn
PD into PS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365268
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Craig Topper [Sat, 6 Jul 2019 17:59:51 +0000 (17:59 +0000)]
[X86] Remove patterns from MOVLPSmr and MOVHPSmr instructions.
These patterns are the same as the MOVLPDmr and MOVHPDmr patterns,
but with a bitcast at the end. We can just select the PD instruction
and let execution domain fixing switch to PS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365267
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Craig Topper [Sat, 6 Jul 2019 17:59:45 +0000 (17:59 +0000)]
[X86] Add patterns to select MOVLPDrm from MOVSD+load and MOVHPD from UNPCKL+load.
These narrow the load so we can only do it if the load isn't
volatile.
There also tests in vector-shuffle-128-v4.ll that this should
support, but we don't seem to fold bitcast+load on pre-sse4.2
targets due to the slow unaligned mem 16 flag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365266
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Craig Topper [Sat, 6 Jul 2019 17:59:41 +0000 (17:59 +0000)]
[X86] Copy some test cases from vector-shuffle-sse1.ll to vector-shuffle-128-v4.ll and v8 where sse1 did better load folding. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365265
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Nikita Popov [Sat, 6 Jul 2019 08:54:15 +0000 (08:54 +0000)]
[LFTR] Regenerate test checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365262
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Philip Reames [Sat, 6 Jul 2019 04:28:00 +0000 (04:28 +0000)]
[IRBuilder] Fold consistently for or/and whether constant is LHS or RHS
Without this, we have the unfortunate property that tests are dependent on the order of operads passed the CreateOr and CreateAnd functions. In actual usage, we'd promptly optimize them away, but it made tests slightly more verbose than they should have been.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365260
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Philip Reames [Sat, 6 Jul 2019 03:46:18 +0000 (03:46 +0000)]
[IRBuilder] Introduce helpers for and/or of multiple values at once
We had versions of this code scattered around, so consolidate into one location.
Not strictly NFC since the order of intermediate results may change in some places, but since these operations are associatives, should not change results.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365259
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Quentin Colombet [Sat, 6 Jul 2019 00:34:54 +0000 (00:34 +0000)]
[RegisterCoalescer] Fix an overzealous assert
Although removeCopyByCommutingDef deals with full copies, it is still
possible to copy undef lanes and thus, we wouldn't have any a value
number for these lanes.
This fixes PR40215.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365256
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Matt Arsenault [Fri, 5 Jul 2019 23:33:43 +0000 (23:33 +0000)]
RegUsageInfoCollector: Skip AMDGPU entry point functions
I'm not sure if it's worth it or not to add a hook to disable the pass
for an arbitrary function.
This pass is taking up to 5% of compile time in tiny programs by
iterating through all of the physical registers in every register
class. This pass should be rewritten in terms of regunits. For now,
skip doing anything for entry point functions. The vast majority of
functions in the real world aren't callable, so just not running this
will give the majority of the benefit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365255
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Michael Liao [Fri, 5 Jul 2019 22:23:27 +0000 (22:23 +0000)]
Revert "[FileCheck] Simplify numeric variable interface"
This reverts commit
096600a4b073dd94a366cc8e57bff93c34ff6966.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365251
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Thomas Preud'homme [Fri, 5 Jul 2019 21:49:59 +0000 (21:49 +0000)]
[FileCheck] Simplify numeric variable interface
Summary:
This patch simplifies 2 aspects in the FileCheckNumericVariable code.
First, setValue() method is turned into a void function since being
called only on undefined variable is an invariant and is now asserted
rather than returned. This remove the assert from the callers.
Second, clearValue() method is also turned into a void function since
the only caller does not check its return value since it may be trying
to clear the value of variable that is already cleared without this
being noteworthy.
Reviewers: jhenderson, chandlerc, jdenny, probinson, grimar, arichardson, rnk
Subscribers: JonChesterfield, rogfer01, hfinkel, kristina, rnk, tra, arichardson, grimar, dblaikie, probinson, llvm-commits, hiraditya
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D64231
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365249
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Matt Arsenault [Fri, 5 Jul 2019 21:09:53 +0000 (21:09 +0000)]
AMDGPU: Fix assert in clang test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365245
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Nikita Popov [Fri, 5 Jul 2019 20:35:11 +0000 (20:35 +0000)]
[SystemZ] Fix addcarry of usubo (PR42512)
Only custom lower uaddo+addcarry or usubo+subcarry chains and leave
mixtures like usubo+addcarry or uaddo+subcarry to the generic
legalizer. Otherwise we run into issues because SystemZ uses
different CC values for carries and borrows.
Fixes https://bugs.llvm.org/show_bug.cgi?id=42512.
Differential Revision: https://reviews.llvm.org/D64213
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365242
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Matt Arsenault [Fri, 5 Jul 2019 20:26:13 +0000 (20:26 +0000)]
AMDGPU: Make AMDGPUPerfHintAnalysis an SCC pass
Add a string attribute instead of directly setting
MachineFunctionInfo. This avoids trying to get the analysis in the
MachineFunctionInfo in a way that doesn't work with the new pass
manager.
This will also avoid re-visiting the call graph for every single
function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365241
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Michael Liao [Fri, 5 Jul 2019 20:23:59 +0000 (20:23 +0000)]
[CodeGen] Enhance `MachineInstrSpan` to allow the end of MBB to be used.
Summary:
- Explicitly specify the parent MBB to allow the end iterator to be
used.
Reviewers: aprantl, MatzeB, craig.topper, qcolombet
Subscribers: arsenm, jvesely, nhaehnle, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D64261
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365240
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Benjamin Kramer [Fri, 5 Jul 2019 19:58:39 +0000 (19:58 +0000)]
[PowerPC] Fold another unused variable into assertion. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365237
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