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Nemanja Ivanovic [Tue, 8 Aug 2017 13:52:45 +0000 (13:52 +0000)]
[PowerPC] Don't crash on larger splats achieved through 1-byte splats
We've implemented a 1-byte splat using XXSPLTISB on P9. However, LLVM will
produce a 1-byte splat even for wider element BUILD_VECTOR nodes. This patch
prevents crashing in that situation.
Differential Revision: https://reviews.llvm.org/D35650
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310358
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Daniel Sanders [Tue, 8 Aug 2017 13:21:26 +0000 (13:21 +0000)]
[globalisel][tablegen] Remove unnecessary ; to satisfy ubuntu-gcc7.1-werror.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310357
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Nemanja Ivanovic [Tue, 8 Aug 2017 12:41:56 +0000 (12:41 +0000)]
Appease compilers that have the -Wcovered-switch-default switch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310356
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Amjad Aboud [Tue, 8 Aug 2017 12:17:56 +0000 (12:17 +0000)]
[X86] Improved X86::CMOV to Branch heuristic.
Resolved PR33954.
This patch contains two more constraints that aim to reduce the noise cases where we convert CMOV into branch for small gain, and end up spending more cycles due to overhead.
Differential Revision: https://reviews.llvm.org/D36081
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310352
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Nemanja Ivanovic [Tue, 8 Aug 2017 11:20:44 +0000 (11:20 +0000)]
[PowerPC] Eliminate compares - add i32 sext/zext handling for SETLE/SETGE
Adds handling for SETLE/SETGE comparisons on i32 values. Furthermore, it adds
the handling for the special case where RHS == 0.
Differential Revision: https://reviews.llvm.org/D34048
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310346
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Simon Pilgrim [Tue, 8 Aug 2017 11:03:30 +0000 (11:03 +0000)]
[DAGCombiner] Simplify shuffle mask index if the referenced input element is UNDEF
Fixes one of the cases in PR34041.
Differential Revision: https://reviews.llvm.org/D36393
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310344
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Daniel Sanders [Tue, 8 Aug 2017 10:44:31 +0000 (10:44 +0000)]
[globalisel][tablegen] Add support for importing 'imm' operands.
Summary:
This patch enables the import of rules containing 'imm' operands that do not
constrain the acceptable values using predicates. Support for ImmLeaf will
arrive in a later patch.
Depends on D35681
Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar
Reviewed By: rovka
Subscribers: kristof.beyls, javed.absar, igorb, llvm-commits
Differential Revision: https://reviews.llvm.org/D35833
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310343
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Chandler Carruth [Tue, 8 Aug 2017 10:13:23 +0000 (10:13 +0000)]
[PM] Fix a likely more critical infloop bug in the CGSCC pass manager.
This was just a bad oversight on my part. The code in question should
never have worked without this fix. But it turns out, there are
relatively few places that involve libfunctions that participate in
a single SCC, and unless they do, this happens to not matter.
The effect of not having this correct is that each time through this
routine, the edge from write_wrapper to write was toggled between a call
edge and a ref edge. First time through, it becomes a demoted call edge
and is turned into a ref edge. Next time it is a promoted call edge from
a ref edge. On, and on it goes forever.
I've added the asserts which should have always been here to catch silly
mistakes like this in the future as well as a test case that will
actually infloop without the fix.
The other (much scarier) infinite-inlining issue I think didn't actually
occur in practice, and I simply misdiagnosed this minor issue as that
much more scary issue. The other issue *is* still a real issue, but I'm
somewhat relieved that so far it hasn't happened in real-world code
yet...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310342
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Craig Topper [Tue, 8 Aug 2017 06:19:24 +0000 (06:19 +0000)]
[InstCombine] Cast to BinaryOperator earlier in foldSelectIntoOp to simplify the code.
We no longer need the explicit operand count check or the later dynamic cast.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310339
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Tom Stellard [Tue, 8 Aug 2017 05:52:00 +0000 (05:52 +0000)]
AMDGPU: Fix warnings introduced by r310336
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310337
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Tom Stellard [Tue, 8 Aug 2017 04:57:55 +0000 (04:57 +0000)]
AMDGPU: Move R600 parts of AMDGPUISelDAGToDAG into their own class
Summary: This refactoring is required in order to split the R600 and GCN tablegen files.
Reviewers: arsenm
Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, llvm-commits, t-tye
Differential Revision: https://reviews.llvm.org/D36286
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310336
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Konstantin Zhuravlyov [Tue, 8 Aug 2017 04:28:31 +0000 (04:28 +0000)]
AMDGPU: Also remove SI from docs
Differential Revision: https://reviews.llvm.org/D36424
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310335
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Chandler Carruth [Tue, 8 Aug 2017 02:27:49 +0000 (02:27 +0000)]
[PM] Relax the spelling of a pass name slightly in this test.
I forgot that MSVC doesn't preserve this typedef, my bad.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310334
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Chandler Carruth [Tue, 8 Aug 2017 02:24:20 +0000 (02:24 +0000)]
[PM] Fix new LoopUnroll function pass by invalidating loop analysis
results when a loop is completely removed.
This is very hard to manifest as a visible bug. You need to arrange for
there to be a subsequent allocation of a 'Loop' object which gets the
exact same address as the one which the unroll deleted, and you need the
LoopAccessAnalysis results to be significant in the way that they're
stale. And you need a million other things to align.
But when it does, you get a deeply mysterious crash due to actually
finding a stale analysis result. This fixes the issue and tests for it
by directly checking we successfully invalidate things. I have not been
able to get *any* test case to reliably trigger this. Changes to LLVM
itself caused the only test case I ever had to cease to crash.
I've looked pretty extensively at less brittle ways of fixing this and
they are actually very, very hard to do. This is a somewhat strange and
unusual case as we have a pass which is deleting an IR unit, but is not
running within that IR unit's pass framework (which is what handles this
cleanly for the normal loop unroll). And where there isn't a definitive
way to clear *all* of the stale cache entries. And where the pass *is*
updating the core analysis that provides the IR units!
For example, we don't have any of these problems with Function analyses
because it is easy to clear out function analyses when the functions
themselves may have been deleted -- we clear an entire module's worth!
But that is too heavy of a hammer down here in the LoopAnalysisManager
layer.
A better long-term solution IMO is to require that AnalysisManager's
make their keys durable to this kind of thing. Specifically, when
caching an analysis for one IR unit that is conceptually "owned" by
a higher level IR unit, the AnalysisManager should incorporate this into
its data structures so that we can reliably clear these results without
having to teach each and every pass to do so manually as we do here. But
that is a change for another day as it will be a fairly invasive change
to the AnalysisManager infrastructure. Until then, this fortunately
seems to be quite rare.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310333
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Eugene Zelenko [Tue, 8 Aug 2017 00:47:13 +0000 (00:47 +0000)]
[AMDGPU] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310328
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Kostya Serebryany [Tue, 8 Aug 2017 00:17:20 +0000 (00:17 +0000)]
[libFuzzer] simplify code, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310326
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Kostya Serebryany [Tue, 8 Aug 2017 00:14:49 +0000 (00:14 +0000)]
[libFuzzer] remove stale code
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310325
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Kostya Serebryany [Tue, 8 Aug 2017 00:12:09 +0000 (00:12 +0000)]
[libFuzzer] simplify the implementation of -print_coverage=1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310324
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Craig Topper [Mon, 7 Aug 2017 22:35:55 +0000 (22:35 +0000)]
[KnownBits] Fix copy pasto in comment. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310320
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Simon Pilgrim [Mon, 7 Aug 2017 22:20:06 +0000 (22:20 +0000)]
[X86][AVX] Added test for broadcast shuffle from binary sources with undefs (D36393)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310317
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Matt Arsenault [Mon, 7 Aug 2017 22:00:58 +0000 (22:00 +0000)]
AMDGPU: Implement getMinimumNopSize
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310310
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Reid Kleckner [Mon, 7 Aug 2017 21:23:38 +0000 (21:23 +0000)]
[Object] Initialize LoadConfig member to null
Executables may not contain a load config, and clients should be able to
test for nullability. Previously we'd return uninitialized memory. Now
getLoadConfig32/64 return valid pointers or null.
Fixes PR34108
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310308
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George Karpenkov [Mon, 7 Aug 2017 20:56:11 +0000 (20:56 +0000)]
Do not instrument libFuzzer itself when built with -DLLVM_USE_SANITIZE_COVERAGE
Fixes regression from https://reviews.llvm.org/D36295
Differential Revision: https://reviews.llvm.org/D36428
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310305
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Zachary Turner [Mon, 7 Aug 2017 20:24:01 +0000 (20:24 +0000)]
[llvm-pdbutil] Don't crash when a section contrib's isect is invalid.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310298
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Dehao Chen [Mon, 7 Aug 2017 20:23:20 +0000 (20:23 +0000)]
Move the SampleProfileLoader right after EarlyFPM.
Summary: SampleProfileLoader pass do need to happen after some early cleanup passes so that inlining can happen correctly inside the SampleProfileLoader pass.
Reviewers: chandlerc, davidxl, tejohnson
Reviewed By: chandlerc, tejohnson
Subscribers: sanjoy, mehdi_amini, eraman, llvm-commits
Differential Revision: https://reviews.llvm.org/D36333
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310296
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Evgeny Stupachenko [Mon, 7 Aug 2017 19:56:34 +0000 (19:56 +0000)]
Reapply fix PR23384 (part 3 of 3) r304824 (was reverted in r305720).
The root cause of reverting was fixed - PR33514.
Summary:
The patch makes instruction count the highest priority for
LSR solution for X86 (previously registers had highest priority).
Reviewers: qcolombet
Differential Revision: http://reviews.llvm.org/D30562
From: Evgeny Stupachenko <evstupac@gmail.com>
<evgeny.v.stupachenko@intel.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310289
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Aaron Ballman [Mon, 7 Aug 2017 19:26:17 +0000 (19:26 +0000)]
Removing an unused variable that was missed with the refactoring in r310272; NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310285
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Connor Abbott [Mon, 7 Aug 2017 19:10:56 +0000 (19:10 +0000)]
[AMDGPU] Add pseudo "old" source to all DPP instructions
Summary:
All instructions with the DPP modifier may not write to certain lanes of
the output if bound_ctrl=1 is set or any bits in bank_mask or row_mask
aren't set, so the destination register may be both defined and modified.
The right way to handle this is to add a constraint that the destination
register is the same as one of the inputs. We could tie the destination
to the first source, but that would be too restrictive for some use-cases
where we want the destination to be some other value before the
instruction executes. Instead, add a fake "old" source and tie it to the
destination. Effectively, the "old" source defines what value unwritten
lanes will get. We'll expose this functionality to users with a new
intrinsic later.
Also, we want to use DPP instructions for computing derivatives, which
means we need to set WQM for them. We also need to enable the entire
wavefront when using DPP intrinsics to implement nonuniform subgroup
reductions, since otherwise we'll get incorrect results in some cases.
To accomodate this, add a new operand to all DPP instructions which will
be interpreted by the SI WQM pass. This will be exposed with a new
intrinsic later. We'll also add support for Whole Wavefront Mode later.
I also fixed llvm.amdgcn.mov.dpp to overwrite the source and fixed up
the test. However, I could also keep the old behavior (where lanes that
aren't written are undefined) if people want it.
Reviewers: tstellar, arsenm
Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye
Differential Revision: https://reviews.llvm.org/D34716
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310283
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Matt Arsenault [Mon, 7 Aug 2017 18:30:35 +0000 (18:30 +0000)]
AMDGPU: Remove -mcpu=SI
Leftover from before amdgcn/r600 split.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310277
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Matt Arsenault [Mon, 7 Aug 2017 18:12:48 +0000 (18:12 +0000)]
AMDGPU: Remove redundant opt level check
addOptimizedRegAlloc isn't used for -O0 already.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310275
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Matt Arsenault [Mon, 7 Aug 2017 18:12:47 +0000 (18:12 +0000)]
AMDGPU: Remove FixControlFlowLiveIntervals pass
This hasn't done anything in a long time. This was
running after the the control flow pseudos were expanded,
so this would never find them. The control flow pseudo
expansion was moved to solve the problem this pass was
supposed to solve in the first place, except handling
it earlier also fixes it for fast regalloc which doesn't
use LiveIntervals.
Noticed by checking LCOV reports.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310274
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Craig Topper [Mon, 7 Aug 2017 18:10:39 +0000 (18:10 +0000)]
[InstCombine] Support (X | C1) & C2 --> (X & C2^(C1&C2)) | (C1&C2) for vector splats
Note the original code I deleted incorrectly listed this as (X | C1) & C2 --> (X & C2^(C1&C2)) | C1 Which is only valid if C1 is a subset of C2. This relied on SimplifyDemandedBits to remove any extra bits from C1 before we got to that code.
My new implementation avoids relying on that behavior so that it can be naively verified with alive.
Differential Revision: https://reviews.llvm.org/D36384
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310272
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Matt Arsenault [Mon, 7 Aug 2017 17:08:44 +0000 (17:08 +0000)]
AMDGPU: Use a custom areInlineCompatible
Fixes not inlining OpenCL library functions on AMDGPU,
which don't have an explicitly set target-cpu.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310269
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Simon Pilgrim [Mon, 7 Aug 2017 16:49:09 +0000 (16:49 +0000)]
[X86][AVX] Add full test coverage of subvector_broadcasts from registers
X86SubVBroadcast is for memory subvector broadcasts, but we must test that it handles all cases without the load as well just in case.
This was noticed while I was triaging the test cases from PR34041.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310268
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Simon Dardis [Mon, 7 Aug 2017 16:08:11 +0000 (16:08 +0000)]
[DebugInfo][DWARF] Address paulr's comment on rL310253.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310267
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Simon Pilgrim [Mon, 7 Aug 2017 15:50:43 +0000 (15:50 +0000)]
[X86][AVX] Cleanup subvector broadcast tests - remove old prefixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310265
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Sanjay Patel [Mon, 7 Aug 2017 15:47:48 +0000 (15:47 +0000)]
[x86] revert r310208 to investigate test-suite failures (PR34105 / PR34097)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310264
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Simon Dardis [Mon, 7 Aug 2017 15:37:57 +0000 (15:37 +0000)]
[DebugInfo][DWARF] Correct some usages of PRIx32 to PRIx64
These lead to tests failing spuriously as the values after being rendered to a
string were incorrect.
Reviewers: clayborg
Differential Revision: https://reviews.llvm.org/D36319
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310262
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Alexey Bataev [Mon, 7 Aug 2017 15:25:49 +0000 (15:25 +0000)]
[SLP] General improvements of SLP vectorization process.
Patch tries to improve two-pass vectorization analysis, existing in SLP vectorizer. What it does:
1. Defines key nodes, that are the vectorization roots. Previously vectorization started if StoreInst or ReturnInst is found. For now, the vectorization started for all Instructions with no users and void types (Terminators, StoreInst) + CallInsts.
2. CmpInsts, InsertElementInsts and InsertValueInsts are stored in the
array. This array is processed only after the vectorization of the
first-after-these instructions key node is finished. Vectorization goes
in reverse order to try to vectorize as much code as possible.
Reviewers: mzolotukhin, Ayal, mkuper, gilr, hfinkel, RKSimon
Subscribers: ashahid, anemet, RKSimon, mssimpso, llvm-commits
Differential Revision: https://reviews.llvm.org/D29826
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310260
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Matt Arsenault [Mon, 7 Aug 2017 14:58:43 +0000 (14:58 +0000)]
Fix typo in comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310259
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Matt Arsenault [Mon, 7 Aug 2017 14:58:04 +0000 (14:58 +0000)]
AMDGPU: Cleanup subtarget features
Try to avoid mutually exclusive features. Don't use
a real default GPU, and use a fake "generic". The goal
is to make it easier to see which set of features are
incompatible between feature strings.
Most of the test changes are due to random scheduling changes
from not having a default fullspeed model.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310258
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Alexey Bataev [Mon, 7 Aug 2017 14:51:52 +0000 (14:51 +0000)]
Revert "[SLP] General improvements of SLP vectorization process."
This reverts commit r310255.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310257
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Nirav Dave [Mon, 7 Aug 2017 14:07:49 +0000 (14:07 +0000)]
[DAG] Extend visitSCALAR_TO_VECTOR optimization to truncated vector.
Relanding after case to insert explicit truncation as necessary.
Allow SCALAR_TO_VECTOR of EXTRACT_VECTOR_ELT to reduce to
EXTRACT_SUBVECTOR of vector shuffle when output is smaller. Marginally
improves vector shuffle computations.
Reviewers: efriedma, RKSimon, spatel
Subscribers: javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D35566
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310256
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Alexey Bataev [Mon, 7 Aug 2017 14:03:17 +0000 (14:03 +0000)]
[SLP] General improvements of SLP vectorization process.
Summary:
Patch tries to improve two-pass vectorization analysis, existing in SLP vectorizer. What it does:
1. Defines key nodes, that are the vectorization roots. Previously vectorization started if StoreInst or ReturnInst is found. For now, the vectorization started for all Instructions with no users and void types (Terminators, StoreInst) + CallInsts.
2. CmpInsts, InsertElementInsts and InsertValueInsts are stored in the array. This array is processed only after the vectorization of the first-after-these instructions key node is finished. Vectorization goes in reverse order to try to vectorize as much code as possible.
Reviewers: mzolotukhin, Ayal, mkuper, gilr, hfinkel, RKSimon
Subscribers: ashahid, anemet, RKSimon, mssimpso, llvm-commits
Differential Revision: https://reviews.llvm.org/D29826
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310255
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Nirav Dave [Mon, 7 Aug 2017 13:55:27 +0000 (13:55 +0000)]
[TableGen] AsmMatcher: fix OpIdx computation when HasOptionalOperands is true
Relanding after fixing UB issue with DefaultOffsets.
Consider the following instruction: "inst.eq $dst, $src" where ".eq"
is an optional flag operand. The $src and $dst operands are
registers. If we parse the instruction "inst r0, r1", the flag is not
present and it will be marked in the "OptionalOperandsMask" variable.
After the matching is complete we call the "convertToMCInst" method.
The current implementation works only if the optional operands are at
the end of the array. The "Operands" array looks like [token:"inst",
reg:r0, reg:r1]. The first operand that must be added to the MCInst
is the destination, the r0 register. The "OpIdx" (in the Operands
array) for this register is 2. However, since the flag is not present
in the Operands, the actual index for r0 should be 1. The flag is not
present since we rely on the default value.
This patch removes the "NumDefaults" variable and replaces it with an
array (DefaultsOffset). This array contains an index for each operand
(excluding the mnemonic). At each index, the array contains the
number of optional operands that should be subtracted. For the
previous example, this array looks like this: [0, 1, 1]. When we need
to access the r0 register, we compute its index as 2 -
DefaultsOffset[1] = 1.
Patch by Alexandru Guduleasa!
Reviewers: SamWot, nhaustov, niravd
Reviewed By: niravd
Subscribers: vitalybuka, llvm-commits
Differential Revision: https://reviews.llvm.org/D35998
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310254
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Simon Dardis [Mon, 7 Aug 2017 13:30:03 +0000 (13:30 +0000)]
[DebugInfo][DWARF] Use PRIx64 explicitly in output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310253
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Michael Zuckerman [Mon, 7 Aug 2017 13:22:39 +0000 (13:22 +0000)]
[X86][LLVM]Expanding Supports lowerInterleavedStore() in X86InterleavedAccess (VF16 stride 4).
This patch expands the support of lowerInterleavedStore to 16x8i stride 4.
LLVM creates suboptimal shuffle code-gen for AVX2. In overall, this patch is a specific fix for the pattern (Strid=4 VF=16) and we plan to include more patterns in the future.
The patch goal is to optimize the following sequence:
At the end of the computation, we have ymm2, ymm0, ymm12 and ymm3 holding
each 16 chars:
c0, c1, , c16
m0, m1, , m16
y0, y1, , y16
k0, k1, ., k16
And these need to be transposed/interleaved and stored like so:
c0 m0 y0 k0 c1 m1 y1 k1 c2 m2 y2 k2 c3 m3 y3 k3 ....
Differential Revision: https://reviews.llvm.org/D35829
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310252
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Dmitry Preobrazhensky [Mon, 7 Aug 2017 13:14:12 +0000 (13:14 +0000)]
[AMDGPU][MC] Corrected VOP3 version of v_interp_* instructions for VI
See bug 32621: https://bugs.llvm.org//show_bug.cgi?id=32621
Reviewers: vpykhtin, SamWot, arsenm
Differential Revision: https://reviews.llvm.org/D35902
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310251
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Simon Dardis [Mon, 7 Aug 2017 12:29:38 +0000 (12:29 +0000)]
[llvm-objdump] Use PRIx64 for output of ARM64_RELOC_ADDEND
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310250
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Simon Pilgrim [Mon, 7 Aug 2017 12:24:33 +0000 (12:24 +0000)]
[X86][AVX] Added test for broadcast shuffle with undefs (PR34041)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310249
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Andre Vieira [Mon, 7 Aug 2017 08:41:05 +0000 (08:41 +0000)]
[ARM] Fix assembly and disassembly for VMRS/VMSR
This patch addresses two issues with assembly and disassembly for VMRS/VMSR:
1.currently VMRS/VMSR instructions accessing fpsid, mvfr{0-2} and fpexc, are
accepted for non ARMv8-A targets.
2. all VMRS/VMSR instructions accept writing/reading to PC and SP, when only
ARMv7-A and ARMv8-A should be allowed to write/read to SP and none to PC.
This patch addresses those issues and adds tests for these cases.
Differential Revision: https://reviews.llvm.org/D36306
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310243
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Vitaly Buka [Mon, 7 Aug 2017 07:35:33 +0000 (07:35 +0000)]
[asan] Fix asan dynamic shadow check before copyArgsPassedByValToAllocas
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310242
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Vitaly Buka [Mon, 7 Aug 2017 07:12:34 +0000 (07:12 +0000)]
[asan] Disable checking of arguments passed by value for --asan-force-dynamic-shadow
Fails with "Instruction does not dominate all uses!"
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310241
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Vitaly Buka [Mon, 7 Aug 2017 07:12:33 +0000 (07:12 +0000)]
Add -asan-force-dynamic-shadow test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310240
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Guy Blank [Mon, 7 Aug 2017 05:51:14 +0000 (05:51 +0000)]
[SelectionDAG] reset NewNodesMustHaveLegalTypes flag between basic blocks
The NewNodesMustHaveLegalTypes flag is set to false at the beginning of CodeGenAndEmitDAG, and set to true after legalizing types.
But before calling CodeGenAndEmitDAG we build the DAG for the basic block.
So for the first basic block NewNodesMustHaveLegalTypes would be 'false' during the SDAG building, and for all other basic blocks it would be 'true'.
This patch sets the flag to false before SDAG building each basic block.
Differential Revision:
https://reviews.llvm.org/D33435
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310239
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Davide Italiano [Mon, 7 Aug 2017 01:57:21 +0000 (01:57 +0000)]
[Reassociate] Use a range loop for clarity. NFCI.
While here, rename `i` to `Rank` as the latter is more
self-explanatory (and this code also uses `I` two lines below to
identify an Instruction).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310238
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Davide Italiano [Mon, 7 Aug 2017 01:49:09 +0000 (01:49 +0000)]
[Reassociate] Try to bail out early when canonicalizing.
This commit rearranges the checks to avoid calls to getRank()
when not needed (e.g. when RHS == LHS).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310237
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Craig Topper [Sun, 6 Aug 2017 23:30:49 +0000 (23:30 +0000)]
[InstCombine] Remove shift handling from OptAndOp.
Summary: This is all handled by SimplifyDemandedBits.
Reviewers: spatel, davide
Reviewed By: davide
Subscribers: davide, llvm-commits
Differential Revision: https://reviews.llvm.org/D36382
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310234
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Craig Topper [Sun, 6 Aug 2017 23:11:49 +0000 (23:11 +0000)]
[InstCombine] Support (X ^ C1) & C2 --> (X & C2) ^ (C1&C2) for vector splats.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310233
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Craig Topper [Sun, 6 Aug 2017 22:17:21 +0000 (22:17 +0000)]
[InstCombine] Support '(C - X) ^ signmask -> (C + signmask - X)' and '(X + C) ^ signmask -> (X + C + signmask)' for vector splats.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310232
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Simon Pilgrim [Sun, 6 Aug 2017 20:50:19 +0000 (20:50 +0000)]
[SLPVectorizer][X86] Cleanup test case. NFCI
Remove excess attributes/metadata
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310227
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Martin Storsjo [Sun, 6 Aug 2017 19:58:13 +0000 (19:58 +0000)]
[llvm-dlltool] Map the "arm64" machine type
Differential Revision: https://reviews.llvm.org/D36365
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310223
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Matt Arsenault [Sun, 6 Aug 2017 18:13:23 +0000 (18:13 +0000)]
AMDGPU: Fix typo in feature description
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310217
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Sanjay Patel [Sun, 6 Aug 2017 16:27:07 +0000 (16:27 +0000)]
[x86] use more shift or LEA for select-of-constants
We can convert any select-of-constants to math ops:
http://rise4fun.com/Alive/d7d
For this patch, I'm enhancing an existing x86 transform that uses fake multiplies
(they always become shl/lea) to avoid cmov or branching. The current code misses
cases where we have a negative constant and a positive constant, so this is just
trying to plug that hole.
The DAGCombiner diff prevents us from hitting a terrible inefficiency: we can start
with a select in IR, create a select DAG node, convert it into a sext, convert it
back into a select, and then lower it to sext machine code.
Some notes about the test diffs:
1. 2010-08-04-MaskedSignedCompare.ll - We were creating control flow that didn't exist in the IR.
2. memcmp.ll - Choose -1 or 1 is the case that got me looking at this again. I
think we could avoid the push/pop in some cases if we used 'movzbl %al' instead of an xor on
a different reg? That's a post-DAG problem though.
3. mul-constant-result.ll - The trade-off between sbb+not vs. setne+neg could be addressed if
that's a regression, but I think those would always be nearly equivalent.
4. pr22338.ll and sext-i1.ll - These tests have undef operands, so I don't think we actually care about these diffs.
5. sbb.ll - This shows a win for what I think is a common case: choose -1 or 0.
6. select.ll - There's another borderline case here: cmp+sbb+or vs. test+set+lea? Also, sbb+not vs. setae+neg shows up again.
7. select_const.ll - These are motivating cases for the enhancement; replace cmov with cheaper ops.
Assembly differences between movzbl and xor to avoid a partial reg stall are caused later by the X86 Fixup SetCC pass.
Differential Revision: https://reviews.llvm.org/D35340
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310208
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Simon Pilgrim [Sun, 6 Aug 2017 13:21:09 +0000 (13:21 +0000)]
[X86] Add comment to match closing Defs = [FPSW]. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310202
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Simon Pilgrim [Sun, 6 Aug 2017 12:17:10 +0000 (12:17 +0000)]
[X86][X87] Regenerate inline-asm tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310201
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Meador Inge [Sun, 6 Aug 2017 12:02:17 +0000 (12:02 +0000)]
[AVR] Compute code model if one is not provided
The patch from r310028 fixed things to work with the new
`LLVMTargetMachine` constructor that came in on r309911.
However, the fix was partial since an object of type
`CodeModel::Model` must be passed to `LLVMTargetMachine`
(not one of `Optional<CodeModel::Model>`).
This patch fixes the problem in the same fashion that r309911
did for other machines: by checking if the passed optional
code model has a value and using `CodeModel::Small` if not.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310200
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Simon Pilgrim [Sun, 6 Aug 2017 11:22:33 +0000 (11:22 +0000)]
[X86][X87] Add test case for PR34080
Test with/without the sandybridge (default) model for SSE2, SSE3 and AVX targets.
pre-SSE3 the issue is the order of the fpsw and fpcw load/stores (with SSE3 trunc-store FIST instructions avoid the sw/cw manipulations).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310198
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Craig Topper [Sun, 6 Aug 2017 06:28:41 +0000 (06:28 +0000)]
[InstCombine] Support ~(c-X) --> X+(-c-1) and ~(X-c) --> (-c-1)-X for splat vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310195
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Craig Topper [Sat, 5 Aug 2017 23:34:44 +0000 (23:34 +0000)]
[X86] Enable isel to use the PAUSE instruction even when SSE2 is disabled
Summary:
On older processors this instruction encoding is treated as a NOP.
MSVC doesn't disable intrinsics based on features the way clang/gcc does. Because the PAUSE instruction encoding doesn't crash older processors, some software out there uses these intrinsics without checking for SSE2.
This change also seems to also be consistent with gcc behavior.
Fixes PR34079
Reviewers: RKSimon, zvi
Reviewed By: RKSimon
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D36361
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310190
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Chandler Carruth [Sat, 5 Aug 2017 22:48:37 +0000 (22:48 +0000)]
[ADT] Add a much simpler loop to DenseMap::clear when the types are
POD-like and we can just splat the empty key across memory.
Sadly we can't optimize the normal loop well enough because we can't
turn the conditional store into an unconditional store according to the
memory model.
This loop actually showed up in a profile of code that was calling clear
as a serious source of time. =[
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310189
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Craig Topper [Sat, 5 Aug 2017 22:44:38 +0000 (22:44 +0000)]
[InstCombine] Regenerate test28_sub test case in xor.ll that I forgot to commit after fixing a typo in r310186.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310188
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Craig Topper [Sat, 5 Aug 2017 20:00:44 +0000 (20:00 +0000)]
[InstCombine] Fold (C - X) ^ signmask -> (C + signmask - X).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310186
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Craig Topper [Sat, 5 Aug 2017 20:00:42 +0000 (20:00 +0000)]
[InstCombine] Teach the code that pulls logical operators through constant shifts to handle vector splats too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310185
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Craig Topper [Sat, 5 Aug 2017 20:00:41 +0000 (20:00 +0000)]
[InstCombine] Support vector splats in foldSelectICmpAnd.
Unfortunately, it looks like there's some other missed optimizations in the generated code for some of these cases. I'll try to look at some of those next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310184
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Dinar Temirbulatov [Sat, 5 Aug 2017 18:43:52 +0000 (18:43 +0000)]
[SLPVectorizer] Add extra parameter to setInsertPointAfterBundle to handle different opcodes, NFCI.
Differential Revision: https://reviews.llvm.org/D35769
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310183
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Sanjay Patel [Sat, 5 Aug 2017 15:19:18 +0000 (15:19 +0000)]
[InstCombine] refactor trunc(binop) transforms; NFCI
In addition to moving the shift transforms over, we may want to
detect too-wide rotate patterns here (PR34046).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310181
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Florian Hahn [Sat, 5 Aug 2017 15:14:06 +0000 (15:14 +0000)]
[ARM] The ARM backend is MachineVerifier clean now.
Summary: Thanks everyone involved in fixing the outstanding issues.
Reviewers: rovka, MatzeB, efriedma
Reviewed By: MatzeB
Subscribers: aemerson, javed.absar, llvm-commits, kristof.beyls
Differential Revision: https://reviews.llvm.org/D36153
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310180
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Florian Hahn [Sat, 5 Aug 2017 12:13:13 +0000 (12:13 +0000)]
[ARM] Add registers to debuginfo MIR test cases.
Summary:
MIRParserImpl::computeFunctionProperties uses MRI.getNumVirtRegs() to
set the NoVReg property. By adding a bunch of registers to the MIR test
cases, the NoVReg property is not set when importing the MIR. Otherwise
NoVReg is set after instruction selection while the machine instructions
still contain virtual registers, causing expensive checks to fail.
Reviewers: efriedma, MatzeB, aprantl
Reviewed By: MatzeB, aprantl
Subscribers: aemerson, javed.absar, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D36152
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310178
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Chandler Carruth [Sat, 5 Aug 2017 08:33:16 +0000 (08:33 +0000)]
[LCG] Remove yet another variable only used inside of asserts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310174
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Benjamin Kramer [Sat, 5 Aug 2017 08:28:48 +0000 (08:28 +0000)]
[LCG] Fold otherwise unused variable into assert.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310173
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Matt Arsenault [Sat, 5 Aug 2017 07:50:18 +0000 (07:50 +0000)]
IPRA: Don't crash on null getCallPreservedMask
Kernels aren't callable, so they don't have a call preserved mask.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310172
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Chandler Carruth [Sat, 5 Aug 2017 07:37:00 +0000 (07:37 +0000)]
[LCG] Completely remove the parent set and leaf tracking for RefSCCs.
After the previous series of patches, this is now trivial and deletes
a pretty astonishing amount of complexity. This has been a long time
coming, as the move toward a PO sequence of RefSCCs started eroding the
underlying use cases for this half of the data structure.
Among the biggest advantages here is that now there aren't two
independent data structures that need to stay in sync.
Some of my profiling has also indicated that updating the parent sets
was among the most expensive parts of the lazy call graph. Eliminating
it whole sale is likely to be a nice win in terms of compile time.
Last but not least, I had discussed with some folks previously keeping
it around for asserts and other correctness checking, but once the
fundamentals of the parent and child checking were implemented without
the parent sets their value in correctness checking was tiny and no
where near worth the cost of the complexity required to keep everything
up-to-date.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310171
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Chandler Carruth [Sat, 5 Aug 2017 06:24:09 +0000 (06:24 +0000)]
[LCG] Re-implement the basic isParentOf, isAncestorOf, isChildOf, and
isDescendantOf methods on RefSCCs in terms of the forward edges rather
than the parent sets.
This is technically slower, but probably not interestingly slower, and
all of these routines were already so expensive that they're guarded
behind both !NDEBUG and EXPENSIVE_CHECKS.
This removes another non-critical usage of parent sets.
I've also added some comments to try and help clarify to any potential
users the costs of these routines. They're mostly useful for debugging,
asserts, or other queries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310170
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Chandler Carruth [Sat, 5 Aug 2017 05:47:37 +0000 (05:47 +0000)]
[LCG] Add the concept of a "dead" node and use it to avoid a complex
walk over the parent set.
When removing a single function from the call graph, we previously would
walk the entire RefSCC's parent set and then walk every outgoing edge
just to find the ones to remove. In addition to this being quite high
complexity in theory, it is also the last fundamental use of the parent
sets.
With this change, when we remove a function we transform the node
containing it to be recognizably "dead" and then teach the edge
iterators to recognize edges to such nodes and skip them the same way
they skip null edges.
We can't move fully to using "dead" nodes -- when disconnecting two live
nodes we need to null out the edge. But the complexity this adds to the
edge sequence isn't too bad and the simplification of lazily handling
this seems like a significant win.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310169
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Joel Jones [Sat, 5 Aug 2017 04:30:55 +0000 (04:30 +0000)]
[AArch64] LSE Atomics reorg - part 1
Add memory synchronization semantics to LSE Atomics.
The memory semantics feature will be added in a subsequent patch.
In this patch, several corrections were added to the existing LSE Atomics
implementation, based on the ARM Errata D11904 from 05/12/2017.
Patch by: steleman
Differential Revision: https://reviews.llvm.org/D35319
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310167
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Chandler Carruth [Sat, 5 Aug 2017 04:04:06 +0000 (04:04 +0000)]
[LCG] Replace an implicit bool operator with a named function. (NFC)
The definition of 'false' here was already pretty vague and debatable,
and I'm about to add another potential 'false' that would actually make
much more sense in a bool operator. Especially given how rarely this is
used, a nicely named method seems better.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310165
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Chandler Carruth [Sat, 5 Aug 2017 03:37:39 +0000 (03:37 +0000)]
[LCG] When removing a dead function and clearing out the data
structures, actually null out the graph pointers as well. We won't ever
update these, and we certainly shouldn't be calling any methods on them,
so it seems good to defensively nuke them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310164
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Chandler Carruth [Sat, 5 Aug 2017 03:37:39 +0000 (03:37 +0000)]
[LCG] Rather than walking the directed graph structure to update graph
pointers in node objects, just walk the map from function to node.
It doesn't have stable ordering, but works just as well and is much
simpler. We don't need ordering when just updating internal pointers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310163
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Chandler Carruth [Sat, 5 Aug 2017 03:37:38 +0000 (03:37 +0000)]
[LCG] Remove the complex walk of the parent sets to update graph
pointers.
This is completely unnecessary as we have a trivial list of RefSCCs now
that we can walk.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310162
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Chandler Carruth [Sat, 5 Aug 2017 03:37:37 +0000 (03:37 +0000)]
[LCG] Remove the use of the parent sets to compute connectivity when
merging RefSCCs.
The logic to directly use the reference edges is simpler and not
substantially slower (despite the comments to the contrary) because this
is not actually an especially hot part of LCG in practice.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310161
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Craig Topper [Sat, 5 Aug 2017 01:45:17 +0000 (01:45 +0000)]
[InstCombine] In foldSelectICmpAnd, if we need to to truncate from the 'and' type to the 'select' type, do it after shifting right instead of just bailing.
Previously we were always trying to emit the zext or truncate before any shift. This meant if the 'and' mask was larger than the size of the truncate we would skip the transformation.
Now we shift the result of the and right first leaving the bit within the range of the truncate.
This matches what we are doing in foldSelectICmpAndOr for the same problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310159
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Reid Kleckner [Sat, 5 Aug 2017 00:15:40 +0000 (00:15 +0000)]
Commit the local change I had to make my test pass
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310153
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Reid Kleckner [Sat, 5 Aug 2017 00:10:43 +0000 (00:10 +0000)]
[X86] Teach fastisel to select calls to dllimport functions
Summary:
Direct calls to dllimport functions are very common Windows. We should
add them to the -O0 fast path.
Reviewers: rafael
Subscribers: llvm-commits, hiraditya
Differential Revision: https://reviews.llvm.org/D36197
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310152
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Kostya Serebryany [Fri, 4 Aug 2017 23:49:53 +0000 (23:49 +0000)]
[libFuzzer] use the in-binary pc table (instead of PCs captured at run-time) to implement -exit_on_src_pos
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310151
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Craig Topper [Fri, 4 Aug 2017 23:36:03 +0000 (23:36 +0000)]
[X86] Regenerate the fsin/fcos instruction test using update_llc_test_checks.py. NFC
This looks to have been converted from a grep based test at some point in a really strange way.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310150
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Petr Hosek [Fri, 4 Aug 2017 23:18:18 +0000 (23:18 +0000)]
[llvm][llvm-objcopy] When outputting to binary don't output segments that cover no sections
Sometimes LLD will produce a PT_LOAD segment that only covers the
headers (and covers no sections). GNU objcopy does not output the
segment contents for these sections. In particular this is an issue in
building magenta because the final link step for the kernel would
produce just such a PT_LOAD segment. This change is to support this case
and to match what GNU objcopy does in this case.
Patch by Jake Ehrlich
Differential Revision: https://reviews.llvm.org/D36196
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310149
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Kostya Serebryany [Fri, 4 Aug 2017 23:13:58 +0000 (23:13 +0000)]
[libFuzzer] print PCs using the in-binary PC-table instead of relying on PCs captured at run-time
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310148
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Adrian McCarthy [Fri, 4 Aug 2017 22:37:58 +0000 (22:37 +0000)]
Enable llvm-pdbutil to list enumerations using native PDB reader
This extends the native reader to enable llvm-pdbutil to list the enums in a
PDB and it includes a simple test. It does not yet list the values in the
enumerations, which requires an actual implementation of
NativeEnumSymbol::FindChildren.
To exercise this code, use a command like:
llvm-pdbutil pretty -native -enums foo.pdb
Differential Revision: https://reviews.llvm.org/D35738
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310144
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Sanjay Patel [Fri, 4 Aug 2017 22:30:34 +0000 (22:30 +0000)]
[InstCombine] narrow truncated add/sub/mul with constant
Name: narrow_sub
%sub = sub i32 C1, %x
%r = trunc i32 %sub to i8
=>
%xn = trunc i32 %x to i8
%narrowC = trunc i32 C1 to i8
%r = sub i8 %narrowC, %xn
Name: narrow_add
%add = add i32 %x, C1
%r = trunc i32 %add to i8
=>
%xn = trunc i32 %x to i8
%narrowC = trunc i32 C1 to i8
%r = add i8 %xn, %narrowC
Name: narrow_mul
%mul = mul i32 %x, C1
%r = trunc i32 %mul to i8
=>
%xn = trunc i32 %x to i8
%narrowC = trunc i32 C1 to i8
%r = mul i8 %xn, %narrowC
http://rise4fun.com/Alive/QpS
This doesn't solve PR34046 (failure to recognize rotate):
https://bugs.llvm.org/show_bug.cgi?id=34046
...but it reduces an extra complication in the description examples
to a form that we can more easily match.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310141
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