OSDN Git Service
Calin Juravle [Tue, 21 Apr 2015 13:08:56 +0000 (13:08 +0000)]
am
2b25ba3c: Merge "[optimzing] Fix codegen bug and improve type propagation"
* commit '
2b25ba3ca9452415cdce88478726272aeec3f77c':
[optimzing] Fix codegen bug and improve type propagation
Calin Juravle [Tue, 21 Apr 2015 13:00:25 +0000 (13:00 +0000)]
Merge "[optimzing] Fix codegen bug and improve type propagation"
Calin Juravle [Mon, 20 Apr 2015 17:30:42 +0000 (18:30 +0100)]
[optimzing] Fix codegen bug and improve type propagation
- don't bound the type if there are no relevant uses
- insert the bound type in the bounded block (this allows for condition
materialization without changing the logic there).
- add more comments
- add tests for BoundType generation
- fix GenerateTestAndBranch
Change-Id: I5c1fdda104da4a46775d207270220d410234a472
Roland Levillain [Tue, 21 Apr 2015 11:33:11 +0000 (11:33 +0000)]
am
c2ea8069: Merge "Opt compiler: Minor object store optimizations for ARM64."
* commit '
c2ea806908e205a808182b2255b6ef5433695375':
Opt compiler: Minor object store optimizations for ARM64.
Roland Levillain [Tue, 21 Apr 2015 11:24:52 +0000 (11:24 +0000)]
Merge "Opt compiler: Minor object store optimizations for ARM64."
Nicolas Geoffray [Tue, 21 Apr 2015 10:26:35 +0000 (10:26 +0000)]
am
769f2d32: Merge "Linear scan: Use FirstUse instead of FirstRegisterUse."
* commit '
769f2d32e4b04758e4dd6ce967f779cbfa74dbcb':
Linear scan: Use FirstUse instead of FirstRegisterUse.
Nicolas Geoffray [Tue, 21 Apr 2015 10:19:21 +0000 (10:19 +0000)]
Merge "Linear scan: Use FirstUse instead of FirstRegisterUse."
Nicolas Geoffray [Tue, 21 Apr 2015 08:12:40 +0000 (09:12 +0100)]
Linear scan: Use FirstUse instead of FirstRegisterUse.
This is in preparation for introducing synthesized used at back edges.
Change-Id: Ie28d6725d2dde982cf2137f2110daabcbab9f789
Nicolas Geoffray [Tue, 21 Apr 2015 09:33:01 +0000 (09:33 +0000)]
am
3d052ba4: Merge "Fix another mistyped location."
* commit '
3d052ba48f84901e89b5ea94c133093dc80bad06':
Fix another mistyped location.
Nicolas Geoffray [Tue, 21 Apr 2015 09:12:44 +0000 (09:12 +0000)]
Merge "Fix another mistyped location."
Nicolas Geoffray [Tue, 21 Apr 2015 09:02:22 +0000 (10:02 +0100)]
Fix another mistyped location.
Change-Id: I52d5a8d34ddc882595da2b53bca0f7eb78d4b3a1
Andreas Gampe [Tue, 21 Apr 2015 04:07:58 +0000 (04:07 +0000)]
am
2fb1639a: Merge "ART: Change image_classes and compiled_classes to unordered set"
* commit '
2fb1639a4bd836f6426cc0d4b8d21c59d2648527':
ART: Change image_classes and compiled_classes to unordered set
Andreas Gampe [Tue, 21 Apr 2015 03:59:32 +0000 (03:59 +0000)]
Merge "ART: Change image_classes and compiled_classes to unordered set"
Andreas Gampe [Tue, 21 Apr 2015 01:53:51 +0000 (18:53 -0700)]
ART: Change image_classes and compiled_classes to unordered set
These lists can be large, and the soon-to-follow compiled_methods
will be potentially even larger. Use a hash set instead of a tree
set.
Change-Id: I7d25c075540f47771354c6f49928b4fd0c76eb2e
Andreas Gampe [Tue, 21 Apr 2015 00:12:59 +0000 (00:12 +0000)]
am
4474073e: Merge "ART: Fix wrong parameter in JIT"
* commit '
4474073ee836d463af29329c86d49354559a41c5':
ART: Fix wrong parameter in JIT
Andreas Gampe [Tue, 21 Apr 2015 00:06:08 +0000 (00:06 +0000)]
Merge "ART: Fix wrong parameter in JIT"
Andreas Gampe [Mon, 20 Apr 2015 23:53:59 +0000 (16:53 -0700)]
ART: Fix wrong parameter in JIT
Do not use an empty set for compiled-classes.
Change-Id: I5062a7886c1a4f5dc8dc9630ce490c71bc607b72
Mathieu Chartier [Mon, 20 Apr 2015 17:19:24 +0000 (17:19 +0000)]
am
b9791aa6: Merge "Add sanity check for large object allocation"
* commit '
b9791aa606834160b085dec7c5b32ccbeaf9a186':
Add sanity check for large object allocation
David Brazdil [Mon, 20 Apr 2015 17:19:22 +0000 (17:19 +0000)]
am
349eded3: Merge "ART: Simplify more bool operations"
* commit '
349eded3bc542c9e6ffb10b6222c6ce372bda9b7':
ART: Simplify more bool operations
Mingyao Yang [Mon, 20 Apr 2015 17:19:21 +0000 (17:19 +0000)]
am
6149f962: Merge "RecordPcInfo() in GenerateStaticOrDirectCall() is misplaced on x86."
* commit '
6149f962cd0815c61c134a7554036ca88d0abef1':
RecordPcInfo() in GenerateStaticOrDirectCall() is misplaced on x86.
Mathieu Chartier [Mon, 20 Apr 2015 17:16:57 +0000 (17:16 +0000)]
Merge "Add sanity check for large object allocation"
David Brazdil [Mon, 20 Apr 2015 17:12:53 +0000 (17:12 +0000)]
Merge "ART: Simplify more bool operations"
David Brazdil [Fri, 17 Apr 2015 13:52:19 +0000 (14:52 +0100)]
ART: Simplify more bool operations
Now that we have the HBooleanNot instruction, the instruction
simplifier can optimize out more conditions comparing a boolean
against a constant, as well as sequences of Boolean negations.
Change-Id: I7f634f6428a3984dd97b27b3d6362491346f1ff6
Mingyao Yang [Mon, 20 Apr 2015 17:11:32 +0000 (17:11 +0000)]
Merge "RecordPcInfo() in GenerateStaticOrDirectCall() is misplaced on x86."
Nicolas Geoffray [Mon, 20 Apr 2015 17:03:37 +0000 (17:03 +0000)]
am
9fab1eea: Merge "Disable tests for volantis."
* commit '
9fab1eea3b9dc7a284dd74487ac603d9ffbb79fb':
Disable tests for volantis.
Nicolas Geoffray [Mon, 20 Apr 2015 16:54:36 +0000 (16:54 +0000)]
Merge "Disable tests for volantis."
Nicolas Geoffray [Mon, 20 Apr 2015 16:52:58 +0000 (17:52 +0100)]
Disable tests for volantis.
They're triggering a segfault.
Change-Id: If99bd9b2faba5422320764ca52808720d533745a
Alexandre Rames [Thu, 16 Apr 2015 14:07:12 +0000 (15:07 +0100)]
Opt compiler: Minor object store optimizations for ARM64.
This is an adaptation of
af07bc121121d7bd7e8329c55dfe24782207b561 for
ARM64.
Change-Id: I5f4984ac86ede89cdf7c915f4bbf8d091059a0eb
Nicolas Geoffray [Mon, 20 Apr 2015 15:22:41 +0000 (15:22 +0000)]
am
27eac12a: Merge "Opt compiler: Implement parallel move resolver without using swap."
* commit '
27eac12a66a73eb38b5ccb45b62350cf341299d0':
Opt compiler: Implement parallel move resolver without using swap.
Roland Levillain [Mon, 20 Apr 2015 15:22:40 +0000 (15:22 +0000)]
am
e40d82ff: Merge changes Ib9648605,I34a3bd17
* commit '
e40d82ffe388458c2674ec051f1dd897362692eb':
Opt compiler: ARM64: Block VIXLpools when recording the pc.
Opt compiler: ARM64: Follow other archs for a few codegen stubs.
Nicolas Geoffray [Mon, 20 Apr 2015 15:20:15 +0000 (15:20 +0000)]
Merge "Opt compiler: Implement parallel move resolver without using swap."
Roland Levillain [Mon, 20 Apr 2015 15:13:07 +0000 (15:13 +0000)]
Merge changes Ib9648605,I34a3bd17
* changes:
Opt compiler: ARM64: Block VIXLpools when recording the pc.
Opt compiler: ARM64: Follow other archs for a few codegen stubs.
Calin Juravle [Mon, 20 Apr 2015 13:59:23 +0000 (13:59 +0000)]
am
90078eec: Merge "optimizing: fix gtests"
* commit '
90078eec8b676d363a8116f487df3596c9f23ea8':
optimizing: fix gtests
Calin Juravle [Mon, 20 Apr 2015 13:50:50 +0000 (13:50 +0000)]
Merge "optimizing: fix gtests"
Calin Juravle [Mon, 20 Apr 2015 13:49:09 +0000 (14:49 +0100)]
optimizing: fix gtests
by taking into account that the compilation unit is null during tests.
Change-Id: I01a28ce8f03c927ff679b84bcdf2464fa97e0924
Alexandre Rames [Thu, 16 Apr 2015 14:07:16 +0000 (15:07 +0100)]
Opt compiler: ARM64: Block VIXLpools when recording the pc.
VIXL automatically handles and generate literal and veneer pools when
using the MacroAssembler. In general, the pools can be emitted
anywhere. Helpers are provided to forbid VIXL from emitting pools
locally.
So when writing the pseudo-code
__ Fmov(d0, 1.2345);
__ Ldr(dst, MemOperand(src, offset));
FunctionRecordingCurrentPC();
__ Add(x0, x1, x2);
VIXL might generate code looking like
0x00: ldr s0, [pc, 0xc]
0x04: ldr dst, [src, offset]
0x08: b #0x10
0x0c: <literal 1.2345>
0x10: add x0, x1, x2
and the program counter recorded by the helper will point after the
literal pool.
So we explicitly stop VIXL from emitting pools when dealing with code
where we care about the program counter.
Change-Id: Ib964860539bdb10f5704c290bdf74e5db149e462
Alexandre Rames [Wed, 15 Apr 2015 10:47:56 +0000 (11:47 +0100)]
Opt compiler: ARM64: Follow other archs for a few codegen stubs.
Code generation for HInstanceFieldGet, HInstanceFieldSet,
HStaticFieldGet, and HStaticFieldSet are refactored to follow the
structure used for other backends.
Change-Id: I34a3bd17effa042238c6bf199848cbc2ec26ac5d
Calin Juravle [Mon, 20 Apr 2015 13:10:35 +0000 (13:10 +0000)]
am
36aafd94: Merge "[optimizing] Add memory barriers in constructors when needed"
* commit '
36aafd94af64d6f1ba603392f66959998f2a93a2':
[optimizing] Add memory barriers in constructors when needed
David Brazdil [Mon, 20 Apr 2015 13:10:34 +0000 (13:10 +0000)]
am
aff3f0a0: Merge "ART: Extend list of instructions accepted as boolean inputs"
* commit '
aff3f0a0a2a080e313ae80c9b0216aa26a668623':
ART: Extend list of instructions accepted as boolean inputs
Calin Juravle [Mon, 20 Apr 2015 13:03:14 +0000 (13:03 +0000)]
Merge "[optimizing] Add memory barriers in constructors when needed"
Calin Juravle [Fri, 17 Apr 2015 18:12:31 +0000 (19:12 +0100)]
[optimizing] Add memory barriers in constructors when needed
If a class has final fields we must add a memory barrier before
returning from constructor. This makes sure the fields are visible to
other threads.
Bug:
19851497
Change-Id: If8c485092fc512efb9636cd568cb0543fb27688e
David Brazdil [Mon, 20 Apr 2015 12:58:55 +0000 (12:58 +0000)]
Merge "ART: Extend list of instructions accepted as boolean inputs"
David Brazdil [Mon, 20 Apr 2015 09:14:42 +0000 (10:14 +0100)]
ART: Extend list of instructions accepted as boolean inputs
Previous change allowed integer Phis as inputs of instructions
expecting a boolean type. This list, however, was not exhaustive as
binary operations And, Or and Xor are also valid inputs. This patch
extends the list in SSAChecker.
Change-Id: I5b5c9e7a17992cc4987e3a078ee23ea80028ecfc
Nicolas Geoffray [Mon, 20 Apr 2015 11:50:42 +0000 (11:50 +0000)]
am
2e0f89b1: Merge "Fix lint error."
* commit '
2e0f89b1b61685f7c322a4c6ec3e3b4839e76d64':
Fix lint error.
Nicolas Geoffray [Mon, 20 Apr 2015 11:40:30 +0000 (11:40 +0000)]
Merge "Fix lint error."
Nicolas Geoffray [Mon, 20 Apr 2015 11:39:57 +0000 (12:39 +0100)]
Fix lint error.
Change-Id: Id956c0e8c864a14c05d291f6b890df4877652306
Nicolas Geoffray [Mon, 20 Apr 2015 11:29:56 +0000 (11:29 +0000)]
am
ae267a22: Merge "Opt compiler: Correctly require register or FPU register."
* commit '
ae267a22e14f3485ecb2191bd5cf50fcc1e4540d':
Opt compiler: Correctly require register or FPU register.
Nicolas Geoffray [Mon, 20 Apr 2015 11:24:01 +0000 (11:24 +0000)]
Merge "Opt compiler: Correctly require register or FPU register."
Alexandre Rames [Tue, 14 Apr 2015 16:35:39 +0000 (17:35 +0100)]
Opt compiler: Correctly require register or FPU register.
Also add a check that location summary are correctly typed
with the HInstruction.
Change-Id: I699762ff4e8f4e321c7db01ea005236ea1934af9
Nicolas Geoffray [Mon, 20 Apr 2015 09:31:30 +0000 (09:31 +0000)]
am
0ca64e92: Merge "Fix codegen_test for long multiplication."
* commit '
0ca64e926f9e55cd369e1afb520d7e05452a6aa6':
Fix codegen_test for long multiplication.
Nicolas Geoffray [Mon, 20 Apr 2015 09:31:28 +0000 (09:31 +0000)]
am
d7265941: Merge "Run jdwp tests now that localhost issues have been solved."
* commit '
d72659412d309b2a99b8f12713774c36fc90348b':
Run jdwp tests now that localhost issues have been solved.
Nicolas Geoffray [Mon, 20 Apr 2015 09:12:07 +0000 (09:12 +0000)]
Merge "Fix codegen_test for long multiplication."
Nicolas Geoffray [Mon, 20 Apr 2015 08:29:18 +0000 (09:29 +0100)]
Fix codegen_test for long multiplication.
It seems like clang (that we use on the host) was *very* forgiving
with this broken test: the code generated for for MulLong used ebx
but this is a callee-save register in C but not ART. Also, the test
was not properly written for handling longs, so it was taking
unitialized stack entries.
GCC on target is not as forgiving.
Change-Id: I5d7a962f8a72b3ce407dce50ca50b4ffc690c99e
Nicolas Geoffray [Mon, 20 Apr 2015 08:38:05 +0000 (08:38 +0000)]
Merge "Run jdwp tests now that localhost issues have been solved."
Nicolas Geoffray [Mon, 20 Apr 2015 08:29:48 +0000 (09:29 +0100)]
Run jdwp tests now that localhost issues have been solved.
Change-Id: I5ae67c2caf73695316ea9530274e97272114af1b
See: https://android-review.googlesource.com/#/c/147244/.
Mathieu Chartier [Sun, 19 Apr 2015 20:36:11 +0000 (13:36 -0700)]
Add sanity check for large object allocation
If there is a large object which ends up being covered by a space
bitmap, it will not be marked correctly by the GC.
Change-Id: Icdd0aaa207f476dd08effcee6cfbbb5de7ca1d17
Andreas Gampe [Sat, 18 Apr 2015 01:00:43 +0000 (01:00 +0000)]
am
f5091eee: Merge "ART: Re-add dlopen"
* commit '
f5091eee4abe73c64959e53bda684bd689569643':
ART: Re-add dlopen
Andreas Gampe [Sat, 18 Apr 2015 00:52:30 +0000 (00:52 +0000)]
Merge "ART: Re-add dlopen"
Andreas Gampe [Wed, 8 Apr 2015 01:34:42 +0000 (18:34 -0700)]
ART: Re-add dlopen
Re-add an oat-file path that uses dlopen to load oat files. This
code-path will be necessary to support libunwind unwinding through
properly CFI-annotated oat files, as libunwind consults the linker
about loaded ELF files.
We avoid the original dlopen issue, namely that the semantics of
dlopen disallow loading the same soname twice, by using an extension
of bionic that supersedes the specified behavior.
Change-Id: I4a7e3cb00d1ea156dad84f76826def2a5967c9ca
Mingyao Yang [Fri, 17 Apr 2015 23:51:08 +0000 (16:51 -0700)]
RecordPcInfo() in GenerateStaticOrDirectCall() is misplaced on x86.
GenerateStaticOrDirectCall() is invoked in intrinsics_x86.cc and
RecordPcInfo() is already taken care of there. It should be moved
to VisitInvokeStaticOrDirect() as done in other archs.
Change-Id: Id08d84c9046e55dea9d8a8452c979294c4183150
Christopher Ferris [Fri, 17 Apr 2015 22:47:29 +0000 (22:47 +0000)]
am
33259fdf: Merge "Fix access past end of args array."
* commit '
33259fdfcd350793d10f67f2ea7dfc6051a8afa2':
Fix access past end of args array.
Christopher Ferris [Fri, 17 Apr 2015 22:36:50 +0000 (22:36 +0000)]
Merge "Fix access past end of args array."
Christopher Ferris [Fri, 17 Apr 2015 20:26:09 +0000 (13:26 -0700)]
Fix access past end of args array.
Bug:
20340831
Change-Id: Ibc0995e28e74c65d81f001e5b4d1e4780ff19686
Dan Albert [Fri, 17 Apr 2015 17:43:57 +0000 (17:43 +0000)]
am
b73f887f: Merge "Fix undefined behavior in hash calculation."
* commit '
b73f887f7e9a6794159d8ae646e9b1d18797125c':
Fix undefined behavior in hash calculation.
David Brazdil [Fri, 17 Apr 2015 17:32:32 +0000 (17:32 +0000)]
am
adf87b0c: Merge "ART: Fix a failing gtest"
* commit '
adf87b0c8cd68ed365e01aec620d016493357cec':
ART: Fix a failing gtest
Dan Albert [Fri, 17 Apr 2015 17:32:28 +0000 (17:32 +0000)]
Merge "Fix undefined behavior in hash calculation."
Dan Albert [Thu, 16 Apr 2015 18:54:24 +0000 (11:54 -0700)]
Fix undefined behavior in hash calculation.
dex_register might be >= the width of the map hash. Shifting by that
value would be undefined behavior. Constrain the value to within the
valid range.
Change-Id: I9037c5c7ec554850ba3385585aca96fde1d50387
David Brazdil [Fri, 17 Apr 2015 17:23:27 +0000 (17:23 +0000)]
Merge "ART: Fix a failing gtest"
David Brazdil [Fri, 17 Apr 2015 17:19:30 +0000 (18:19 +0100)]
ART: Fix a failing gtest
Stricter assumptions about the state of linear scan caused a reg alloc
gtest to fail.
Change-Id: I0c568bf996ce6adefe4f000524b38acd3967421e
David Brazdil [Fri, 17 Apr 2015 16:34:42 +0000 (16:34 +0000)]
am
41de2239: Merge "ART: Improve range search caching in LiveInterval"
* commit '
41de22394e0108f6216a56193b579a199fc37649':
ART: Improve range search caching in LiveInterval
David Brazdil [Fri, 17 Apr 2015 16:25:16 +0000 (16:25 +0000)]
Merge "ART: Improve range search caching in LiveInterval"
David Brazdil [Thu, 16 Apr 2015 17:31:55 +0000 (18:31 +0100)]
ART: Improve range search caching in LiveInterval
Register allocator spends too long in LiveInterval queries. This patch
builds on previously introduced caching of range search results to
further speed up LiveInterval's Covers and FindIntersectionWith.
Only calls which are guaranteed to query the current->GetStart()
position are cached. Other calls are replaced with CoversSlow which
searches through the entire list of ranges.
Change-Id: I84d92b526e174caa70d6477497a06afd85016c4a
David Brazdil [Fri, 17 Apr 2015 15:13:28 +0000 (15:13 +0000)]
am
81b13f6b: Merge "ART: Fix incorrect last range when adding high interval"
* commit '
81b13f6b5244b664000d4bcad16920aadf3b7e29':
ART: Fix incorrect last range when adding high interval
David Brazdil [Fri, 17 Apr 2015 15:07:25 +0000 (15:07 +0000)]
Merge "ART: Fix incorrect last range when adding high interval"
David Brazdil [Fri, 17 Apr 2015 14:49:51 +0000 (15:49 +0100)]
ART: Fix incorrect last range when adding high interval
Adding a high interval clones live ranges but assigns last_range from
the low interval. This should not cause any problems as last_range
is only used for constant-time GetEnd which will return the same
value for both low/high intervals.
Change-Id: Iaf242183436c8ac2f78c0aeea22cd07cd4beacc0
Zheng Xu [Fri, 17 Apr 2015 10:48:56 +0000 (18:48 +0800)]
Opt compiler: Implement parallel move resolver without using swap.
The algorithm of ParallelMoveResolverNoSwap() is almost the same with
ParallelMoveResolverWithSwap(), except the way we resolve the circular
dependency. NoSwap() uses additional scratch register to resolve the
circular dependency. For example, (0->1) (1->2) (2->0) will be performed
as (2->scratch) (1->2) (0->1) (scratch->0).
On architectures without swap register support, NoSwap() can reduce the
number of moves from 3x(N-1) to (N+1) when there is circular dependency
with N moves.
And also, NoSwap() algorithm does not depend on architecture register
layout information, which means it can support register pairs on arm32
and X/W, D/S registers on arm64 without additional modification.
Change-Id: Idf56bd5469bb78c0e339e43ab16387428a082318
Calin Juravle [Fri, 17 Apr 2015 10:11:21 +0000 (10:11 +0000)]
am
dd2cf0c7: Merge "Cleanup unnecessary test conditions in ssa builder."
* commit '
dd2cf0c7a5dc7f2c89b8ac217f16b7529461e509':
Cleanup unnecessary test conditions in ssa builder.
Calin Juravle [Fri, 17 Apr 2015 10:03:22 +0000 (10:03 +0000)]
Merge "Cleanup unnecessary test conditions in ssa builder."
Calin Juravle [Fri, 17 Apr 2015 09:36:57 +0000 (10:36 +0100)]
Cleanup unnecessary test conditions in ssa builder.
Change-Id: Ic36e535aec3f977ebe36bfe20bc54a1033de62c6
Dan Albert [Thu, 16 Apr 2015 23:35:02 +0000 (23:35 +0000)]
am
f8bdd9f3: Merge "Fix value used for shift in quick_cfi_test."
* commit '
f8bdd9f3a002970e4b8fdcf6fe6730116f1626c3':
Fix value used for shift in quick_cfi_test.
Dan Albert [Thu, 16 Apr 2015 23:24:24 +0000 (23:24 +0000)]
Merge "Fix value used for shift in quick_cfi_test."
Mathieu Chartier [Thu, 16 Apr 2015 21:45:54 +0000 (21:45 +0000)]
Mathieu Chartier [Thu, 16 Apr 2015 21:39:11 +0000 (21:39 +0000)]
Merge "Fix build"
Mathieu Chartier [Thu, 16 Apr 2015 21:34:45 +0000 (14:34 -0700)]
Fix build
art/runtime/mirror/art_method-inl.h:142: error: undefined
reference to 'art::ClassLinker::ResolveType(unsigned short,
art::mirror::ArtMethod*)'
Change-Id: I3c5d26eed13e3f8d0a4d96756c09364707b6358e
Dan Albert [Thu, 16 Apr 2015 18:52:45 +0000 (11:52 -0700)]
Fix value used for shift in quick_cfi_test.
The spill mask bit should be shifted by the register number, not the
whole register mask.
Previously this test was shifting by values well over the width of the
type, which is undefined behavior.
Change-Id: Idf750be6d95b4487f8f4570b8c7ff9dba38be9f2
Yabin Cui [Thu, 16 Apr 2015 18:44:43 +0000 (18:44 +0000)]
am
e50dffa2: Merge "Remove transitive dependency on <cutils/atomic.h>."
* commit '
e50dffa29fb6c67eba44e267aa890d35712de9dd':
Remove transitive dependency on <cutils/atomic.h>.
Yabin Cui [Thu, 16 Apr 2015 18:35:13 +0000 (18:35 +0000)]
Merge "Remove transitive dependency on <cutils/atomic.h>."
Yabin Cui [Wed, 15 Apr 2015 22:40:18 +0000 (15:40 -0700)]
Remove transitive dependency on <cutils/atomic.h>.
Bug:
20262261
Change-Id: Ic6c2ed76e692fc09100b917e00ee9b73621ec8f0
Mathieu Chartier [Thu, 16 Apr 2015 17:30:39 +0000 (17:30 +0000)]
am
73a3fb3d: Merge "Disable parallel GC by default"
* commit '
73a3fb3d884f14e5de488bc679da4ce5ac7700be':
Disable parallel GC by default
David Brazdil [Thu, 16 Apr 2015 17:30:37 +0000 (17:30 +0000)]
am
50a4d671: Merge "ART: Replace expensive calls to Covers in reg alloc"
* commit '
50a4d671268cff5041fb09dcb9f64515dd809e4a':
ART: Replace expensive calls to Covers in reg alloc
Mathieu Chartier [Thu, 16 Apr 2015 17:23:31 +0000 (17:23 +0000)]
Merge "Disable parallel GC by default"
David Brazdil [Thu, 16 Apr 2015 17:22:19 +0000 (17:22 +0000)]
Merge "ART: Replace expensive calls to Covers in reg alloc"
David Brazdil [Thu, 16 Apr 2015 16:59:03 +0000 (17:59 +0100)]
ART: Replace expensive calls to Covers in reg alloc
LiveInterval::Covers is implemented as a linear-time search over
liveness ranges and can therefore be rather expensive and should be
avoided unless necessary. This patch replaces calls to Covers when
searching for a sibling with the cheaper IsDefinedAt call.
Change-Id: I93fc73529c15a518335f4cbdc3a0def52d9501e5
Mathieu Chartier [Thu, 16 Apr 2015 17:02:43 +0000 (17:02 +0000)]
am
f458ba7d: Merge "Don\'t call ComputeEagerResolvedStrings"
* commit '
f458ba7d9c04bc8d499532b5470af28db18e4149':
Don't call ComputeEagerResolvedStrings
Mathieu Chartier [Thu, 16 Apr 2015 16:52:33 +0000 (16:52 +0000)]
Merge "Don't call ComputeEagerResolvedStrings"
Mathieu Chartier [Thu, 16 Apr 2015 03:03:16 +0000 (20:03 -0700)]
Don't call ComputeEagerResolvedStrings
Doesn't add any strings to the dex caches, takes 50ms on nexus 5
during image writing.
Change-Id: Ib38d456b765a90efc0008955f974446fbe285bff
Calin Juravle [Thu, 16 Apr 2015 16:01:34 +0000 (16:01 +0000)]
am
e7bee3b7: Merge "Remove duplicates phis created during SSA transformation"
* commit '
e7bee3b7d307508243f4a00b5cf8a8867fcaaff5':
Remove duplicates phis created during SSA transformation
Calin Juravle [Thu, 16 Apr 2015 15:53:22 +0000 (15:53 +0000)]
Merge "Remove duplicates phis created during SSA transformation"
David Brazdil [Thu, 16 Apr 2015 15:51:07 +0000 (15:51 +0000)]
am
59bb4767: Merge "ART: Fix whitespace in test"
* commit '
59bb47675b1f1bafbcababadb4a6ba1c345fec1a':
ART: Fix whitespace in test
Calin Juravle [Thu, 16 Apr 2015 15:51:05 +0000 (15:51 +0000)]
am
8aec061f: Merge "Fallback to quick in case of soft verification errors"
* commit '
8aec061f5e58876bcc892d8c0309bc13b5349f5c':
Fallback to quick in case of soft verification errors