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Bob Wilson [Thu, 4 Jan 2018 02:58:15 +0000 (02:58 +0000)]
support phi ranges for machine-level IR
Add iterator ranges for machine instruction phis, similar to the IR-level
phi ranges added in r303964. I updated a few places to use this. Besides
general code simplification, this change will allow removing a non-upstream
change from Swift's copy of LLVM (in a better way than my previous attempt
in http://reviews.llvm.org/D19080).
https://reviews.llvm.org/D41672
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321783
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Michael Trent [Wed, 3 Jan 2018 23:28:32 +0000 (23:28 +0000)]
Do not look up symbol names when n_strx == 0
Summary:
Historical tools for working with mach-o binaries verify the nlist field
n_strx has a non-zero value before using that value to retrieve symbol names.
Under some cirumstances, llvm-nm will attempt to display the symbol name at
position 0, even though symbol names at that position are not well defined.
This change addresses this problem by returning an empty string when n_strx
is zero.
rdar://problem/
35750548
Reviewers: enderby, davide
Reviewed By: enderby, davide
Subscribers: davide, llvm-commits, JDevlieghere
Differential Revision: https://reviews.llvm.org/D41657
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321773
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Simon Pilgrim [Wed, 3 Jan 2018 22:42:33 +0000 (22:42 +0000)]
[DAGCombine] Handle out of range EXTRACT_VECTOR_ELT indices
Handle this in DAGCombiner::visitEXTRACT_VECTOR_ELT the same as we already do in SelectionDAG::getNode and use APInt instead of getZExtValue.
This should also fix oss-fuzz #4910
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321767
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Philip Reames [Wed, 3 Jan 2018 22:28:26 +0000 (22:28 +0000)]
[PRE] Add a bunch of test cases for LICM-like PRE patterns
These were inspired by a very old review I'm about to abandon (https://reviews.llvm.org/D7061). Several of the test cases from that worked without modification and expanding test coverage of such cases is always worthwhile.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321764
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Francis Visoiu Mistrih [Wed, 3 Jan 2018 20:56:29 +0000 (20:56 +0000)]
[CodeGen][NFC] Remove unused function declaration
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321758
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Sanjay Patel [Wed, 3 Jan 2018 20:02:39 +0000 (20:02 +0000)]
[ExpandMemcmp] rename variables and add hook to override pref for number of loads per block; NFC
The preference only applies to 'memcmp() == 0' expansion, so try to make that clearer.
x86 will likely benefit by increasing the default value from '1' to '2' as seen in PR33325:
https://bugs.llvm.org/show_bug.cgi?id=33325
...so that is the planned follow-up to this clean-up step.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321756
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Craig Topper [Wed, 3 Jan 2018 19:15:43 +0000 (19:15 +0000)]
[X86] Remove 'else' after 'return' I forgot to cleanup before committing D41691.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321755
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Matt Arsenault [Wed, 3 Jan 2018 18:51:22 +0000 (18:51 +0000)]
Fix missing release metabug in merge-request.sh
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321753
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Matt Arsenault [Wed, 3 Jan 2018 18:45:42 +0000 (18:45 +0000)]
AMDGPU: Remove dead file
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321752
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Matt Arsenault [Wed, 3 Jan 2018 18:45:37 +0000 (18:45 +0000)]
StructurizeCFG: Fix broken backedge detection
The work order was changed in r228186 from SCC order
to RPO with an arbitrary sorting function. The sorting
function attempted to move inner loop nodes earlier. This
was was apparently relying on an assumption that every block
in a given loop / the same loop depth would be seen before
visiting another loop. In the broken testcase, a block
outside of the loop was encountered before moving onto
another block in the same loop. The testcase would then
structurize such that one blocks unconditional successor
could never be reached.
Revert to plain RPO for the analysis phase. This fixes
detecting edges as backedges that aren't really.
The processing phase does use another visited set, and
I'm unclear on whether the order there is as important.
An arbitrary order doesn't work, and triggers some infinite
loops. The reversed RPO list seems to work and is closer
to the order that was used before, minus the arbitary
custom sorting.
A few of the changed tests now produce smaller code,
and a few are slightly worse looking.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321751
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Simon Pilgrim [Wed, 3 Jan 2018 18:28:20 +0000 (18:28 +0000)]
[InstCombine] Check for out of range shift values using APInt before calling getZExtValue
Reduced from oss-fuzz #4871 test case
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321748
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Craig Topper [Wed, 3 Jan 2018 18:20:36 +0000 (18:20 +0000)]
[X86] Remove useless custom inserter for 64-bit TAILJMP and TCRETURN opcodes
This custom inserter was added in r124272 at which time it added about bunch of Defs for Win64. In r150708, those defs were removed leaving only the "return BB". So I think this means the custom inserter is a NOP these days.
This patch removes the remaining code and stops tagging the instructions for custom insertion
Differential Revision: https://reviews.llvm.org/D41671
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321747
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Craig Topper [Wed, 3 Jan 2018 18:11:01 +0000 (18:11 +0000)]
[X86] Use ANY_EXTEND instead of SIGN_EXTEND in lowerMasksToReg
Currently we use SIGN_EXTEND in lowerMasksToReg as part of calling convention setup, but we don't require a specific value for the upper bits.
This patch changes it to ANY_EXTEND which will be lowered as SIGN_EXTEND if it ends up sticking around.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321746
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Tom Stellard [Wed, 3 Jan 2018 16:35:51 +0000 (16:35 +0000)]
[lit] Bump version number
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321735
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Hans Wennborg [Wed, 3 Jan 2018 15:45:32 +0000 (15:45 +0000)]
Clear release notes for 7.0.0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321727
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Hans Wennborg [Wed, 3 Jan 2018 14:52:54 +0000 (14:52 +0000)]
The trunk version is now 7.0.0svn
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321712
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Hans Wennborg [Wed, 3 Jan 2018 14:48:19 +0000 (14:48 +0000)]
Remove left-over debug printout from r321692
Besides the unsightly print-out, it was causing some buildbots to fail,
e.g. http://lab.llvm.org:8011/builders/clang-x86-windows-msvc2015/builds/9311
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321711
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Dmitry Venikov [Wed, 3 Jan 2018 14:37:42 +0000 (14:37 +0000)]
[InstSimplify] Missed optimization in math expression: squashing exp(log), log(exp)
Summary: This patch enables folding following expressions under -ffast-math flag: exp(log(x)) -> x, exp2(log2(x)) -> x, log(exp(x)) -> x, log2(exp2(x)) -> x
Reviewers: spatel, hfinkel, davide
Reviewed By: spatel, hfinkel, davide
Subscribers: scanon, llvm-commits
Differential Revision: https://reviews.llvm.org/D41381
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321710
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Alex Bradbury [Wed, 3 Jan 2018 13:46:21 +0000 (13:46 +0000)]
[ARM][NFC] Avoid recreating MCSubtargetInfo in ARMAsmBackend
After D41349, we can now directly access MCSubtargetInfo from
createARM*AsmBackend. This patch makes use of this, avoiding the need to
create a fresh MCSubtargetInfo (which was previously always done with a blank
CPU and feature string). Given the total size of the change remains pretty
tiny and we're removing the old explicit destructor, I changed the STI field
to a reference rather than a pointer.
Differential Revision: https://reviews.llvm.org/D41693
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321707
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Florian Hahn [Wed, 3 Jan 2018 13:35:43 +0000 (13:35 +0000)]
[InstCombine] Add test to remove VarArg casts (NFC)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321706
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Hal Finkel [Wed, 3 Jan 2018 11:35:09 +0000 (11:35 +0000)]
[TableGen] Add support of Intrinsics with multiple returns
This change deals with intrinsics with multiple outputs, for example load
instrinsic with address updated.
DAG selection for Instrinsics could be done either through source code or
tablegen. Handling all intrinsics in source code would introduce a huge chunk
of repetitive code if we have a large number of intrinsic that return multiple
values (see NVPTX as an example). While intrinsic class in tablegen supports
multiple outputs, tablegen only supports Intrinsics with zero or one output on
TreePattern. This appears to be a simple bug in tablegen that is fixed by this
change.
For Intrinsics defined as:
def int_xxx_load_addr_updated: Intrinsic<[llvm_i32_ty, llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty], []>;
Instruction will be defined as:
def L32_X: Inst<(outs reg:$d1, reg:$d2), (ins reg:$s1, reg:$s2), "ld32_x $d1, $d2, $s2", [(set i32:$d1, i32:$d2, (int_xxx_load_addr_updated i32:$s1, i32:$s2))]>;
Patch by Wenbo Sun, thanks!
Differential Revision: https://reviews.llvm.org/D32888
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321704
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Sander de Smalen [Wed, 3 Jan 2018 10:15:46 +0000 (10:15 +0000)]
[AArch64][SVE] Asm: Add restricted register classes for SVE predicate vectors.
Summary:
Add a register class for SVE predicate operands that can only be p0-p7 (as opposed to p0-p15)
Patch [1/3] in a series to add predicated ADD/SUB instructions for SVE.
Reviewers: rengolin, mcrosier, evandro, fhahn, echristo, olista01, SjoerdMeijer, javed.absar
Reviewed By: fhahn
Subscribers: aemerson, javed.absar, tschuett, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D41441
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321699
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Alex Bradbury [Wed, 3 Jan 2018 09:30:39 +0000 (09:30 +0000)]
Fix build of WebAssembly and AVR backends after r321692
As experimental backends, I didn't have them configured to build in my local
build config.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321696
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Alex Bradbury [Wed, 3 Jan 2018 09:14:02 +0000 (09:14 +0000)]
Fix incorrect documentation comment left after r321692
TargetRegistryInfo::createMCAsmBackend no longer takes a TheTriple parameter.
The majory of the TargetRegistryInfo::create* functions have no or very
limitied per-parameter doc comments, and adding a comment for the
MCSubtargetInfo, MCRegisterInfo and MCTargetOptions parameters seems like it
would add no real value beyond reading the function signature. As such, I've
just deleted the doc comment for TheTriple.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321694
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Alex Bradbury [Wed, 3 Jan 2018 08:53:05 +0000 (08:53 +0000)]
Thread MCSubtargetInfo through Target::createMCAsmBackend
Currently it's not possible to access MCSubtargetInfo from a TgtMCAsmBackend.
D20830 threaded an MCSubtargetInfo reference through
MCAsmBackend::relaxInstruction, but this isn't the only function that would
benefit from access. This patch removes the Triple and CPUString arguments
from createMCAsmBackend and replaces them with MCSubtargetInfo.
This patch just changes the interface without making any intentional
functional changes. Once in, several cleanups are possible:
* Get rid of the awkward MCSubtargetInfo handling in ARMAsmBackend
* Support 16-bit instructions when valid in MipsAsmBackend::writeNopData
* Get rid of the CPU string parsing in X86AsmBackend and just use a SubtargetFeature for HasNopl
* Emit 16-bit nops in RISCVAsmBackend::writeNopData if the compressed instruction set extension is enabled (see D41221)
This change initially exposed PR35686, which has since been resolved in r321026.
Differential Revision: https://reviews.llvm.org/D41349
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321692
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Amara Emerson [Wed, 3 Jan 2018 04:56:56 +0000 (04:56 +0000)]
[GlobalISel][Legalizer] Fix legalization of llvm.smul.with.overflow
Previously the code for handling G_SMULO didn't properly check for the signed
multiply overflow, instead treating it the same as the unsigned G_UMULO.
Fixes PR35800.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321690
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Jake Ehrlich [Tue, 2 Jan 2018 23:01:24 +0000 (23:01 +0000)]
[llvm-objcopy] Add support for visibility
I have no clue how this was missed when symbol table support was added. This
change ensures that the visibility of symbols is preserved by default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321681
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Andrew Kaylor [Tue, 2 Jan 2018 21:04:38 +0000 (21:04 +0000)]
Handle the case of live 16-bit subregisters in X86FixupBWInsts
Differential Revision: https://reviews.llvm.org/D40524
Change-Id: Ie3a405b28503ceae999f5f3ba07a68fa733a2400
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321674
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Sanjay Patel [Tue, 2 Jan 2018 21:04:08 +0000 (21:04 +0000)]
[AArch64] fix typos in comments; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321673
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Sanjay Patel [Tue, 2 Jan 2018 20:56:45 +0000 (20:56 +0000)]
[ValueTracking] recognize min/max of min/max patterns
This is part of solving PR35717:
https://bugs.llvm.org/show_bug.cgi?id=35717
The larger IR optimization is proposed in D41603, but we can show
the improvement in ValueTracking using codegen tests because
SelectionDAG creates min/max nodes based on ValueTracking.
Any target with min/max ops should show wins here. I chose AArch64
vector ops because they're clean and uniform.
Some Alive proofs for the tests (can't put more than 2 tests in 1
page currently because the web app says it's too long):
https://rise4fun.com/Alive/WRN
https://rise4fun.com/Alive/iPm
https://rise4fun.com/Alive/HmY
https://rise4fun.com/Alive/CNm
https://rise4fun.com/Alive/LYf
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321672
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Sanjay Patel [Tue, 2 Jan 2018 20:16:45 +0000 (20:16 +0000)]
[AArch64] add tests for min/max of min/max (PR35717); NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321668
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Amara Emerson [Tue, 2 Jan 2018 18:56:39 +0000 (18:56 +0000)]
[AArch64][GlobalISel] Fix assert fail with unknown intrinsic.
A call may have an intrinsic name but not have a valid intrinsic ID,
for example with llvm.invariant.group.barrier. If so, treat it as a
normal call like FastISel does.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321662
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Jonas Hahnfeld [Tue, 2 Jan 2018 17:53:08 +0000 (17:53 +0000)]
[opt-viewer] Check for pygments.lexer.c_cpp
Some systems still don't have this module which was introduced in
version 2.0 (CentOS 7, sigh).
Differential Revision: https://reviews.llvm.org/D41611
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321659
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Sanjay Patel [Tue, 2 Jan 2018 16:38:29 +0000 (16:38 +0000)]
[x86] allow pairs of PCMPEQ for vector-sized integer equality comparisons (PR33325)
This is an extension of D31156 with the goal that we'll allow memcmp() == 0 expansion
for x86 to use 2 pairs of loads per block.
The memcmp expansion pass (formerly part of CGP) will generate this kind of pattern
with oversized integer compares, so we want to transform these into x86-specific vector
nodes before legalization splits things into scalar chunks.
See PR33325 for more details:
https://bugs.llvm.org/show_bug.cgi?id=33325
Differential Revision: https://reviews.llvm.org/D41618
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321656
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Amara Emerson [Tue, 2 Jan 2018 16:30:47 +0000 (16:30 +0000)]
[AArch64][GlobalISel] Enable GlobalISel at -O0 by default
Tests updated to explicitly use fast-isel at -O0 instead of implicitly.
This change also allows an explicit -fast-isel option to override an
implicitly enabled global-isel. Otherwise -fast-isel would have no effect at -O0.
Differential Revision: https://reviews.llvm.org/D41362
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321655
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Anna Thomas [Tue, 2 Jan 2018 16:25:50 +0000 (16:25 +0000)]
[BasicBlockUtils] Check for unreachable preds before updating LI in UpdateAnalysisInformation
Summary:
We are incorrectly updating the LI when loop-simplify generates
dedicated exit blocks for a loop. The issue is that there's an implicit
assumption that the Preds passed into UpdateAnalysisInformation are
reachable. However, this is not true and breaks LI by incorrectly
updating the header of a loop.
One such case is when we generate dedicated exits when the exit block is
a landing pad (through SplitLandingPadPredecessors). There maybe other
cases as well, since we do not guarantee that Preds passed in are
reachable basic blocks.
The added test case shows how loop-simplify breaks LI for the outer loop (and DT in turn)
after we try to generate the LoopSimplifyForm.
Reviewers: davide, chandlerc, sanjoy
Reviewed By: davide
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D41519
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321653
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Krzysztof Parzyszek [Tue, 2 Jan 2018 15:28:49 +0000 (15:28 +0000)]
[Hexagon] Fix generation of vector sign extensions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321650
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Daniel Jasper [Tue, 2 Jan 2018 14:38:52 +0000 (14:38 +0000)]
Revert r321089: "[DAG] Elide overlapping store" (and subsequent fix in r321204)
Our internal testing has revealed has discovered bugs in PPC builds.
I have forward reproduction instructions to the original author (Nirav).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321649
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Dmitry Venikov [Tue, 2 Jan 2018 14:13:16 +0000 (14:13 +0000)]
NFC. Add description comments to Function header
Reviewers: ruiu, davidxl, silvas, brzycki
Reviewed By: brzycki
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D41609
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321648
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Sander de Smalen [Tue, 2 Jan 2018 13:39:44 +0000 (13:39 +0000)]
[AArch64][AsmParser] Add isScalarReg() and repurpose isReg()
Summary:
isReg() in AArch64AsmParser.cpp is a bit of a misnomer, and would be better named 'isScalarReg()' instead.
Patch [1/3] in a series to add operand constraint checks for SVE's predicated ADD/SUB.
Reviewers: rengolin, mcrosier, evandro, fhahn, echristo
Reviewed By: fhahn
Subscribers: aemerson, javed.absar, llvm-commits, kristof.beyls
Differential Revision: https://reviews.llvm.org/D41445
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321646
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Simon Pilgrim [Tue, 2 Jan 2018 12:41:29 +0000 (12:41 +0000)]
Strip trailing whitespace. NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321644
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Alex Bradbury [Tue, 2 Jan 2018 12:09:29 +0000 (12:09 +0000)]
[RISCV] Add Defs Uses information for c.jal and c.addi4spn
Differential Revision: https://reviews.llvm.org/D41339
Patch by Shiva Chen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321643
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Alex Bradbury [Tue, 2 Jan 2018 11:54:59 +0000 (11:54 +0000)]
[RISCV][NFC] Resolve unused variable warning in RISCVISelLowering
XLenVT in LowerFormalArguments is used only in an assert.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321642
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Sam Parker [Tue, 2 Jan 2018 10:19:01 +0000 (10:19 +0000)]
[DAGCombine] Fix for PR35765
Remove the acceptance of ANY_EXTEND nodes while trying to move and
nodes back to loads.
Bugzilla: https://bugs.llvm.org/show_bug.cgi?id=35765
Differential Revision: https://reviews.llvm.org/D41625
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321641
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Sam Parker [Tue, 2 Jan 2018 10:14:00 +0000 (10:14 +0000)]
[X86] Codegen test for pr35765
Committing reproducer test for pr35765, fix to follow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321640
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Craig Topper [Tue, 2 Jan 2018 07:30:53 +0000 (07:30 +0000)]
[SelectionDAG] Teach WidenVecOp_Convert to widen the operation if a widened result type would still be legal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321638
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Dmitry Venikov [Tue, 2 Jan 2018 05:58:11 +0000 (05:58 +0000)]
[InstCombine] Missed optimization in math expression: squashing sqrt functions
Summary: This patch enables folding under -ffast-math flag sqrt(a) * sqrt(b) -> sqrt(a*b)
Reviewers: hfinkel, spatel, davide
Reviewed By: spatel, davide
Subscribers: davide, llvm-commits
Differential Revision: https://reviews.llvm.org/D41322
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321637
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Dmitry Venikov [Tue, 2 Jan 2018 05:47:42 +0000 (05:47 +0000)]
Test commit
Reviewers: Quolyk
Reviewed By: Quolyk
Differential Revision: https://reviews.llvm.org/D41561
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321636
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Craig Topper [Tue, 2 Jan 2018 01:55:07 +0000 (01:55 +0000)]
[SelectionDAG] Remove ifs on getTypeAction being TypeWidenVector from some of the WideVecOp handlers.
We should only be in the handler if the tyep action is TypeWidenVector. There's no reason to try to do anything else.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321635
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Simon Pilgrim [Mon, 1 Jan 2018 22:44:59 +0000 (22:44 +0000)]
[ValueTracking] Don't assume shift values are in range
Reduced (as best I could...) from oss-fuzz #4857 test case
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321634
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Simon Pilgrim [Mon, 1 Jan 2018 22:27:49 +0000 (22:27 +0000)]
[InstCombine] Regenerate udiv tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321633
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Craig Topper [Mon, 1 Jan 2018 21:12:18 +0000 (21:12 +0000)]
[X86] Promote vXi1 fp_to_uint/fp_to_sint to vXi32 to avoid scalarization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321632
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Craig Topper [Mon, 1 Jan 2018 21:12:10 +0000 (21:12 +0000)]
[X86] Add test cases for vXi1 fptosi/fptoui.
Currently we do a lot of scalarization in these test cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321631
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Craig Topper [Mon, 1 Jan 2018 20:08:43 +0000 (20:08 +0000)]
[X86] Replace custom lowering of vXi1 SINT_TO_FP/UINT_TO_FP with promotion.
The custom lowering was just doing the same thing promotion would do.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321630
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Craig Topper [Mon, 1 Jan 2018 19:21:35 +0000 (19:21 +0000)]
[SelectionDAG][X86][AArch64] Require targets to specify the promotion type when using setOperationAction Promote for INT_TO_FP and FP_TO_INT
Currently the promotion for these ignores the normal getTypeToPromoteTo and instead just tries to double the element width. This is because the default behavior of getTypeToPromote to just adds 1 to the SimpleVT, which has the affect of increasing the element count while keeping the scalar size the same.
If multiple steps are required to get to a legal operation type, int_to_fp will be promoted multiple times. And fp_to_int will keep trying wider types in a loop until it finds one that works.
getTypeToPromoteTo does have the ability to query a promotion map to get the type and not do the increasing behavior. It seems better to just let the target specify the promotion type in the map explicitly instead of letting the legalizer iterate via widening.
FWIW, it's worth I think for any other vector operations that need to be promoted, we have to specify the type explicitly because the default behavior of getTypeToPromote isn't useful for vectors. The other types of promotion already require either the element count is constant or the total vector width is constant, but neither happens by incrementing the SimpleVT enum.
Differential Revision: https://reviews.llvm.org/D40664
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321629
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Sanjay Patel [Mon, 1 Jan 2018 16:36:47 +0000 (16:36 +0000)]
[x86] add runs for more vector variants; NFC
Preliminary step to see what the effects of D41618 look like.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321624
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Simon Pilgrim [Mon, 1 Jan 2018 13:04:04 +0000 (13:04 +0000)]
[X86][SSE] Add test case from PR32160
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321620
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Uriel Korach [Mon, 1 Jan 2018 09:00:13 +0000 (09:00 +0000)]
[X86] Regenerate test checks in sse-intrinsics-x86-upgrade with update-llc
Removing outdated checks.
NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321619
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Uriel Korach [Mon, 1 Jan 2018 08:47:50 +0000 (08:47 +0000)]
[X86] Regenerate test checks in sse2-intrinsics-x86-upgrade with update-llc
Removing outdated checks.
NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321618
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Craig Topper [Mon, 1 Jan 2018 04:52:58 +0000 (04:52 +0000)]
[X86] In LowerTruncateVecI1, don't add SHL if the input is known to be all sign bits.
If the input is all sign bits then the LSB through MSB are all the same so we don't need to be move the LSB to the MSB.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321617
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Craig Topper [Mon, 1 Jan 2018 01:11:32 +0000 (01:11 +0000)]
[X86] Add missing NoVLX predicate around some patterns that use zmm registers to implement 128/256-bit operations without VLX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321613
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Craig Topper [Mon, 1 Jan 2018 01:11:29 +0000 (01:11 +0000)]
[X86] Add patterns for using zmm registers for v8i32/v8f32 vselect with the false input being zero.
We can use zmm move with zero masking for this. We already had patterns for using a masked move, but we didn't check for the zero masking case separately.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321612
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Craig Topper [Sun, 31 Dec 2017 19:17:52 +0000 (19:17 +0000)]
[X86] Use CONCAT_VECTORS instead of INSERT_SUBVECTOR for padding v4i1/v2i1 vector to v8i1 pre-legalize.
The CONCAT_VECTORS will be lowered to INSERT_SUBVECTOR later. In the modified cases this seems to be enough to trick a later DAG combine into running in a different order than allows the ANDs to be removed.
I'll admit this is a bit of a hack that happens to work, but using CONCAT_VECTORS is more consistent with other legalization code anyway.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321611
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Simon Pilgrim [Sun, 31 Dec 2017 18:59:30 +0000 (18:59 +0000)]
[X86][AVX2] Combine extract(broadcast(scalar_value)) --> scalar_value
As it has a scalar source we don't treat it as a target shuffle so needs special handling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321610
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Simon Pilgrim [Sun, 31 Dec 2017 17:16:48 +0000 (17:16 +0000)]
[X86][AVX] Add test case from PR33740
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321608
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Simon Pilgrim [Sun, 31 Dec 2017 17:07:47 +0000 (17:07 +0000)]
[X86][SSE] Don't vectorize splat buildvector of binops (PR30780)
Don't combine buildvector(binop(),binop(),binop(),binop()) -> binop(buildvector(), buildvector()) if its a splat - keep the binop scalar and just splat the result to avoid large vector constants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321607
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Davide Italiano [Sun, 31 Dec 2017 16:54:03 +0000 (16:54 +0000)]
[SimplifyCFG] Return to the pass manager the correct value.
I wanted to commit this with r321603, but I failed to squash
the two commits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321606
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Davide Italiano [Sun, 31 Dec 2017 16:51:50 +0000 (16:51 +0000)]
[Utils/Local] Use `auto` when the type is obvious. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321605
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Davide Italiano [Sun, 31 Dec 2017 16:48:44 +0000 (16:48 +0000)]
[Utils] Remove commented debug message. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321604
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Davide Italiano [Sun, 31 Dec 2017 16:47:16 +0000 (16:47 +0000)]
[SimplifyCFG] Stop hoisting musttail calls incorrectly.
PR35774.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321603
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Craig Topper [Sun, 31 Dec 2017 09:50:38 +0000 (09:50 +0000)]
[X86] Add a DAG combine to widen (i4 (bitcast (v4i1))) before type legalization sees the i4 and changes to load/store.
Same for v2i1 and i2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321602
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Craig Topper [Sun, 31 Dec 2017 08:25:50 +0000 (08:25 +0000)]
[X86] Add a DAG combine to fix (v4i1 (bitcast (i4))) before type legalization sees the i4 and changes to load/store.
Same for i2 and v2i1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321601
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George Rimar [Sun, 31 Dec 2017 07:41:02 +0000 (07:41 +0000)]
[MC] - Stop ignoring invalid meta data symbols.
Previously llvm-mc would silently accept code from testcase,
that contains invalid metadata symbol in section declaration.
Patch fixes the issue.
Differential revision: https://reviews.llvm.org/D41641
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321599
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Craig Topper [Sun, 31 Dec 2017 07:38:41 +0000 (07:38 +0000)]
[X86] Prevent combining (v8i1 (bitconvert (i8 load)))->(v8i1 load) if we don't have DQI.
We end up using an i8 load via an isel pattern from v8i1 anyway. This just makes it more explicit. This seems to improve codgen in some cases and I'd like to kill off some of the load patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321598
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Craig Topper [Sun, 31 Dec 2017 07:38:36 +0000 (07:38 +0000)]
[X86] Remove patterns for load/store of vXi with bitcasts to/from integer.
This is better handled by a DAG combine if its not already being done. No lit tests fail from the removal of these patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321597
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Craig Topper [Sun, 31 Dec 2017 07:38:33 +0000 (07:38 +0000)]
[X86] Remove AND32ri8 from pattern for v1i1 load.
I don't think anything would actually expect the other bits to be zero.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321596
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Craig Topper [Sun, 31 Dec 2017 07:38:30 +0000 (07:38 +0000)]
[X86] Fix a crash when returning a <1 x i1> value>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321595
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Craig Topper [Sun, 31 Dec 2017 07:38:26 +0000 (07:38 +0000)]
[X86] Cleanup store splitting in LowerTruncatingStore
Use getMemBasePlusOffset and calculate proper pointer info and alignment for the second store.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321594
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Philip Reames [Sun, 31 Dec 2017 03:34:36 +0000 (03:34 +0000)]
2nd attempt at "fixing" amdgpu tests after r321575
The test needs to be changed; it was exercising UB and that likely wasn't the intent of the test author. I simply removed the checks because I have absolutely no idea what this test was trying to accomplish. With multiple check patterns, no explanation, and no familiarity on my part with the ISA a true fix is going to have to come from someone familiar with the target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321591
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Philip Reames [Sat, 30 Dec 2017 18:42:37 +0000 (18:42 +0000)]
Test fix after r321575
The test in question was checking for a particular intepretation of undefined behavior. Relax the test to check that we simply don't crash.
Sorry for the breakage, I don't generally build AMDGPU locally and just saw the failure this morning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321589
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Serge Pavlov [Sat, 30 Dec 2017 15:37:46 +0000 (15:37 +0000)]
Added support for reading configuration files
Configuration file is read as a response file in which file names in
the nested constructs `@file` are resolved relative to the directory
where the including file resides. Lines in which the first non-whitespace
character is '#' are considered as comments and are skipped. Trailing
backslashes are used to concatenate lines in the same way as they
are used in shell scripts.
Differential Revision: https://reviews.llvm.org/D24926
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321586
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Benjamin Kramer [Sat, 30 Dec 2017 15:27:33 +0000 (15:27 +0000)]
Use phi ranges to simplify code. No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321585
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Simon Pilgrim [Sat, 30 Dec 2017 11:51:45 +0000 (11:51 +0000)]
[X86][SSE] Add PR30780 test cases
Broadcast of sign/zero extended scalars resulting in unnecessary vector constants
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321584
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Simon Pilgrim [Sat, 30 Dec 2017 11:20:56 +0000 (11:20 +0000)]
[X86][SSE] Add test for (v2f32 uitofp(build_vector(i32, i32))) (PR35732)
To compare against (v2f32 build_vector(f32 uitofp(i32), f32 uitofp(i32)))
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321583
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Serge Pavlov [Sat, 30 Dec 2017 09:15:59 +0000 (09:15 +0000)]
Reverted 321580: Added support for reading configuration files
It caused buildbot fails.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321582
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Serge Pavlov [Sat, 30 Dec 2017 08:15:15 +0000 (08:15 +0000)]
Added support for reading configuration files
Configuration file is read as a response file in which file names in
the nested constructs `@file` are resolved relative to the directory
where the including file resides. Lines in which the first non-whitespace
character is '#' are considered as comments and are skipped. Trailing
backslashes are used to concatenate lines in the same way as they
are used in shell scripts.
Differential Revision: https://reviews.llvm.org/D24926
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321580
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Hiroshi Inoue [Sat, 30 Dec 2017 08:09:04 +0000 (08:09 +0000)]
[PowerPC] fix a bug in TCO eligibility check
If the callee and caller use different calling convensions, we cannot apply TCO if the callee requires arguments on stack; e.g. C calling convention and Fast CC use the same registers for parameter passing, but the stack offset is not necessarily same.
This patch also recommit r319218 "[PowerPC] Allow tail calls of fastcc functions from C CallingConv functions." by @sfertile since the problem reported in r320106 should be fixed.
Differential Revision: https://reviews.llvm.org/D40893
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321579
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Craig Topper [Sat, 30 Dec 2017 06:45:46 +0000 (06:45 +0000)]
[X86] Remove isel patterns for kshifts with types that don't support kshift natively.
We should only be creating natively supported kshifts now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321577
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Craig Topper [Sat, 30 Dec 2017 06:45:43 +0000 (06:45 +0000)]
[X86] Custom legalize vXi1 extract_subvector with KSHIFTR.
This allows us to remove some isel patterns.
This is mostly NFC, but we now use KSHIFTB instead of KSHIFTW with DQI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321576
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Philip Reames [Sat, 30 Dec 2017 05:54:22 +0000 (05:54 +0000)]
[instsimplify] consistently handle undef and out of bound indices for insertelement and extractelement
In one case, we were handling out of bounds, but not undef indices. In the other, we were handling undef (with the comment making the analogy to out of bounds), but not out of bounds. Be consistent and treat both undef and constant out of bounds indices as producing undefined results.
As a side effect, this also protects instcombine from having to handle large constant indices as we always simplify first.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321575
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Philip Reames [Sat, 30 Dec 2017 04:10:48 +0000 (04:10 +0000)]
Add another test case for r321489
Went to reduce another fuzzer failure to find it's already been fixed, but the test case is slightly different so it's worth adding anyways.
Reduced from oss-fuzz #4768 test case
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321573
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Philip Reames [Sat, 30 Dec 2017 03:13:00 +0000 (03:13 +0000)]
Move tests associated with transforms moved in r321467
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321572
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Geoff Berry [Fri, 29 Dec 2017 21:01:09 +0000 (21:01 +0000)]
[MachineOperand] Fix LiveDebugVariables code after isRenamable change.
Fix code in LiveDebugVariables that was changing def MachineOperands to
uses, which will hit an assert for dead operands after the change to add
the renamable bit to MachineOperands. Avoid the assert by clearing the
dead bit before changing the operand to a use.
Fixes issue reported in out of tree target by Jesper Antonsson at Ericsson.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321571
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Matt Arsenault [Fri, 29 Dec 2017 19:25:57 +0000 (19:25 +0000)]
StructurizeCFG: Use phi iterator range
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321568
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Matt Arsenault [Fri, 29 Dec 2017 19:25:53 +0000 (19:25 +0000)]
IR: Fix BasicBlock::phis for empty blocks
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321567
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Simon Atanasyan [Fri, 29 Dec 2017 19:18:30 +0000 (19:18 +0000)]
[mips] Provide correct descriptions of asm constraints in the comments. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321566
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Simon Atanasyan [Fri, 29 Dec 2017 19:18:24 +0000 (19:18 +0000)]
[mips] Replace assert by an error message
Initially, if the `c` constraint applied to the wrong data type that
causes LLVM to assert. This commit replaces the assert by an error
message.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321565
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Matt Arsenault [Fri, 29 Dec 2017 17:18:21 +0000 (17:18 +0000)]
AMDGPU: Use unique PSVs for buffer resources
Also fixes using the wrong memory type for some
intrinsics when custom lowering them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321557
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Matt Arsenault [Fri, 29 Dec 2017 17:18:18 +0000 (17:18 +0000)]
AMDGPU: Remove mayLoad/hasSideEffects from MIMG stores
Atomics still have hasSideEffects set on them because
of the mess that is the memory properties.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321556
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Matt Arsenault [Fri, 29 Dec 2017 17:18:14 +0000 (17:18 +0000)]
AMDGPU: Implement getTgtMemIntrinsic for images
Currently all images are lowered to have a single
image PseudoSourceValue. Image stores happen to have
overly strict mayLoad/mayStore/hasSideEffects flags
set on them, so this happens to work. When these
are fixed to be correct, the scheduler breaks
this because the identical PSVs are assumed to
be the same address. These need to be unique
to the image resource value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321555
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