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Topi Pohjolainen [Tue, 10 Dec 2013 14:36:31 +0000 (16:36 +0200)]
i965: rename tex_ms to tex_cms
Prepares for the introduction of non-compressed multi-sampled
lookup used in the blorp programs.
v2: now also taking into account gen8
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Topi Pohjolainen [Mon, 2 Dec 2013 09:09:19 +0000 (11:09 +0200)]
i965/blorp: move emission of pixel kill into eu-emitter
The combination of four separate comparison operations and
and the masked "and" require special treatment when moving
to FS LIR.
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Topi Pohjolainen [Fri, 29 Nov 2013 09:57:15 +0000 (11:57 +0200)]
i965/blorp: introduce separate eu-emitter for blit compiler
Prepares for presenting blorp blit programs using FS IR that
allows EU-assembly generation using i965 glsl-compiler
backend (fs_generator).
v2: rebased on top of endif-jump counter fix (moving the
added brw_set_uip_jip() into the emitter)
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Kenneth Graunke [Wed, 15 Jan 2014 18:08:38 +0000 (10:08 -0800)]
i965: Support 32 texture image units on Haswell+.
The Intel closed source OpenGL driver recently began supporting 32
texture image units on Haswell. This makes the open source driver
support 32 as well.
Earlier generations don't have the message header field required to
support more than 16 sampler states, so we continue to advertise 16
there.
On Haswell, this causes us to advertise:
- GL_MAX_TEXTURE_IMAGE_UNITS = 32
- GL_MAX_VERTEX_TEXTURE_IMAGE_UNITS = 32
- GL_MAX_COMBINED_TEXTURE_IMAGE_UNITS = 96
instead of the old values of 16, 16, and 48.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Kenneth Graunke [Sat, 18 Jan 2014 22:48:11 +0000 (14:48 -0800)]
i965/fs: Switch from BRW_MAX_TEX_UNIT to the actual limit.
BRW_MAX_TEX_UNIT is about to grow, but only Gen7+ will be able to
support the new larger value. On older platforms, we don't want to
allocate the extra space - it would just be a waste.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Kenneth Graunke [Wed, 15 Jan 2014 18:08:06 +0000 (10:08 -0800)]
mesa: Bump MAX_TEXTURE_IMAGE_UNITS to 32.
This allows drivers to optionally support more than 16 texture units.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Kenneth Graunke [Sat, 18 Jan 2014 22:32:49 +0000 (14:32 -0800)]
i965/vec4: Support arbitrarily large sampler state indices on Haswell+.
Like the scalar backend, we add an offset to the "Sampler State Pointer"
field to select a group of 16 samplers, then use the "Sampler Index"
field to select within that group.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Kenneth Graunke [Sat, 18 Jan 2014 22:29:19 +0000 (14:29 -0800)]
i965/vec4: Refactor sampler message setup.
The next patch adds an additional case where the message header is
necessary. So we want to do the g0 copy if inst->header_present is set,
rather than inst->texture_offset.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Kenneth Graunke [Sat, 18 Jan 2014 22:34:07 +0000 (14:34 -0800)]
i965/vec4: Don't set header_present if texel offsets are all 0.
In theory, a shader might use textureOffset() but set all the texel
offsets to zero. In that case, we don't actually need to set up the
message header - zero is the implicit default.
By moving the texture_offset setup before the header_present setup, we
can easily only set header_present when there are non-zero texel offset
values.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Kenneth Graunke [Sat, 18 Jan 2014 21:29:39 +0000 (13:29 -0800)]
i965/fs: Support arbitrarily large sampler state indices on Haswell+.
The message descriptor's "Sampler Index" field is only 4 bits (on all
generations of hardware), so it can only represent indices 0 through 15.
Haswell introduced a new field in the message header - "Sampler State
Pointer". Normally, this is copied straight from g0, but we can also
add a byte offset (as long as it's a multiple of 32).
This patch uses a "Sampler State Pointer" offset to select a group of
16 sampler states, and then uses the "Sampler Index" field to select
the state within that group.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Kenneth Graunke [Sat, 18 Jan 2014 21:28:40 +0000 (13:28 -0800)]
i965/fs: Plumb sampler index into emit_texture_gen7.
We'll need this in the next patch.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Kenneth Graunke [Sat, 18 Jan 2014 20:48:18 +0000 (12:48 -0800)]
i965/fs: Refactor sampler message header to duplicate less code.
Previously, the code to copy g0 to the message header existed in two
places - one for the texture offset case, and one for any other case.
By treating texture_offset as a special case of header_present, we can
remove this duplication and shorten the code. Future patches which add
new header fields also won't have to add additional duplication.
This also clarifies a confusing construct. The old code contained:
} else if (inst->header_present) {
if (brw->gen >= 7) {
...explicit copy from g0 to the message header...
} else {
/* Set up an implied move from g0 to the MRF. */
}
}
This looks like it might set up an implied move on Sandybridge, which
doesn't support those. However, Sandybridge only uses a message header
for texture offsets, so it would never hit this code path. The new code
avoids this implicit knowledge by only setting up an implied move on
Gen4-5.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Kenneth Graunke [Sat, 18 Jan 2014 20:49:58 +0000 (12:49 -0800)]
i965: Use get_element_ud to shorten texture header access.
This is shorter, easier to read, and further from the 80 column limit.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Marek Olšák [Tue, 21 Jan 2014 18:53:45 +0000 (19:53 +0100)]
gallium/util: util_format_srgb should not return FORMAT_NONE for sRGB formats
This fixes a serious regression introduced
in
4e549ddb500cf677b6fa16d9ebdfa67cc23da097.
Cc: 9.2 10.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Brian Paul <brianp@vmware.com>
Marek Olšák [Fri, 17 Jan 2014 21:57:39 +0000 (22:57 +0100)]
gallium: remove PIPE_CAP_SCALED_RESOLVE
If any driver doesn't support this, it can use a blit after resolving
the samples.
Reviewed-by: Brian Paul <brianp@vmware.com>
Marek Olšák [Mon, 13 Jan 2014 22:42:18 +0000 (23:42 +0100)]
radeonsi: use hardware scissors correctly
Use the WINDOW and VPORT scissors for the framebuffer and scissor test,
respectively. The other two scissors are disabled (they cover the max fb size).
We actually have 16 VPORT scissors, which will map well to ARB_viewport_array.
Also, we don't need to write SC_WINDOW_OFFSET with this commit, because it's
disabled everywhere.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Marek Olšák [Mon, 13 Jan 2014 12:15:19 +0000 (13:15 +0100)]
radeonsi: handle R600_CONTEXT_PS_PARTIAL_FLUSH in si_emit_cache_flush
For consistency only, This is unused by radeonsi currently.
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Marek Olšák [Mon, 13 Jan 2014 12:10:06 +0000 (13:10 +0100)]
r600g,radeonsi: if discarding whole buffer range, discard whole resource instead
Also set the unsynchronized flag if the whole resource was discarded
to avoid doing buffer-busy checks again.
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Marek Olšák [Mon, 13 Jan 2014 12:03:25 +0000 (13:03 +0100)]
gallium/u_upload_mgr: don't expose u_upload_flush
It's unused and shouldn't be used at all in my opinion.
If some driver doesn't support the unsynchronized flag, u_upload_mgr should
avoid the synchronization by other means, e.g. by using the DONTBLOCK flag.
Marek Olšák [Mon, 13 Jan 2014 11:59:14 +0000 (12:59 +0100)]
gallium/hud: just unmap the upload vertex buffer instead of recreating it
Marek Olšák [Mon, 13 Jan 2014 12:51:21 +0000 (13:51 +0100)]
gallium/vl: use u_upload_mgr to upload vertices for vl_compositor
This is the recommended way for streaming vertices. Always use this if you
need to upload vertices every frame.
Reviewed-by: Christian König <christian.koenig@amd.com>
Kristian Høgsberg [Tue, 21 Jan 2014 20:17:03 +0000 (12:17 -0800)]
intel: Fix initial MakeCurrent for single-buffer drawables
Commit
05da4a7a5e7d5bd988cb31f94ed8e1f053d9ee39 attempts to eliminate the
call to intel_update_renderbuffer() in the case where we already have a
drawbuffer for the drawable. Unfortunately this only checks the
back left renderbuffer, which breaks in case of single buffer drawables.
This means that the initial viewport will not be set in that case. Instead,
we now check whether the initial viewport has not been set, in which case
we call out to intel_update_renderbuffer().
https://bugs.freedesktop.org/show_bug.cgi?id=73862
Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
Paul Berry [Tue, 21 Jan 2014 23:41:26 +0000 (15:41 -0800)]
glsl: Simplify aggregate type inference to prepare for ARB_arrays_of_arrays.
Most of the time it is not necessary to perform type inference to
compile GLSL; the type of every expression can be inferred from the
contents of the expression itself (and previous type declarations).
The exception is aggregate initializers: their type is determined by
the LHS of the variable being assigned to. For example, in the
statement:
mat2 foo = { { 1, 2 }, { 3, 4 } };
the type of { 1, 2 } is only known to be vec2 (as opposed to, say,
ivec2, uvec2, int[2], or a struct) because of the fact that the result
is being assigned to a mat2.
Previous to this patch, we handled this situation by doing some type
inference during parsing: when parsing a declaration like the one
above, we would call _mesa_set_aggregate_type(), which would infer the
type of each aggregate initializer and store it in the corresponding
ast_aggregate_initializer::constructor_type field. Since this
happened at parse time, we couldn't do the type inference using
glsl_type objects; we had to use ast_type_specifiers, which are much
more awkward to work with. Things are about to get more complicated
when we add support for ARB_arrays_of_arrays.
This patch simplifies things by postponing the call to
_mesa_set_aggregate_type() until ast-to-hir time, when we have access
to glsl_type objects. As a side benefit, we only need to have one
call to _mesa_set_aggregate_type() now, instead of six.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Jan Vesely [Fri, 17 Jan 2014 01:22:14 +0000 (20:22 -0500)]
clover: Don't crash on NULL global buffer objects.
Specs say "If the argument is a buffer object, the arg_value
pointer can be NULL or point to a NULL value in which case a NULL
value will be used as the value for the argument declared as a
pointer to __global or __constant memory in the kernel."
So don't crash when somebody does that.
v2: Insert NULL into input buffer instead of buffer handle pair
Fix constant_argument too
Drop r600 driver changes
v3: Fix inserting NULL pointer
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Vinson Lee [Wed, 22 Jan 2014 06:46:39 +0000 (22:46 -0800)]
meta: Move loop variable declaration outside loop.
Fixes MSVC build error introduced with commit
69b258cb4636315b4c1aaaceeedd1eed8af98ba8.
meta.c(618) : error C2143: syntax error : missing ';' before 'type'
meta.c(618) : error C2143: syntax error : missing ')' before 'type'
meta.c(618) : error C2065: 'i' : undeclared identifier
meta.c(618) : warning C4552: '<' : operator has no effect; expected operator with side-effect
meta.c(618) : error C2059: syntax error : ')'
meta.c(618) : error C2143: syntax error : missing ';' before '{'
meta.c(619) : error C2065: 'i' : undeclared identifier
meta.c(620) : error C2065: 'i' : undeclared identifier
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Topi Pohjolainen [Tue, 21 Jan 2014 09:33:58 +0000 (11:33 +0200)]
i965/blorp: use BRW_COMPRESSION_2NDHALF for second half LPR
No known bugs fixed but this is now in line with fs-generator.
No regresssions on IVB.
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Topi Pohjolainen [Tue, 21 Jan 2014 08:31:10 +0000 (10:31 +0200)]
i965/blorp: patch jump counters also for endif
No known bugs fixed but this is now in line with fs-generator.
No regresssions on IVB.
Eric further explained that:
"The endif jump, since it's forward, is just an optimization to
have set right -- otherwise, the GPU will just step forward
instruction by instruction until it hits something else that
updates the per-channel PC."
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Paul Berry [Thu, 9 Jan 2014 19:34:33 +0000 (11:34 -0800)]
mesa: Change redundant code into loops in texstate.c.
This is possible now that ctx->Shader.CurrentProgram is an array.
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Brian Paul <brianp@vmware.com>
Paul Berry [Thu, 9 Jan 2014 19:33:15 +0000 (11:33 -0800)]
mesa: Change redundant code into loops in shaderapi.c.
This is possible now that ctx->Shader.CurrentProgram is an array.
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Brian Paul <brianp@vmware.com>
Paul Berry [Thu, 9 Jan 2014 19:32:00 +0000 (11:32 -0800)]
mesa: Remove ad-hoc arrays of gl_shader_program.
Now that we have a ctx->Shader.CurrentProgram array, we can just use
it directly.
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Brian Paul <brianp@vmware.com>
Paul Berry [Thu, 9 Jan 2014 19:29:17 +0000 (11:29 -0800)]
meta: Replace save_state::{Vertex,Geometry,Fragment}Shader with an array.
Since ctx->Shader.Current{Vertex,Geometry,Fragment}Program is an
array, this allows some meta code to be rolled up into loops.
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Brian Paul <brianp@vmware.com>
Paul Berry [Thu, 9 Jan 2014 19:28:20 +0000 (11:28 -0800)]
i965: Fix comments to refer to the new ctx->Shader.CurrentProgram array.
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Brian Paul <brianp@vmware.com>
Paul Berry [Thu, 9 Jan 2014 19:27:38 +0000 (11:27 -0800)]
mesa: Fold long lines introduced by the previous patch.
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Brian Paul <brianp@vmware.com>
Paul Berry [Thu, 9 Jan 2014 19:16:27 +0000 (11:16 -0800)]
mesa: Replace ctx->Shader.Current{Vertex,Fragment,Geometry}Program with an array.
These are replaced with
ctx->Shader.CurrentProgram[MESA_SHADER_{VERTEX,FRAGMENT,GEOMETRY}].
In patches to follow, this will allow us to replace a lot of ad-hoc
logic with a variable index into the array.
With the exception of the changes to mtypes.h, this patch was
generated entirely by the command:
find src -type f '(' -iname '*.c' -o -iname '*.cpp' ')' \
-print0 | xargs -0 sed -i \
-e 's/\.CurrentVertexProgram/.CurrentProgram[MESA_SHADER_VERTEX]/g' \
-e 's/\.CurrentGeometryProgram/.CurrentProgram[MESA_SHADER_GEOMETRY]/g' \
-e 's/\.CurrentFragmentProgram/.CurrentProgram[MESA_SHADER_FRAGMENT]/g'
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Brian Paul <brianp@vmware.com>
Paul Berry [Tue, 7 Jan 2014 16:56:57 +0000 (08:56 -0800)]
glsl/linker: Refactor in preparation for adding more shader stages.
Rather than maintain separately named arrays and counts for vertex,
geometry, and fragment shaders, just maintain these as arrays indexed
by the gl_shader_type enum.
v2: When there is neither a vertex nor a geometry shader, set
prog->LastClipDistanceArraySize = 0, and clarify that the values is
not used.
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Brian Paul <brianp@vmware.com>
Paul Berry [Tue, 7 Jan 2014 23:19:07 +0000 (15:19 -0800)]
mesa: use _mesa_validate_shader_target() more frequently.
This patch replaces code in _mesa_new_shader() and delete_shader_cb()
that checks the type of a shader with calls to
_mesa_validate_shader_target(). This has two advantages: it allows
for a more thorough check (since _mesa_validate_shader_target()
doesn't permit shader targets that aren't supported by the back-end),
and it reduces the amount of code that will need to be modified when
adding new shader stages.
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Brian Paul <brianp@vmware.com>
Paul Berry [Thu, 9 Jan 2014 23:30:10 +0000 (15:30 -0800)]
main: Allow ctx == NULL in _mesa_validate_shader_target().
This will allow this function to be used in circumstances where there
is no context available, such as when building built-in GLSL
functions.
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Brian Paul <brianp@vmware.com>
Paul Berry [Tue, 7 Jan 2014 23:13:52 +0000 (15:13 -0800)]
mesa: Make validate_shader_target() non-static.
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Brian Paul <brianp@vmware.com>
Paul Berry [Thu, 9 Jan 2014 21:42:05 +0000 (13:42 -0800)]
mesa: Replace _mesa_program_index_to_target with _mesa_shader_stage_to_program.
In my recent zeal to refactor Mesa's handling of the gl_shader_stage
enum, I accidentally wound up with two functions that do the same
thing: _mesa_program_index_to_target(), and
_mesa_shader_stage_to_program().
This patch keeps _mesa_shader_stage_to_program(), since its name is
more consistent with other related functions. However, it changes the
signature so that it accepts an unsigned integer instead of a
gl_shader_stage--this avoids awkward casts when the function is called
from C++ code.
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Brian Paul <brianp@vmware.com>
Dave Airlie [Tue, 21 Jan 2014 04:54:05 +0000 (14:54 +1000)]
llvmpipe: dump geometry shaders when using LP_DEBUG=tgsi
for consistency with vs and fs dumpers.
Reviewed-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Ian Romanick [Wed, 18 Dec 2013 22:43:19 +0000 (14:43 -0800)]
mesa: Generate GL_INVALID_OPERATION for unsupported DSA TexStorage functions
We have to make the functions available to work around a GLEW bug (see
comments already in the code), but if an application calls one of these
functions we should still generate GL_INVALID_OPERATION.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Ian Romanick [Wed, 18 Dec 2013 22:39:26 +0000 (14:39 -0800)]
mesa: Silence many unused parameter warnings
main/texstorage.c: In function '_mesa_alloc_texture_storage':
main/texstorage.c:240:53: warning: unused parameter 'width' [-Wunused-parameter]
main/texstorage.c:241:37: warning: unused parameter 'height' [-Wunused-parameter]
main/texstorage.c:241:53: warning: unused parameter 'depth' [-Wunused-parameter]
main/texstorage.c: In function '_mesa_TextureStorage1DEXT':
main/texstorage.c:464:34: warning: unused parameter 'texture' [-Wunused-parameter]
main/texstorage.c:464:50: warning: unused parameter 'target' [-Wunused-parameter]
main/texstorage.c:464:66: warning: unused parameter 'levels' [-Wunused-parameter]
main/texstorage.c:465:34: warning: unused parameter 'internalformat' [-Wunused-parameter]
main/texstorage.c:466:35: warning: unused parameter 'width' [-Wunused-parameter]
main/texstorage.c: In function '_mesa_TextureStorage2DEXT':
main/texstorage.c:473:34: warning: unused parameter 'texture' [-Wunused-parameter]
main/texstorage.c:473:50: warning: unused parameter 'target' [-Wunused-parameter]
main/texstorage.c:473:66: warning: unused parameter 'levels' [-Wunused-parameter]
main/texstorage.c:474:34: warning: unused parameter 'internalformat' [-Wunused-parameter]
main/texstorage.c:475:35: warning: unused parameter 'width' [-Wunused-parameter]
main/texstorage.c:475:50: warning: unused parameter 'height' [-Wunused-parameter]
main/texstorage.c: In function '_mesa_TextureStorage3DEXT':
main/texstorage.c:483:34: warning: unused parameter 'texture' [-Wunused-parameter]
main/texstorage.c:483:50: warning: unused parameter 'target' [-Wunused-parameter]
main/texstorage.c:483:66: warning: unused parameter 'levels' [-Wunused-parameter]
main/texstorage.c:484:34: warning: unused parameter 'internalformat' [-Wunused-parameter]
main/texstorage.c:485:35: warning: unused parameter 'width' [-Wunused-parameter]
main/texstorage.c:485:50: warning: unused parameter 'height' [-Wunused-parameter]
main/texstorage.c:485:66: warning: unused parameter 'depth' [-Wunused-parameter]
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Anuj Phogat [Wed, 15 Jan 2014 18:23:02 +0000 (10:23 -0800)]
i965: Ignore 'centroid' interpolation qualifier in case of persample shading
This patch handles the use of 'centroid' qualifier with 'in' variables
in a fragment shader when persample shading is enabled. Per sample
shading for the whole fragment shader can be enabled by:
glEnable(GL_SAMPLE_SHADING) or using {gl_SamplePosition, gl_SampleID}
builtin variables in fragment shader. Explaining it below in more
detail.
/* Enable sample shading using OpenGL API */
glEnable(GL_SAMPLE_SHADING);
glMinSampleShading(1.0);
Example fragment shader:
in vec4 a;
centroid in vec4 b;
main()
{
...
}
Variable 'a' will be interpolated at sample location. But, what
interpolation should we use for variable 'b' ?
ARB_sample_shading recommends interpolation at sample position for
all the variables. GLSL 400 (and earlier) spec says that:
"When an interpolation qualifier is used, it overrides settings
established through the OpenGL API."
But, this text got deleted in later versions of GLSL.
NVIDIA's and AMD's proprietary linux drivers (at OpenGL 4.3)
interpolates at sample position. This convinces me to use
the similar approach on intel hardware.
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Anuj Phogat [Mon, 6 Jan 2014 21:59:18 +0000 (13:59 -0800)]
i965: Use sample barycentric coordinates with per sample shading
Current implementation of arb_sample_shading doesn't set 'Barycentric
Interpolation Mode' correctly. We use pixel barycentric coordinates
for per sample shading. Instead we should select perspective sample
or non-perspective sample barycentric coordinates.
It also enables using sample barycentric coordinates in case of a
fragment shader variable declared with 'sample' qualifier.
e.g. sample in vec4 pos;
A piglit test to verify the implementation has been posted on piglit
mailing list for review.
V2: Do not interpolate all the 'in' variables at sample position
if fragment shader uses 'sample' qualifier with one of them.
For example we have a fragment shader:
#version 330
#extension ARB_gpu_shader5: require
sample in vec4 a;
in vec4 b;
main()
{
...
}
Only 'a' should be sampled at sample location, not 'b'.
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Anuj Phogat [Mon, 13 Jan 2014 20:26:55 +0000 (12:26 -0800)]
i965: Add an option to ignore sample qualifier
This will be useful in my next patch which depends on a functionality
of _mesa_get_min_invocations_per_fragment() to ignore the sample
qualifier (prog->IsSample) based on a flag passed to it.
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Matt Turner [Sun, 12 Jan 2014 04:37:51 +0000 (20:37 -0800)]
mesa/x86: Remove dead read_rgba_span_x86.h.
Dead since
304f7a13.
Matt Turner [Fri, 10 Jan 2014 04:57:36 +0000 (20:57 -0800)]
i965/fs: Optimize LRP with x == y into a MOV.
total instructions in shared programs:
1487331 ->
1485988 (-0.09%)
instructions in affected programs: 45638 -> 44295 (-2.94%)
GAINED: 7
LOST: 0
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Jordan Justen [Mon, 4 Nov 2013 18:23:24 +0000 (10:23 -0800)]
glsl: Optimize open-coded lrp into lrp.
total instructions in shared programs:
1498191 ->
1487051 (-0.74%)
instructions in affected programs: 669388 -> 658248 (-1.66%)
GAINED: 1
LOST: 0
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Matt Turner [Fri, 3 Jan 2014 22:52:55 +0000 (14:52 -0800)]
i965: Enable AOS optimizations for the geometry shader.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Matt Turner [Sat, 21 Dec 2013 19:28:05 +0000 (11:28 -0800)]
glsl: Vectorize multiple scalar assignments
Reduces vertex shader instruction counts in DOTA2 by 6.42%, L4D2 by
4.61%, and CS:GO by 5.71%.
total instructions in shared programs:
1500153 ->
1498191 (-0.13%)
instructions in affected programs: 59919 -> 57957 (-3.27%)
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Matt Turner [Thu, 2 Jan 2014 00:52:32 +0000 (16:52 -0800)]
glsl: Add parameter to .equals() to ignore an IR type.
Only implemented for ir_swizzles currently, but perhaps will be useful
for other IR types in the future.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Matt Turner [Fri, 3 Jan 2014 22:48:53 +0000 (14:48 -0800)]
mesa: rename PreferDP4 to OptimizeForAOS.
This flag was really just a proxy for determining whether the backend
was vector (AOS) or scalar (SOA). It will be used to apply a future
optimization only for vector backends.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Matt Turner [Sun, 15 Dec 2013 02:37:16 +0000 (18:37 -0800)]
i965/fs: Print the maximum register pressure.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Kenneth Graunke [Mon, 5 Aug 2013 06:34:01 +0000 (23:34 -0700)]
i965/fs: Show register pressure in dump_instructions() output.
Dumping the number of live registers at each IP allows us to see
register pressure and identify any local maxima. This should
aid in debugging passes designed to reduce register pressure, as
well as optimizations that suddenly trigger spilling.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Kenneth Graunke [Mon, 5 Aug 2013 06:27:14 +0000 (23:27 -0700)]
i965: Compute the number of live registers at each IP.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Matt Turner [Mon, 16 Dec 2013 04:07:05 +0000 (20:07 -0800)]
i965/fs: Call opt_peephole_sel later in the optimization loop.
Calling it after value numbering (added in the next commit) prevents
some instruction count regressions.
total instructions in shared programs:
1524387 ->
1523905 (-0.03%)
instructions in affected programs: 13112 -> 12630 (-3.68%)
GAINED: 0
LOST: 3
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Matt Turner [Sun, 15 Dec 2013 23:39:29 +0000 (15:39 -0800)]
i965/fs: Calculate interference better in register_coalesce.
Previously we simply considered two registers whose live ranges
overlapped to interfere. Cases such as
set A ------
... |
mov B, A -- |
... | B | A
use B -- |
... |
use A ------
would be considered to interfere, even though B is an unmodified copy of
A whose live range fit wholly inside that of A.
If no writes to A or B occur between the mov B, A and the use of B then
we can safely coalesce them.
Instead of removing MOV instructions, we make them NOPs and remove them
at once after the main pass is finished in order to avoid recomputing
live intervals (which are needed to perform the previous step).
total instructions in shared programs:
1543768 ->
1513077 (-1.99%)
instructions in affected programs: 951563 -> 920872 (-3.23%)
GAINED: 46
LOST: 22
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Matt Turner [Wed, 11 Dec 2013 00:04:27 +0000 (16:04 -0800)]
i965/fs: Support coalescing registers of size > 1.
total instructions in shared programs:
1550048 ->
1549880 (-0.01%)
instructions in affected programs: 1896 -> 1728 (-8.86%)
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Matt Turner [Sun, 8 Dec 2013 00:22:08 +0000 (16:22 -0800)]
i965/fs: Assert that var < num_vars.
Helped to track down a problem in a version of the next commit.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Matt Turner [Wed, 11 Dec 2013 00:05:19 +0000 (16:05 -0800)]
i965/fs: Add a comment explaining how register coalescing works.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Matt Turner [Wed, 11 Dec 2013 00:22:56 +0000 (16:22 -0800)]
i965/fs: Add and use MAX_SAMPLER_MESSAGE_SIZE definition.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Matt Turner [Wed, 11 Dec 2013 00:21:16 +0000 (16:21 -0800)]
mesa: Add STRINGIFY macro.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Matt Turner [Sat, 7 Dec 2013 20:59:59 +0000 (12:59 -0800)]
i965/fs: Fix the example about overwriting uniforms in SIMD16.
mov takes only a single source argument. Example instruction
inexplicably changed from add to mov in commit
f10f5e49.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Matt Turner [Wed, 4 Dec 2013 23:01:16 +0000 (15:01 -0800)]
i965: Print reg_offset for vgrf of size > 1 in dump_instruction().
Previously we wouldn't print the +0 for the first part of a VGRF of size
greater than 1.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Grigori Goronzy [Tue, 26 Nov 2013 23:15:06 +0000 (00:15 +0100)]
glsl: Match unnamed record types across stages.
Unnamed record types are assigned to separate types per stage, e.g. if
uniform struct { ... } a;
is defined in both vertex and fragment shader, two separate types will
result with different names. When linking the shader, this results in a
type conflict. However, there is no reason why this should not be
allowed according to GLSL specifications. Compare and match record types
when linking shader stages to avoid this conflict.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Grigori Goronzy [Tue, 26 Nov 2013 23:15:05 +0000 (00:15 +0100)]
glsl: Extract function for record comparisons.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Brian Paul [Fri, 17 Jan 2014 16:18:32 +0000 (08:18 -0800)]
docs: remove some ancient README.* files
None of this info is relevant anymore.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Brian Paul [Fri, 17 Jan 2014 02:32:47 +0000 (18:32 -0800)]
svga: implement TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS
Fixes several colorbuffer tests, including piglit "fbo-drawbuffers-none"
for "gl_FragColor" and "glDrawPixels" cases.
v2: rework patch to only avoid creating extra shader variants when
TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS is not specified. Per Jose.
Use a write_color0_to_n_cbufs key field to replicate color0 to N
color buffers only when N > 0 and WRITES_ALL_CBUFS is set.
Reviewed-by: José Fonseca <jfonseca@vmware.com>
Brian Paul [Fri, 17 Jan 2014 02:05:00 +0000 (18:05 -0800)]
svga: rename color output variables
Just to be bit more readable.
Reviewed-by: José Fonseca <jfonseca@vmware.com>
Brian Paul [Fri, 17 Jan 2014 02:01:57 +0000 (18:01 -0800)]
svga: fix clearing for null color buffers
Fixes piglit "fbo-drawbuffers-none glClear" test.
Reviewed-by: José Fonseca <jfonseca@vmware.com>
Brian Paul [Tue, 21 Jan 2014 16:18:13 +0000 (08:18 -0800)]
mesa: add missing TYPE_DOUBLEN_2 cases in get.c
The new TYPE_DOUBLEN_2 type was added in
0e60d850 but the code to
return values of that type wasn't completed.
Fixes conform's default state test. glGetFloatv(GL_DEPTH_RANGE)
wasn't returning anything.
v2: remove stray 'break' statements.
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Paul Berry [Sat, 23 Mar 2013 14:22:08 +0000 (07:22 -0700)]
i965: Modify some error messages to refer to "vec4" instead of "vs".
These messages are in code that is shared between the VS and GS
back-ends, so use the terminology "vec4" to avoid confusion.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Paul Berry [Fri, 17 Jan 2014 22:42:48 +0000 (14:42 -0800)]
i965: Add GS support to INTEL_DEBUG=shader_time.
Previously, time spent in geometry shaders would be counted as part of
the vertex shader time.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Roland Scheidegger [Tue, 21 Jan 2014 16:47:08 +0000 (17:47 +0100)]
draw: fix points with negative w coords for d3d style point clipping
Even with depth clipping disabled, vertices which have negative w coords
must be discarded. And since we don't have a proper guardband implementation
yet (relying on driver to handle all values except infs/nans in rasterization
for such points) we need to kill them off manually (as they can end up with
coordinates inside viewport otherwise).
v2: use 0.0f instead of 0 (spotted by Brian).
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Kenneth Graunke [Wed, 6 Nov 2013 00:55:06 +0000 (16:55 -0800)]
i965: Reserve space for "Vertex Count" in GS outputs.
v2: Also increment ir->offset in the GS visitor, rather than at the
final assembly generation stage (requested by Paul).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Kenneth Graunke [Sun, 13 Jan 2013 00:12:38 +0000 (16:12 -0800)]
i965: Update blitter code for 48-bit addresses.
v2: Rebase on Eric's SET_FIELD changes.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net> [v1]
Kenneth Graunke [Wed, 11 Dec 2013 23:54:07 +0000 (15:54 -0800)]
i965: Update PIPE_CONTROL packet lengths for Broadwell.
On Broadwell, PIPE_CONTROL needs an extra DWord to accomodate the
48-bit addressing.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Kenneth Graunke [Thu, 12 Dec 2013 08:44:11 +0000 (00:44 -0800)]
i965: Re-combine the Gen4-5 and Gen6+ write_depth_count functions.
Now that we have a helper function that handles the PIPE_CONTROL
variations between the various platforms, these are basically the same.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Kenneth Graunke [Tue, 14 Jan 2014 00:00:18 +0000 (16:00 -0800)]
i965: Create a helper function for emitting PIPE_CONTROL writes.
There are a lot of places that use PIPE_CONTROL to write a value to a
buffer (either an immediate write, TIMESTAMP, or PS_DEPTH_COUNT).
Creating a single function to do this seems convenient.
As part of this refactor, we now set the PPGTT/GTT selection bit
correctly on Gen7+. Previously, we set bit 2 of DW2 on all platforms.
This is correct for Sandybridge, but actually part of the address on
Ivybridge and later!
Broadwell will also increase the length of these packets by 1; with the
refactoring, we should have to adjust that in substantially fewer
places, giving us confidence that we've hit them all.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Kenneth Graunke [Wed, 11 Dec 2013 23:25:58 +0000 (15:25 -0800)]
i965: Use full-length PIPE_CONTROL packets for workaround writes.
I believe that PIPE_CONTROL uses the length field to decide whether to
do 32-bit or 64-bit writes. A length of 4 would do a 32-bit write,
while a length of 5 would do a 64-bit write. (I haven't verified this,
though.)
For workaround writes, we don't care what value gets written, or how
much data. We're only writing something because hardware bugs mandate
that do so. So using a 64-bit write should be fine.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Kenneth Graunke [Wed, 11 Dec 2013 23:22:26 +0000 (15:22 -0800)]
i965: Emit full-length PIPE_CONTROLs for (non-write) flushes.
The PIPE_CONTROL packet actually has 5 DWords on Gen6+:
1. Header
2. Flags
3. Address
4. Immediate Data: Lower DWord
5. Immediate Data: Upper DWord
We just never emitted the last one. While it appears to work, it's
probably safer to emit the entire thing.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Kenneth Graunke [Wed, 11 Dec 2013 22:44:45 +0000 (14:44 -0800)]
i965: Create a helper function for emitting PIPE_CONTROL flushes.
These days, we need to emit PIPE_CONTROL flushes all over the place.
Being able to do that via a single function call seems convenient.
Broadwell will also increase the length of these packets by 1; with the
refactoring, we should have to do this in substantially fewer places.
v2: Add back forgotten intel_emit_post_sync_nonzero_flush (caught by
Eric Anholt). Drop unlikely() from BLT_RING check.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Kenneth Graunke [Mon, 18 Nov 2013 18:10:07 +0000 (10:10 -0800)]
i965: Fix MI_STORE_REGISTER_MEM for Broadwell.
It now takes a 48-bit address.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Kenneth Graunke [Tue, 5 Nov 2013 00:55:26 +0000 (16:55 -0800)]
i965: Introduce an OUT_RELOC64 macro.
Broadwell uses 48-bit addresses. The first DWord is the low 32 bits,
and the second DWord is the high 16 bits.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Kenneth Graunke [Mon, 13 Jan 2014 22:32:56 +0000 (14:32 -0800)]
i965: Use the new drm_intel_bo offset64 field.
libdrm 2.4.52 introduces a new 'uint64_t offset64' field, intended to
replace the old 'unsigned long offset' field. To preserve ABI, libdrm
continues to store the presumed offset in both locations.
On Broadwell, a 64-bit kernel may place BOs at "high" (> 4G) addresses.
However, with a 32-bit userspace, the 'unsigned long offset' field will
only be 32-bit, which is not large enough to hold this value. We need
to use a proper uint64_t (like the kernel does).
Technically, a lot of this code doesn't affect Broadwell, so we could
leave it using the old field. But it makes sense to just switch to the
new, properly typed field.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Kenneth Graunke [Mon, 20 Jan 2014 18:46:53 +0000 (10:46 -0800)]
build: Require libdrm 2.4.52 for Intel.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Kenneth Graunke [Mon, 13 Jan 2014 23:01:35 +0000 (15:01 -0800)]
i965: Delete intel_batchbuffer_emit_reloc_fenced.
Nothing in i965 uses it.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Ian Romanick [Mon, 23 Dec 2013 04:05:50 +0000 (20:05 -0800)]
i915: Silence warning: unused parameter warning in intel_bufferobj_buffer
intel_buffer_objects.c: In function 'old_intel_bufferobj_buffer':
intel_buffer_objects.c:471:17: warning: unused parameter 'flag' [-Wunused-parameter]
The parameter hasn't been used since the i915 and i965 drivers had their
breakup. i965 got the flags, and i915 got to cry itself to sleep.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Ian Romanick [Fri, 20 Dec 2013 20:58:41 +0000 (12:58 -0800)]
i915: Ensure that intel_bufferobj_map_range meets alignment guarantees
Not actually tested, but the changes are identical to the i965 changes
that are tested.
v2: Remove MAX2(64, ...). Suggested by Ken (in the i965 version of this
patch).
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Cc: Siavash Eliasi <siavashserver@gmail.com>
Ian Romanick [Fri, 20 Dec 2013 20:42:33 +0000 (12:42 -0800)]
i965: Ensure that intel_bufferobj_map_range meets alignment guarantees
No piglit regressions on IVB.
With minor tweaks to the arb_map_buffer_alignment-map-invalidate-range
test (disable the extension check, set alignment to 64 instead of
querying), the i965 driver would fail the test without this patch (as
predicted by Eric). With this patch, it passes.
v2: Remove MAX2(64, ...). Suggested by Ken.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Cc: Siavash Eliasi <siavashserver@gmail.com>
Ian Romanick [Sat, 11 Jan 2014 00:07:55 +0000 (16:07 -0800)]
docs: Note that GL_ARB_viewport_array is done on i965
At least for GEN7+, anyway.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Courtney Goeltzenleuchter [Wed, 13 Nov 2013 20:15:19 +0000 (13:15 -0700)]
i965: Enable ARB_viewport_array
v2 (idr): Only enable the extension on GEN7+ w/core profile because it
requires geometry shaders.
v3 (idr): Add some casting to fix setting of ViewportBounds.Min.
Negating an unsigned value, then casting to float doesn't do what you
might think it does.
Signed-off-by: Courtney Goeltzenleuchter <courtney@LunarG.com>
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Ian Romanick [Wed, 8 Jan 2014 20:14:49 +0000 (12:14 -0800)]
i965: Consider all viewports before enabling guardband clipping
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Ian Romanick [Fri, 17 Jan 2014 23:28:23 +0000 (15:28 -0800)]
i965: Consider only the scissor rectangle for viewport 0 for clears
noop_scissor (correctly) only examines the scissor rectangle for
viewport 0. Therefore, it should only be called when that scissor
rectangle is enabled.
v2: Remove spurious change to radeon code. Noticed by Ken.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Ian Romanick [Wed, 8 Jan 2014 20:14:11 +0000 (12:14 -0800)]
i965: Set all the supported scissor rectangles for GEN7
Currently MaxViewports is still 1, so this won't affect any change.
v2: Minor code reformatting suggested by Ken.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Ian Romanick [Wed, 8 Jan 2014 20:10:41 +0000 (12:10 -0800)]
mesa: Refactor bounding-box calculation out of _mesa_update_draw_buffer_bounds
Drivers that currently use _Xmin and friends to set their scissor
rectangle will need to use this code directly once they are updated for
GL_ARB_viewport_array.
v2: Use different bit-test idiom and fix mixed tabs and spaces. Both
were suggested by Ken.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Ian Romanick [Wed, 6 Nov 2013 06:50:02 +0000 (22:50 -0800)]
i965: Set all the supported viewports for GEN7
Currently MaxViewports is still 1, so this won't affect any change.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Ian Romanick [Tue, 5 Nov 2013 20:19:23 +0000 (12:19 -0800)]
i965: Emit writes to viewport index
This variable is handled in a fashion identical to gl_Layer.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Ian Romanick [Fri, 10 Jan 2014 21:43:24 +0000 (13:43 -0800)]
i965: Set the maximum VPIndex
At various stages the hardware clamps the gl_ViewportIndex to these
values. Setting them to zero effectively makes gl_ViewportIndex be
ignored. This is acutally useful in blorp (so that we don't have to
modify all of the viewport / scissor state).
v2: Use INTEL_MASK to create GEN6_CLIP_MAX_VP_INDEX_MASK. Suggested by
Ken.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Courtney Goeltzenleuchter [Thu, 14 Nov 2013 17:10:47 +0000 (10:10 -0700)]
mesa: Add ARB_viewport_array plumbing
Define API connections to extension entry points added in previous
commits. Update entry points to use floating point arguments as
required by the extension.
Add get tokens for ARB_viewport_array state.
v2: Include review feedback.
v3 (idr): Fix 'make check'. Add missing Get infrastructure (some was
culled from other pathces).
Signed-off-by: Courtney Goeltzenleuchter <courtney@LunarG.com>
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>