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Bhawanpreet Lakha [Wed, 2 Oct 2019 15:50:15 +0000 (11:50 -0400)]
drm/amd/display: Add DP_DPHY_INTERNAL_CTR regs
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Roman Li <Roman.Li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Roman Li [Tue, 8 Oct 2019 21:35:48 +0000 (17:35 -0400)]
drm/amd/display: disable ext aux support for vega
[Why]
Earlier changes to support configurable aux timeout
caused dc init failure on vega due to missing reg defs.
Needs to be disabled until implemented for vega.
[How]
Set extended aux timeout cap for vega to false.
Signed-off-by: Roman Li <Roman.Li@amd.com>
Reviewed-By: abdoulaye berthe <abdoulaye.berthe@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
abdoulaye berthe [Thu, 18 Jul 2019 19:58:25 +0000 (15:58 -0400)]
drm/amd/display: configurable aux timeout support
[Description]
1-add configurable timeout support to aux engine.
2-add timeout support field to dc_caps
3-add reg_key to override extended timeout support
Signed-off-by: abdoulaye berthe <abdoulaye.berthe@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Roman Li <Roman.Li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
abdoulaye berthe [Tue, 13 Aug 2019 13:24:10 +0000 (09:24 -0400)]
drm/amd/display: update register field access mechanism
1-add timeout length and multiplier fields to aux_control1 register
2-update access mechanism from macro constructed name to uint32_t
defined addresses.
3-define registers and field per asic family
Signed-off-by: abdoulaye berthe <abdoulaye.berthe@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Roman Li <Roman.Li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
chen gong [Wed, 16 Oct 2019 10:04:02 +0000 (18:04 +0800)]
drm/amdgpu: No need to check gfxoff status after enable gfxoff feature
smu_send_smc_msg(smu, SMU_MSG_AllowGfxOff) Just turn on a switch.
As to when GPU get into "GFXoff" will be up to drawing load.
So we can not sure which state GPU should be in after enable gfxoff
feature.
Signed-off-by: chen gong <curry.gong@amd.com>
Acked-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kenneth Feng [Wed, 16 Oct 2019 08:20:38 +0000 (16:20 +0800)]
drm/amd/powerplay: bug fix for memory clock request from display
In some cases, display fixes memory clock frequency to a high value
rather than the natural memory clock switching.
When we comes back from s3 resume, the request from display is not reset,
this causes the bug which makes the memory clock goes into a low value.
Then due to the insuffcient memory clock, the screen flicks.
Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Prike Liang [Tue, 15 Oct 2019 09:11:49 +0000 (17:11 +0800)]
drm/amdgpu: fix S3 failed as RLC safe mode entry stucked in polloing gfx acq
Fix gfx cgpg setting sequence for RLC deadlock at safe mode entry in polling gfx response.
The patch can fix VCN IB test failed and DAL get dispaly count failed issue.
Signed-off-by: Prike Liang <Prike.Liang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Prike Liang [Tue, 15 Oct 2019 09:24:25 +0000 (17:24 +0800)]
drm/amdgpu: add GFX_PIPELINE capacity check for updating gfx cgpg
Before disable gfx pipeline power gating need check the flag AMD_PG_SUPPORT_GFX_PIPELINE.
Signed-off-by: Prike Liang <Prike.Liang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Ahzo [Fri, 11 Oct 2019 17:55:03 +0000 (19:55 +0200)]
drm/amd/display: add NULL checks for clock manager pointer
This fixes kernel NULL pointer dereferences on shutdown:
RIP: 0010:build_audio_output.isra.0+0x97/0x110 [amdgpu]
RIP: 0010:enable_link_dp+0x186/0x300 [amdgpu]
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Ahzo <Ahzo@tutanota.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Mon, 11 Mar 2019 23:05:12 +0000 (18:05 -0500)]
drm/amdgpu: enable BACO reset for SMU7 based dGPUs (v2)
Use BACO to reset the GPU if supported on SMU7 based
dGPUs.
v2: don't use baco on CI parts
Reviewed-by: Evan Quan <evan.quan@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Fri, 15 Feb 2019 23:17:24 +0000 (18:17 -0500)]
drm/amdgpu/powerplay: wire up BACO to powerplay API for smu7
Wire up the powerplay callbacks for for BACO for smu7 devices.
Reviewed-by: Evan Quan <evan.quan@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Fri, 15 Feb 2019 22:39:33 +0000 (17:39 -0500)]
drm/amdgpu/powerplay: split out common smu7 BACO code
Several of the BACO functions are common across smu7-based
asics. Split the common code out.
Reviewed-by: Evan Quan <evan.quan@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Fri, 15 Feb 2019 22:38:44 +0000 (17:38 -0500)]
drm/amdgpu/powerplay: add support for BACO on CI
This adds BACO support for CI asics.
Reviewed-by: Evan Quan <evan.quan@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Fri, 15 Feb 2019 22:37:46 +0000 (17:37 -0500)]
drm/amdgpu/powerplay: add support for BACO on Fiji
This adds BACO support for Fiji asics.
Reviewed-by: Evan Quan <evan.quan@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 14 Feb 2019 21:53:42 +0000 (16:53 -0500)]
drm/amdgpu/powerplay: add support for BACO on VegaM
This adds BACO support for VegaM asics.
Reviewed-by: Evan Quan <evan.quan@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Fri, 15 Feb 2019 22:36:40 +0000 (17:36 -0500)]
drm/amdgpu/powerplay: add support for BACO on polaris
This adds BACO support for Polaris asics.
Reviewed-by: Evan Quan <evan.quan@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Fri, 15 Feb 2019 16:56:56 +0000 (11:56 -0500)]
drm/amdgpu/powerplay: add support for BACO on Iceland
This adds BACO support for Iceland asics.
Reviewed-by: Evan Quan <evan.quan@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Fri, 15 Feb 2019 22:35:50 +0000 (17:35 -0500)]
drm/amdgpu/powerplay: add support for BACO on tonga
This adds BACO support for Tonga.
Reviewed-by: Evan Quan <evan.quan@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Mon, 11 Feb 2019 02:57:55 +0000 (21:57 -0500)]
drm/amdgpu/powerplay: add core support for pre-SOC15 baco
This adds core support for BACO on pre-vega asics.
Reviewed-by: Evan Quan <evan.quan@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Fri, 4 Oct 2019 20:18:52 +0000 (15:18 -0500)]
drm/amdgpu: add new SMU 7.1.3 registers for BACO
Reviewed-by: Evan Quan <evan.quan@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Fri, 4 Oct 2019 20:16:43 +0000 (15:16 -0500)]
drm/amdgpu: add new SMU 7.1.2 registers for BACO
Reviewed-by: Evan Quan <evan.quan@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Fri, 4 Oct 2019 20:14:18 +0000 (15:14 -0500)]
drm/amdgpu: add new SMU 7.0.1 registers for BACO
Reviewed-by: Evan Quan <evan.quan@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Mon, 11 Feb 2019 17:28:45 +0000 (12:28 -0500)]
drm/amdgpu: add new BIF 5.0 register for BACO
Reviewed-by: Evan Quan <evan.quan@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Fri, 15 Feb 2019 19:40:26 +0000 (14:40 -0500)]
drm/amdgpu: add new BIF 4.1 register for BACO
Reviewed-by: Evan Quan <evan.quan@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Tue, 15 Oct 2019 18:27:01 +0000 (14:27 -0400)]
drm/amdgpu/soc15: add support for baco reset with swSMU
Add support for vega20 when the swSMU path is used.
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Fri, 4 Oct 2019 16:01:11 +0000 (11:01 -0500)]
drm/amdgpu: remove in_baco_reset hack
It was a vega20 specific hack. Check if we are in reset
and what reset method we are using.
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Wed, 9 Oct 2019 19:39:37 +0000 (14:39 -0500)]
drm/amdgpu: simplify ATPX detection
Use the base class rather than the specific class and drop
the second loop.
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Fri, 4 Oct 2019 19:57:21 +0000 (14:57 -0500)]
drm/amdgpu: move gpu reset out of amdgpu_device_suspend
Move it into the caller. There are cases were we don't
want it. We need it for hibernation, but we don't need
it for runtime pm, so drop it for runtime pm.
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Fri, 4 Oct 2019 19:33:39 +0000 (14:33 -0500)]
drm/amdgpu: move pci_save_state into suspend path
for amdgpu_device_suspend. This follows the logic
in the resume path.
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Wed, 9 Oct 2019 18:12:37 +0000 (13:12 -0500)]
Revert "drm/radeon: Fix EEH during kexec"
This reverts commit
6f7fe9a93e6c09bf988c5059403f5f88e17e21e6.
This breaks some boards. Maybe just enable this on PPC for
now?
Bug: https://bugzilla.kernel.org/show_bug.cgi?id=205147
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hersen Wu [Tue, 15 Oct 2019 16:47:31 +0000 (12:47 -0400)]
drm/amdgpu/display: fix build error casused by CONFIG_DRM_AMD_DC_DCN2_1
when CONFIG_DRM_AMD_DC_DCN2_1 is not enable in .config,
there is build error. struct dpm_clocks shoud not be
guarded.
Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
Reviewed-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hersen Wu [Tue, 15 Oct 2019 14:34:54 +0000 (10:34 -0400)]
drm/amdgpu/display: hook renoir dc to pplib funcs
enable dc get dmp clock table and set dcn watermarks
via pplib.
Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
Reviewed-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Andrey Grodzovsky [Fri, 11 Oct 2019 14:32:59 +0000 (10:32 -0400)]
dmr/amdgpu: Fix crash on SRIOV for ERREVENT_ATHUB_INTERRUPT interrupt.
Ignre the ERREVENT_ATHUB_INTERRUPT for systems without RAS.
Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-and-tested-by: Jack Zhang <Jack.Zhang1@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Philip Yang [Thu, 3 Oct 2019 18:18:25 +0000 (14:18 -0400)]
drm/amdgpu: user pages array memory leak fix
user_pages array should always be freed after validation regardless if
user pages are changed after bo is created because with HMM change parse
bo always allocate user pages array to get user pages for userptr bo.
v2: remove unused local variable and amend commit
v3: add back get user pages in gem_userptr_ioctl, to detect application
bug where an userptr VMA is not ananymous memory and reject it.
Bugzilla: https://bugs.launchpad.net/ubuntu/+source/linux/+bug/
1844962
Signed-off-by: Philip Yang <Philip.Yang@amd.com>
Tested-by: Joe Barnett <thejoe@gmail.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hersen Wu [Wed, 18 Sep 2019 13:53:30 +0000 (09:53 -0400)]
drm/amdgpu/powerplay: add renoir funcs to support dc
there are two paths for renoir dc access smu.
one dc access smu directly using bios smc
interface: set disply, dprefclk, etc.
another goes through pplib for get dpm clock
table and set watermmark.
Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Thu, 10 Oct 2019 08:42:31 +0000 (16:42 +0800)]
drm/amd/powerplay: enable Arcturus runtime VCN dpm on/off
Enable runtime VCN DPM on/off on Arcturus.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kenneth Feng [Fri, 11 Oct 2019 09:51:34 +0000 (17:51 +0800)]
drm/amd/powerplay: bug fix for pcie parameters override
Bug fix for pcie paramerers override on swsmu.
Below is a scenario to have this problem.
pptable definition on pcie dpm:
0 -> pcie gen speed:1, pcie lanes: *16
1 -> pcie gen speed:4, pcie lanes: *16
Then if we have a system only have the capbility:
pcie gen speed: 3, pcie lanes: *8,
we will override dpm 1 to pcie gen speed 3, pcie lanes *8.
But the code skips the dpm 0 configuration.
So the real pcie dpm parameters are:
0 -> pcie gen speed:1, pcie lanes: *16
1 -> pcie gen speed:3, pcie lanes: *8
Then the wrong pcie lanes will be toggled.
Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Emily Deng [Tue, 15 Oct 2019 02:08:22 +0000 (10:08 +0800)]
drm/amdgpu: Fix tdr3 could hang with slow compute issue
When index is 1, need to set compute ring timeout for sriov and passthrough.
Signed-off-by: Emily Deng <Emily.Deng@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Thu, 19 Sep 2019 08:38:57 +0000 (10:38 +0200)]
drm/amdgpu: fix potential VM faults
When we allocate new page tables under memory
pressure we should not evict old ones.
Signed-off-by: Christian König <christian.koenig@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Wed, 18 Sep 2019 17:42:14 +0000 (19:42 +0200)]
drm/amdgpu: fix error handling in amdgpu_bo_list_create
We need to drop normal and userptr BOs separately.
Signed-off-by: Christian König <christian.koenig@amd.com>
Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dennis Li [Sun, 29 Sep 2019 08:04:10 +0000 (16:04 +0800)]
drm/amdgpu: add RAS support for VML2 and ATCL2
v1: Add codes to query the EDC count of VML2 & ATCL2
v2: Rename VML2/ATCL2 registers and drop their mask define
v3: Add back the ECC mask for VML2 registers
Signed-off-by: Dennis Li <Dennis.Li@amd.com>
Reviewed-by: Hawking Zhang <hawking.zhang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dennis Li [Fri, 9 Aug 2019 06:30:29 +0000 (14:30 +0800)]
drm/amd/include: add register define for VML2 and ATCL2
Add VML2 and ATCL2 ECC registers to support VEGA20 RAS
Signed-off-by: Dennis Li <Dennis.Li@amd.com>
Reviewed-by: Hawking Zhang <hawking.zhang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dennis Li [Sat, 12 Oct 2019 05:00:22 +0000 (13:00 +0800)]
drm/amdgpu: change to query the actual EDC counter
For the potential request in the future, change to
query the actual EDC counter.
Signed-off-by: Dennis Li <Dennis.Li@amd.com>
Reviewed-by: Hawking Zhang <hawking.zhang@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Le Ma [Fri, 11 Oct 2019 11:00:00 +0000 (19:00 +0800)]
drm/amd/powerplay: add BACO platformCaps for VEGA20
BACO reset is needed for RAS recovery.
Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Le Ma [Fri, 11 Oct 2019 10:50:44 +0000 (18:50 +0800)]
drm/amd/powerplay: send EnterBaco msg with argument as RAS recovery flag
1 indicates RAS recovery flag in SMU FW.
Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Le Ma [Fri, 11 Oct 2019 10:37:49 +0000 (18:37 +0800)]
drm/amd/powerplay: avoid disabling ECC if RAS is enabled for VEGA20
Program THM_BACO_CNTL.SOC_DOMAIN_IDLE=1 will tell VBIOS to disable ECC when
BACO exit. This can save BACO exit time by PSP on none-ECC SKU. Drop the setting
for ECC supported SKU.
Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Le Ma [Fri, 11 Oct 2019 10:21:16 +0000 (18:21 +0800)]
drm/amdgpu/soc15: disable doorbell interrupt as part of BACO entry sequence
Workaround to make RAS recovery work in BACO reset.
Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hans de Goede [Thu, 10 Oct 2019 16:28:17 +0000 (18:28 +0200)]
drm/amdgpu: Bail earlier when amdgpu.cik_/si_support is not set to 1
Bail from the pci_driver probe function instead of from the drm_driver
load function.
This avoid /dev/dri/card0 temporarily getting registered and then
unregistered again, sending unwanted add / remove udev events to
userspace.
Specifically this avoids triggering the (userspace) bug fixed by this
plymouth merge-request:
https://gitlab.freedesktop.org/plymouth/plymouth/merge_requests/59
Note that despite that being a userspace bug, not sending unnecessary
udev events is a good idea in general.
BugLink: https://bugzilla.redhat.com/show_bug.cgi?id=1490490
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 10 Oct 2019 15:07:40 +0000 (10:07 -0500)]
drm/amdgpu/display: clean up dcn2*_pp_smu functions
Use the dcn21 functions in dcn21_resource.c and make the
dcn20 functions static since they are only used in
dcn20_resource now.
Cc: bhawanpreet.lakha@amd.com
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Wed, 9 Oct 2019 10:52:51 +0000 (18:52 +0800)]
drm/amd/powerplay: re-enable FW_DSTATE feature bit
SMU firmware has fix the bug, so remove this workaround.
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Thu, 10 Oct 2019 12:44:20 +0000 (20:44 +0800)]
drm/amdgpu/discovery: reserve discovery data at the top of VRAM
IP Discovery data is TMR fenced by the latest PSP BL,
so we need to reserve this region.
Tested on navi10/12/14 with VBIOS integrated with latest PSP BL.
v2: use DISCOVERY_TMR_SIZE macro as bo size
use amdgpu_bo_create_kernel_at() to allocate bo
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kevin Wang [Fri, 11 Oct 2019 00:45:41 +0000 (08:45 +0800)]
drm/amdgpu/swSMU: custom UMD pstate peak clock for navi14
add navi14 umd pstate peak clock support.
NAVI14_UMD_PSTATE_PEAK_XT_GFXCLK 1670 MHz
NAVI14_UMD_PSTATE_PEAK_XTM_GFXCLK 1448 MHz
NAVI14_UMD_PSTATE_PEAK_XLM_GFXCLK 1181 MHz
NAVI14_UMD_PSTATE_PEAK_XTX_GFXCLK 1717 MHz
NAVI14_UMD_PSTATE_PEAK_XL_GFXCLK 1448 MHz
Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Thu, 10 Oct 2019 03:40:37 +0000 (11:40 +0800)]
drm/amd/powerplay: enable df cstate control on swSMU routine
Currently this is only supported on Vega20 with 40.50 and later
SMC firmware.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Thu, 10 Oct 2019 03:34:51 +0000 (11:34 +0800)]
drm/amd/powerplay: enable df cstate control on powerplay routine
Currently this is only supported on Vega20 with 40.50 and later
SMC firmware.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Wed, 9 Oct 2019 13:14:03 +0000 (08:14 -0500)]
drm/amdgpu/swSMU/navi: add feature toggles for more things
Add toggles for more power features. Helpful in debugging.
Reviewed-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Ville Syrjälä [Thu, 10 Oct 2019 13:11:58 +0000 (16:11 +0300)]
drm/amdgpu/powerplay: Use swap() where appropriate
@swap@
identifier TEMP;
expression A,B;
@@
- TEMP = A;
- A = B;
- B = TEMP;
+ swap(A, B);
@@
type T;
identifier swap.TEMP;
@@
(
- T TEMP;
|
- T TEMP = {...};
)
... when != TEMP
Cc: Rex Zhu <rex.zhu@amd.com>
Cc: Evan Quan <evan.quan@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: "Christian König" <christian.koenig@amd.com>
Cc: "David (ChunMing) Zhou" <David1.Zhou@amd.com>
Cc: amd-gfx@lists.freedesktop.org
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Ville Syrjälä [Thu, 10 Oct 2019 13:11:57 +0000 (16:11 +0300)]
drm/amd/display: Use swap() where appropriate
Mostly a cocci-job, but it flat out refused to remove the
declaration in drivers/gpu/drm/amd/display/dc/core/dc.c so
had to do that part manually.
@swap@
identifier TEMP;
expression A,B;
@@
- TEMP = A;
- A = B;
- B = TEMP;
+ swap(A, B);
@@
type T;
identifier swap.TEMP;
@@
(
- T TEMP;
|
- T TEMP = {...};
)
... when != TEMP
Cc: Harry Wentland <harry.wentland@amd.com>
Cc: Leo Li <sunpeng.li@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: "Christian König" <christian.koenig@amd.com>
Cc: "David (ChunMing) Zhou" <David1.Zhou@amd.com>
Cc: amd-gfx@lists.freedesktop.org
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
chen gong [Sun, 29 Sep 2019 02:58:43 +0000 (10:58 +0800)]
drm/amdgpu: Do not implement power-on for SDMA after do mode2 reset on Renoir
Find that ring sdma0 test failed if turn on SDMA powergating after do
mode2 reset.
Perhaps the mode2 reset does not reset the SDMA PG state, SDMA is
already powered up so there is no need to ask the SMU to power it up
again. So I skip this function for a moment.
Signed-off-by: chen gong <curry.gong@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Wed, 9 Oct 2019 08:40:59 +0000 (16:40 +0800)]
drm/amd/powerplay: add more feature bits
Additional features that can be enabled in the SMU.
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Wed, 9 Oct 2019 17:01:23 +0000 (01:01 +0800)]
drm/amdgpu/sdma5: fix mask value of POLL_REGMEM packet for pipe sync
sdma will hang once sequence number to be polled reaches 0x1000_0000
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Wed, 2 Oct 2019 21:10:24 +0000 (16:10 -0500)]
drm/amdgpu/powerplay: fix typo in mvdd table setup
Polaris and vegam use count for the value rather than
level. This looks like a copy paste typo from when
the code was adapted from previous asics.
I'm not sure that the SMU actually uses this value, so
I don't know that it actually is a bug per se.
Bug: https://bugs.freedesktop.org/show_bug.cgi?id=108609
Reported-by: Robert Strube <rstrube@gmail.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nirmoy Das [Fri, 4 Oct 2019 09:53:37 +0000 (11:53 +0200)]
drm/amdgpu: fix memory leak
cleanup error handling code and make sure temporary info array
with the handles are freed by amdgpu_bo_list_put() on
idr_replace()'s failure.
Signed-off-by: Nirmoy Das <nirmoy.das@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Mon, 30 Sep 2019 06:48:19 +0000 (14:48 +0800)]
drm/amdgpu: avoid ras error injection for retired page
check whether a page is bad page before umc error injection, bad page
should not be accessed again
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Guchun Chen <guchun.chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Luben Tuikov [Wed, 2 Oct 2019 04:02:18 +0000 (00:02 -0400)]
drm/amdgpu: Use the ALIGN() macro
Use the ALIGN() macro to set "num_dw" to a
multiple of 8, i.e. lower 3 bits cleared.
Signed-off-by: Luben Tuikov <luben.tuikov@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Tue, 8 Oct 2019 18:08:30 +0000 (13:08 -0500)]
drm/amdgpu/ras: document the reboot ras option
We recently added it, but never documented it.
Reviewed-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Tue, 8 Oct 2019 18:04:33 +0000 (13:04 -0500)]
drm/amdgpu/ras: fix typos in documentation
Fix a couple of spelling typos.
Reviewed-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dmytro Laktyushkin [Fri, 13 Sep 2019 15:33:27 +0000 (11:33 -0400)]
drm/amd/display: add renoir specific watermark range and clk helper
Doing this allows us to split it for diffrent asics. This design will
be helpful for future Asciis.
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Eric Yang [Thu, 22 Aug 2019 15:54:41 +0000 (11:54 -0400)]
drm/amd/display: hook up notify watermark ranges and get clock table
[Why]
Previously SMU was giving us 0s for the clock table. Now they have valid
clock table. We should use theirs. Also, need to send SMU watermark
ranges for selecting optimal watermarks.
Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Sung Lee [Tue, 24 Sep 2019 17:20:33 +0000 (13:20 -0400)]
drm/amd/display: Skip DIG Check if Link is Virtual for Display Count
[WHY]
Without a check for virtual links, every link's DIG was getting
checked for enabled or disabled. If link was virtual, since it
did not have a DIG, this would cause issues.
[HOW]
Skip DIG Enable check if link is virtual and add virtual link to
to display count.
Signed-off-by: Sung Lee <sung.lee@amd.com>
Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Wayne Lin [Thu, 19 Sep 2019 09:41:02 +0000 (17:41 +0800)]
drm/amd/display: correct stream LTE_340MCSC_SCRAMBLE value
[Why]
HDMI 2.0 requires scrambling under specific conditions. We refer to
stream property LTE_340MCSC_SCRAMBLE to determine whether en/dis
scrambling.
While creating stream for sink, we setup LTE_340MCSC_SCRAMBLE by
referring to edid_caps. However, dm_helpers_parse_edid_caps()
doesn't construct HDMI Forum block data for edid_caps.
Moreover, fill_stream_properties_from_drm_display_mode() aslo
unconsciously clear the LTE_340MCSC_SCRAMBLE flag.
[How]
Drm already provides drm_display_info to refer HDMI Forum vsdb info.
Set stream LTE_340MCSC_SCRAMBLE by drm_display_info and remove
memset in fill_stream_properties_from_drm_display_mode()
Signed-off-by: Wayne Lin <Wayne.Lin@amd.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
David Galiffi [Sat, 21 Sep 2019 00:20:23 +0000 (20:20 -0400)]
drm/amd/display: Fix dongle_caps containing stale information.
[WHY]
During detection:
function: get_active_converter_info populates link->dpcd_caps.dongle_caps
only when dpcd_rev >= DPCD_REV_11 and DWN_STRM_PORTX_TYPE is
DOWN_STREAM_DETAILED_HDMI or DOWN_STREAM_DETAILED_DP_PLUS_PLUS.
Otherwise, it is not cleared, and stale information remains.
During mode validation:
function: dp_active_dongle_validate_timing reads
link->dpcd_caps.dongle_caps->dongle_type to determine the maximum
pixel clock to support. This information is now stale and no longer
valid.
[HOW]
dp_active_dongle_validate_timing should be using
link->dpcd_caps->dongle_type instead.
Signed-off-by: David Galiffi <david.galiffi@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jaehyun Chung [Mon, 23 Sep 2019 14:00:57 +0000 (10:00 -0400)]
drm/amd/display: Add capability check for static ramp calc
[Why]
Static ramp to max refresh rate does not have capability check on
calculated v_total. Programming a lower v_total_min and max than the
total causes continuous spurious HPDs.
[How]
Add a capability check after v_total calculation similar to calculate
v_total helper functions.
Signed-off-by: Jaehyun Chung <jaehyun.chung@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aric Cyr [Mon, 23 Sep 2019 12:16:36 +0000 (08:16 -0400)]
drm/amd/display: 3.2.54
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaodong Yan [Fri, 30 Aug 2019 09:07:01 +0000 (17:07 +0800)]
drm/amd/display: make aux defer delay and aux sw start delay seperate
[why]
1. defer delay and sw start delay has been mixed up, defer delay was
programmed to AUX_SW_CONTROL:AUX_SW_START_DELAY.
2. There's no delay for defer
[how]
1. Set aux sw start to 0
2. Add delay for defer scenario
Signed-off-by: Xiaodong Yan <Xiaodong.Yan@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Charlene Liu [Wed, 18 Sep 2019 00:28:40 +0000 (20:28 -0400)]
drm/amd/display: use vbios message to call smu for dpm level
[Description]
use vbios message to call smu for dpm level
also only program dmdata in vsyncflip as HW requirement.
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leo Li [Fri, 20 Sep 2019 13:43:36 +0000 (09:43 -0400)]
drm/amd/display: Fix maybe-uninitialized warning
[Why]
Compiling with GCC 9.1.0 gives the following warning (I have
warnings-as-errors enabled):
drivers/gpu/drm/amd/amdgpu/../dal-dev/dc/core/dc.c: In function 'dc_validate_seamless_boot_timing':
drivers/gpu/drm/amd/amdgpu/../dal-dev/dc/core/dc.c:1180:8: error: 'se' may be used uninitialized in this function [-Werror=maybe-uninitialized]
1180 | if (!se->funcs->dp_get_pixel_format(
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1181 | se,
| ~~~
1182 | &hw_crtc_timing.pixel_encoding,
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1183 | &hw_crtc_timing.display_color_depth))
[How]
Initialize se to NULL.
Signed-off-by: Leo Li <sunpeng.li@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Martin Leung [Tue, 17 Sep 2019 18:50:22 +0000 (14:50 -0400)]
drm/amd/display: add more checks to validate seamless boot timing
[why]
we found using an active DP to HDMI panel that we weren't validating
dp_pixel_format and hardware timing v_front_porch, causing screen to
blank and/or corrupt while attempting a seamless boot.
[how]
added checks during dc_validate_seamless_boot_timing for these values
Signed-off-by: Martin Leung <martin.leung@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Vitaly Prosyak [Mon, 16 Sep 2019 22:04:33 +0000 (17:04 -0500)]
drm/amd/display: add new active dongle to existent w/a
[Why & How]
Dongle 0x00E04C power down all internal circuits including
AUX communication preventing reading DPCD table.
Encoder will skip DP RX power down on disable output
to keep receiver powered all the time.
Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Acked-by: Vitaly Prosyak <Vitaly.Prosyak@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Michael Strauss [Tue, 17 Sep 2019 13:02:01 +0000 (09:02 -0400)]
drm/amd/display: Update number of dcn21 audio endpoints
[WHY]
Number of audio endpoints wasn't updated from dcn20's 6 when created
[HOW]
Changed num_audio to 4 to match the correct sbios value
Signed-off-by: Michael Strauss <michael.strauss@amd.com>
Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Joseph Gravenor [Mon, 16 Sep 2019 19:13:33 +0000 (15:13 -0400)]
drm/amd/display: add guard for SMU ver, for 48mhz clk
[why]
dp_48m_refclk_driver_pwdn is persistent through S3 and S5.
This was worked arround in SMU FW 55.21.0. Earlier FW don't have this fix
so we will hang on reboot
[how]
add a guard for smu versions before SMU FW 55.21.0
Signed-off-by: Joseph Gravenor <joseph.gravenor@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Eric Yang [Thu, 18 Jul 2019 17:56:59 +0000 (13:56 -0400)]
drm/amd/display: fix code to control 48mhz refclk
[Why]
The SMU message to enable this feature looks at argument. Previous code
didn't send right argument. This change will allow the feature to be
be enabled.
[How]
Fixed one issue where SMU message to enable the feature was sent without
setting the parameter.
Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Eric Yang [Fri, 6 Sep 2019 22:26:23 +0000 (18:26 -0400)]
drm/amd/display: exit PSR during detection
[Why]
If 48mhz refclk is turned off during PSR, we will have issue doing
link training during detection.
[How]
Get out of PSR before detection
Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Julian Parkin [Thu, 29 Aug 2019 21:06:05 +0000 (17:06 -0400)]
drm/amd/display: Program DWB watermarks from correct state
[Why]
When diags adds a DWB via a stream update, we calculate MMHUBBUB
paramaters, but dc->current_state has not yet been updated
when the DWB programming happens. This leads to overflow on
high bandwidth tests since the incorrect MMHUBBUB arbitration
parameters are programmed.
[How]
Pass the updated context down to the (enable|update)_writeback functions
so that they can use the correct watermarks when programming MMHUBBUB.
Signed-off-by: Julian Parkin <julian.parkin@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aric Cyr [Sat, 14 Sep 2019 15:19:18 +0000 (11:19 -0400)]
drm/amd/display: 3.2.53
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Wesley Chalmers [Fri, 13 Sep 2019 17:43:36 +0000 (13:43 -0400)]
drm/amd/display: Use dcn1 Optimal Taps Get
[WHY]
dpp2_get_optimal_number_of_taps is incorrect, and dcn2 should be using
dpp1_get_optimal_number_of_taps instead
Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Sivapiriyan Kumarasamy [Thu, 12 Sep 2019 19:55:44 +0000 (15:55 -0400)]
drm/amd/display: fix bug with check for HPD Low in verify link cap
[Why]
There is a bug when determining if link training should be retried when
HPD is low in dp_verify_link_cap_with_retries.
[How]
Correctly, fail dp_verify_link_cap_with_retries without retry when
HPD is low.
Signed-off-by: Sivapiriyan Kumarasamy <sivapiriyan.kumarasamy@amd.com>
Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
Acked-by: Abdoulaye Berthe <Abdoulaye.Berthe@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Josip Pavic [Thu, 12 Sep 2019 19:40:08 +0000 (15:40 -0400)]
drm/amd/display: wait for set pipe mcp command completion
[Why]
When the driver sends a pipe set command to the DMCU FW, it does not wait
for the command to complete. This can lead to unpredictable behavior if,
for example, the driver were to request a pipe disable to the FW via MCP,
then power down some hardware before the firmware has completed processing
the command.
[How]
Wait for the DMCU FW to finish processing set pipe commands
Signed-off-by: Josip Pavic <Josip.Pavic@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nikola Cornij [Thu, 12 Sep 2019 21:15:16 +0000 (17:15 -0400)]
drm/amd/display: Add output bitrate to DML calculations
[why]
Output bitrate was mistakenly left out, causing corruption on some
DSC low resolution (such as 800x600) modes.
Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aric Cyr [Wed, 11 Sep 2019 20:17:08 +0000 (16:17 -0400)]
drm/amd/display: Properly round nominal frequency for SPD
[Why]
Some displays rely on the SPD verticle frequency maximum value.
Must round the calculated refresh rate to the nearest integer.
[How]
Round the nominal calculated refresh rate to the nearest whole
integer.
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Joshua Aberback [Thu, 12 Sep 2019 17:14:52 +0000 (13:14 -0400)]
drm/amd/display: Restore should_update_pstate_support after bad revert
[Why]
This function was mistakenly reverted as part of a legitimate revert. The
old version that was reverted to has bad logic, and is causing situations
where p-state change support is being toggled when it shouldn't be,
resulting in hangs.
Signed-off-by: Joshua Aberback <joshua.aberback@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Lewis Huang [Thu, 5 Sep 2019 07:33:58 +0000 (15:33 +0800)]
drm/amd/display: check phy dpalt lane count config
[Why]
Type-c PHY config is not align with dpcd lane count.
When those values didn't match, it cause driver do
link training with 4 lane but phy only can output 2 lane.
The link trainig always fail.
[How]
1. Modify get_max_link_cap function. According DPALT_DP4
to update max lane count.
2. Add dp_mst_verify_link_cap to handle MST case because
we didn't call dp_mst_verify_link_cap for MST case.
Signed-off-by: Lewis Huang <Lewis.Huang@amd.com>
Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Wayne Lin [Tue, 3 Sep 2019 21:31:16 +0000 (05:31 +0800)]
drm/amd/display: build up VSIF infopacket
[Why]
Didn't send VSIF infopacket when it's 4k mode defined in HDMI 1.4b.
For HDMI 1.4b, While displaying 4k modes, it should send VSP.
[How]
Call mod_build_hf_vsif_infopacket() function to build info frame
and send it.
Signed-off-by: Wayne Lin <Wayne.Lin@amd.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Anthony Koo [Mon, 9 Sep 2019 14:27:31 +0000 (10:27 -0400)]
drm/amd/display: 3.2.52
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Joshua Aberback [Fri, 6 Sep 2019 21:34:19 +0000 (17:34 -0400)]
drm/amd/display: Add missing shifts and masks for dpp registers on dcn2
[Why]
The register CM_TEST_DEBUG_DATA is used in dpp1_program_input_csc, which is
called from dpp2_cnv_setup, but the shifts and masks for the fields of that
register are not initialized for dcn2. This causes all reads of that register
to return 0.
Signed-off-by: Joshua Aberback <joshua.aberback@amd.com>
Reviewed-by: Jaehyun Chung <Jaehyun.Chung@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jun Lei [Mon, 9 Sep 2019 15:05:33 +0000 (11:05 -0400)]
drm/amd/display: add explicit comparator as default optimization check
[why]
memcmp is vulnerable to regression due to dc_clocks structures not being
organized properly (not "current" clock related structures being at the beginning
of the structure) and causes unnecessary setting of the optimize bit
[how]
add a dcn sepcific comparator, implement for dcn2
Signed-off-by: Jun Lei <Jun.Lei@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Wayne Lin [Tue, 3 Sep 2019 21:18:31 +0000 (05:18 +0800)]
drm/amd/display: add support for VSIP info packet
[Why]
The vendor specific infoframe is needed for HDMI while displaying
specific modes.
DC supports sending it, but we aren't currently building it
[How]
Add mod_build_hf_vsif_infopacket() to build the vendor specific
info packet.
Signed-off-by: Wayne Lin <Wayne.Lin@amd.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Joseph Gravenor [Wed, 4 Sep 2019 16:43:05 +0000 (12:43 -0400)]
drm/amd/display: fix hotplug during display off
[why]
HPD is not suppressed when we lower
clocks on renoir. B/c of this we do link
training when the 48mhz refclk is off, which
will cause ASIC hang.
[how]
Exit optimized power state for detection purpose.
Signed-off-by: Joseph Gravenor <joseph.gravenor@amd.com>
Reviewed-by: Eric Yang <eric.yang2@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dmytro Laktyushkin [Fri, 6 Sep 2019 15:12:14 +0000 (11:12 -0400)]
drm/amd/display: fix pipe re-assignment when odm present
Currently pipe split may steal an existing ODM pipe depending on stream
sequence. This change prevents that from happening as easily.
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Gary Kattan <Gary.Kattan@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Julian Parkin [Thu, 22 Aug 2019 20:32:05 +0000 (16:32 -0400)]
drm/amd/display: Reprogram FMT on pipe change
[Why]
When planes are added or removed from a stream, the change
in pipe usage from dynamic MPC combine can cause a second
stream using ODM combine to pick a different pipe to combine with.
In this scenario, a different OPP is connected to the ODM without
programming its FMT.
[How]
Reprogram the FMT in dcn20_program_pipe whenever a pipe is
newly enabled, or when its opp changes.
Signed-off-by: Julian Parkin <julian.parkin@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aric Cyr [Fri, 6 Sep 2019 20:24:54 +0000 (16:24 -0400)]
drm/amd/display: Update V_UPDATE whenever VSTARTUP changes
[Why]
If VSTARTUP changes due to bandwidth requirements, we must
recalculate and update VLINE2 as well for proper flip reporting.
[How]
After all calls to program_global_sync which reconfigures
VSTARTUP, also make sure to update V_UPDATE (i.e. VLINE2 on DCNx).
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Reviewed-by: Sivapiriyan Kumarasamy <Sivapiriyan.Kumarasamy@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>