OSDN Git Service
Craig Topper [Sun, 10 Dec 2017 09:14:42 +0000 (09:14 +0000)]
[X86] Add LEA64_32r to scheduler models for Sandybridge,Haswell,Broadwell,Skylake
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320293
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Craig Topper [Sun, 10 Dec 2017 09:14:41 +0000 (09:14 +0000)]
[X86] Add IN16/OUT16 to scheduling information for Haswell,Broadwell,Skylake
Sandy Bridge is also missing it, but it has other issues. See PR35590.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320292
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Craig Topper [Sun, 10 Dec 2017 09:14:39 +0000 (09:14 +0000)]
[X86] Fix scheduler models to support ADD32ri in addition to ADD32ri8. Similar for all sizes of AND/OR/XOR/SUB/ADC/SBB/CMP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320291
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Craig Topper [Sun, 10 Dec 2017 09:14:38 +0000 (09:14 +0000)]
[X86] Rename some instructions so that 'b' is added as a suffix instead of replacing an 'r'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320290
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Craig Topper [Sun, 10 Dec 2017 09:14:37 +0000 (09:14 +0000)]
[X86] Add CMPSDrr/rm to the scheduler models.
Somehow CMPSSrr/rm was there and the VEX version was there, but this was consistently missing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320289
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Craig Topper [Sun, 10 Dec 2017 09:14:35 +0000 (09:14 +0000)]
[Docs] Fix typo in scheduler model documentation. enumemation->enumeration
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320288
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Tim Northover [Sun, 10 Dec 2017 08:43:19 +0000 (08:43 +0000)]
PowerPC: support external pid instructions in MC layer.
This adds assembly & disassembly support for the e500mc "external pid"
instructions.
See https://reviews.llvm.org/D39249.
Patch by vit9696 <vit9696@avp.su>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320287
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Xinliang David Li [Sun, 10 Dec 2017 07:39:53 +0000 (07:39 +0000)]
[PGO] change arg type to uint64_t to match member field type
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320285
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Craig Topper [Sun, 10 Dec 2017 04:07:28 +0000 (04:07 +0000)]
[X86] Rename the rb form of scalar ADD/SUB/MUL/DIV to include _Int since they can only be selected by intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320283
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Craig Topper [Sun, 10 Dec 2017 03:16:38 +0000 (03:16 +0000)]
[X86] Correct the _Int part of more scheduler model instrexes. Put _b in the correct order relative to _Int
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320282
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Craig Topper [Sun, 10 Dec 2017 03:16:36 +0000 (03:16 +0000)]
[X86] Remove ReadAfterLd from several several rb instructions
This affects CVTSD2SS, FMA, RCP28, RSQRT28, and SQRT scalar instructions
'b' here refers to 'sae' not broadcast. These aren't memory instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320281
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Craig Topper [Sun, 10 Dec 2017 01:27:54 +0000 (01:27 +0000)]
[X86] Fix test case I failed ot update in r320279.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320280
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Craig Topper [Sun, 10 Dec 2017 01:24:08 +0000 (01:24 +0000)]
[X86] Fix bad regular expressions in the scheduler models. Question marks should be outside of multicharacter parenthesized expressions
If the question mark is inside the parentheses it only applies to the single character proceeding it.
I had to make a few additional cleanups to fix some duplicate warnings that were exposed by fixing this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320279
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Craig Topper [Sun, 10 Dec 2017 01:24:06 +0000 (01:24 +0000)]
[X86] Make the _Int part of some instregex sheduler patterns optional
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320278
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Craig Topper [Sun, 10 Dec 2017 01:24:05 +0000 (01:24 +0000)]
[X86] Add the commutable floating point min/max pseudo instructions to sandybridge,haswell,broadwell,skylakeclient scheduler models.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320277
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Simon Pilgrim [Sun, 10 Dec 2017 00:40:37 +0000 (00:40 +0000)]
[X86] Tag PIC setup instruction as jump scheduler class
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320276
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Simon Pilgrim [Sun, 10 Dec 2017 00:30:57 +0000 (00:30 +0000)]
[X86] Tag ACQUIRE/RELEASE atomic instructions as microcoded scheduler classes
Note: We may be too pessimistic here and should possibly use something closer to the LOCK arithmetic instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320275
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Simon Pilgrim [Sun, 10 Dec 2017 00:12:57 +0000 (00:12 +0000)]
[X86] Tag TLS instructions as system scheduler classes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320274
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Simon Pilgrim [Sun, 10 Dec 2017 00:03:16 +0000 (00:03 +0000)]
[X86] Tag ALLOCA/VAARG instructions as system scheduler classes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320273
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Joel Jones [Sat, 9 Dec 2017 23:59:55 +0000 (23:59 +0000)]
[AArch64] Improve loop unrolling performance on Cavium T99
This patch improves performance on Cavium T99 as shown here (libquantum 0.2.4):
https://docs.google.com/spreadsheets/d/1Lo1o2E1NjrpkwS7DvYYWsiVvPdd93h7KBaqeptMrZPY/edit?usp=sharing
By increasing the LoopMicroOpsBufferSize in the Cavium T99 Scheduler file,
loop unrolling becomes more aggressive. This helps performance on T99.
Test case included.
Patch by Stefan Teleman
Differential Revision: https://reviews.llvm.org/D40695
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320272
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Simon Pilgrim [Sat, 9 Dec 2017 23:42:56 +0000 (23:42 +0000)]
[InstCombine] Fix SimplifyDemandedUseBits SHL handling (PR35515)
Don't assume that the pattern matched SRL can be cast to an Instruction (might be ConstExpr etc.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320270
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Simon Dardis [Sat, 9 Dec 2017 23:25:57 +0000 (23:25 +0000)]
Infer lowest bits of an integer Multiply when the low bits of the operands are known
When the lowest bits of the operands to an integer multiply are known, the low bits of the result are deducible.
Code to deduce known-zero bottom bits already existed, but this change improves on that by deducing known-ones.
Patch by: Pedro Ferreira
Reviewers: craig.topper, sanjoy, efriedma
Differential Revision: https://reviews.llvm.org/D34029
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320269
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Craig Topper [Sat, 9 Dec 2017 23:10:59 +0000 (23:10 +0000)]
[X86] Use KMOV instructions to zero upper bits of vectors when possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320268
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Craig Topper [Sat, 9 Dec 2017 22:44:42 +0000 (22:44 +0000)]
[X86] Improve lowering of vXi1 insert_subvectors to better utilize (insert_subvector zero, vec, 0) for zeroing upper bits.
This can be better recognized during isel when the producer already zeroed the upper bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320267
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Simon Pilgrim [Sat, 9 Dec 2017 21:27:03 +0000 (21:27 +0000)]
[X86] Tag LOCK/REX64/DATA16/DATA32 instruction prefix scheduler classes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320266
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Simon Pilgrim [Sat, 9 Dec 2017 20:44:51 +0000 (20:44 +0000)]
Strip trailing whitespace. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320265
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Simon Pilgrim [Sat, 9 Dec 2017 20:42:27 +0000 (20:42 +0000)]
[X86] Tag FS/GS BASE R/W instruction scheduler classes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320264
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Simon Pilgrim [Sat, 9 Dec 2017 20:16:37 +0000 (20:16 +0000)]
[X86] Tag REP/REPNE prefix instructions as microcoded scheduler classes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320263
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Simon Pilgrim [Sat, 9 Dec 2017 20:04:02 +0000 (20:04 +0000)]
[X86] Tag missing EH pseudo instruction scheduler classes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320262
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Simon Pilgrim [Sat, 9 Dec 2017 19:56:39 +0000 (19:56 +0000)]
[X86] Tag frame pointer XORs instruction scheduler classes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320261
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Craig Topper [Sat, 9 Dec 2017 19:18:30 +0000 (19:18 +0000)]
[X86] Don't use getTargetConstant for all 0s and all 1s mask vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320260
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Adrian Prantl [Sat, 9 Dec 2017 19:09:59 +0000 (19:09 +0000)]
Remove duplicate option from documentation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320258
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Simon Pilgrim [Sat, 9 Dec 2017 16:58:34 +0000 (16:58 +0000)]
[X86] Tag segment prefixes as NOP instruction scheduling classes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320257
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Simon Pilgrim [Sat, 9 Dec 2017 16:20:54 +0000 (16:20 +0000)]
[X86][AVX512] Drop a default NoItinerary argument that isn't used any more. NFCI.
Requires re-ordering of AVX512_maskable_custom arguments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320255
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Simon Pilgrim [Sat, 9 Dec 2017 16:19:18 +0000 (16:19 +0000)]
Fix 'enumeral and non-enumeral type in conditional expression' gcc warning. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320254
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Simon Pilgrim [Sat, 9 Dec 2017 16:04:57 +0000 (16:04 +0000)]
Fix signed/unsigned gcc warning. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320253
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Florian Hahn [Sat, 9 Dec 2017 14:25:33 +0000 (14:25 +0000)]
[InlineFunction] Set debug loc for call to forward varargs.
Reviewers: aprantl, dblaikie, rnk
Reviewed By: rnk
Subscribers: eraman, llvm-commits, JDevlieghere
Differential Revision: https://reviews.llvm.org/D40432
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320252
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Craig Topper [Sat, 9 Dec 2017 08:19:07 +0000 (08:19 +0000)]
[X86] When inserting into the upper bits of a vXi1 vector, make sure we shift enough bits if we widened the vector.
We may need to widen the vector to make the shifts legal, but if we do that we need to make sure we shift left/right after accounting for the new size. If not we can't guarantee we are shifting in zeros.
The test cases affected actually show cases where we should move the shifts all together, but that's another problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320248
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Dylan McKay [Sat, 9 Dec 2017 08:01:28 +0000 (08:01 +0000)]
Revert and accidentally committed revert commit
This reverts commit r320245.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320247
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Dylan McKay [Sat, 9 Dec 2017 07:51:43 +0000 (07:51 +0000)]
[AVR] Fix two CodeGen tests
These were broken because of various printing format changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320246
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Dylan McKay [Sat, 9 Dec 2017 07:51:37 +0000 (07:51 +0000)]
Revert "[AVR] Override ParseDirective"
This reverts commit
57c16f9267969ebb09d6448607999b4a9f40c418.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320245
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Craig Topper [Sat, 9 Dec 2017 07:02:19 +0000 (07:02 +0000)]
[X86] Improve lowering of concats of mask vectors to better optimize zero vector inputs.
We were previously using kunpck with zero inputs unnecessarily. And we had cases where we would insert into a zero vector and then insert into larger zero vector incurring two sets of shifts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320244
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Dylan McKay [Sat, 9 Dec 2017 06:45:36 +0000 (06:45 +0000)]
Relax unaligned access assertion when type is byte aligned
Summary:
This relaxes an assertion inside SelectionDAGBuilder which is overly
restrictive on targets which have no concept of alignment (such as AVR).
In these architectures, all types are aligned to 8-bits.
After this, LLVM will only assert that accesses are aligned on targets
which actually require alignment.
This patch follows from a discussion on llvm-dev a few months ago
http://llvm.
1065342.n5.nabble.com/llvm-dev-Unaligned-atomic-load-store-td112815.html
Reviewers: bogner, nemanjai, joerg, efriedma
Reviewed By: efriedma
Subscribers: efriedma, cactus, llvm-commits
Differential Revision: https://reviews.llvm.org/D39946
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320243
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Jessica Paquette [Sat, 9 Dec 2017 00:43:49 +0000 (00:43 +0000)]
[MachineOutliner] Outline calls
The outliner previously would never outline calls. Calls are pretty common in
files, so it makes sense to outline them. In fact, in the LLVM test suite, if
you count the number of instructions that the outliner misses when you outline
calls vs when you don't, it turns out that, on average, around 6% of the
instructions encountered are calls. So, if we outline calls, we can find more
candidates, and thus save some more space.
This commit adds that functionality and updates the mir test to reflect that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320229
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Wolfgang Pieb [Sat, 9 Dec 2017 00:39:53 +0000 (00:39 +0000)]
[NFC] Change the string offsets table tests to generate the object on the fly
which enables us to remove the test scripts and object files from the repository.
https://reviews.llvm.org/D40914
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320227
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Kamil Rytarowski [Sat, 9 Dec 2017 00:32:09 +0000 (00:32 +0000)]
Register NetBSD/x86_64 in MemorySanitizer.cpp
Summary:
Reuse the Linux new mapping as it is.
Sponsored by <The NetBSD Foundation>
Reviewers: joerg, eugenis, vitalybuka
Reviewed By: vitalybuka
Subscribers: llvm-commits, #sanitizers
Tags: #sanitizers
Differential Revision: https://reviews.llvm.org/D41022
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320219
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Evgeniy Stepanov [Sat, 9 Dec 2017 00:21:41 +0000 (00:21 +0000)]
Hardware-assisted AddressSanitizer (llvm part).
Summary:
This is LLVM instrumentation for the new HWASan tool. It is basically
a stripped down copy of ASan at this point, w/o stack or global
support. Instrumenation adds a global constructor + runtime callbacks
for every load and store.
HWASan comes with its own IR attribute.
A brief design document can be found in
clang/docs/HardwareAssistedAddressSanitizerDesign.rst (submitted earlier).
Reviewers: kcc, pcc, alekseyshl
Subscribers: srhines, mehdi_amini, mgorny, javed.absar, eraman, llvm-commits, hiraditya
Differential Revision: https://reviews.llvm.org/D40932
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320217
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Paul Robinson [Sat, 9 Dec 2017 00:17:01 +0000 (00:17 +0000)]
Fix out-of-order stepping behavior in programs with sunk instructions.
MachineSink attempts to place instructions near the basic blocks where
they are needed. Once an instruction has been sunk, its location
relative to other instructions no longer is consistent with the
original source code. In order to ensure correct stepping in the
debugger, the debug location for sunk instructions is either merged
with the insertion point or erased if the target successor block is
empty.
Originally submitted as r318679, revised to fix sanitizer failure and
improve testing.
Patch by Matthew Voss!
Differential Revision: https://reviews.llvm.org/D39933
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320216
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Adrian Prantl [Fri, 8 Dec 2017 23:32:47 +0000 (23:32 +0000)]
dwarfdump: Add support for the --diff option.
--diff Emit the output in a diff-friendly way by omitting offsets and
addresses.
<rdar://problem/
34502625>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320214
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Craig Topper [Fri, 8 Dec 2017 23:30:03 +0000 (23:30 +0000)]
[X86][Mips] Remove unused method declaration from the X86 and Mips AsmPrinters.
Both had a declaration of EmitXRayTable, but there is no method defined in either with that name. There is a emitXRayTable in the base class with a lower case 'e' and they both call that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320213
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Francis Visoiu Mistrih [Fri, 8 Dec 2017 22:53:21 +0000 (22:53 +0000)]
[CodeGen] Move printing MO_Immediate operands to MachineOperand::print
Work towards the unification of MIR and debug output by refactoring the
interfaces.
Add support for operand subreg index as an immediate to debug printing
and use ::print in the MIRPrinter.
Differential Review: https://reviews.llvm.org/D40965
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320209
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Duncan P. N. Exon Smith [Fri, 8 Dec 2017 22:42:43 +0000 (22:42 +0000)]
Revert part of "Cleanup some GraphTraits iteration code"
This reverts part of r300656, which caused a regression in
propagateMassToSuccessors by counting edges n^2 times, where n is the
number of edges from the source basic block to the same successor basic
block. The result was both incorrect and very slow to compute for large
values of n (e.g. switches with multiple cases that go to the same basic
block).
Patch by Andrew Scheidecker!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320208
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Richard Smith [Fri, 8 Dec 2017 22:32:35 +0000 (22:32 +0000)]
Avoid constructing an out-of-range value for an enumeration (which results in UB).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320206
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Abderrazek Zaafrani [Fri, 8 Dec 2017 22:04:13 +0000 (22:04 +0000)]
[AArch64] Rename AArch64VecorByElementOpt.cpp into AArch64SIMDInstrOpt.cpp to reflect the recently added features.
The name change is dicsussed in https://reviews.llvm.org/D38196
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320204
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Adrian Prantl [Fri, 8 Dec 2017 21:58:18 +0000 (21:58 +0000)]
Generalize llvm::replaceDbgDeclare and actually support the use-case that
is mentioned in the documentation (inserting a deref before the plus_uconst).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320203
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Vedant Kumar [Fri, 8 Dec 2017 21:57:28 +0000 (21:57 +0000)]
[Debugify] Add a pass to test debug info preservation
The Debugify pass synthesizes debug info for IR. It's paired with a
CheckDebugify pass which determines how much of the original debug info
is preserved. These passes make it easier to create targeted tests for
debug info preservation.
Here is the Debugify algorithm:
NextLine = 1
for (Instruction &I : M)
attach DebugLoc(NextLine++) to I
NextVar = 1
for (Instruction &I : M)
if (canAttachDebugValue(I))
attach dbg.value(NextVar++) to I
The CheckDebugify pass expects contiguous ranges of DILocations and
DILocalVariables. If it fails to find all of the expected debug info, it
prints a specific error to stderr which can be FileChecked.
This was discussed on llvm-dev in the thread:
"Passes to add/validate synthetic debug info"
Differential Revision: https://reviews.llvm.org/D40512
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320202
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Florian Hahn [Fri, 8 Dec 2017 21:49:03 +0000 (21:49 +0000)]
[CodeExtractor] Add debug locations for new call and branch instrs.
Summary:
If a partially inlined function has debug info, we have to add debug
locations to the call instruction calling the outlined function.
We use the debug location of the first instruction in the outlined
function, as the introduced call transfers control to this statement and
there is no other equivalent line in the source code.
We also use the same debug location for the branch instruction added
to jump from artificial entry block for the outlined function, which just
jumps to the first actual basic block of the outlined function.
Reviewers: davide, aprantl, rriddle, dblaikie, danielcdh, wmi
Reviewed By: aprantl, rriddle, danielcdh
Subscribers: eraman, JDevlieghere, llvm-commits
Differential Revision: https://reviews.llvm.org/D40413
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320199
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Dan Gohman [Fri, 8 Dec 2017 21:27:00 +0000 (21:27 +0000)]
[WebAssembly] Reapply r319186: "Support bitcasted function addresses with varargs."
This puts the functionality under control of a command-line option which is
off by default to avoid breaking existing setups.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320197
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Dan Gohman [Fri, 8 Dec 2017 21:18:21 +0000 (21:18 +0000)]
[WebAssemby] Re-apply r320041: "Support main functions with alternate signatures."
This includes a fix so that it doesn't transform declarations, and it
puts the functionality under control of a command-line option which is off
by default to avoid breaking existing setups.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320196
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Evandro Menezes [Fri, 8 Dec 2017 21:09:59 +0000 (21:09 +0000)]
[AArch64] Add Exynos to host detection
Differential revision: https://reviews.llvm.org/D40985
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320195
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Konstantin Zhuravlyov [Fri, 8 Dec 2017 20:52:28 +0000 (20:52 +0000)]
AMDGPU/GCN: Bring processors in sync with AMDGPUUsage
- Add gfx704
- Change bonaire to gfx704
- Remove gfx804
- Remove gfx901
- Remove gfx903
Differential Revision: https://reviews.llvm.org/D40046
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320194
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Simon Pilgrim [Fri, 8 Dec 2017 20:42:35 +0000 (20:42 +0000)]
[X86] CMOV pseudo instructions shouldn't need scheduling info as they should be lowered early
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320193
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Simon Pilgrim [Fri, 8 Dec 2017 20:31:48 +0000 (20:31 +0000)]
[X86][X87] Tag x87 load/store instructions scheduler classes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320192
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Craig Topper [Fri, 8 Dec 2017 20:10:33 +0000 (20:10 +0000)]
[X86] Teach lowering to only let through (insert_subvector (vXi1 zeros), subvec, 0) for vector sizes that have native KSHIFT support.
For narrow sizes we'll widen the zero vector and widen the insert. Then do an extract_subvector to get back down to correct size.
This allows us to remove some patterns from the isel table that had to COPY_TO_REGCLASS to an oversized register, do the shift and then COPY_TO_REGCLASS back to the narrow register. Now this is represented explicitly in the DAG.
This seems to have perturbed the register allocation in one of the tests, but the number of instructions didn't change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320190
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Simon Pilgrim [Fri, 8 Dec 2017 20:10:31 +0000 (20:10 +0000)]
[X86][X87] Tag x87 float compare instructions scheduler classes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320189
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Matt Arsenault [Fri, 8 Dec 2017 20:01:02 +0000 (20:01 +0000)]
AMDGPU: Set IntrReadMem on memtime intrinsics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320188
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Matt Arsenault [Fri, 8 Dec 2017 20:00:57 +0000 (20:00 +0000)]
AMDGPU: image_getlod and image_getresinfo do not read memory
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320187
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Matt Arsenault [Fri, 8 Dec 2017 20:00:45 +0000 (20:00 +0000)]
AMDGPU: Preserve MMO in adjustWritemask
Follow up to r319705. Currently the MMO is
produced after this in the custom inserter,
so this doesn't change anything yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320186
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Shoaib Meenai [Fri, 8 Dec 2017 19:44:45 +0000 (19:44 +0000)]
[llvm] Add install-distribution-stripped
This is identical to the install-distribution target, except that it
strips the installed binaries.
Differential Revision: https://reviews.llvm.org/D40689
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320184
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Shoaib Meenai [Fri, 8 Dec 2017 19:42:47 +0000 (19:42 +0000)]
[cmake] Only pass CMAKE_SYSROOT if non-empty
In my build environment (cmake 3.6.1 and gcc 4.8.5 on CentOS 7), having
an empty CMAKE_SYSROOT in the cache results in --sysroot="" being passed
to all compile commands, and then the compiler errors out because of the
empty sysroot. Only set CMAKE_SYSROOT if non-empty to avoid this.
Differential Revision: https://reviews.llvm.org/D40934
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320183
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Shoaib Meenai [Fri, 8 Dec 2017 19:42:46 +0000 (19:42 +0000)]
[runtimes] Add install-*-stripped targets
These should be the only remaining missing install-*-stripped targets.
They're modeled after the existing install targets.
Differential Revision: https://reviews.llvm.org/D40927
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320182
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Xinliang David Li [Fri, 8 Dec 2017 19:38:07 +0000 (19:38 +0000)]
Revert r320104: infinite loop profiling bug fix
Causes unexpected memory issue with New PM this time.
The new PM invalidates BPI but not BFI, leaving the
reference to BPI from BFI invalid.
Abandon this patch. There is a more general solution
which also handles runtime infinite loop (but not statically).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320180
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Brian M. Rzycki [Fri, 8 Dec 2017 19:36:32 +0000 (19:36 +0000)]
[JumpThreading] Minor comment cleanup. NFC. (test commit)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320179
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Simon Pilgrim [Fri, 8 Dec 2017 19:26:22 +0000 (19:26 +0000)]
[X86][MPX] Tag TSX/HLE/SGX instructions scheduler classes
Currently tagged these as system instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320177
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Konstantin Zhuravlyov [Fri, 8 Dec 2017 19:22:12 +0000 (19:22 +0000)]
AMDGPU: Report Arg's Value name in metadata if kernel_arg_name metadata is not available
Differential Revision: https://reviews.llvm.org/D40924
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320176
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Michael Trent [Fri, 8 Dec 2017 19:09:26 +0000 (19:09 +0000)]
Reverting r320166 to fix test failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320174
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Simon Pilgrim [Fri, 8 Dec 2017 19:03:42 +0000 (19:03 +0000)]
[X86][MPX] Tag MPX instructions scheduler classes
Currently tagged these as system instructions, once we have uses for them (ASAN?) and they are faster we will need to improve on this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320173
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Sanjay Patel [Fri, 8 Dec 2017 18:35:51 +0000 (18:35 +0000)]
[x86] use hasAVX2() rather than hasInt256(); NFC
These are aliases, but the thing we're checking here is that the target has
vpsllv*, not that the data type is 256-bit. Those instructions exist for
128-bit vectors too...but sadly, not for all element sizes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320170
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Simon Pilgrim [Fri, 8 Dec 2017 18:35:40 +0000 (18:35 +0000)]
[X86] Tag move immediate instructions scheduler classes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320169
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Michael Trent [Fri, 8 Dec 2017 17:51:04 +0000 (17:51 +0000)]
Updated llvm-objdump to display local relocations in Mach-O binaries
Summary:
llvm-objdump's Mach-O parser was updated in r306037 to display external
relocations for MH_KEXT_BUNDLE file types. This change extends the Macho-O
parser to display local relocations for MH_PRELOAD files. When used with
the -macho option relocations will be displayed in a historical format.
rdar://
35778019
Reviewers: enderby
Reviewed By: enderby
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D40867
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320166
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Davide Italiano [Fri, 8 Dec 2017 17:15:50 +0000 (17:15 +0000)]
[DebugInfo] Use llc instead of llc_dwarf to fix this test.
We work around the fact that some platforms add a triple when
they expand llc_dwarf in lit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320164
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Simon Pilgrim [Fri, 8 Dec 2017 16:38:41 +0000 (16:38 +0000)]
[X86][SHA] Tag SHA instructions scheduler classes
Put these under VecIMul itinerary classes for now - seems to be a good average value
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320161
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Simon Pilgrim [Fri, 8 Dec 2017 16:06:40 +0000 (16:06 +0000)]
[X86] Tag VIA PadLock crypto instructions scheduler classes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320159
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Simon Pilgrim [Fri, 8 Dec 2017 15:48:37 +0000 (15:48 +0000)]
[X86] Tag PKU/INVPCID/RDPID/SMAP/SMX/PTWRITE system instructions scheduler classes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320158
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Alexey Bataev [Fri, 8 Dec 2017 15:32:10 +0000 (15:32 +0000)]
[InstCombine] PR35354: Convert store(bitcast, load bitcast (select (Cond, &V1, &V2)) --> store (, load (select(Cond, load &V1, load &V2)))
Summary:
If we have the code like this:
```
float a, b;
a = std::max(a ,b);
```
it is converted into something like this:
```
%call = call dereferenceable(4) float* @_ZSt3maxIfERKT_S2_S2_(float* nonnull dereferenceable(4) %a.addr, float* nonnull dereferenceable(4) %b.addr)
%1 = bitcast float* %call to i32*
%2 = load i32, i32* %1, align 4
%3 = bitcast float* %a.addr to i32*
store i32 %2, i32* %3, align 4
```
After inlinning this code is converted to the next:
```
%1 = load float, float* %a.addr
%2 = load float, float* %b.addr
%cmp.i = fcmp fast olt float %1, %2
%__b.__a.i = select i1 %cmp.i, float* %a.addr, float* %b.addr
%3 = bitcast float* %__b.__a.i to i32*
%4 = load i32, i32* %3, align 4
%5 = bitcast float* %arrayidx to i32*
store i32 %4, i32* %5, align 4
```
This pattern is not recognized as minmax pattern.
Patch solves this problem by converting sequence
```
store (bitcast, (load bitcast (select ((cmp V1, V2), &V1, &V2))))
```
to a sequence
```
store (,load (select((cmp V1, V2), &V1, &V2)))
```
After this the code is recognized as minmax pattern.
Reviewers: RKSimon, spatel
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D40304
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320157
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Simon Pilgrim [Fri, 8 Dec 2017 15:19:10 +0000 (15:19 +0000)]
[X86][AVX512] Tag CLWB instruction to CLFLUSH/PREFETCH scheduler class
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320156
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Alexey Bataev [Fri, 8 Dec 2017 15:17:37 +0000 (15:17 +0000)]
[PatternMatch] Add matcher for LoadInst, NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320155
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Simon Pilgrim [Fri, 8 Dec 2017 15:17:32 +0000 (15:17 +0000)]
[X86][AVX512] Tag AVX512_512_SEXT_MASK_* instructions scheduler classes
Match VPTERNLOG which these pseudos will eventually alias to
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320154
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Tim Renouf [Fri, 8 Dec 2017 14:09:34 +0000 (14:09 +0000)]
[AMDGPU] add labels to +DumpCode output
Summary:
+DumpCode is a hack to embed disassembly in the ELF file. This commit
fixes it to include labels, to make it slightly more useful.
Reviewers: arsenm, kzhuravl
Subscribers: nhaehnle, timcorringham, dstuttard, llvm-commits, t-tye, yaxunl, wdng, kzhuravl
Differential Revision: https://reviews.llvm.org/D40169
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320146
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Max Kazantsev [Fri, 8 Dec 2017 12:54:32 +0000 (12:54 +0000)]
[NFC] Rename variable from Cond to Pred to make it more sound
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320144
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Max Kazantsev [Fri, 8 Dec 2017 12:19:45 +0000 (12:19 +0000)]
[SCEV] Fix predicate usage in computeExitLimitFromICmp
In this method, we invoke `SimplifyICmpOperands` which takes the `Cond` predicate
by reference and may change it along with `LHS` and `RHS` SCEVs. But then we invoke
`computeShiftCompareExitLimit` with Values from which the SCEVs have been derived,
these Values have not been modified while `Cond` could be.
One of possible outcomes of this is that we may falsely prove that an infinite loop ends
within some finite number of iterations.
In this patch, we save the original `Cond` and pass it along with original operands.
This logic may be removed in future once `computeShiftCompareExitLimit` works
with SCEVs instead of value operands.
Reviewed By: sanjoy
Differential Revision: https://reviews.llvm.org/D40953
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320142
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Francis Visoiu Mistrih [Fri, 8 Dec 2017 11:48:02 +0000 (11:48 +0000)]
[CodeGen] Move printing MO_MachineBasicBlock operands to MachineOperand::print
Work towards the unification of MIR and debug output by refactoring the
interfaces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320141
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Francis Visoiu Mistrih [Fri, 8 Dec 2017 11:40:06 +0000 (11:40 +0000)]
[CodeGen] Move printing MO_CImmediate operands to MachineOperand::print
Work towards the unification of MIR and debug output by refactoring the
interfaces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320140
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Pavel Labath [Fri, 8 Dec 2017 09:59:48 +0000 (09:59 +0000)]
[cmake] Make setting of CMAKE_C(XX)_COMPILER flags overridable for cross-builds
Summary:
r319898 made it possible to override these variables via the
CROSS_TOOLCHAIN_FLAGS setting, but this only worked if one explicitly
specifies these variables there. If, instead, one uses
CROSS_TOOLCHAIN_FLAGS to specify a toolchain file (as our internal
builds do, to point cmake to a checked-in toolchain), the
CMAKE_C(XX)_COMPILER flags would still win over the ones specified by
the toolchain file.
To fix is to make the mere presence of these flags overridable. I do
this by putting them as a default value for the CROSS_TOOLCHAIN_FLAGS
setting, so they can be overridden at cmake configuration time.
Reviewers: hintonda, beanz
Subscribers: bogner, llvm-commits, mgorny
Differential Revision: https://reviews.llvm.org/D40947
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320138
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Gadi Haber [Fri, 8 Dec 2017 09:48:44 +0000 (09:48 +0000)]
[X86][Haswell]: Updating the scheduling information for the Haswell subtarget.
Updated the scheduling information for the Haswell subtarget with the following changes:
Regrouped the instructions after adding appropriate load + store latencies.
Added scheduling for missing instructions such as the GATHER instrs.
The changes were made after revisiting the latencies impact of all memory uOps.
Reviewers: RKSimon, zvi, craig.topper, apilipenko
Differential Revision: https://reviews.llvm.org/D40021
Change-Id: Iaf6c1f5169add1552845a8a566af4e5a359217a7
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320137
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Igor Laevsky [Fri, 8 Dec 2017 08:53:16 +0000 (08:53 +0000)]
[FuzzMutate] Correctly insert sinks and sources around invoke instructions
Differential Revision: https://reviews.llvm.org/D40840
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320136
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Craig Topper [Fri, 8 Dec 2017 08:10:58 +0000 (08:10 +0000)]
[X86] Always consider inserting a vXi1 vector into the lsbs of a zero vector to be legal during lowering. Add isel patterns to emit shifts.
Previously we only allowed these through if the subvector came from a compare or test instruction which we would again check for during isel.
With this change we only check for the compare and test instructions during isel and have fallback patterns that emit the shifts if needed.
I noticed that in a lot of cases we don't actually see the compare during lowering and rely on an odd legalization of concat_vectors with a zero vector as the second argument. This keeps the concat_vectors around long enough for a later dag combine to expose the compare then we re-legalize the concat_vectors and catch the compare.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320134
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Abderrazek Zaafrani [Fri, 8 Dec 2017 00:58:49 +0000 (00:58 +0000)]
[AArch64] Avoid SIMD interleaved store instruction for Exynos.
Replace interleaved store instructions by equivalent and more efficient instructions based on latency cost model.
Https://reviews.llvm.org/D38196
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320123
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Derek Schuff [Fri, 8 Dec 2017 00:39:54 +0000 (00:39 +0000)]
Revert "[WebAssemby] Support main functions with alternate signatures."
This reverts commit
959e37e669b0c3cfad4cb9f1f7c9261ce9f5e9ae.
That commit doesn't handle the case where main is declared rather than defined,
in particular the even-more special case where main is a prototypeless
declaration (which is of course the one actually used by musl currently).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320121
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Craig Topper [Fri, 8 Dec 2017 00:16:09 +0000 (00:16 +0000)]
[X86] Handle alls version of vXi1 insert_vector_elt with a constant index without falling back to shuffles.
We previously only supported inserting to the LSB or MSB where it was easy to zero to perform an OR to insert.
This change effectively extracts the old value and the new value, xors them together and then xors that single bit with the correct location in the original vector. This will cancel out the old value in the first xor leaving the new value in the position.
The way I've implemented this uses 3 shifts and two xors and uses an additional register. We can avoid the additional register at the cost of another shift.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320120
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