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Reid Kleckner [Thu, 1 Nov 2018 19:11:05 +0000 (19:11 +0000)]
Remove unnecessary fallthrough annotation after unreachable
Clang's -Wimplicit-fallthrough implementation warns on this. I built
clang with GCC 7.3 in +asserts and -asserts mode, and GCC doesn't warn
on this in either configuration. I think it is unnecessary. I separated
it from the large mechanical patch (https://reviews.llvm.org/D53950) in
case I am wrong and it has to be reverted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345876
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Volkan Keles [Thu, 1 Nov 2018 19:01:53 +0000 (19:01 +0000)]
[GlobalISel] Fix a bug in LegalizeRuleSet::clampMaxNumElements
Summary:
This function was causing a crash when `MaxElements == 1` because
it was trying to create a single element vector type.
Reviewers: dsanders, aemerson, aditya_nandakumar
Reviewed By: dsanders
Subscribers: rovka, kristof.beyls, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D53734
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345875
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Simon Pilgrim [Thu, 1 Nov 2018 18:22:11 +0000 (18:22 +0000)]
[LegalizeDAG] Add generic vector CTPOP expansion (PR32655)
This patch adds support for expanding vector CTPOP instructions and removes the x86 'bitmath' lowering which replicates the same expansion.
Differential Revision: https://reviews.llvm.org/D53258
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345869
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Reid Kleckner [Thu, 1 Nov 2018 18:14:45 +0000 (18:14 +0000)]
[Hexagon] Fix MO_JumpTable const extender conversion
Previously this case fell through to unreachable, so it is clearly not
covered by any test case in LLVM. It may be dynamically unreachable, in
fact. However, if it were to run, this is what it would logically do.
The assert suggests that the intended behavior was not to allow folding
offsets from jump table indices, which makes sense.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345868
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Andrea Di Biagio [Thu, 1 Nov 2018 18:04:39 +0000 (18:04 +0000)]
[llvm-mca] Add extra counters for move elimination in view RegisterFileStatistics.
This patch teaches view RegisterFileStatistics how to report events for
optimizable register moves.
For each processor register file, view RegisterFileStatistics reports the
following extra information:
- Number of optimizable register moves
- Number of register moves eliminated
- Number of zero moves (i.e. register moves that propagate a zero)
- Max Number of moves eliminated per cycle.
Differential Revision: https://reviews.llvm.org/D53976
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345865
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Reid Kleckner [Thu, 1 Nov 2018 18:02:27 +0000 (18:02 +0000)]
[AArch64] Fix unintended fallthrough and strengthen cast
This was added in r330630. GCC's -Wimplicit-fallthrough seems to not
fire when the previous case contains a switch itself.
This fallthrough was bening because the helper function implementing the
case used dyn_cast to re-check the type of the node in question. After
fixing the fallthrough, we can strengthen the cast.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345864
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Mandeep Singh Grang [Thu, 1 Nov 2018 17:53:57 +0000 (17:53 +0000)]
Revert "[COFF, ARM64] Implement Intrinsic.sponentry for AArch64"
This reverts commit
585b6667b4712e3c7f32401e929855b3313b4ff2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345863
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Jordan Rupprecht [Thu, 1 Nov 2018 17:48:46 +0000 (17:48 +0000)]
[llvm-strip] Support --keep and --strip-all-gnu from llvm-objcopy
Summary: Add --keep and --strip-all-gnu from llvm-objcopy into llvm-strip.
Reviewers: jakehehrlich, jhenderson, alexshap
Reviewed By: jhenderson, alexshap
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D53954
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345861
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Jordan Rupprecht [Thu, 1 Nov 2018 17:36:37 +0000 (17:36 +0000)]
[llvm-objcopy] Support --{enable,disable}-deterministic-archives
Summary: ar and objcopy/strip all support configuring whether archives are written deterministically (timestamps/UIDs/GIDs/etc zero'd). This has been ported to llvm-ar (the U/D modifiers) but not yet to llvm-objcopy/strip.
Reviewers: jakehehrlich, jhenderson, alexshap
Reviewed By: jhenderson
Subscribers: ruiu, mgrang, llvm-commits
Differential Revision: https://reviews.llvm.org/D53913
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345859
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Jordan Rupprecht [Thu, 1 Nov 2018 17:26:36 +0000 (17:26 +0000)]
[llvm-objcopy] Don't apply --localize flags to common symbols
Summary:
--localize-symbol and --localize-hidden will currently localize common symbols. GNU objcopy will not localize these symbols even when explicitly requested, which seems reasonable; common symbols should always be global so they can be merged during linking.
See PR39461
Reviewers: jakehehrlich, jhenderson, alexshap, MaskRay, espindola
Reviewed By: jakehehrlich, jhenderson, alexshap, MaskRay
Subscribers: emaste, arichardson, alexshap, MaskRay, llvm-commits
Differential Revision: https://reviews.llvm.org/D53782
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345856
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Fangrui Song [Thu, 1 Nov 2018 17:20:40 +0000 (17:20 +0000)]
[llvm-objcopy] For multiclass Eq, associate help text with --name= , not with --name
Summary:
Before:
% llvm-objcopy -help
...
--weaken-symbol=symbol Mark <symbol> as weak
--weaken-symbol symbol Mark <symbol> as weak
After:
% llvm-objcopy -help
...
--weaken-symbol=symbol Mark <symbol> as weak
Reviewers: jhenderson, rupprecht, alexshap, jakehehrlich
Reviewed By: jhenderson
Subscribers: llvm-commits, kristina
Differential Revision: https://reviews.llvm.org/D53983
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345855
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Sanjay Patel [Thu, 1 Nov 2018 16:57:54 +0000 (16:57 +0000)]
[InstCombine] add test for ComputeNumSignBits on 2-input shuffle; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345852
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Cameron McInally [Thu, 1 Nov 2018 16:57:52 +0000 (16:57 +0000)]
Fix whitespace in test/Assembler/fast-math-flags.ll
Differential Revision: https://reviews.llvm.org/D53981
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345851
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Sam Parker [Thu, 1 Nov 2018 16:44:45 +0000 (16:44 +0000)]
[ARM] Attempt to fix ppc64be buildbot
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345850
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Zachary Turner [Thu, 1 Nov 2018 16:37:29 +0000 (16:37 +0000)]
[NativePDB] Get LLDB types from PDB function types.
This adds basic support for getting function signature types
into LLDB's type system, including into clang's AST. There are
a few edge cases which are not correctly handled, mostly dealing
with nested classes, but this isn't specific to functions and
apply equally to variable types. Note that no attempt has been
made yet to deal with member function types, which will happen
in subsequent patches.
Differential Revision: https://reviews.llvm.org/D53951
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345848
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Fangrui Song [Thu, 1 Nov 2018 16:02:12 +0000 (16:02 +0000)]
[llvm-objcopy] Use proper cases
Reviewers: jhenderson, alexshap, jakehehrlich, espindola, rupprecht
Reviewed By: jhenderson, rupprecht
Subscribers: emaste, arichardson, rupprecht, llvm-commits
Differential Revision: https://reviews.llvm.org/D53971
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345845
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Sanjay Patel [Thu, 1 Nov 2018 15:41:12 +0000 (15:41 +0000)]
[DAGCombiner] make sure we have a whole-number extract before trying to narrow a vector op (PR39511)
The test causes a crash because we were trying to extract v4f32 to v3f32, and the
narrowing factor was then 4/3 = 1 producing a bogus narrow type.
This should fix:
https://bugs.llvm.org/show_bug.cgi?id=39511
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345842
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Daniel Sanders [Thu, 1 Nov 2018 15:41:11 +0000 (15:41 +0000)]
[MC] Implement EmitRawText in MCNullStreamer
Summary:
This adds dummy implementation of `EmitRawText` in `MCNullStreamer`.
This fixes the behavior of `AsmPrinter` with `MCNullStreamer` on targets
on which no integrated assembler is used. An attempt to emit inline asm
on such a target would previously lead to a crash, since `AsmPrinter` does not
check for `hasRawTextSupport` in `EmitInlineAsm` and calls `EmitRawText`
anyway if integrated assembler is disabled (the behavior has changed
in D2686).
Error message printed by MCStreamer:
> EmitRawText called on an MCStreamer that doesn't support it, something
> must not be fully mc'ized
Patch by Eugene Sharygin
Reviewers: dsanders, echristo
Reviewed By: dsanders
Subscribers: eraman, llvm-commits
Differential Revision: https://reviews.llvm.org/D53938
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345841
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Sam Parker [Thu, 1 Nov 2018 15:23:42 +0000 (15:23 +0000)]
[ARM][CGP] Negative constant operand handling
While mutating instructions, we sign extended negative constant
operands for binary operators that can safely overflow. This was to
allow instructions, such as add nuw i8 %a, -2, to still be able to
perform a subtraction. However, the code to handle constants doesn't
take into consideration that instructions, such as sub nuw i8 -2, %a,
require the i8 -2 to be converted into i32 254.
This is a relatively simple fix, but I've taken the time to
reorganise the code a bit - mainly that instructions that can be
promoted are cached and splitting up the Mutate function.
Differential Revision: https://reviews.llvm.org/D53972
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345840
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Zachary Turner [Thu, 1 Nov 2018 15:07:32 +0000 (15:07 +0000)]
[MS Demangler] Expose the Demangler AST publicly.
LLDB would like to use this in order to build a clang AST from
a mangled name.
This is NFC otherwise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345837
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Simon Pilgrim [Thu, 1 Nov 2018 14:57:07 +0000 (14:57 +0000)]
[X86][X86FixupLEA] Rename processInstructionForSLM to processInstructionForSlowLEA (NFCI)
The function isn't SLM specific (its driven by the FeatureSlowLEA flag).
Minor tidyup prior to PR38225.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345836
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Sanjay Patel [Thu, 1 Nov 2018 14:07:39 +0000 (14:07 +0000)]
[InstSimplify] fold icmp based on range of abs/nabs (2nd try)
This is retrying the fold from rL345717
(reverted at rL347780)
...with a fix for the miscompile
demonstrated by PR39510:
https://bugs.llvm.org/show_bug.cgi?id=39510
Original commit message:
This is a fix for PR39475:
https://bugs.llvm.org/show_bug.cgi?id=39475
We managed to get some of these patterns using computeKnownBits in https://reviews.llvm.org/D47041, but that
can't be used for nabs(). Instead, put in some range-based logic, so we can fold
both abs/nabs with icmp with a constant value.
Alive proofs:
https://rise4fun.com/Alive/21r
Name: abs_nsw_is_positive
%cmp = icmp slt i32 %x, 0
%negx = sub nsw i32 0, %x
%abs = select i1 %cmp, i32 %negx, i32 %x
%r = icmp sgt i32 %abs, -1
=>
%r = i1 true
Name: abs_nsw_is_not_negative
%cmp = icmp slt i32 %x, 0
%negx = sub nsw i32 0, %x
%abs = select i1 %cmp, i32 %negx, i32 %x
%r = icmp slt i32 %abs, 0
=>
%r = i1 false
Name: nabs_is_negative_or_0
%cmp = icmp slt i32 %x, 0
%negx = sub i32 0, %x
%nabs = select i1 %cmp, i32 %x, i32 %negx
%r = icmp slt i32 %nabs, 1
=>
%r = i1 true
Name: nabs_is_not_over_0
%cmp = icmp slt i32 %x, 0
%negx = sub i32 0, %x
%nabs = select i1 %cmp, i32 %x, i32 %negx
%r = icmp sgt i32 %nabs, 0
=>
%r = i1 false
Differential Revision: https://reviews.llvm.org/D53844
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345832
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Sanjay Patel [Thu, 1 Nov 2018 14:03:22 +0000 (14:03 +0000)]
[InstSimplify] add tests for icmp fold bug (PR39510); NFC
Verify that set intersection/subset are not confused.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345831
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Aleksandar Beserminji [Thu, 1 Nov 2018 13:57:54 +0000 (13:57 +0000)]
[mips][micromips] Fix JmpLink to TargetExternalSymbol
When matching MipsISD::JmpLink t9, TargetExternalSymbol:i32'...',
wrong JALR16_MM is selected. This patch adds missing pattern for
JmpLink, so that JAL instruction is selected.
Differential Revision: https://reviews.llvm.org/D53366
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345830
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Benjamin Kramer [Thu, 1 Nov 2018 13:55:59 +0000 (13:55 +0000)]
[ADT] Clean up SparseBitVector copying and make it moveable
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345829
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Chad Rosier [Thu, 1 Nov 2018 13:45:16 +0000 (13:45 +0000)]
[AArch64] Add support for ARMv8.4 in Saphira.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345827
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Simon Pilgrim [Thu, 1 Nov 2018 11:52:09 +0000 (11:52 +0000)]
[X86][SSE] Move 2-input limit up from getFauxShuffleMask to resolveTargetShuffleInputs (reapplied)
Reapplying an updated version of rL345395 (reverted in rL345451), now the issues noticed in PR39483 have been fixed.
This patch allows resolveTargetShuffleInputs to remove UNDEF inputs from cases where we have more than 2 inputs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345824
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Max Kazantsev [Thu, 1 Nov 2018 10:16:06 +0000 (10:16 +0000)]
[NFC] Specialize public API of ICFLoopSafetyInfo for insertions and removals
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345822
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Stefan Maksimovic [Thu, 1 Nov 2018 10:10:42 +0000 (10:10 +0000)]
[Mips] Conditionally remove successor block
In MipsBranchExpansion::splitMBB, upon splitting
a block with two direct branches, remove the successor
of the newly created block (which inherits successors from
the original block) which is pointed to by the last
branch in the original block only if the targets of two
branches differ.
This is to fix the failing test when ran with
-verify-machineinstrs enabled.
Differential Revision: https://reviews.llvm.org/D53756
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345821
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Max Kazantsev [Thu, 1 Nov 2018 09:42:50 +0000 (09:42 +0000)]
[NFC] Reorganize code to prepare it for more transforms
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345820
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Jonas Paulsson [Thu, 1 Nov 2018 09:05:32 +0000 (09:05 +0000)]
[SystemZ::TTI] Recognize the higher cost of scalar i1 -> fp conversion
Scalar i1 to fp conversions are done with a branch sequence, so it should
have a higher cost.
Review: Ulrich Weigand
https://reviews.llvm.org/D53924
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345818
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Jonas Paulsson [Thu, 1 Nov 2018 09:01:51 +0000 (09:01 +0000)]
[SystemZ::TTI] Accurate costs for i1->double vector conversions
This factors out a new method getBoolVecToIntConversionCost() containing the
code for vector sext/zext of i1, in order to reuse it for i1 to double vector
conversions.
Review: Ulrich Weigand
https://reviews.llvm.org/D53923
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345817
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Max Kazantsev [Thu, 1 Nov 2018 06:47:01 +0000 (06:47 +0000)]
[IndVars] Smart hard uses detection
When rewriting loop exit values, IndVars considers this transform not profitable if
the loop instruction has a loop user which it believes cannot be optimized away.
In current implementation only calls that immediately use the instruction are considered
as such.
This patch extends the definition of "hard" users to any side-effecting instructions
(which usually cannot be optimized away from the loop) and also allows handling
of not just immediate users, but use chains.
Differentlai Revision: https://reviews.llvm.org/D51584
Reviewed By: etherzhhb
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345814
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Max Kazantsev [Thu, 1 Nov 2018 06:18:27 +0000 (06:18 +0000)]
[SCEV] Avoid redundant computations when doing AddRec merge
When we calculate a product of 2 AddRecs, we end up making quite massive
computations to deduce the operands of resulting AddRec. This process can
be optimized by computing all args of intermediate sum and then calling
`getAddExpr` once rather than calling `getAddExpr` with intermediate
result every time a new argument is computed.
Differential Revision: https://reviews.llvm.org/D53189
Reviewed By: rtereshin
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345813
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Zachary Turner [Thu, 1 Nov 2018 04:02:41 +0000 (04:02 +0000)]
[CodeView] Emit the correct TypeIndex for std::nullptr_t.
The TypeIndex used by cl.exe is 0x103, which indicates a SimpleTypeMode
of NearPointer (note the absence of the bitness, normally pointers use a
mode of NearPointer32 or NearPointer64) and a SimpleTypeKind of void.
So this is basically a void*, but without a specified size, which makes
sense given how std::nullptr_t is defined.
clang-cl was actually not emitting *anything* for this. Instead, when we
encountered std::nullptr_t in a DIType, we would actually just emit a
TypeIndex of 0, which is obviously wrong.
std::nullptr_t in DWARF is represented as a DW_TAG_unspecified_type with
a name of "decltype(nullptr)", so we add that logic along with a test,
as well as an update to the dumping code so that we no longer print
void* when dumping 0x103 (which would previously treat Void/NearPointer
no differently than Void/NearPointer64).
Differential Revision: https://reviews.llvm.org/D53957
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345811
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Li Jia He [Thu, 1 Nov 2018 02:35:17 +0000 (02:35 +0000)]
[PowerPC] Support constraint 'wi' in asm
From the gcc manual, we can see that the specific limit of wi inline asm is “FP or VSX register to hold 64-bit integers for VSX insns or NO_REGS”. The link is https://gcc.gnu.org/onlinedocs/gcc-8.2.0/gcc/Machine-Constraints.html#Machine-Constraints. We should accept this constraint.
Reviewed By: jsji
Differential Revision: https://reviews.llvm.org/D53265
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345810
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Matthias Braun [Thu, 1 Nov 2018 00:38:01 +0000 (00:38 +0000)]
X86: Consistently declare pass initializers in X86.h; NFC
This avoids declaring them twice: in X86TargetMachine.cpp and the file
implementing the pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345801
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Dean Michael Berris [Thu, 1 Nov 2018 00:18:52 +0000 (00:18 +0000)]
[XRay] Add CPU ID in Custom Event FDR Records
Summary:
This change cuts across compiler-rt and llvm, to increment the FDR log
version number to 4, and include the CPU ID in the custom event records.
This is a step towards allowing us to change the `llvm::xray::Trace`
object to start representing both custom and typed events in the stream
of records. Follow-on changes will allow us to change the kinds of
records we're presenting in the stream of traces, to incorporate the
data in custom/typed events.
A follow-on change will handle the typed event case, where it may not
fit within the 15-byte buffer for metadata records.
This work is part of the larger effort to enable writing analysis and
processing tools using a common in-memory representation of the events
found in traces. The work will focus on porting existing tools in LLVM
to use the common representation and informing the design of a
library/framework for expressing trace event analysis as C++ programs.
Reviewers: mboerger, eizan
Subscribers: hiraditya, mgrang, llvm-commits
Differential Revision: https://reviews.llvm.org/D53920
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345798
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Thomas Lively [Thu, 1 Nov 2018 00:01:02 +0000 (00:01 +0000)]
[WebAssembly] Lower vselect
Reviewers: aheejin, dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D53630
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345797
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Thomas Lively [Wed, 31 Oct 2018 23:58:20 +0000 (23:58 +0000)]
[WebAssembly] Process p2align operands for SIMD loads and stores
Reviewers: aheejin, dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D53886
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345795
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Thomas Lively [Wed, 31 Oct 2018 23:50:53 +0000 (23:50 +0000)]
[WebAssembly] Handle vector IMPLICIT_DEFs.
Summary:
Also reduce the test case for implicit defs and test it with all
register classes.
Reviewers: aheejin, dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D53855
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345794
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Jonas Devlieghere [Wed, 31 Oct 2018 23:36:10 +0000 (23:36 +0000)]
[VFS] Add support for "no_push" to VFS recursive iterators.
The "regular" file system has a useful feature that makes it possible to
stop recursing when using the recursive directory iterators. This
functionality was missing for the VFS recursive iterator and this patch
adds that.
Differential revision: https://reviews.llvm.org/D53465
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345793
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Mandeep Singh Grang [Wed, 31 Oct 2018 23:16:20 +0000 (23:16 +0000)]
[COFF, ARM64] Implement Intrinsic.sponentry for AArch64
Summary: This patch adds Intrinsic.sponentry. This intrinsic is required to correctly support setjmp for AArch64 Windows platform.
Reviewers: mgrang, TomTan, rnk, compnerd, mstorsjo, efriedma
Reviewed By: efriedma
Subscribers: majnemer, chrib, javed.absar, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D53673
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345791
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Eli Friedman [Wed, 31 Oct 2018 23:03:58 +0000 (23:03 +0000)]
[IR] Allow increasing the alignment of dso-local globals.
I think this is the actual important property; the previous visibility
check was an approximation.
Differential Revision: https://reviews.llvm.org/D53852
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345790
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George Burgess IV [Wed, 31 Oct 2018 22:45:31 +0000 (22:45 +0000)]
[InlineCost] Remove a dead constant; NFC
My `grep`-fu indicates that this hasn't been used for years. It also no
longer makes much sense to have this flavor of penalty in general, since
a call to a noreturn should mean that we're in a BB that's terminated by
`unreachable`. That case is accounted for by
CallAnalyzer::allowSizeGrowth.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345789
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Evandro Menezes [Wed, 31 Oct 2018 21:56:49 +0000 (21:56 +0000)]
[AArch64] Sort switch cases (NFC)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345786
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Craig Topper [Wed, 31 Oct 2018 21:53:24 +0000 (21:53 +0000)]
Revert r345165 "[X86] Bring back the MOV64r0 pseudo instruction"
Google is reporting regressions on some benchmarks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345785
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Eli Friedman [Wed, 31 Oct 2018 21:45:48 +0000 (21:45 +0000)]
[ARM] Add missing pseudo-instruction for Thumb1 RSBS.
Shows up rarely for 64-bit arithmetic, more frequently for the compare
patterns added in r325323.
Differential Revision: https://reviews.llvm.org/D53848
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345782
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Sanjay Patel [Wed, 31 Oct 2018 21:37:40 +0000 (21:37 +0000)]
revert rL345717 : [InstSimplify] fold icmp based on range of abs/nabs
This can miscompile as shown in PR39510:
https://bugs.llvm.org/show_bug.cgi?id=39510
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345780
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Stanislav Mekhanoshin [Wed, 31 Oct 2018 21:24:30 +0000 (21:24 +0000)]
Check shouldReduceLoadWidth from SimplifySetCC
SimplifySetCC could shrink a load without checking for
profitability or legality of such shink with a target.
Added checks to prevent shrinking of aligned scalar loads
in AMDGPU below dword as scalar engine does not support it.
Differential Revision: https://reviews.llvm.org/D53846
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345778
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Sanjay Patel [Wed, 31 Oct 2018 21:11:59 +0000 (21:11 +0000)]
[ValueTracking] add tests for fmin/fmax; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345777
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Wolfgang Pieb [Wed, 31 Oct 2018 21:05:51 +0000 (21:05 +0000)]
[DWARF][NFC] Refactor a function to return Optional<> instead of bool
Minor refactor of DWARFUnit::getStringOffsetSectionItem().
Differential Revision: https://reviews.llvm.org/D53948
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345776
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Richard Smith [Wed, 31 Oct 2018 20:38:41 +0000 (20:38 +0000)]
Remove unused internal template parameter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345773
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Daniel Sanders [Wed, 31 Oct 2018 20:05:32 +0000 (20:05 +0000)]
[adt] SparseBitVector::test() should be const
Summary:
Re-worked SparseBitVector's most-recently-used-word caching (CurrElementIter)
such that SparseBitVector::test() can be made const. This came up when
attempting to test individual bits in a SparseBitVector which was a member of a
const object.
The cached iterator has no bearing on the externally visible state, it's merely
a performance optimization. Therefore it has been made mutable and
FindLowerBound() has been split into a const and non-const function
(FindLowerBound/FindLowerBoundConst) for the const/non-const
interfaces.
Reviewers: rtereshin
Reviewed By: rtereshin
Subscribers: rtereshin, dexonsmith, kristina, llvm-commits
Differential Revision: https://reviews.llvm.org/D53447
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345772
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Sanjay Patel [Wed, 31 Oct 2018 20:03:27 +0000 (20:03 +0000)]
[InstCombine] add tests for fmin/fmax pattern matching failure; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345771
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Scott Linder [Wed, 31 Oct 2018 19:57:36 +0000 (19:57 +0000)]
[SelectionDAG] Handle constant range [0,1) in lowerRangeToAssertZExt
lowerRangeToAssertZExt currently relies on something like EarlyCSE having
eliminated the constant range [0,1). At -O0 this leads to an assert.
Differential Revision: https://reviews.llvm.org/D53888
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345770
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Daniel Sanders [Wed, 31 Oct 2018 19:49:37 +0000 (19:49 +0000)]
[globalisel] Add comments indicating the operand order
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345769
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Scott Linder [Wed, 31 Oct 2018 18:54:06 +0000 (18:54 +0000)]
[AMDGPU] Remove FeatureVGPRSpilling
This feature is only relevant to shaders, and is no longer used. When disabled,
lowering of reserved registers for shaders causes a compiler crash.
Remove the feature and add a test for compilation of shaders at OptNone.
Differential Revision: https://reviews.llvm.org/D53829
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345763
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Craig Topper [Wed, 31 Oct 2018 18:46:15 +0000 (18:46 +0000)]
[SelectionDAGISel] Suppress a -Wunused-but-set-variable warning in release builds. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345761
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Simon Pilgrim [Wed, 31 Oct 2018 18:19:52 +0000 (18:19 +0000)]
Fix comment typo. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345758
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Sanjay Patel [Wed, 31 Oct 2018 18:17:51 +0000 (18:17 +0000)]
[InstCombine] regenerate test checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345757
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Simon Pilgrim [Wed, 31 Oct 2018 18:14:14 +0000 (18:14 +0000)]
[SelectionDAG] SelectionDAGLegalize::ExpandBITREVERSE - ensure we use ShiftTy
We should be using the getShiftAmountTy value type for shift amounts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345756
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Daniel Sanders [Wed, 31 Oct 2018 17:58:47 +0000 (17:58 +0000)]
[globalisel][irtranslator] Fix test from r345743 on non-asserts builds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345754
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Sanjay Patel [Wed, 31 Oct 2018 17:55:40 +0000 (17:55 +0000)]
[InstCombine] add tests for fcmp with -0.0; NFC
From IEEE754: "Comparisons shall ignore the sign of zero (so +0 = −0)."
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345752
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Volkan Keles [Wed, 31 Oct 2018 17:50:52 +0000 (17:50 +0000)]
[InstCombine] Combine nested min/max intrinsics with constants
Reviewers: arsenm, spatel
Reviewed By: spatel
Subscribers: lebedev.ri, wdng, llvm-commits
Differential Revision: https://reviews.llvm.org/D53774
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345751
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Matt Davis [Wed, 31 Oct 2018 17:47:25 +0000 (17:47 +0000)]
[llvm-mca] Remove the verb 'assemble' from a few options in help. NFC.
* MCA does not assemble anything.
* Ran clang-format.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345750
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Nicolai Haehnle [Wed, 31 Oct 2018 17:46:21 +0000 (17:46 +0000)]
TableGen: Fix ASAN error
Summary:
As a bonus, this arguably improves the code by making it simpler.
gcc 8 on Ubuntu 18.10 reports the following:
==39667==ERROR: AddressSanitizer: stack-use-after-scope on address 0x7fffffff8ae0 at pc 0x555555dbfc68 bp 0x7fffffff8760 sp 0x7fffffff8750
WRITE of size 8 at 0x7fffffff8ae0 thread T0
#0 0x555555dbfc67 in std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> >::_Alloc_hider::_Alloc_hider(char*, std::allocator<char>&&) /usr/include/c++/8/bits/basic_string.h:149
#1 0x555555dbfc67 in std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> >::basic_string(std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> >&&) /usr/include/c++/8/bits/basic_string.h:542
#2 0x555555dbfc67 in std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> > std::operator+<char, std::char_traits<char>, std::allocator<char> >(char const*, std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> >&&) /usr/include/c++/8/bits/basic_string.h:6009
#3 0x555555dbfc67 in searchableFieldType /home/nha/amd/build/san/llvm-src/utils/TableGen/SearchableTableEmitter.cpp:168
(...)
Address 0x7fffffff8ae0 is located in stack of thread T0 at offset 864 in frame
#0 0x555555dbef3f in searchableFieldType /home/nha/amd/build/san/llvm-src/utils/TableGen/SearchableTableEmitter.cpp:148
Reviewers: fhahn, simon_tatham, kparzysz
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D53931
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345749
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Daniel Sanders [Wed, 31 Oct 2018 17:31:23 +0000 (17:31 +0000)]
[globalisel][irtranslator] Verify that DILocations aren't lost in translation
Summary:
Also fix a couple bugs where DILocations are lost. EntryBuilder wasn't passing
on debug locations for PHI's, constants, GLOBAL_VALUE, etc.
Reviewers: aprantl, vsk, bogner, aditya_nandakumar, volkan, rtereshin, aemerson
Reviewed By: aemerson
Subscribers: aemerson, rovka, kristof.beyls, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D53740
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345743
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Matthias Braun [Wed, 31 Oct 2018 17:18:41 +0000 (17:18 +0000)]
MachineModuleInfo: Initialize DbgInfoAvailable depending on debug_cus existing
Before this patch DbgInfoAvailable was set to true in
DwarfDebug::beginModule() or CodeViewDebug::CodeViewDebug(). This made
MIR testing weird since passes would suddenly stop dealing with debug
info just because we stopped the pipeline before the debug printers.
This patch changes the logic to initialize DbgInfoAvailable based on the
fact that debug_compile_units exist in the llvm Module. The debug
printers may then override it with false in case of debug printing being
disabled.
Differential Revision: https://reviews.llvm.org/D53885
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345740
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Sanjay Patel [Wed, 31 Oct 2018 16:34:43 +0000 (16:34 +0000)]
[InstCombine] refactor fabs+fcmp fold; NFC
Also, remove/replace/minimize/enhance the tests for this fold.
The code drops FMF, so it needs more tests and at least 1 fix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345734
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Krzysztof Parzyszek [Wed, 31 Oct 2018 15:54:31 +0000 (15:54 +0000)]
[Hexagon] Make sure not to use GP-relative addressing with PIC
Make sure that -relocation-model=pic prevents use of GP-relative
addressing modes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345731
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Andrea Di Biagio [Wed, 31 Oct 2018 15:53:28 +0000 (15:53 +0000)]
[llvm-mca] Remove namespace prefixes made redundant by r345612. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345730
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Sanjay Patel [Wed, 31 Oct 2018 15:35:46 +0000 (15:35 +0000)]
[InstSimplify] fold 'fcmp nnan ult X, 0.0' when X is not negative
This is the inverted case for the transform added with D53874 / rL345725.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345728
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Sanjay Patel [Wed, 31 Oct 2018 15:31:45 +0000 (15:31 +0000)]
[InstCombine] add assertion that InstSimplify has folded a fabs+fcmp; NFC
The 'OLT' case was updated at rL266175, so I assume it was just an
oversight that 'UGE' was not included because that patch handled
both predicates in InstSimplify.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345727
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Sanjay Patel [Wed, 31 Oct 2018 14:57:23 +0000 (14:57 +0000)]
[InstSimplify] fold 'fcmp nnan oge X, 0.0' when X is not negative
This re-raises some of the open questions about how to apply and use fast-math-flags in IR from PR38086:
https://bugs.llvm.org/show_bug.cgi?id=38086
...but given the current implementation (no FMF on casts), this is likely the only way to predicate the
transform.
This is part of solving PR39475:
https://bugs.llvm.org/show_bug.cgi?id=39475
Differential Revision: https://reviews.llvm.org/D53874
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345725
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Fedor Sergeev [Wed, 31 Oct 2018 14:33:14 +0000 (14:33 +0000)]
[LoopUnroll] allow customization for new-pass-manager version of LoopUnroll
Unlike its legacy counterpart new pass manager's LoopUnrollPass does
not provide any means to select which flavors of unroll to run
(runtime, peeling, partial), relying on global defaults.
In some cases having ability to run a restricted LoopUnroll that
does more than LoopFullUnroll is needed.
Introduced LoopUnrollOptions to select optional unroll behaviors.
Added 'unroll<peeling>' to PassRegistry mainly for the sake of testing.
Reviewers: chandlerc, tejohnson
Differential Revision: https://reviews.llvm.org/D53440
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345723
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Sanjay Patel [Wed, 31 Oct 2018 14:29:21 +0000 (14:29 +0000)]
[InstSimplify] add tests for fcmp and known positive; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345722
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David Bolvansky [Wed, 31 Oct 2018 14:18:57 +0000 (14:18 +0000)]
[DAGCombiner] Fold 0 div/rem X to 0
Reviewers: RKSimon, spatel, javed.absar, craig.topper, t.p.northover
Reviewed By: RKSimon
Subscribers: craig.topper, llvm-commits
Differential Revision: https://reviews.llvm.org/D52504
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345721
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Nicolai Haehnle [Wed, 31 Oct 2018 13:27:08 +0000 (13:27 +0000)]
AMDGPU: Rewrite SILowerI1Copies to always stay on SALU
Summary:
Instead of writing boolean values temporarily into 32-bit VGPRs
if they are involved in PHIs or are observed from outside a loop,
we use bitwise masking operations to combine lane masks in a way
that is consistent with wave control flow.
Move SIFixSGPRCopies to before this pass, since that pass
incorrectly attempts to move SGPR phis to VGPRs.
This should recover most of the code quality that was lost with
the bug fix in "AMDGPU: Remove PHI loop condition optimization".
There are still some relevant cases where code quality could be
improved, in particular:
- We often introduce redundant masks with EXEC. Ideally, we'd
have a generic computeKnownBits-like analysis to determine
whether masks are already masked by EXEC, so we can avoid this
masking both here and when lowering uniform control flow.
- The criterion we use to determine whether a def is observed
from outside a loop is conservative: it doesn't check whether
(loop) branch conditions are uniform.
Change-Id: Ibabdb373a7510e426b90deef00f5e16c5d56e64b
Reviewers: arsenm, rampitec, tpr
Subscribers: kzhuravl, jvesely, wdng, mgorny, yaxunl, dstuttard, t-tye, eraman, llvm-commits
Differential Revision: https://reviews.llvm.org/D53496
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345719
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Nicolai Haehnle [Wed, 31 Oct 2018 13:26:48 +0000 (13:26 +0000)]
AMDGPU: Remove PHI loop condition optimization
Summary:
The optimization to early break out of loops if all threads are dead was
never fully implemented.
But the PHI node analyzing is actually causing a number of problems, so
remove all the extra code for it.
(This does actually regress code quality in a few places because it
ends up relying more heavily on phi's of i1, which we don't do a
great job with. However, since it fixes real bugs in the wild, we
should take this change. I have some prototype changes to improve
i1 lowering in general -- not just for control flow -- which should
help recover the code quality, I just need to make those changes
fit for general consumption. -- Nicolai)
Change-Id: I6fc6c6c8961857ac6009fcfb9f7e5e48dc23fbb1
Patch-by: Christian König <christian.koenig@amd.com>
Reviewers: arsenm, rampitec, tpr
Subscribers: kzhuravl, jvesely, wdng, yaxunl, dstuttard, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D53359
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345718
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Sanjay Patel [Wed, 31 Oct 2018 13:25:10 +0000 (13:25 +0000)]
[InstSimplify] fold icmp based on range of abs/nabs
This is a fix for PR39475:
https://bugs.llvm.org/show_bug.cgi?id=39475
We managed to get some of these patterns using computeKnownBits in D47041, but that
can't be used for nabs(). Instead, put in some range-based logic, so we can fold
both abs/nabs with icmp with a constant value.
Alive proofs:
https://rise4fun.com/Alive/21r
Name: abs_nsw_is_positive
%cmp = icmp slt i32 %x, 0
%negx = sub nsw i32 0, %x
%abs = select i1 %cmp, i32 %negx, i32 %x
%r = icmp sgt i32 %abs, -1
=>
%r = i1 true
Name: abs_nsw_is_not_negative
%cmp = icmp slt i32 %x, 0
%negx = sub nsw i32 0, %x
%abs = select i1 %cmp, i32 %negx, i32 %x
%r = icmp slt i32 %abs, 0
=>
%r = i1 false
Name: nabs_is_negative_or_0
%cmp = icmp slt i32 %x, 0
%negx = sub i32 0, %x
%nabs = select i1 %cmp, i32 %x, i32 %negx
%r = icmp slt i32 %nabs, 1
=>
%r = i1 true
Name: nabs_is_not_over_0
%cmp = icmp slt i32 %x, 0
%negx = sub i32 0, %x
%nabs = select i1 %cmp, i32 %x, i32 %negx
%r = icmp sgt i32 %nabs, 0
=>
%r = i1 false
Differential Revision: https://reviews.llvm.org/D53844
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345717
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Andrea Di Biagio [Wed, 31 Oct 2018 12:28:05 +0000 (12:28 +0000)]
[tblgen][PredicateExpander] Add the ability to describe more complex constraints on instruction operands.
Before this patch, class PredicateExpander only knew how to expand simple
predicates that performed checks on instruction operands.
In particular, the new scheduling predicate syntax was not rich enough to
express checks like this one:
Foo(MI->getOperand(0).getImm()) == ExpectedVal;
Here, the immediate operand value at index zero is passed in input to function
Foo, and ExpectedVal is compared against the value returned by function Foo.
While this predicate pattern doesn't show up in any X86 model, it shows up in
other upstream targets. So, being able to support those predicates is
fundamental if we want to be able to modernize all the scheduling models
upstream.
With this patch, we allow users to specify if a register/immediate operand value
needs to be passed in input to a function as part of the predicate check. Now,
register/immediate operand checks all derive from base class CheckOperandBase.
This patch also changes where TIIPredicate definitions are expanded by the
instructon info emitter. Before, definitions were expanded in class
XXXGenInstrInfo (where XXX is a target name).
With the introduction of this new syntax, we may want to have TIIPredicates
expanded directly in XXXInstrInfo. That is because functions used by the new
operand predicates may only exist in the derived class (i.e. XXXInstrInfo).
This patch is a non functional change for the existing scheduling models.
In future, we will be able to use this richer syntax to better describe complex
scheduling predicates, and expose them to llvm-mca.
Differential Revision: https://reviews.llvm.org/D53880
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345714
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Max Kazantsev [Wed, 31 Oct 2018 11:28:23 +0000 (11:28 +0000)]
[NFC] Add tests for loop-simplifycfg for further development
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345713
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Florian Hahn [Wed, 31 Oct 2018 11:00:48 +0000 (11:00 +0000)]
[ADT] Remove illegal comparison of singular iterators from SmallSetTest
This removes the assertion that a copy of a moved-from SmallSetIterator
equals the original, which is illegal due to SmallSetIterator including
an instance of a standard `std::set` iterator.
C++ [iterator.requirements.general] states that comparing singular
iterators has undefined result:
> Iterators can also have singular values that are not associated with
> any sequence. [...] Results of most expressions are undefined for
> singular values; the only exceptions are destroying an iterator that
> holds a singular value, the assignment of a non-singular value to an
> iterator that holds a singular value, and, for iterators that satisfy
> the Cpp17DefaultConstructible requirements, using a value-initialized
> iterator as the source of a copy or move operation.
This assertion triggers the following error in the GNU C++ Library in
debug mode under EXPENSIVE_CHECKS:
/usr/include/c++/8.2.1/debug/safe_iterator.h:518:
Error: attempt to compare a singular iterator to a singular iterator.
Objects involved in the operation:
iterator "lhs" @ 0x0x7fff86420670 {
state = singular;
}
iterator "rhs" @ 0x0x7fff86420640 {
state = singular;
}
Patch by Eugene Sharygin.
Reviewers: fhahn, dblaikie, chandlerc
Reviewed By: fhahn, dblaikie
Differential Revision: https://reviews.llvm.org/D53793
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345712
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Neil Henning [Wed, 31 Oct 2018 10:34:48 +0000 (10:34 +0000)]
[AMDGPU] support image load/store a16
Our a16 support was only enabled for sample/gather and buffer
load/store, but not for image load/store operations (which take an i16
as the pixel index rather than a half).
Fix our isel lowering and add test cases to prove it out.
Differential Revision: https://reviews.llvm.org/D53750
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345710
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Max Kazantsev [Wed, 31 Oct 2018 10:30:50 +0000 (10:30 +0000)]
[IndVars] Strengthen restricton in rewriteLoopExitValues
For some unclear reason rewriteLoopExitValues considers recalculation
after the loop profitable if it has some "soft uses" outside the loop (i.e. any
use other than call and return), even if we have proved that it has a user inside
the loop which we think will not be optimized away.
There is no existing unit test that would explain this. This patch provides an
example when rematerialisation of exit value is not profitable but it passes
this check due to presence of a "soft use" outside the loop.
It makes no sense to recalculate value on exit if we are going to compute it
due to some irremovable within the loop. This patch disallows applying this
transform in the described situation.
Differential Revision: https://reviews.llvm.org/D51581
Reviewed By: etherzhhb
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345708
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Dorit Nuzman [Wed, 31 Oct 2018 09:57:56 +0000 (09:57 +0000)]
[LV] Support vectorization of interleave-groups that require an epilog under
optsize using masked wide loads
Under Opt for Size, the vectorizer does not vectorize interleave-groups that
have gaps at the end of the group (such as a loop that reads only the even
elements: a[2*i]) because that implies that we'll require a scalar epilogue
(which is not allowed under Opt for Size). This patch extends the support for
masked-interleave-groups (introduced by D53011 for conditional accesses) to
also cover the case of gaps in a group of loads; Targets that enable the
masked-interleave-group feature don't have to invalidate interleave-groups of
loads with gaps; they could now use masked wide-loads and shuffles (if that's
what the cost model selects).
Reviewers: Ayal, hsaito, dcaballe, fhahn
Reviewed By: Ayal
Differential Revision: https://reviews.llvm.org/D53668
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345705
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Kristina Brooks [Wed, 31 Oct 2018 09:35:25 +0000 (09:35 +0000)]
[llvm-objdump] Mark syms/t flags as NotHidden. NFC.
Slight improvement to help output of llvm-objdump that exposes the
shorter -t flag for -syms instead of it being hidden away.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345704
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Kristina Brooks [Wed, 31 Oct 2018 09:34:08 +0000 (09:34 +0000)]
[llvm-objdump] Add --reloc alias for -r (PR39407)
This addresses PR39407 (https://bugs.llvm.org/show_bug.cgi?id=39407)
improving compatibility with GNU binutils counterparts.
Reviewed By: kristina
Patch by Higuoxing (Xing).
Differential Revision: https://reviews.llvm.org/D53804
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345703
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Alexander Potapenko [Wed, 31 Oct 2018 09:32:47 +0000 (09:32 +0000)]
[MSan] another take at instrumenting inline assembly - now with calls
Turns out it's not always possible to figure out whether an asm()
statement argument points to a valid memory region.
One example would be per-CPU objects in the Linux kernel, for which the
addresses are calculated using the FS register and a small offset in the
.data..percpu section.
To avoid pulling all sorts of checks into the instrumentation, we replace
actual checking/unpoisoning code with calls to
msan_instrument_asm_load(ptr, size) and
msan_instrument_asm_store(ptr, size) functions in the runtime.
This patch doesn't implement the runtime hooks in compiler-rt, as there's
been no demand in assembly instrumentation for userspace apps so far.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345702
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Sanjin Sijaric [Wed, 31 Oct 2018 09:27:01 +0000 (09:27 +0000)]
[ARM64] [Windows] Exception handling support in frame lowering
Emit pseudo instructions indicating unwind codes corresponding to each
instruction inside the prologue/epilogue. These are used by the MCLayer to
populate the .xdata section.
Differential Revision: https://reviews.llvm.org/D50288
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345701
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Martin Storsjo [Wed, 31 Oct 2018 08:14:09 +0000 (08:14 +0000)]
[AArch64] Mark condition flags and x16/x17 as clobbered when calling __chkstk
This is similar to SVN r311061 for ARM.
Differential Revision: https://reviews.llvm.org/D53878
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345698
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Kristina Brooks [Wed, 31 Oct 2018 05:45:01 +0000 (05:45 +0000)]
[llvm-objdump] support '--syms' as an alias of -t
This adds support for '--syms' as an alias of '-t' for llvm-objdump,
fixing PR39406 (https://bugs.llvm.org/show_bug.cgi?id=39406).
Patch by Higuoxing (Xing).
Differential Revision: https://reviews.llvm.org/D53803
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345697
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Lang Hames [Wed, 31 Oct 2018 05:16:14 +0000 (05:16 +0000)]
[ORC] Fix hex printing of uint64_t values.
A plain "%x" format string will drop the high 32-bits. Use the PRIx64 macro
instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345696
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Matthias Braun [Wed, 31 Oct 2018 01:58:00 +0000 (01:58 +0000)]
2nd attempt to fix ambiguities because of ADL
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345690
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Matthias Braun [Wed, 31 Oct 2018 01:30:41 +0000 (01:30 +0000)]
Try to fix ambiguities with C++17 headers in unittest
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345689
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Wolfgang Pieb [Wed, 31 Oct 2018 01:12:58 +0000 (01:12 +0000)]
[DWARF] Revert r345546: Refactor range list extraction and dumping
This patch caused some internal tests to break which are being investigated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345687
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Fangrui Song [Wed, 31 Oct 2018 00:31:07 +0000 (00:31 +0000)]
[llvm-objcopy] Delete a redundant override whose base is empty
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345684
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Fangrui Song [Wed, 31 Oct 2018 00:31:06 +0000 (00:31 +0000)]
Use llvm::any_of instead std::any_of. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345683
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Fangrui Song [Wed, 31 Oct 2018 00:31:06 +0000 (00:31 +0000)]
Use the container form llvm::sort(C)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345682
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