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Andrea Di Biagio [Wed, 31 Oct 2018 12:28:05 +0000 (12:28 +0000)]
[tblgen][PredicateExpander] Add the ability to describe more complex constraints on instruction operands.
Before this patch, class PredicateExpander only knew how to expand simple
predicates that performed checks on instruction operands.
In particular, the new scheduling predicate syntax was not rich enough to
express checks like this one:
Foo(MI->getOperand(0).getImm()) == ExpectedVal;
Here, the immediate operand value at index zero is passed in input to function
Foo, and ExpectedVal is compared against the value returned by function Foo.
While this predicate pattern doesn't show up in any X86 model, it shows up in
other upstream targets. So, being able to support those predicates is
fundamental if we want to be able to modernize all the scheduling models
upstream.
With this patch, we allow users to specify if a register/immediate operand value
needs to be passed in input to a function as part of the predicate check. Now,
register/immediate operand checks all derive from base class CheckOperandBase.
This patch also changes where TIIPredicate definitions are expanded by the
instructon info emitter. Before, definitions were expanded in class
XXXGenInstrInfo (where XXX is a target name).
With the introduction of this new syntax, we may want to have TIIPredicates
expanded directly in XXXInstrInfo. That is because functions used by the new
operand predicates may only exist in the derived class (i.e. XXXInstrInfo).
This patch is a non functional change for the existing scheduling models.
In future, we will be able to use this richer syntax to better describe complex
scheduling predicates, and expose them to llvm-mca.
Differential Revision: https://reviews.llvm.org/D53880
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345714
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Max Kazantsev [Wed, 31 Oct 2018 11:28:23 +0000 (11:28 +0000)]
[NFC] Add tests for loop-simplifycfg for further development
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345713
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Florian Hahn [Wed, 31 Oct 2018 11:00:48 +0000 (11:00 +0000)]
[ADT] Remove illegal comparison of singular iterators from SmallSetTest
This removes the assertion that a copy of a moved-from SmallSetIterator
equals the original, which is illegal due to SmallSetIterator including
an instance of a standard `std::set` iterator.
C++ [iterator.requirements.general] states that comparing singular
iterators has undefined result:
> Iterators can also have singular values that are not associated with
> any sequence. [...] Results of most expressions are undefined for
> singular values; the only exceptions are destroying an iterator that
> holds a singular value, the assignment of a non-singular value to an
> iterator that holds a singular value, and, for iterators that satisfy
> the Cpp17DefaultConstructible requirements, using a value-initialized
> iterator as the source of a copy or move operation.
This assertion triggers the following error in the GNU C++ Library in
debug mode under EXPENSIVE_CHECKS:
/usr/include/c++/8.2.1/debug/safe_iterator.h:518:
Error: attempt to compare a singular iterator to a singular iterator.
Objects involved in the operation:
iterator "lhs" @ 0x0x7fff86420670 {
state = singular;
}
iterator "rhs" @ 0x0x7fff86420640 {
state = singular;
}
Patch by Eugene Sharygin.
Reviewers: fhahn, dblaikie, chandlerc
Reviewed By: fhahn, dblaikie
Differential Revision: https://reviews.llvm.org/D53793
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345712
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Neil Henning [Wed, 31 Oct 2018 10:34:48 +0000 (10:34 +0000)]
[AMDGPU] support image load/store a16
Our a16 support was only enabled for sample/gather and buffer
load/store, but not for image load/store operations (which take an i16
as the pixel index rather than a half).
Fix our isel lowering and add test cases to prove it out.
Differential Revision: https://reviews.llvm.org/D53750
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345710
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Max Kazantsev [Wed, 31 Oct 2018 10:30:50 +0000 (10:30 +0000)]
[IndVars] Strengthen restricton in rewriteLoopExitValues
For some unclear reason rewriteLoopExitValues considers recalculation
after the loop profitable if it has some "soft uses" outside the loop (i.e. any
use other than call and return), even if we have proved that it has a user inside
the loop which we think will not be optimized away.
There is no existing unit test that would explain this. This patch provides an
example when rematerialisation of exit value is not profitable but it passes
this check due to presence of a "soft use" outside the loop.
It makes no sense to recalculate value on exit if we are going to compute it
due to some irremovable within the loop. This patch disallows applying this
transform in the described situation.
Differential Revision: https://reviews.llvm.org/D51581
Reviewed By: etherzhhb
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345708
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Dorit Nuzman [Wed, 31 Oct 2018 09:57:56 +0000 (09:57 +0000)]
[LV] Support vectorization of interleave-groups that require an epilog under
optsize using masked wide loads
Under Opt for Size, the vectorizer does not vectorize interleave-groups that
have gaps at the end of the group (such as a loop that reads only the even
elements: a[2*i]) because that implies that we'll require a scalar epilogue
(which is not allowed under Opt for Size). This patch extends the support for
masked-interleave-groups (introduced by D53011 for conditional accesses) to
also cover the case of gaps in a group of loads; Targets that enable the
masked-interleave-group feature don't have to invalidate interleave-groups of
loads with gaps; they could now use masked wide-loads and shuffles (if that's
what the cost model selects).
Reviewers: Ayal, hsaito, dcaballe, fhahn
Reviewed By: Ayal
Differential Revision: https://reviews.llvm.org/D53668
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345705
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Kristina Brooks [Wed, 31 Oct 2018 09:35:25 +0000 (09:35 +0000)]
[llvm-objdump] Mark syms/t flags as NotHidden. NFC.
Slight improvement to help output of llvm-objdump that exposes the
shorter -t flag for -syms instead of it being hidden away.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345704
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Kristina Brooks [Wed, 31 Oct 2018 09:34:08 +0000 (09:34 +0000)]
[llvm-objdump] Add --reloc alias for -r (PR39407)
This addresses PR39407 (https://bugs.llvm.org/show_bug.cgi?id=39407)
improving compatibility with GNU binutils counterparts.
Reviewed By: kristina
Patch by Higuoxing (Xing).
Differential Revision: https://reviews.llvm.org/D53804
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345703
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Alexander Potapenko [Wed, 31 Oct 2018 09:32:47 +0000 (09:32 +0000)]
[MSan] another take at instrumenting inline assembly - now with calls
Turns out it's not always possible to figure out whether an asm()
statement argument points to a valid memory region.
One example would be per-CPU objects in the Linux kernel, for which the
addresses are calculated using the FS register and a small offset in the
.data..percpu section.
To avoid pulling all sorts of checks into the instrumentation, we replace
actual checking/unpoisoning code with calls to
msan_instrument_asm_load(ptr, size) and
msan_instrument_asm_store(ptr, size) functions in the runtime.
This patch doesn't implement the runtime hooks in compiler-rt, as there's
been no demand in assembly instrumentation for userspace apps so far.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345702
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Sanjin Sijaric [Wed, 31 Oct 2018 09:27:01 +0000 (09:27 +0000)]
[ARM64] [Windows] Exception handling support in frame lowering
Emit pseudo instructions indicating unwind codes corresponding to each
instruction inside the prologue/epilogue. These are used by the MCLayer to
populate the .xdata section.
Differential Revision: https://reviews.llvm.org/D50288
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345701
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Martin Storsjo [Wed, 31 Oct 2018 08:14:09 +0000 (08:14 +0000)]
[AArch64] Mark condition flags and x16/x17 as clobbered when calling __chkstk
This is similar to SVN r311061 for ARM.
Differential Revision: https://reviews.llvm.org/D53878
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345698
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Kristina Brooks [Wed, 31 Oct 2018 05:45:01 +0000 (05:45 +0000)]
[llvm-objdump] support '--syms' as an alias of -t
This adds support for '--syms' as an alias of '-t' for llvm-objdump,
fixing PR39406 (https://bugs.llvm.org/show_bug.cgi?id=39406).
Patch by Higuoxing (Xing).
Differential Revision: https://reviews.llvm.org/D53803
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345697
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Lang Hames [Wed, 31 Oct 2018 05:16:14 +0000 (05:16 +0000)]
[ORC] Fix hex printing of uint64_t values.
A plain "%x" format string will drop the high 32-bits. Use the PRIx64 macro
instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345696
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Matthias Braun [Wed, 31 Oct 2018 01:58:00 +0000 (01:58 +0000)]
2nd attempt to fix ambiguities because of ADL
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345690
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Matthias Braun [Wed, 31 Oct 2018 01:30:41 +0000 (01:30 +0000)]
Try to fix ambiguities with C++17 headers in unittest
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345689
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Wolfgang Pieb [Wed, 31 Oct 2018 01:12:58 +0000 (01:12 +0000)]
[DWARF] Revert r345546: Refactor range list extraction and dumping
This patch caused some internal tests to break which are being investigated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345687
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Fangrui Song [Wed, 31 Oct 2018 00:31:07 +0000 (00:31 +0000)]
[llvm-objcopy] Delete a redundant override whose base is empty
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345684
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Fangrui Song [Wed, 31 Oct 2018 00:31:06 +0000 (00:31 +0000)]
Use llvm::any_of instead std::any_of. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345683
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Fangrui Song [Wed, 31 Oct 2018 00:31:06 +0000 (00:31 +0000)]
Use the container form llvm::sort(C)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345682
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Fangrui Song [Wed, 31 Oct 2018 00:31:02 +0000 (00:31 +0000)]
Don't duplicate function/class name at the beginning of the comment. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345681
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Matthias Braun [Wed, 31 Oct 2018 00:23:23 +0000 (00:23 +0000)]
ADT/STLExtras: Introduce llvm::empty; NFC
This is modeled after C++17 std::empty().
Differential Revision: https://reviews.llvm.org/D53909
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345679
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Saleem Abdulrasool [Tue, 30 Oct 2018 23:45:27 +0000 (23:45 +0000)]
DWARFVerifier: make the verifier more comprehensive for objects
Make the code do what was mentioned in the comment: only skip the CU types.
This enables the lexical blocks to be verified as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345675
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Matthias Braun [Tue, 30 Oct 2018 23:28:27 +0000 (23:28 +0000)]
MachineOperand/MIParser: Do not print debug-use flag, infer it
The debug-use flag must be set exactly for uses on DBG_VALUEs. This is
so obvious that it can be trivially inferred while parsing. This will
reduce noise when printing while omitting an information that has little
value to the user.
The parser will keep recognizing the flag for compatibility with old
`.mir` files.
Differential Revision: https://reviews.llvm.org/D53903
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345671
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David Bolvansky [Tue, 30 Oct 2018 22:08:13 +0000 (22:08 +0000)]
[ARM][NFC] Make tests immune to better div optimizations
Summary: Related to D52504
Reviewers: spatel
Reviewed By: spatel
Subscribers: javed.absar, kristof.beyls, chrib, llvm-commits
Differential Revision: https://reviews.llvm.org/D53901
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345665
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Konstantin Zhuravlyov [Tue, 30 Oct 2018 22:02:40 +0000 (22:02 +0000)]
Revert r345542: AMDGPU: Enable code object v3 by default
It breaks mesa.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345662
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Cameron McInally [Tue, 30 Oct 2018 21:01:29 +0000 (21:01 +0000)]
[FPEnv] [FPEnv] Add constrained intrinsics for MAXNUM and MINNUM
Differential Revision: https://reviews.llvm.org/D53216
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345650
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Sanjay Patel [Tue, 30 Oct 2018 20:52:25 +0000 (20:52 +0000)]
[InstCombine] use 'match' to reduce code; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345647
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Quentin Colombet [Tue, 30 Oct 2018 20:51:04 +0000 (20:51 +0000)]
[InstCombine] Teach the move free before null test opti how to deal with noop casts
InstCombine features an optimization that essentially replaces:
if (a)
free(a)
into:
free(a)
Right now, this optimization is gated by the minsize attribute and therefore
we only perform it if we can prove that we are going to be able to eliminate
the branch and the destination block.
However when casts are involved the optimization would fail to apply, because
the optimization was not smart enough to realize that it is possible to also
move the casts away from the destination block and that is harmless to the
performance since they are just noops.
E.g.,
foo(int *a)
if (a)
free((char*)a)
Wouldn't be optimized by instcombine, because
- We would refuse to hoist the `bitcast i32* %a to i8` in the source block
- We would fail to see that `bitcast i32* %a to i8` and %a are the same value.
This patch fixes both these problems:
- It teaches the pattern matching of the comparison how to look
through casts.
- It checks that whether the additional instruction in the destination block
can be hoisted and are harmless performance-wise.
- It hoists all the code of the destination block in the source block.
Differential Revision: D53356
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345644
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Sanjay Patel [Tue, 30 Oct 2018 20:46:23 +0000 (20:46 +0000)]
[x86] try to make test immune to better div optimization; NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345642
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Mandeep Singh Grang [Tue, 30 Oct 2018 20:46:10 +0000 (20:46 +0000)]
[COFF, ARM64] Make sure to forward arguments from vararg to musttail vararg
Summary:
Thunk functions in Windows are varag functions that call a musttail function
to pass the arguments after the fixup is done. We need to make sure that we
forward the arguments from the caller vararg to the callee vararg function.
This is the same mechanism that is used for Windows on X86.
Reviewers: ssijaric, eli.friedman, TomTan, mgrang, mstorsjo, rnk, compnerd, efriedma
Reviewed By: efriedma
Subscribers: efriedma, kristof.beyls, chrib, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D53843
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345641
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Sanjay Patel [Tue, 30 Oct 2018 20:44:54 +0000 (20:44 +0000)]
[x86] try to make test immune to better div optimization; NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345640
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Sanjay Patel [Tue, 30 Oct 2018 20:42:03 +0000 (20:42 +0000)]
[x86] try to make test immune to better div optimization; NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345639
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Craig Topper [Tue, 30 Oct 2018 20:33:58 +0000 (20:33 +0000)]
[ScalarizeMaskedMemIntrin] Limit the scope of some variables that are only used inside loops.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345638
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Bjorn Pettersson [Tue, 30 Oct 2018 20:16:39 +0000 (20:16 +0000)]
[DAGCombiner] Fix for big endian in ForwardStoreValueToDirectLoad
Summary:
Normalize the offset for endianess before checking
if the store cover the load in ForwardStoreValueToDirectLoad.
Without this we missed out on some optimizations for big
endian targets. If for example having a 4 bytes store followed
by a 1 byte load, loading the least significant byte from the
store, the STCoversLD check would fail (see @test4 in
test/CodeGen/AArch64/load-store-forwarding.ll).
This patch also fixes a problem seen in an out-of-tree target.
The target has i40 as a legal type, it is big endian,
and the StoreSize for i40 is 48 bits. So when normalizing
the offset for endianess we need to take the StoreSize into
account (assuming that padding added when storing into
a larger StoreSize always is added at the most significant
end).
Reviewers: niravd
Reviewed By: niravd
Subscribers: javed.absar, kristof.beyls, llvm-commits, uabelho
Differential Revision: https://reviews.llvm.org/D53776
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345636
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Eli Friedman [Tue, 30 Oct 2018 19:24:51 +0000 (19:24 +0000)]
[AArch64] [Windows] SEH opcodes should be scheduling boundaries.
Prevents the post-RA scheduler from modifying the prologue sequences
emitting by frame lowering. This is roughly similar to what we do for
other targets: TargetInstrInfo::isSchedulingBoundary checks
isPosition(), which checks for CFI_INSTRUCTION.
isSEHInstruction is taken from D50288; it'll land with whatever patch
lands first.
Differential Revision: https://reviews.llvm.org/D53851
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345634
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David Greene [Tue, 30 Oct 2018 19:17:51 +0000 (19:17 +0000)]
[AArch64] Create proper memoperand for multi-vector stores
Re-apply r345315 with testcase fixes.
Include all of the store's source vector operands when creating the
MachineMemOperand. Previously, we were missing the first operand,
making the store size seem smaller than it really is.
Differential Revision: https://reviews.llvm.org/D52816
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345631
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Craig Topper [Tue, 30 Oct 2018 18:48:42 +0000 (18:48 +0000)]
[X86] In lowerVectorShuffleAsBroadcast, make peeking through CONCAT_VECTORS work correctly if we already walked through a bitcast that changed the element size.
The CONCAT_VECTORS case was using the original mask element count to determine how to adjust the broadcast index. But if we looked through a bitcast the original mask size doesn't tell us anything about the concat_vectors.
This patch switchs to using the concat_vectors input element count directly instead.
Differential Revision: https://reviews.llvm.org/D53823
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345626
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Calixte Denizet [Tue, 30 Oct 2018 18:41:31 +0000 (18:41 +0000)]
[GCOV] Function counters are wrong when on one line
Summary:
After commit https://reviews.llvm.org/rL344228, the function definitions have a counter but when on one line the counter is wrong (e.g. void foo() { })
I added a test in: https://reviews.llvm.org/D53601
Reviewers: marco-c
Reviewed By: marco-c
Subscribers: llvm-commits, sylvestre.ledru
Differential Revision: https://reviews.llvm.org/D53600
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345624
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Nirav Dave [Tue, 30 Oct 2018 18:26:43 +0000 (18:26 +0000)]
[DAG] Add const variants for BaseIndexOffset functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345623
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Zachary Turner [Tue, 30 Oct 2018 18:25:38 +0000 (18:25 +0000)]
Fix printing bug in pdb2yaml.
We were using the wrong enum table when mapping enum values
to strings for public symbol flags.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345622
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Jonas Devlieghere [Tue, 30 Oct 2018 18:25:28 +0000 (18:25 +0000)]
[DebugInfo] Define base function on DWARFDie reverse iterators
This defines member function base on the specialization of
std::reverse_iterator for DWARFDie::iterator as required by C++
[reverse.iter.conv].
This fixes unit test DWARFDebugInfoTest.cpp under EXPENSIVE_CHECKS which
currently can't be built due to GNU C++ Library calling this member
function in debug mode.
This fixes https://llvm.org/PR38785
Patch by: Eugene Sharygin
Differential revision: https://reviews.llvm.org/D53792
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345621
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Ulrich Weigand [Tue, 30 Oct 2018 18:20:59 +0000 (18:20 +0000)]
[SystemZ] Simplify LRV/STRV ISD nodes
The LRV and STRV nodes carry an extra operand to indicate the
type of the memory access. This is redundant, since the nodes
are actually of class MemIntrinsicNode and therefore hold that
same information already as MemoryVT.
NFC intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345618
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Simon Pilgrim [Tue, 30 Oct 2018 18:10:02 +0000 (18:10 +0000)]
[TTI] Fix uses of SK_ExtractSubvector shuffle costs (PR39368)
Correct costings of SK_ExtractSubvector requires the SubTy argument to indicate the type/size of the extracted subvector.
Unlike the rest of the shuffle kinds this means that the main Ty argument represents the source vector type not the destination!
I've done my best to fix a number of vectorizer uses:
SLP - the reduction epilogue costs should be using a SK_PermuteSingleSrc shuffle as these all occur at the hardware vector width - we're not extracting (illegal) subvector types. This is causing the cost model diffs as SK_ExtractSubvector costs are poorly handled and tend to just return 1 at the moment.
LV - I'm not clear on what the SK_ExtractSubvector should represents for recurrences - I've used a <1 x ?> subvector extraction as that seems to match the VF delta.
Differential Revision: https://reviews.llvm.org/D53573
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345617
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Volkan Keles [Tue, 30 Oct 2018 17:51:14 +0000 (17:51 +0000)]
[InstCombine] Add preliminary tests for nested min/max combines. NFC
Summary: As requested in D53774.
Reviewers: spatel
Reviewed By: spatel
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D53875
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345616
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Sanjay Patel [Tue, 30 Oct 2018 16:58:43 +0000 (16:58 +0000)]
[InstSimplify] add tests for fcmp folds; NFC
This is part of a problem noted in PR39475:
https://bugs.llvm.org/show_bug.cgi?id=39475
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345615
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Jordan Rupprecht [Tue, 30 Oct 2018 16:23:38 +0000 (16:23 +0000)]
[llvm-objcopy] Fix --keep-global-symbol/--globalize-symbol for undefined symbols.
Summary: --keep-global-symbol and --globalize-symbol don't make sense for undefined symbols, so it should be ignored for those symbols. This matches GNU objcopy behavior.
Reviewers: jhenderson, alexshap, jakehehrlich, espindola
Reviewed By: jhenderson, jakehehrlich
Subscribers: emaste, arichardson, llvm-commits
Differential Revision: https://reviews.llvm.org/D53733
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345614
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Sanjay Patel [Tue, 30 Oct 2018 16:21:56 +0000 (16:21 +0000)]
[InstCombine] use getFltSemantics() instead of duplicating it; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345613
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Fangrui Song [Tue, 30 Oct 2018 15:56:08 +0000 (15:56 +0000)]
[llvm-mca] Move namespace mca inside llvm::
Summary: This allows to remove `using namespace llvm;` in those *.cpp files
When we want to revisit the decision (everything resides in llvm::mca::*) in the future, we can move things to a nested namespace of llvm::mca::, to conceptually make them separate from the rest of llvm::mca::*
Reviewers: andreadb, mattd
Reviewed By: andreadb
Subscribers: javed.absar, tschuett, gbedwell, llvm-commits
Differential Revision: https://reviews.llvm.org/D53407
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345612
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Sanjay Patel [Tue, 30 Oct 2018 15:26:39 +0000 (15:26 +0000)]
[InstCombine] try to turn shuffle into insertelement
shuffle (insert ?, Scalar, IndexC), V1, Mask --> insert V1, Scalar, IndexC'
The motivating case is at least a couple of steps away: I noticed that
SLPVectorizer does not analyze shuffles as well as sequences of
insert/extract in PR34724:
https://bugs.llvm.org/show_bug.cgi?id=34724
...so SLP may fail to vectorize when source code has shuffles to start
with or instcombine has converted insert/extract to shuffles.
Independent of that, an insertelement is always a simpler op for IR
analysis vs. a shuffle, so we should transform to insert when possible.
I don't think there's any codegen concern here - if a target can't insert
a scalar directly to some fixed element in a vector (x86?), then this
should get expanded to the insert+shuffle that we started with.
Differential Revision: https://reviews.llvm.org/D53507
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345607
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Jonas Paulsson [Tue, 30 Oct 2018 15:04:40 +0000 (15:04 +0000)]
[SchedModel] Fix for read advance cycles with implicit pseudo operands.
The SchedModel allows the addition of ReadAdvances to express that certain
operands of the instructions are needed at a later point than the others.
RegAlloc may add pseudo operands that are not part of the instruction
descriptor, and therefore cannot have any read advance entries. This meant
that in some cases the desired read advance was nullified by such a pseudo
operand, which still had the original latency.
This patch fixes this by making sure that such pseudo operands get a zero
latency during DAG construction.
Review: Matthias Braun, Ulrich Weigand.
https://reviews.llvm.org/D49671
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345606
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Jonas Paulsson [Tue, 30 Oct 2018 14:34:15 +0000 (14:34 +0000)]
[LoopVectorizer] Fix for cost values of memory accesses.
This commit is a combination of two patches:
* "Fix in getScalarizationOverhead()"
If target returns false in TTI.prefersVectorizedAddressing(), it means the
address registers will not need to be extracted. Therefore, there should
be no operands scalarization overhead for a load instruction.
* "Don't pass the instruction pointer from getMemInstScalarizationCost."
Since VF is always > 1, this is a cost query for an instruction in the
vectorized loop and it should not be evaluated within the scalar
context of the instruction.
Review: Ulrich Weigand, Hal Finkel
https://reviews.llvm.org/D52351
https://reviews.llvm.org/D52417
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345603
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Sanjay Patel [Tue, 30 Oct 2018 14:14:34 +0000 (14:14 +0000)]
[DAGCombiner] narrow vector binops when extraction is cheap
Narrowing vector binops came up in the demanded bits discussion in D52912.
I don't think we're going to be able to do this transform in IR as a canonicalization
because of the risk of creating unsupported widths for vector ops, but we already have
a DAG TLI hook to allow what I was hoping for: isExtractSubvectorCheap(). This is
currently enabled for x86, ARM, and AArch64 (although only x86 has existing regression
test diffs).
This is artificially limited to not look through bitcasts because there are so many
test diffs already, but that's marked with a TODO and is a small follow-up.
Differential Revision: https://reviews.llvm.org/D53784
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345602
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Diogo N. Sampaio [Tue, 30 Oct 2018 13:59:21 +0000 (13:59 +0000)]
[FIX][AArch64] Add support for UDF instruction
Fix: Simplify test files from rL345581 failing
in windows bots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345601
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Sanjay Patel [Tue, 30 Oct 2018 13:47:19 +0000 (13:47 +0000)]
[SelectionDAG] fix build warning for mismatched signs in compare; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345598
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Jonas Paulsson [Tue, 30 Oct 2018 13:41:03 +0000 (13:41 +0000)]
[SystemZ] Improve isFoldableLoad() for Sub, SDiv and UDiv.
Sub, SDiv and UDiv are not commutative, so only the RHS operand can fold a
load. This patch adds a check for this.
Review: Ulrich Weigand
https://reviews.llvm.org/D53791
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345596
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Francis Visoiu Mistrih [Tue, 30 Oct 2018 12:20:17 +0000 (12:20 +0000)]
[X86] Re-enable the machine verifier after fixing more tests
Was disabled again in r345528. Hopefully this the bots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345593
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Francis Visoiu Mistrih [Tue, 30 Oct 2018 12:07:18 +0000 (12:07 +0000)]
[llc] Error out when -print-machineinstrs is used with an unknown pass
We used to assert instead of reporting an error.
PR39494
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345589
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James Henderson [Tue, 30 Oct 2018 11:52:47 +0000 (11:52 +0000)]
[llvm-size] Reject unknown radix values
This addresses https://bugs.llvm.org/show_bug.cgi?id=39403 by making
-radix an enumeration option with 8, 10, and 16 as the only accepted
values.
Reviewed by: jhenderson, MaskRay
Differential Revision: https://reviews.llvm.org/D53799
Patch by Eugene Sharygin
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345588
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Diogo N. Sampaio [Tue, 30 Oct 2018 11:39:33 +0000 (11:39 +0000)]
[FIX][AArch64] Add support for UDF instruction
Fix wrong test files submited
in rL345581
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345587
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Nicola Zaghen [Tue, 30 Oct 2018 11:15:04 +0000 (11:15 +0000)]
[SROA] Use offset sizes from the DataLayout instead of the pointer siezes.
This fixes an assertion when constant folding a GEP when the part of the offset
was in i32 (IndexSize, as per DataLayout) and part in the i64 (PointerSize) in
the newly created test case.
Differential Revision: https://reviews.llvm.org/D52609
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345585
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Roman Lebedev [Tue, 30 Oct 2018 11:12:34 +0000 (11:12 +0000)]
[X86][BMI1] X86DAGToDAGISel: select BEXTR from x & (-1 >> (32 - y)) pattern
Summary:
The final pattern.
There is no test changes:
* We are looking for the pattern with one-use of it's mask,
* If the mask is one-use, D48768 will unfold it into pattern d.
* Thus, the tests have extra-use on the mask.
* Thus, only the BMI2 BZHI can be tested, and it already worked.
* So there is no BMI1 test coverage, we just assume it works since it uses the same codepath.
Reviewers: craig.topper, RKSimon
Reviewed By: RKSimon
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D53575
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345584
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Roman Lebedev [Tue, 30 Oct 2018 11:12:29 +0000 (11:12 +0000)]
[X86] Add extra-uses on the mask of pattern c of extract-{low,}bits.ll tests
Summary:
Because of the D48768, that pattern is always unfolded into pattern d,
thus we had no test coverage.
Reviewers: RKSimon, craig.topper
Reviewed By: craig.topper
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D53574
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345583
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Diogo N. Sampaio [Tue, 30 Oct 2018 11:06:50 +0000 (11:06 +0000)]
[AArch64] Add support for UDF instruction
Summary: Add support for AArch64 UDF instruction.
UDF - Permanently Undefined generates an Undefined
Instruction exception (ESR_ELx.EC =
0b000000).
Reviewers: DavidSpickett, javed.absar, t.p.northover
Reviewed By: javed.absar
Subscribers: nhaehnle, kristof.beyls
Differential Revision: https://reviews.llvm.org/D53319
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345581
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Simon Pilgrim [Tue, 30 Oct 2018 10:32:11 +0000 (10:32 +0000)]
[SelectionDAG] Add FoldBUILD_VECTOR to simplify new BUILD_VECTOR nodes
Similar to FoldCONCAT_VECTORS, this patch adds FoldBUILD_VECTOR to simplify cases that can avoid the creation of the BUILD_VECTOR - if all the operands are UNDEF or if the BUILD_VECTOR simplifies to a copy.
This exposed an assumption in some AMDGPU code that getBuildVector was guaranteed to be a BUILD_VECTOR node that I've tried to handle.
Differential Revision: https://reviews.llvm.org/D53760
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345578
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David Bolvansky [Tue, 30 Oct 2018 09:07:22 +0000 (09:07 +0000)]
[DAGCombiner] Improve X div/rem Y fold if single bit element type
Summary: Tests by @spatel, thanks
Reviewers: spatel, RKSimon
Reviewed By: spatel
Subscribers: sdardis, atanasyan, llvm-commits, spatel
Differential Revision: https://reviews.llvm.org/D52668
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345575
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Craig Topper [Tue, 30 Oct 2018 03:27:15 +0000 (03:27 +0000)]
[LegalizeTypes] Teach PromoteIntRes_BITCAST to better handle a bitcast with vector output type and a vector input type that needs to be widened
Summary: Previously if we had a bitcast vector output type that needs promotion and a vector input type that needs widening we would just do a stack store and load to handle the conversion. We can do a little better if we can widen the bitcast to a legal vector type the same size as the widened input type. Then we can do the bitcast between this widened type and the widened input type. Afterwards we can extract_subvector back to the original output and any_extend that. Type legalization will then circle back and handle promotion of the extract_subvector and the any_extend will just be removed. This will avoid going through the stack and allows us to remove a custom version of this legalization from X86.
Reviewers: efriedma, RKSimon
Reviewed By: efriedma
Subscribers: javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D53229
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345567
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Craig Topper [Tue, 30 Oct 2018 03:27:13 +0000 (03:27 +0000)]
[AArch64] Add test case for D53229. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345566
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Craig Topper [Tue, 30 Oct 2018 03:27:12 +0000 (03:27 +0000)]
[X86] Cleanup the code in LowerFABSorFNEG and LowerFCOPYSIGN a little. NFC
Use SelectionDAG::EVTToAPFloatSemantics. Make the LogicVT calculation in LowerFABSorFNEG similar to LowerFCOPYSIGN. Use APInt::getSignedMaxValue instead of ~APInt::getSignMask.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345565
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Craig Topper [Tue, 30 Oct 2018 03:27:11 +0000 (03:27 +0000)]
[X86] Stop changing f128 fand/for/fxor to v2i64.
The additional patterns don't cost us much and it seems better than changing element widths.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345564
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Matt Arsenault [Tue, 30 Oct 2018 01:37:59 +0000 (01:37 +0000)]
AMDGPU: Remove custom BUILD_VECTOR combine
This was looping in a testcase and removing it
now slightly improves a test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345560
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Matt Arsenault [Tue, 30 Oct 2018 01:33:14 +0000 (01:33 +0000)]
AMDGPU: Use scavengeRegisterBackwards
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345559
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Matt Arsenault [Tue, 30 Oct 2018 01:12:12 +0000 (01:12 +0000)]
Remove dead declaration
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345555
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Matt Arsenault [Tue, 30 Oct 2018 01:11:52 +0000 (01:11 +0000)]
Fix typos in comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345554
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Matt Arsenault [Tue, 30 Oct 2018 01:11:31 +0000 (01:11 +0000)]
Pass TRI to printReg
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345553
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Reid Kleckner [Mon, 29 Oct 2018 22:38:13 +0000 (22:38 +0000)]
Remove unneeded friend declarations that clang-cl warns on
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345549
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Alina Sbirlea [Mon, 29 Oct 2018 22:25:59 +0000 (22:25 +0000)]
[AliasSetTracker] Cleanup addPointer interface. [NFCI]
Summary:
Attempting to simplify the addPointer interface.
Currently there's code decomposing a MemoryLocation into (Ptr, Size, AAMDNodes) only to recreate the MemoryLocation inside the call.
Reviewers: reames, mkazantsev
Subscribers: sanjoy, jlebar, llvm-commits
Differential Revision: https://reviews.llvm.org/D53836
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345548
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Wolfgang Pieb [Mon, 29 Oct 2018 22:16:47 +0000 (22:16 +0000)]
[DWARF][NFC] Refactor range list extraction and dumping
The purpose of this patch is twofold:
- Fold pre-DWARF v5 functionality into v5 to eliminate the need for 2 different
versions of range list handling. We get rid of DWARFDebugRangelist{.cpp,.h}.
- Templatize the handling of range list tables so that location list handling
can take advantage of it as well. Location list and range list tables have the
same basic layout.
A non-NFC version of this patch was previously submitted with r342218, but it caused
errors with some TSan tests. This patch has no functional changes. The difference to
the non-NFC patch is that there are no changes to rangelist dumping in this patch.
Differential Revision: https://reviews.llvm.org/D53545
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345546
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Alexander Shaposhnikov [Mon, 29 Oct 2018 21:22:58 +0000 (21:22 +0000)]
[llvm-objcopy] Move elf-specific code into subfolder
In this diff the elf-specific code is moved into the subfolder ELF
(and factored out from llvm-objcopy.cpp).
Test plan: make check-all
Differential revision: https://reviews.llvm.org/D53790
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345544
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Erich Keane [Mon, 29 Oct 2018 21:21:55 +0000 (21:21 +0000)]
Add parens to fix incorrect assert check.
&& has higher priority than ||, so this assert works really oddly. Add
parens to match the programmer's intent.
Change-Id: I3abe1361ee0694462190c5015779db664012f3d4
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345543
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Konstantin Zhuravlyov [Mon, 29 Oct 2018 21:07:27 +0000 (21:07 +0000)]
AMDGPU: Enable code object v3 by default
Differential Revision: https://reviews.llvm.org/D53525
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345542
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Sanjay Patel [Mon, 29 Oct 2018 21:05:41 +0000 (21:05 +0000)]
[InstSimplify] add tests for abs/nabs+icmp folding; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345541
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Fedor Sergeev [Mon, 29 Oct 2018 20:38:23 +0000 (20:38 +0000)]
[LoopUnroll] NFC. Factor out runtime-loop.ll common test behavior.
Adding COMMON prefix to get common part handled there.
Needed to simplify test changes for D53440.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345538
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Jessica Paquette [Mon, 29 Oct 2018 20:27:07 +0000 (20:27 +0000)]
[MachineOutliner] Inherit target features from parent function
If a function has target features, it may contain instructions that aren't
represented in the default set of instructions. If the outliner pulls out one
of these instructions, and the function doesn't have the right attributes
attached, we'll run into an LLVM error explaining that the target doesn't
support the necessary feature for the instruction.
This makes outlined functions inherit target features from their parents.
It also updates the machine-outliner.ll test to check that we're properly
inheriting target features.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345535
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Matthias Braun [Mon, 29 Oct 2018 20:10:42 +0000 (20:10 +0000)]
Relax fast register allocator related test cases; NFC
- Relex hard coded registers and stack frame sizes
- Some test cleanups
- Change phi-dbg.ll to match on mir output after phi elimination instead
of going through the whole codegen pipeline.
This is in preparation for https://reviews.llvm.org/D52010
I'm committing all the test changes upfront that work before and after
independently.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345532
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Simon Pilgrim [Mon, 29 Oct 2018 19:51:52 +0000 (19:51 +0000)]
[X86] Set isMachineVerifierClean() back to false (PR27481)
Put back the isMachineVerifierClean() override removed at rL345513 to fix Windows ThinLTO tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345528
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Vedant Kumar [Mon, 29 Oct 2018 19:15:39 +0000 (19:15 +0000)]
[HotColdSplitting] Allow outlining single-block cold regions
It can be profitable to outline single-block cold regions because they
may be large.
Allow outlining single-block regions if they have over some threshold of
non-debug, non-terminator instructions. I chose 3 as the threshold after
experimenting with several internal frameworks.
In practice, reducing the threshold further did not give much
improvement, whereas increasing it resulted in substantial regressions.
Differential Revision: https://reviews.llvm.org/D53824
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345524
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Thomas Lively [Mon, 29 Oct 2018 18:38:12 +0000 (18:38 +0000)]
[WebAssembly] Lower away condition truncations for scalar selects
Reviewers: aheejin, dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D53676
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345521
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Simon Pilgrim [Mon, 29 Oct 2018 18:25:48 +0000 (18:25 +0000)]
[X86][SSE] getFauxShuffleMask - Fix shuffle mask adjustment for multiple inserted subvectors
Part of the issue discovered in PR39483, although its not fully exposed until I reapply rL345395 (by reverting rL345451)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345520
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Craig Topper [Mon, 29 Oct 2018 18:17:01 +0000 (18:17 +0000)]
[X86] Add AES to KNL CPUs to match clang.
I believe this was lost from KNL when AES was pushed from Westmere to Skylake recently. KNL used to inherit from IVB.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345519
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Stanislav Mekhanoshin [Mon, 29 Oct 2018 17:53:23 +0000 (17:53 +0000)]
[AMDGPU] Fixed return value causing warning and regression
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345518
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Bryan Chan [Mon, 29 Oct 2018 17:27:34 +0000 (17:27 +0000)]
[AArch64] Rename FP16FML instruction format (NFC)
Rename SIMDThreeSameMult (etc.) to SIMDThreeSameVectorFML (etc.) to follow
usual naming convention, and add some comments in the .td files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345515
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Stanislav Mekhanoshin [Mon, 29 Oct 2018 17:26:01 +0000 (17:26 +0000)]
[AMDGPU] Match v_swap_b32
Differential Revision: https://reviews.llvm.org/D52677
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345514
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Francis Visoiu Mistrih [Mon, 29 Oct 2018 16:57:43 +0000 (16:57 +0000)]
[X86] Enable the MachineVerifier by default
The machine verifier was disabled for x86 by default. There are now only
9 tests failing, compared to what previously was between 20 and 30.
This is a good opportunity to file bugs for all the remaining issues,
then explicitly disable the failing tests and enabling the machine
verifier by default.
This allows us to avoid adding new tests that break the verifier.
PR27481
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345513
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Leonard Chan [Mon, 29 Oct 2018 16:54:37 +0000 (16:54 +0000)]
[Intrinsic] Signed and Unsigned Saturation Subtraction Intirnsics
Add an intrinsic that takes 2 integers and perform saturation subtraction on
them.
This is a part of implementing fixed point arithmetic in clang where some of
the more complex operations will be implemented as intrinsics.
Differential Revision: https://reviews.llvm.org/D53783
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345512
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Luke Cheeseman [Mon, 29 Oct 2018 16:26:58 +0000 (16:26 +0000)]
[AArch64] Return address signing B key support
- Add support to generate AUTIBSP, PACIBSP, RETAB instructions for return
address signing
- The key used to sign the function is controlled by the function attribute
"sign-return-address-key"
Differential Revision: https://reviews.llvm.org/D51427
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345511
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Robert Widmann [Mon, 29 Oct 2018 15:31:40 +0000 (15:31 +0000)]
[LLVM-C] Add Builder Bindings to Common Memory Intrinsics
Summary: Add IRBuilder bindings for memmove, memcpy, and memset.
Reviewers: whitequark, deadalnix
Reviewed By: whitequark
Subscribers: harlanhaskins, llvm-commits
Differential Revision: https://reviews.llvm.org/D53555
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345508
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Michael Kruse [Mon, 29 Oct 2018 14:51:02 +0000 (14:51 +0000)]
[git/svn] Ignore Visual Studio's CMakeSettings.json.
When using Visual Studio's built-in support for CMake, the CMakeSettings.json contains the build configurations (build dir, generator, toolchain, cmake variables, etc). It is specific to the build machine, therefore should not be versioned.
Differential Revision: https://reviews.llvm.org/D53775
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345504
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James Henderson [Mon, 29 Oct 2018 14:17:08 +0000 (14:17 +0000)]
[llvm-objdump] Don't crash when using `-a` on non-archives
This fixes PR39402. The crash was caused when dereferencing nullptr in
DumpObject and printArchiveChild.
Reviewed By: jhenderson
Differential Revision: https://reviews.llvm.org/D53690
Patch by Xing GUO
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345503
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Francis Visoiu Mistrih [Mon, 29 Oct 2018 13:41:46 +0000 (13:41 +0000)]
[X86] Remove outdated test
This test breaks the X86 MachineVerifier. It looks like the MIR part is
completely useless.
The original author suggests that it can be removed.
Differential Revision: https://reviews.llvm.org/D53767
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345501
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Andrea Di Biagio [Mon, 29 Oct 2018 13:29:22 +0000 (13:29 +0000)]
[llvm-mca] Lower to mca::Instructon before the pipeline is run.
Before this change, the lowering of instructions from llvm::MCInst to
mca::Instruction was done as part of the first stage of the pipeline (i.e. the
FetchStage). In particular, FetchStage was responsible for picking the next
instruction from the source sequence, and lower it to an mca::Instruction with
the help of an object of class InstrBuilder.
The dependency on InstrBuilder was problematic for a number of reasons. Class
InstrBuilder only knows how to lower from llvm::MCInst to mca::Instruction.
That means, it is hard to support a different scenario where instructions
in input are not instances of class llvm::MCInst. Even if we managed to
specialize InstrBuilder, and generalize most of its internal logic, the
dependency on InstrBuilder in FetchStage would have caused more troubles (other
than complicating the pipeline logic).
With this patch, the lowering step is done before the pipeline is run. The
pipeline is no longer responsible for lowering from MCInst to mca::Instruction.
As a consequence of this, the FetchStage no longer needs to interact with an
InstrBuilder. The mca::SourceMgr class now simply wraps a reference to a
sequence of mca::Instruction objects.
This simplifies the logic of FetchStage, and increases the usability of it. As
a result, on a debug build, we see a 7-9% speedup; on a release build, the
speedup is around 3-4%.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345500
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