OSDN Git Service
Tim Northover [Mon, 13 Mar 2017 21:25:10 +0000 (21:25 +0000)]
Revert "GlobalISel: move vector extract/insert inside generic opcode region."
I was writing against an earlier branch and Volkan had already fixed this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297668
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Simon Pilgrim [Mon, 13 Mar 2017 21:23:29 +0000 (21:23 +0000)]
[X86][MMX] Fix folding of shift value loads to cover whole 64-bits
rL230225 made the assumption that only the lower 32-bits of an MMX register load is used as a shift value, when in fact the whole 64-bits are reloaded and treated as a i64 to determine the shift value.
This patch reverts rL230225 to ensure that the whole 64-bits of memory are folded and ensures that the upper 32-bit are zero'd for cases where the shift value has come from a scalar source.
Found during fuzz testing.
Differential Revision: https://reviews.llvm.org/D30833
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297667
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Tim Northover [Mon, 13 Mar 2017 21:18:59 +0000 (21:18 +0000)]
GlobalISel: move vector extract/insert inside generic opcode region.
Otherwise they won't be legalized or selected, causing instruction selection to
fail horribly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297666
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Andrew Kaylor [Mon, 13 Mar 2017 20:35:10 +0000 (20:35 +0000)]
Revert r295004 (Add MXCSR) due to errors reported by MachineVerifier
I am leaving the code in clang which filters mxcsr from the clobber list because that is still technically correct and will be useful again when the MXCSR register is reintroduced.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297664
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Volkan Keles [Mon, 13 Mar 2017 20:31:45 +0000 (20:31 +0000)]
[GlobalISel] Update PRE_ISEL_GENERIC_OPCODE_END marker
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297663
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Matt Arsenault [Mon, 13 Mar 2017 20:18:14 +0000 (20:18 +0000)]
AMDGPU: Re-use TM.getNullPointerValue
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297662
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Rafael Espindola [Mon, 13 Mar 2017 20:00:25 +0000 (20:00 +0000)]
Bring back r297624.
The issues was just a missing REQUIRES in the test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297661
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Sanjay Patel [Mon, 13 Mar 2017 19:59:14 +0000 (19:59 +0000)]
[SimplifyCFG] move tests for PR31028 from CGP
Hopefully, this will make sense with a forthcoming patch. If not, we can move these back.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297660
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Matt Arsenault [Mon, 13 Mar 2017 19:47:31 +0000 (19:47 +0000)]
AMDGPU: Treat 0 as private null pointer in addrspacecast lowering
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297658
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Rafael Espindola [Mon, 13 Mar 2017 19:38:32 +0000 (19:38 +0000)]
Revert "Fix crash when multiple raw_fd_ostreams to stdout are created."
This reverts commit r297624.
It was failing on the bots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297657
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Daniel Berlin [Mon, 13 Mar 2017 19:09:23 +0000 (19:09 +0000)]
Fix some indenting and line-wrapping issues identified in ProgrammersManual. Make description of debugCounters a little clearer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297656
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Jessica Paquette [Mon, 13 Mar 2017 18:39:33 +0000 (18:39 +0000)]
[Outliner] Add tail call support
This commit adds tail call support to the MachineOutliner pass. This allows
the outliner to insert jumps rather than calls in areas where tail calling is
possible. Outlined tail calls include the return or terminator of the basic
block being outlined from.
Tail call support allows the outliner to take returns and terminators into
consideration while finding candidates to outline. It also allows the outliner
to save more instructions. For example, in the X86-64 outliner, a tail called
outlined function saves one instruction since no return has to be inserted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297653
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Craig Topper [Mon, 13 Mar 2017 18:34:46 +0000 (18:34 +0000)]
[X86] Lower AVX2 gather intrinsics similar to AVX-512. Apply the same input source optimizations to break execution dependencies.
For AVX-512 we force the input to zero if the input is undef or the mask is all ones to break an execution dependency. This patch brings the same behavior to AVX2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297652
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Craig Topper [Mon, 13 Mar 2017 18:17:46 +0000 (18:17 +0000)]
[AVX-512] If gather mask is all ones, force the input to a zero vector.
We were already forcing undef inputs to become a zero vector, this now catches an all ones mask too.
Ideally we'd use undef and let execution dep fix handle picking the best register/clearance for the undef, but I don't think it can handle the early clobber today.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297651
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Matt Arsenault [Mon, 13 Mar 2017 18:14:02 +0000 (18:14 +0000)]
AMDGPU: Fold icmp/fcmp into icmp intrinsic
The typical use is a library vote function which
compares to 0. Fold the user condition into the intrinsic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297650
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Jonas Devlieghere [Mon, 13 Mar 2017 18:08:11 +0000 (18:08 +0000)]
[Linker] Provide callback for internalization
Differential Revision: https://reviews.llvm.org/D30738
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297649
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Craig Topper [Mon, 13 Mar 2017 17:37:14 +0000 (17:37 +0000)]
[SelectionDAG] Enhance SDTCisSameNumEltsAs to work with scalar types and use it on extend/trunc/round operations.
Currently we don't enforce that ISD::ANY_EXTEND, ZERO_EXTEND, SIGN_EXTEND, TRUNC, FP_ROUND, FP_EXTEND have the same number of elements(including scalar) between their input and output. Though we have them documented as such. Up until a few months ago x86 created nodes that violated this rule. That's all been fixed now, and we should enforce the rule going forward.
In order to do this we need to allow SDTCisSameNumEltsAs to support scalar types and not enforce being a vector. If one type is scalar we will force the other type to also be scalar.
Differential Revision: https://reviews.llvm.org/D30878
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297648
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Zachary Turner [Mon, 13 Mar 2017 17:25:47 +0000 (17:25 +0000)]
Add missing include on <limits>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297646
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Adrian Prantl [Mon, 13 Mar 2017 17:20:47 +0000 (17:20 +0000)]
API gardening: Rename FindAllocaDbgValue to findDbgValue (NFC)
and use have it use SmallVectorImpl.
There is nothing specific about allocas in this function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297643
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Zachary Turner [Mon, 13 Mar 2017 17:12:37 +0000 (17:12 +0000)]
Use numeric_limits<size_t>::max() instead of size_t(-1).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297641
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Zachary Turner [Mon, 13 Mar 2017 16:41:49 +0000 (16:41 +0000)]
Fix a warning due to signed/unsigned comparison.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297639
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Zachary Turner [Mon, 13 Mar 2017 16:32:08 +0000 (16:32 +0000)]
Use the new member accessors of llvm::enumerate.
The value_type is no longer a struct, it's a class whose
members you have to access via a method.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297635
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Zachary Turner [Mon, 13 Mar 2017 16:24:10 +0000 (16:24 +0000)]
[ADT] Improve the genericity of llvm::enumerate().
There were some issues in the implementation of enumerate()
preventing it from being used in various contexts. These were
all related to the fact that it did not supporter llvm's
iterator_facade_base class. So this patch adds support for that
and additionally exposes a new helper method to_vector() that
will evaluate an entire range and store the results in a
vector.
Differential Revision: https://reviews.llvm.org/D30853
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297633
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Zachary Turner [Mon, 13 Mar 2017 16:18:08 +0000 (16:18 +0000)]
Remove an unused variable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297632
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Sanjay Patel [Mon, 13 Mar 2017 15:45:37 +0000 (15:45 +0000)]
[CGP] add tests for PR31028; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297629
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Zachary Turner [Mon, 13 Mar 2017 14:57:45 +0000 (14:57 +0000)]
[llvm-pdbdump] Add support for dumping symbols from Yaml -> PDB.
Previously we could round-trip type records from PDB -> Yaml ->
PDB, but for symbols we could only go from PDB -> Yaml. This
completes the round-tripping for symbols as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297625
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Rafael Espindola [Mon, 13 Mar 2017 14:45:06 +0000 (14:45 +0000)]
Fix crash when multiple raw_fd_ostreams to stdout are created.
If raw_fd_ostream is constructed with the path of "-", it claims
ownership of the stdout file descriptor. This means that it closes
stdout when it is destroyed. If there are multiple users of
raw_fd_ostream wrapped around stdout, then a crash can occur because
of operations on a closed stream.
An example of this would be running something like "clang -S -o - -MD
-MF - test.cpp". Alternatively, using outs() (which creates a local
version of raw_fd_stream to stdout) anywhere combined with such a
stream usage would cause the crash.
The fix duplicates the stdout file descriptor when used within
raw_fd_ostream, so that only that particular descriptor is closed when
the stream is destroyed.
Patch by James Henderson!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297624
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Diana Picus [Mon, 13 Mar 2017 14:28:34 +0000 (14:28 +0000)]
[ARM] GlobalISel: Support SP in regbankselect
We used to hit an unreachable in getRegBankFromRegClass when dealing with the
stack pointer. This commit adds support for the GPRsp reg class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297621
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Aaron Ballman [Mon, 13 Mar 2017 12:24:51 +0000 (12:24 +0000)]
Reverting r297617 because it broke some bots:
http://bb.pgr.jp/builders/cmake-llvm-x86_64-linux/builds/49970
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297618
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Aaron Ballman [Mon, 13 Mar 2017 12:17:14 +0000 (12:17 +0000)]
Add support for getting file system permissions and implement sys::fs::permissions to set them.
Patch by James Henderson.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297617
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Balaram Makam [Mon, 13 Mar 2017 10:42:17 +0000 (10:42 +0000)]
[AArch64] Map Sched Read/Write resources for Falkor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297611
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Gil Rapaport [Mon, 13 Mar 2017 10:23:46 +0000 (10:23 +0000)]
[LV] Set memcheck metadata also for VF==1
This commit is a follow-up on r297580. It fixes the FIXME added temporarily
by that commit to keep the removal of Unroller's specialized version of
scalarizeInstruction() an NFC. See https://reviews.llvm.org/D30715 for details.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297610
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Sjoerd Meijer [Mon, 13 Mar 2017 09:41:10 +0000 (09:41 +0000)]
ARMDisassembler: loop over ARM decode tables
Loop over the ARM decode tables; this is a clean-up to reduce some code
duplication.
Differential Revision: https://reviews.llvm.org/D30814
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297608
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Konstantin Zhuravlyov [Mon, 13 Mar 2017 06:03:11 +0000 (06:03 +0000)]
AMDGPU/RelocVisitor: Handle R_AMDGPU_ABS64
Test is in the separate patch.
Differential Revision: https://reviews.llvm.org/D30027
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297604
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Craig Topper [Mon, 13 Mar 2017 05:47:56 +0000 (05:47 +0000)]
[AVX-512] Add EVEX2VEX test cases for the cvt instructions fixed in r297599 and r297600.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297603
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Craig Topper [Mon, 13 Mar 2017 05:34:03 +0000 (05:34 +0000)]
Revert "[AVX-512] EVEX2VEX, don't reject intrinsic instructions when both have a memory operand. We should just continue to check other operands instead."
This reverts r297596.
There were other issues that were making this not work that have been fixed now. Reverting this results in a more accurate table.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297602
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Craig Topper [Mon, 13 Mar 2017 05:14:47 +0000 (05:14 +0000)]
[AVX-512] Add VEX_WIG to VEX vcvtsd2ss/vcvtss2sd intrinsic instructions so they can be correctly matched by EVEX2VEX table generation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297601
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Craig Topper [Mon, 13 Mar 2017 05:14:44 +0000 (05:14 +0000)]
[AVX-512] Use sse_loadf32/f64 for vcvtss2sd and vcvtsd2ss intrinsic patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297600
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Craig Topper [Mon, 13 Mar 2017 03:59:06 +0000 (03:59 +0000)]
[AVX-512] Use sse_load_f64/f32 in VCVTSS2SI/VCVTSD2SI patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297599
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Craig Topper [Mon, 13 Mar 2017 00:36:49 +0000 (00:36 +0000)]
[AVX-512] EVEX2VEX, don't reject intrinsic instructions when both have a memory operand. We should just continue to check other operands instead.
This exposed that we have several intrinsic instructions that have identical TSFlags to other instructions. We should merge their patterns and kill of the duplicate. I'll fix that in a follow up patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297596
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Craig Topper [Mon, 13 Mar 2017 00:36:46 +0000 (00:36 +0000)]
[X86] Minor formatting tweaks in EVEX to VEX tables. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297595
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Craig Topper [Sun, 12 Mar 2017 23:05:03 +0000 (23:05 +0000)]
[X86] Remove unused SDTypeProfile. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297594
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Craig Topper [Sun, 12 Mar 2017 23:05:00 +0000 (23:05 +0000)]
[X86] Lower SSE/AVX cmpps/pd intrinsics directly to X86ISD::CMPP SDNodes.
This allows us to remove a duplicate set of patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297593
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Craig Topper [Sun, 12 Mar 2017 22:29:12 +0000 (22:29 +0000)]
[AVX-512] Fix the valid immediates for the scatter/gather prefetch intrinsics.
The immediate should be 1 or 2, not 0 or 1. This was found while adding bounds checking to clang. In fact the existing clang builtin test failed if we ran it all the way to assembly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297591
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Sanjay Patel [Sun, 12 Mar 2017 18:28:48 +0000 (18:28 +0000)]
[x86] don't blindly transform SETB into SBB
I noticed unnecessary 'sbb' instructions in D30472 and while looking at 'ptest' codegen recently.
This happens because we were transforming any 'setb' - even when we only wanted a single-bit result.
This patch moves those transforms under visitAdd/visitSub, so we we're only creating sbb/adc when it
is a win. I don't know why we need a SETCC_CARRY node type, but I'm not proposing to change that
existing behavior in this patch.
Also, I'm skeptical that sbb/adc are a win for all micro-arches, so I added comments to the test files
where this transform still fires.
The test changes here are all cases where we no longer produce sbb/adc. Avoiding partial register
stalls (generating an xor to clear a register) is not handled in some cases, but that's a separate
issue.
Differential Revision: https://reviews.llvm.org/D30611
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297586
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Anna Thomas [Sun, 12 Mar 2017 14:06:41 +0000 (14:06 +0000)]
[LVI] Add Datalayout to the class LazyValueInfo since all its Impls require it. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297583
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Azharuddin Mohammed [Sun, 12 Mar 2017 14:02:32 +0000 (14:02 +0000)]
Remove CRC32 instructions from AArch64InstrInfo::hasShiftedReg
Summary:
A53 scheduler causes an assertion failure on all CRC instructions:
include/llvm/CodeGen/MachineInstr.h:280: const llvm::MachineOperand
&llvm::MachineInstr::getOperand(unsigned int) const: Assertion `i <
getNumOperands() && "getOperand() out of range!"' failed.
The case statements corresponding to CRC instructions are incorrect and should
be removed.
Also adding a testcase while on this.
Reviewers: t.p.northover, javed.absar, apazos, rengolin
Reviewed By: rengolin
Subscribers: evandro, aemerson, llvm-commits, rengolin
Differential Revision: https://reviews.llvm.org/D30274
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297582
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Igor Breger [Sun, 12 Mar 2017 13:20:10 +0000 (13:20 +0000)]
[X86] Add vector zext tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297581
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Gil Rapaport [Sun, 12 Mar 2017 12:31:38 +0000 (12:31 +0000)]
[LV] A unified scalarizeInstruction() for Vectorizer and Unroller; NFC
Unroller's specialized scalarizeInstruction() is mostly duplicating Vectorizer's
variant. OTOH Vectorizer's scalarizeInstruction() already supports the special
case of VF==1 except for avoiding mask-bit extraction in that case. This patch
removes Unroller's specialized version in favor of a unified method.
The only functional difference between the two variants seems to be setting
memcheck metadata for loads and stores only in Vectorizer's variant, which is a
bug in Unroller. To keep this patch an NFC the unified method doesn't set
memcheck metadata for VF==1.
Differential Revision: https://reviews.llvm.org/D30715
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297580
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Ayal Zaks [Sun, 12 Mar 2017 09:48:06 +0000 (09:48 +0000)]
Test commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297579
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Daniel Berlin [Sun, 12 Mar 2017 04:46:45 +0000 (04:46 +0000)]
Split NewGVN class into a legacy pass and an impl, instead of a merged class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297576
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Daniel Berlin [Sun, 12 Mar 2017 04:46:41 +0000 (04:46 +0000)]
Add documentation on debug counters to Programmers Manual.
Reviewers: mehdi_amini
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D30842
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297575
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Craig Topper [Sun, 12 Mar 2017 03:37:37 +0000 (03:37 +0000)]
[AVX-512] Fix a bad use of a high GR8 register after copying from a mask register during fast isel. This ends up extracting from bits 15:8 instead of the lower bits of the mask.
I'm pretty sure there are more problems lurking here. But I think this fixes PR32241.
I've added the test case from that bug and added asserts that will fail if we ever try to copy between high registers and mask registers again.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297574
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Craig Topper [Sun, 12 Mar 2017 03:37:34 +0000 (03:37 +0000)]
[AVX-512] Add test case for PR32241. Fix coming in another commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297573
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Craig Topper [Sun, 12 Mar 2017 03:37:32 +0000 (03:37 +0000)]
[AVX-512] Remove unused field in X86VectorVTInfo tablegen class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297572
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Simon Pilgrim [Sat, 11 Mar 2017 20:42:31 +0000 (20:42 +0000)]
[X86][SSE] Improve extraction of elements from v16i8 (pre-SSE41)
Without SSE41 (pextrb) we currently extract byte elements from a vector by spilling to stack and reloading the byte.
This patch is an initial attempt at using MOVD/PEXTRW to extract the relevant DWORD/WORD from the vector and then shift+truncate to collect the correct byte.
Extraction of multiple bytes this way would result in code bloat, but as explained in the patch we could probably afford to be more aggressive with the supported extractions before again falling back on spilling - possibly through counting the number of extracts and which DWORD/WORD they originate?
Differential Revision: https://reviews.llvm.org/D29841
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297568
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Simon Pilgrim [Sat, 11 Mar 2017 20:23:59 +0000 (20:23 +0000)]
Remove unnecessary whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297567
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Simon Pilgrim [Sat, 11 Mar 2017 19:38:22 +0000 (19:38 +0000)]
Fix signed/unsigned comparison warning
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297565
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Craig Topper [Sat, 11 Mar 2017 18:26:00 +0000 (18:26 +0000)]
[X86] Add avx2 gather tests cases that show a failure to remove zeroing of the source when the mask is all ones.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297564
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Craig Topper [Sat, 11 Mar 2017 18:25:56 +0000 (18:25 +0000)]
[X86] Remove unnecessary commented out code. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297563
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Simon Pilgrim [Sat, 11 Mar 2017 13:02:31 +0000 (13:02 +0000)]
Fix signed/unsigned comparison warnings
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297561
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Simon Pilgrim [Sat, 11 Mar 2017 12:56:02 +0000 (12:56 +0000)]
Fix -Wsentinel warning
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297560
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Amaury Sechet [Sat, 11 Mar 2017 11:24:03 +0000 (11:24 +0000)]
Use setBits in SelectionDAG
Summary: As per title.
Reviewers: RKSimon
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D30836
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297559
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Matt Arsenault [Sat, 11 Mar 2017 05:51:16 +0000 (05:51 +0000)]
AMDGPU: Remove packf16 intrinsic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297557
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Matt Arsenault [Sat, 11 Mar 2017 05:40:40 +0000 (05:40 +0000)]
AMDGPU: Keep track of modifiers when converting v_mac to v_mad
Since v_max_f32_e64/v_max_f16_e64 can be folded if the target
instruction supports the clamp bit, we also need to maintain
modifiers when converting v_mac to v_mad.
This fixes a rendering issue with Dirt Rally because a v_mac
instruction with the clamp bit set was converted to a v_mad
but that bit was lost during the conversion.
Fixes:
e184e01dd79 ("AMDGPU: Fold FP clamp as modifier bit")
Patch by Samuel Pitoiset <samuel.pitoiset@gmail.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297556
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Kostya Serebryany [Sat, 11 Mar 2017 05:14:49 +0000 (05:14 +0000)]
[libFuzzer] add more iterations to LLVMFuzzer-Memcmp64BytesTest
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297554
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Zachary Turner [Sat, 11 Mar 2017 02:52:48 +0000 (02:52 +0000)]
[ADT] Add a DenseMapInfo<T> for shorts.
Differential Revision: https://reviews.llvm.org/D30857
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297552
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Kostya Serebryany [Sat, 11 Mar 2017 02:50:47 +0000 (02:50 +0000)]
[libFuzzer] reduce the number of vector resizes during merge (https://github.com/google/oss-fuzz/issues/445)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297551
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Zachary Turner [Sat, 11 Mar 2017 02:50:18 +0000 (02:50 +0000)]
Fix line endings of DenseMapInfo.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297550
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Zachary Turner [Sat, 11 Mar 2017 02:47:59 +0000 (02:47 +0000)]
Remove eol-style:native from DenseMapInfo.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297549
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Zachary Turner [Sat, 11 Mar 2017 02:45:50 +0000 (02:45 +0000)]
[Support] Add a formatv provider for Twine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297548
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Kostya Serebryany [Sat, 11 Mar 2017 02:26:20 +0000 (02:26 +0000)]
[libFuzzer] print how much memory is consumed by the outer merge process (https://github.com/google/oss-fuzz/issues/445)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297546
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Eric Fiselier [Sat, 11 Mar 2017 02:24:13 +0000 (02:24 +0000)]
Revert r297516 - Respect CMAKE_INSTALL_MANDIR for sphinx generated manpages
When CMAKE_INSTALL_MANDIR isn't defined it ends up attempting to install
the man pages under "/man1" and we really don't want to accidentally install
stuff at the filesystem root.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297545
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Kostya Serebryany [Sat, 11 Mar 2017 01:54:06 +0000 (01:54 +0000)]
[libFuzzer] add test/LargeTest.cpp, mostly for manual experiments with large number of edges, not yet suitable for unit testing
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297544
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Kostya Serebryany [Sat, 11 Mar 2017 01:48:54 +0000 (01:48 +0000)]
[libFuzzer] remove fuzzer-jobs.test which is flaky and not very useful
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297543
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Daniel Berlin [Sat, 11 Mar 2017 01:41:03 +0000 (01:41 +0000)]
Remove opt-bisect support for "cases" in favor of debug counters
Summary:
Ths "cases" support was not quite finished, is unused, and is really just debug counters.
(well, almost, debug counters are slightly more powerful, in that they can skip things at the start, too).
Note, opt-bisect itself could also be implemented as a wrapper around
debug counters, but not sure it's worth it ATM.
I'll shove it on a todo list if we think it is.
Reviewers: MatzeB, chandlerc
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D30856
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297542
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Jordan Rose [Sat, 11 Mar 2017 01:24:56 +0000 (01:24 +0000)]
[unittest] Explicitly specify alignment when using BumpPtrAllocator.
r297310 began inserting red zones around allocations under ASan, which
perturbs the alignment of subsequent allocations. Deliberately specify
this in two places where it matters.
Fixes failures when these tests are run under ASan and UBSan together.
Reviewed by Duncan Exon Smith.
rdar://problem/
30980047
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297540
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Sanjoy Das [Sat, 11 Mar 2017 01:15:48 +0000 (01:15 +0000)]
Use a WeakVH for UnknownInstructions in AliasSetTracker
Summary:
This change solves the same problem as D30726, except that this only
throws out the bathwater.
AST was not correctly tracking and deleting UnknownInstructions via
handles. The existing code only tracks "pointers" in its
`ASTCallbackVH`, so an UnknownInstruction (that isn't also def'ing a
pointer used by another memory instruction) never gets a
`ASTCallbackVH`.
There are two other ways to solve this problem:
- Use the `PointerRec` scheme for both known and unknown instructions.
- Use a `CallbackVH` that erases the offending Instruction from the
UnknownInstruction list.
Both of the above changes seemed to be significantly (and unnecessarily
IMO) more complex than this.
Reviewers: chandlerc, dberlin, hfinkel, reames
Subscribers: mcrosier, llvm-commits
Differential Revision: https://reviews.llvm.org/D30849
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297539
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Daniel Berlin [Sat, 11 Mar 2017 00:51:01 +0000 (00:51 +0000)]
VNCoercion: Make the function signatures all consistent
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297537
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Stanislav Mekhanoshin [Sat, 11 Mar 2017 00:29:27 +0000 (00:29 +0000)]
[AMDGPU] Remove getBidirectionalReasonRank
This method inverts the Reason field of a scheduling candidate.
It does right comparison between RegCritical and RegExcess, but
everything else is broken. In fact it can prefer less strong reason
such as Weak over RegCritical because Weak > -RegCritical.
The CandReason enum is properly sorted, so just remove artificial
ranking.
Differential Revision: https://reviews.llvm.org/D30557
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297536
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Quentin Colombet [Sat, 11 Mar 2017 00:28:33 +0000 (00:28 +0000)]
[IRTranslator] Simplify error handling for translating constants. NFC.
We don't need to check whether the fallback path is enabled to return
false. Just do that all the time on error cases, the caller knows (or
at least should know!) how to handle the failing case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297535
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Stanislav Mekhanoshin [Sat, 11 Mar 2017 00:14:52 +0000 (00:14 +0000)]
Fix subreg value numbers in handleMoveUp
The problem can occur in presence of subregs. If we are swapping two
instructions defining different subregs of the same register we will
get a new liveout from a block. We need to preserve value number for
block's liveout for successor block's livein to match.
Differential Revision: https://reviews.llvm.org/D30558
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297534
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Simon Pilgrim [Fri, 10 Mar 2017 22:53:19 +0000 (22:53 +0000)]
Strip trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297529
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Simon Pilgrim [Fri, 10 Mar 2017 22:44:47 +0000 (22:44 +0000)]
Fix redundant condition (PR32138)
'!A || (A && B)' is equivalent to '!A || B'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297527
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Krzysztof Parzyszek [Fri, 10 Mar 2017 22:44:24 +0000 (22:44 +0000)]
[RDF] Remove the map of reaching defs from copy propagation
Use Liveness::getNearestAliasedRef to find the reaching def instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297526
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Krzysztof Parzyszek [Fri, 10 Mar 2017 22:42:17 +0000 (22:42 +0000)]
[RDF] Implement Liveness::getNearestAliasedRef(Reg, Inst)
This function will find the closest ref node aliased to Reg that is
in an instruction preceding Inst. This could be used to identify the
hypothetical reaching def of Reg, if Reg was a member of Inst.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297524
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Simon Pilgrim [Fri, 10 Mar 2017 22:35:07 +0000 (22:35 +0000)]
[X86][SSE] Fix load folding for (V)CVTDQ2PD
This only requires a 64-bit memory source, not the whole 128-bits. But the 128-bit case is still supported via X86InstrInfo::foldMemoryOperandImpl
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297523
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Simon Pilgrim [Fri, 10 Mar 2017 22:10:34 +0000 (22:10 +0000)]
[X86] Fix Wunused-lambda-capture warning
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297521
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Simon Pilgrim [Fri, 10 Mar 2017 21:55:24 +0000 (21:55 +0000)]
[X86][RTM] Regenerate RTM intrinsic tests for 32/64-bit targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297518
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Jonathan Roelofs [Fri, 10 Mar 2017 21:44:16 +0000 (21:44 +0000)]
Respect CMAKE_INSTALL_MANDIR for sphinx generated manpages
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297516
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Peter Collingbourne [Fri, 10 Mar 2017 21:37:10 +0000 (21:37 +0000)]
LTO: Hash type identifier resolutions for WholeProgramDevirt.
Differential Revision: https://reviews.llvm.org/D30555
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297514
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Peter Collingbourne [Fri, 10 Mar 2017 21:35:17 +0000 (21:35 +0000)]
LTO: Hash type identifier resolutions for LowerTypeTests.
Differential Revision: https://reviews.llvm.org/D30553
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297513
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Volkan Keles [Fri, 10 Mar 2017 21:25:09 +0000 (21:25 +0000)]
[GlobalISel] LegalizerHelper: Lower (G_FSUB X, Y) to (G_FADD X, (G_FNEG Y))
Summary: No test case as none of the in-tree targets with GlobalISel support has this condition.
Reviewers: qcolombet, aditya_nandakumar, dsanders, t.p.northover, ab
Reviewed By: qcolombet
Subscribers: dberris, rovka, kristof.beyls, llvm-commits, igorb
Differential Revision: https://reviews.llvm.org/D30786
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297512
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Volkan Keles [Fri, 10 Mar 2017 21:23:13 +0000 (21:23 +0000)]
GlobalISel: Translate ConstantAggregateZero vectors
Reviewers: qcolombet, aditya_nandakumar, dsanders, ab, t.p.northover, javed.absar
Reviewed By: qcolombet
Subscribers: dberris, rovka, llvm-commits, kristof.beyls
Differential Revision: https://reviews.llvm.org/D30259
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297509
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Eric Christopher [Fri, 10 Mar 2017 21:20:17 +0000 (21:20 +0000)]
Sink accessing TII to fix release Werror builds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297507
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Davide Italiano [Fri, 10 Mar 2017 20:50:51 +0000 (20:50 +0000)]
[ProfileSummaryInfo] Remove unneeded braces. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297506
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Daniel Berlin [Fri, 10 Mar 2017 20:44:39 +0000 (20:44 +0000)]
Fix all these headers to properly mark the doxygen comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297505
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Evandro Menezes [Fri, 10 Mar 2017 20:20:04 +0000 (20:20 +0000)]
[AArch64, X86] Additional debug information for MacroFusion
In order to make it easier to parse information about the performance of
MacroFusion, this patch adds the function and the instruction names to the
debug output of this pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297504
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Peter Collingbourne [Fri, 10 Mar 2017 20:13:58 +0000 (20:13 +0000)]
WholeProgramDevirt: Implement export/import support for VCP.
Differential Revision: https://reviews.llvm.org/D30017
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297503
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Peter Collingbourne [Fri, 10 Mar 2017 20:09:11 +0000 (20:09 +0000)]
WholeProgramDevirt: Implement export/import support for unique ret val opt.
Differential Revision: https://reviews.llvm.org/D29917
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297502
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