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Nikolay Haustov [Tue, 1 Mar 2016 13:57:29 +0000 (13:57 +0000)]
[AMDGPU] Disassembler code refactored + error messages.
Idea behind this change is to make code shorter and as much common for all targets as possible. Let's even accept more code than is valid for a particular target, leaving it for the assembler to sort out.
64bit instructions decoding added.
Error\warning messages on unrecognized instructions operands added, InstPrinter allowed to print invalid operands helping to find invalid/unsupported code.
The change is massive and hard to compare with previous version, so it makes sense just to take a look on the new version. As a bonus, with a few TD changes following, it disassembles the majority of instructions. Currently it fully disassembles >300K binary source of some blas kernel.
Previous TODOs were saved whenever possible.
Patch by: Valery Pykhtin
Differential Revision: http://reviews.llvm.org/D17720
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262332
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Petr Pavlu [Tue, 1 Mar 2016 13:13:49 +0000 (13:13 +0000)]
[LTO] Fix error reporting from lto_module_create_in_local_context()
Function lto_module_create_in_local_context() would previously
rely on the default LLVMContext being created for it by
LTOModule::makeLTOModule(). This context exits the program on
error and is not arranged to update sLastStringError in
tools/lto/lto.cpp.
Function lto_module_create_in_local_context() now creates an
LLVMContext by itself, sets it up correctly to its needs and then
passes it to LTOModule::createInLocalContext() which takes
ownership of the context and keeps it present for the lifetime of
the returned LTOModule.
Function LTOModule::makeLTOModule() is modified to take a
reference to LLVMContext (instead of a pointer) and no longer
creates a default context when nullptr is passed to it. Method
LTOModule::createInContext() that takes a pointer to LLVMContext
is removed because it allows to pass a nullptr to it. Instead
LTOModule::createFromBuffer() (that takes a reference to
LLVMContext) should be used.
Differential Revision: http://reviews.llvm.org/D17715
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262330
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Michael Zuckerman [Tue, 1 Mar 2016 11:36:23 +0000 (11:36 +0000)]
[AVX512][PSRAQ][PSRAD] Change imm8 to int.
Differential Revision: http://reviews.llvm.org/D17692
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262320
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Amjad Aboud [Tue, 1 Mar 2016 11:32:03 +0000 (11:32 +0000)]
Disallow generating vzeroupper before return instruction (iret) in interrupt handler function.
This resolves https://llvm.org/bugs/show_bug.cgi?id=26412
Differential Revision: http://reviews.llvm.org/D17542
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262319
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Simon Atanasyan [Tue, 1 Mar 2016 10:11:27 +0000 (10:11 +0000)]
[MC][YAML] Rangify the loop. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262317
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Vasileios Kalintiris [Tue, 1 Mar 2016 10:08:01 +0000 (10:08 +0000)]
[mips] Promote the result of SETCC nodes to GPR width.
Summary:
This patch modifies the existing comparison, branch, conditional-move
and select patterns, and adds new ones where needed. Also, the updated
SLT{u,i,iu} set of instructions generate a GPR width result.
The majority of the code changes in the Mips back-end fix the wrong
assumption that the result of SETCC nodes always produce an i32 value.
The changes in the common code path account for the fact that in 64-bit
MIPS targets, i1 is promoted to i32 instead of i64.
Reviewers: dsanders
Subscribers: dsanders, llvm-commits
Differential Revision: http://reviews.llvm.org/D10970
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262316
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Nikolay Haustov [Tue, 1 Mar 2016 08:34:43 +0000 (08:34 +0000)]
[TableGen] AsmMatcher: Skip optional operands in the midle of instruction if it is not present
Previosy, if actual instruction have one of optional operands then other optional operands listed before this also should be presented.
For example instruction v_fract_f32 v0, v1, mul:2 have one optional operand - OMod and do not have optional operand clamp. Previously this was not allowed because clamp is listed before omod in AsmString:
string AsmString = "v_fract_f32$vdst, $src0_modifiers$clamp$omod";
Making this work required some hacks (both OMod and Clamp match classes have same PredicateMethod).
Now, if MatchInstructionImpl meets formal optional operand that is not presented in actual instruction it skips this formal operand and tries to match current actual operand with next formal.
Patch by: Sam Kolton
Review: http://reviews.llvm.org/D17568
[AMDGPU] Assembler: Check immediate types for several optional operands in predicate methods
With this change you should place optional operands in order specified by asm string:
clamp -> omod
offset -> glc -> slc -> tfe
Fixes for several tests.
Depends on D17568
Patch by: Sam Kolton
Review: http://reviews.llvm.org/D17644
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262314
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Nikolay Haustov [Tue, 1 Mar 2016 08:18:28 +0000 (08:18 +0000)]
AsmParser: Fix nested .irp/.irpc
Count .irp/.irpc in parseMacroLikeBody similar to .rept
Update tests.
Review: http://reviews.llvm.org/D17707
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262313
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Craig Topper [Tue, 1 Mar 2016 07:15:59 +0000 (07:15 +0000)]
[X86] Centralize the masking of TSFlags with FormMask into a variable earlier so we can stop masking in multiple places. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262312
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Craig Topper [Tue, 1 Mar 2016 06:42:48 +0000 (06:42 +0000)]
[X86] Localize a temporary variable into the cases its need in. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262310
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Craig Topper [Tue, 1 Mar 2016 06:42:46 +0000 (06:42 +0000)]
[X86] Be consistent about using pre/post increment/decrement in nearby code. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262309
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Craig Topper [Tue, 1 Mar 2016 05:42:16 +0000 (05:42 +0000)]
[X86] Combine some initialization code with variable declaration and comments. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262301
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Matt Arsenault [Tue, 1 Mar 2016 05:13:35 +0000 (05:13 +0000)]
LegalizeDAG: Use correct ptr type when expanding unaligned load/store
This fixes regressions exposed in existing AMDGPU tests in a
future commit when all loads are custom lowered.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262299
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Matt Arsenault [Tue, 1 Mar 2016 05:06:05 +0000 (05:06 +0000)]
AMDGPU: Don't emit build_pair during udivrem legalization
Technically you aren't supposed to emit these after type legalization
for some reason, and we use vector extracts of bitcasted integers
as the canonical way to do this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262298
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Matt Arsenault [Tue, 1 Mar 2016 04:58:20 +0000 (04:58 +0000)]
AMDGPU: Don't use estimated stack size when we know the real stack size
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262297
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Matt Arsenault [Tue, 1 Mar 2016 04:58:17 +0000 (04:58 +0000)]
AMDGPU: Set HasExtractBitInsn
This currently does not have the control over the bitwidth,
and there are missing optimizations to reduce the integer to
32-bit if it can be.
But in most situations we do want the sinking to occur.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262296
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David Majnemer [Tue, 1 Mar 2016 04:30:16 +0000 (04:30 +0000)]
[WinEH] Allocate the registration node before the catch objects
The CatchObjOffset is relative to the end of the EH registration node
for 32-bit x86 WinEH targets. A special sentinel value, 0, is used to
indicate that no catch object should be initialized.
This means that a catch object allocated immediately before the
registration node would be assigned a CatchObjOffset of 0, leading the
runtime to believe that a catch object should not be initialized.
To handle this, allocate the registration node prior to any other frame
object. This will ensure that catch objects will not be allocated
before the registration node.
This fixes PR26757.
Differential Revision: http://reviews.llvm.org/D17689
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262294
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David Majnemer [Tue, 1 Mar 2016 01:19:05 +0000 (01:19 +0000)]
[Verifier] Diagnose when unwinding out of cycles of blocks
Generally speaking, this can only happen with unreachable code.
However, neglecting to check for this condition would lead us to loop
forever.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262284
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Adam Nemet [Tue, 1 Mar 2016 00:50:14 +0000 (00:50 +0000)]
[LLE] Add testcase for the fix in r262267
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262280
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Adam Nemet [Tue, 1 Mar 2016 00:50:08 +0000 (00:50 +0000)]
[LAA] Add missing debug output
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262279
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Sanjay Patel [Mon, 29 Feb 2016 23:59:00 +0000 (23:59 +0000)]
[x86, InstCombine] transform more x86 masked loads to LLVM intrinsics
Continuation of:
http://reviews.llvm.org/rL262269
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262273
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Adam Nemet [Mon, 29 Feb 2016 23:21:12 +0000 (23:21 +0000)]
[LLE] Fix a comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262270
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Sanjay Patel [Mon, 29 Feb 2016 23:16:48 +0000 (23:16 +0000)]
[x86, InstCombine] transform x86 AVX masked loads to LLVM intrinsics
The intended effect of this patch in conjunction with:
http://reviews.llvm.org/rL259392
http://reviews.llvm.org/rL260145
is that customers using the AVX intrinsics in C will benefit from combines when
the load mask is constant:
__m128 mload_zeros(float *f) {
return _mm_maskload_ps(f, _mm_set1_epi32(0));
}
__m128 mload_fakeones(float *f) {
return _mm_maskload_ps(f, _mm_set1_epi32(1));
}
__m128 mload_ones(float *f) {
return _mm_maskload_ps(f, _mm_set1_epi32(0x80000000));
}
__m128 mload_oneset(float *f) {
return _mm_maskload_ps(f, _mm_set_epi32(0x80000000, 0, 0, 0));
}
...so none of the above will actually generate a masked load for optimized code.
This is the masked load counterpart to:
http://reviews.llvm.org/rL262064
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262269
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David Majnemer [Mon, 29 Feb 2016 22:56:36 +0000 (22:56 +0000)]
[Verifier] Handle more funclet edge cases
This change makes the verifier a little more paranoid. It was possible
to trick the verifier into crashing or infinite looping.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262268
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Adam Nemet [Mon, 29 Feb 2016 22:53:59 +0000 (22:53 +0000)]
[LLE] Fix SingleSource/Benchmarks/Polybench/stencils/jacobi-2d-imper with Polly
We can actually have dependences between accesses with different
underlying types. Bail in this case.
A test will follow shortly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262267
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Eric Christopher [Mon, 29 Feb 2016 22:50:49 +0000 (22:50 +0000)]
Simplify some boolean conditional return statements in AArch64.
http://reviews.llvm.org/D9979
Patch by Richard Thomson (and some conflict resolution by me).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262266
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Adrian Prantl [Mon, 29 Feb 2016 22:28:22 +0000 (22:28 +0000)]
Improve the debug output of DwarfDebug::buildLocationList().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262265
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Adrian Prantl [Mon, 29 Feb 2016 22:28:16 +0000 (22:28 +0000)]
Document an anomaly in this testcase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262264
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Paul Robinson [Mon, 29 Feb 2016 22:13:03 +0000 (22:13 +0000)]
Reapply r262092: [FileCheck] Abort if -NOT is combined with another suffix.
Combinations of suffixes that look useful are actually ignored;
complaining about them will avoid mistakes.
Differential Revision: http://reviews.llvm.org/D17587
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262263
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Sanjoy Das [Mon, 29 Feb 2016 22:04:25 +0000 (22:04 +0000)]
[Verifier] Minor fix to error message; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262262
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Colin LeMahieu [Mon, 29 Feb 2016 21:21:56 +0000 (21:21 +0000)]
[Hexagon] As a size optimization, not lazy extending TPREL or DTPREL variants since they're usually in range.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262258
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Colin LeMahieu [Mon, 29 Feb 2016 20:42:25 +0000 (20:42 +0000)]
[Hexagon] Missed member initialization causing ubsan failure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262252
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Adam Nemet [Mon, 29 Feb 2016 20:35:11 +0000 (20:35 +0000)]
Enable LoopLoadElimination by default
Summary:
I re-benchmarked this and results are similar to original results in
D13259:
On ARM64:
SingleSource/Benchmarks/Polybench/linear-algebra/solvers/dynprog -59.27%
SingleSource/Benchmarks/Polybench/stencils/adi -19.78%
On x86:
SingleSource/Benchmarks/Polybench/linear-algebra/solvers/dynprog -27.14%
And of course the original ~20% gain on SPECint_2006/456.hmmer with Loop
Distribution.
In terms of compile time, there is ~5% increase on both
SingleSource/Benchmarks/Misc/oourafft and
SingleSource/Benchmarks/Linkpack/linkpack-pc. These are both very tiny
loop-intensive programs where SCEV computations dominates compile time.
The reason that time spent in SCEV increases has to do with the design
of the old pass manager. If a transform pass does not preserve an
analysis we *invalidate* the analysis even if there was *no*
modification made by the transform pass.
This means that currently we don't take advantage of LLE and LV sharing
the same analysis (LAA) and unfortunately we recompute LAA *and* SCEV
for LLE.
(There should be a way to work around this limitation in the case of
SCEV and LAA since both compute things on demand and internally cache
their result. Thus we could pretend that transform passes preserve
these analyses and manually invalidate them upon actual modification.
On the other hand the new pass manager is supposed to solve so I am not
sure if this is worthwhile.)
Reviewers: hfinkel, dberlin
Subscribers: dberlin, reames, mssimpso, aemerson, joker.eph, llvm-commits
Differential Revision: http://reviews.llvm.org/D16300
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262250
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Adrian Prantl [Mon, 29 Feb 2016 20:25:10 +0000 (20:25 +0000)]
Fixup MIPS testcase after r262247 and make it a little more robust.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262249
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Geoff Berry [Mon, 29 Feb 2016 19:53:22 +0000 (19:53 +0000)]
[AArch64] Fix isLegalAddImmediate() to return true for valid negative values.
Reviewers: t.p.northover, jmolloy
Subscribers: mcrosier, aemerson, llvm-commits, rengolin
Differential Revision: http://reviews.llvm.org/D17463
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262248
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Adrian Prantl [Mon, 29 Feb 2016 19:49:46 +0000 (19:49 +0000)]
Fix PR26585 by improving the promotion of DBG_VALUEs to DW_AT_locations.
When a variable is described by a single DBG_VALUE instruction we can
often use a more efficient inline DW_AT_location instead of using a
location list.
This commit makes the heuristic that decides when to apply this
optimization stricter by also verifying that the DBG_VALUE is live at the
entry of the function (instead of just checking that it is valid until
the end of the function).
<rdar://problem/
24611008>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262247
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Steven Wu [Mon, 29 Feb 2016 19:40:10 +0000 (19:40 +0000)]
Rename embedded bitcode section in MachO
Summary:
Rename the section embeds bitcode from ".llvmbc,.llvmbc" to "__LLVM,__bitcode".
The new name matches MachO section naming convention.
Reviewers: rafael, pcc
Subscribers: davide, llvm-commits, joker.eph
Differential Revision: http://reviews.llvm.org/D17388
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262245
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Ahmed Bougacha [Mon, 29 Feb 2016 19:28:07 +0000 (19:28 +0000)]
[X86] Move the ATOMIC_LOAD_OP ISel from DAGToDAG to ISelLowering. NFCI.
This is long-standing dirtiness, as acknowledged by r77582:
The current trick is to select it into a merge_values with
the first definition being an implicit_def. The proper solution is
to add new ISD opcodes for the no-output variant.
Doing this before selection will let us combine away some constructs.
Differential Revision: http://reviews.llvm.org/D17659
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262244
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Colin LeMahieu [Mon, 29 Feb 2016 19:17:56 +0000 (19:17 +0000)]
[Hexagon] Setting sign mismatch flag on expression instead of using bit tricks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262243
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Rong Xu [Mon, 29 Feb 2016 19:16:04 +0000 (19:16 +0000)]
Minor code cleanup. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262242
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David Majnemer [Mon, 29 Feb 2016 19:16:03 +0000 (19:16 +0000)]
[WinEH] Make setjmp work correctly with EH
32-bit X86 EH on Windows utilizes a stack of registration nodes
allocated and deallocated on entry/exit. A registration node contains a
bunch of EH personality specific information like which try-state we are
currently in.
Because a setjmp target allows control flow from arbitrary program
points, there is no way to ensure that the try-state we are in is
correctly updated once we transfer control.
MSVC compatible compilers, like MSVC and ICC, utilize runtime helpers to
reinitialize the try-state when a longjmp occurs. This is implemented
by adding additional arguments to _setjmp3: the desired try-state and
a helper routine to update the try-state.
Differential Revision: http://reviews.llvm.org/D17721
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262241
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Dehao Chen [Mon, 29 Feb 2016 18:59:48 +0000 (18:59 +0000)]
Move discriminator assignment to the right place.
Summary: Now discriminator is assigned per-function instead of per-module.
Reviewers: davidxl, dnovillo
Subscribers: dblaikie, llvm-commits
Differential Revision: http://reviews.llvm.org/D17664
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262240
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Colin LeMahieu [Mon, 29 Feb 2016 18:39:51 +0000 (18:39 +0000)]
[Hexagon] Using MustExtend flag on expression instead of passing around bools.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262238
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Adrian Prantl [Mon, 29 Feb 2016 17:06:46 +0000 (17:06 +0000)]
fix typo in comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262236
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Nemanja Ivanovic [Mon, 29 Feb 2016 16:42:27 +0000 (16:42 +0000)]
Fix for PR26180
Corresponds to Phabricator review:
http://reviews.llvm.org/D16592
This fix includes both an update to how we handle the "generic" CPU on LE
systems as well as Anton's fix for the Fast Isel issue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262233
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Daniel Sanders [Mon, 29 Feb 2016 16:06:38 +0000 (16:06 +0000)]
[mips] Range check uimm20 and fixed a bug this revealed.
Summary:
The bug was that dextu's operand 3 would print 0-31 instead of 32-63 when
printing assembly. This came up when replacing
MipsInstPrinter::printUnsignedImm() with a version that could handle arbitrary
bit widths.
MipsAsmPrinter::printUnsignedImm*() don't seem to be used so they have been
removed.
Reviewers: vkalintiris
Subscribers: dsanders, llvm-commits
Differential Revision: http://reviews.llvm.org/D15521
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262231
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Vasileios Kalintiris [Mon, 29 Feb 2016 15:58:12 +0000 (15:58 +0000)]
[mips] Do not use SLL for ANY_EXTEND nodes as the high bits are undefined.
Reviewers: dsanders
Subscribers: dsanders, llvm-commits
Differential Revision: http://reviews.llvm.org/D15420
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262230
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Daniel Sanders [Mon, 29 Feb 2016 15:26:54 +0000 (15:26 +0000)]
[mips] Make isel select the correct DEXT variant up front.
Summary:
Previously, it would always select DEXT and substitute any invalid matches
for DEXTU/DEXTM during MipsMCCodeEmitter::encodeInstruction(). This works
but causes problems when adding range checked immediates to IAS.
Now isel selects the correct variant up front.
Reviewers: vkalintiris
Subscribers: dsanders, llvm-commits
Differential Revision: http://reviews.llvm.org/D16810
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262229
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Rafael Espindola [Mon, 29 Feb 2016 14:26:06 +0000 (14:26 +0000)]
IRObject: Mark extern_weak as weak.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262222
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Benjamin Kramer [Mon, 29 Feb 2016 12:18:25 +0000 (12:18 +0000)]
[InstSimplify] Restore fsub 0.0, (fsub 0.0, X) ==> X optzn
I accidentally removed this in r262212 but there was no test coverage to
detect it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262215
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Daniel Sanders [Mon, 29 Feb 2016 11:24:49 +0000 (11:24 +0000)]
[mips] Make symbols an acceptable branch target when expanding compare-to-immediate-and-branch macros.
Reviewers: vkalintiris
Subscribers: llvm-commits, vkalintiris, dim, seanbruno, dsanders
Differential Revision: http://reviews.llvm.org/D15369
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262213
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Benjamin Kramer [Mon, 29 Feb 2016 11:12:23 +0000 (11:12 +0000)]
[InstSimplify] fsub 0.0, (fsub -0.0, X) ==> X is only safe if signed zeros are ignored.
Only allow fsub -0.0, (fsub -0.0, X) ==> X without nsz. PR26746.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262212
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Daniel Sanders [Mon, 29 Feb 2016 11:04:39 +0000 (11:04 +0000)]
[test-release.sh] Add lldb to list of projects (disabled by default)
Reviewers: hans
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D17070
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262211
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Chandler Carruth [Sun, 28 Feb 2016 22:16:03 +0000 (22:16 +0000)]
[PM] Wire up optimization levels and default pipeline construction APIs
in the PassBuilder.
These are really just stubs for now, but they give a nice API surface
that Clang or other tools can start learning about and enabling for
experimentation.
I've also wired up parsing various synthetic module pass names to
generate these set pipelines. This allows the pipelines to be combined
with other passes and have their order controlled, with clear separation
between the *kind* of canned pipeline, and the *level* of optimization
to be used within that canned pipeline.
The most interesting part of this patch is almost certainly the spec for
the different optimization levels. I don't think we can ever have hard
and fast rules that would make it easy to determine whether a particular
optimization makes sense at a particular level -- it will always be in
large part a judgement call. But hopefully this will outline the
expected rationale that should be used, and the direction that the
pipelines should be taken. Much of this was based on a long llvm-dev
discussion I started years ago to try and crystalize the intent behind
these pipelines, and now, at long long last I'm returning to the task of
actually writing it down somewhere that we can cite and try to be
consistent with.
Differential Revision: http://reviews.llvm.org/D12826
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262196
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NAKAMURA Takumi [Sun, 28 Feb 2016 17:17:00 +0000 (17:17 +0000)]
[PM] Appease mingw32's auto-import DLL build with minimal tweaks, with fix for clang.
char AnalysisBase::ID should be declared as extern and defined in one module.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262188
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Vasileios Kalintiris [Sun, 28 Feb 2016 16:55:28 +0000 (16:55 +0000)]
[mips] Remove unused function declarations from MipsRegisterInfo.h. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262187
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NAKAMURA Takumi [Sun, 28 Feb 2016 16:54:06 +0000 (16:54 +0000)]
Revert r262185, "[PM] Appease mingw32's auto-import DLL build with minimal tweaks."
I'll rework soon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262186
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NAKAMURA Takumi [Sun, 28 Feb 2016 16:38:46 +0000 (16:38 +0000)]
[PM] Appease mingw32's auto-import DLL build with minimal tweaks.
char AnalysisBase::ID should be declared as extern and defined in one module.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262185
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JF Bastien [Sun, 28 Feb 2016 15:44:54 +0000 (15:44 +0000)]
WebAssembly: fix test
Operand order seems to have changed, the new one is nicer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262180
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JF Bastien [Sun, 28 Feb 2016 15:33:53 +0000 (15:33 +0000)]
WebAssembly: fix build
More API churn, experimental target got sad.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262179
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Michael Zuckerman [Sun, 28 Feb 2016 07:32:10 +0000 (07:32 +0000)]
[AVX512][PSLLW ][PSLLV] Change imm8 to int
Differential Revision: http://reviews.llvm.org/D17684
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262176
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Xinliang David Li [Sat, 27 Feb 2016 23:11:30 +0000 (23:11 +0000)]
[PGO] Remove redundant counter copies for avail_extern functions.
Differential Revision: http://reviews.llvm.org/D17654
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262157
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Duncan P. N. Exon Smith [Sat, 27 Feb 2016 20:27:44 +0000 (20:27 +0000)]
CodeGen: Remove an iterator => pointer conversion, NFC
Part of PR26753.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262154
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Matt Arsenault [Sat, 27 Feb 2016 20:26:57 +0000 (20:26 +0000)]
AMDGPU: More bits of frame index are known to be zero
The maximum private allocation for the whole GPU is 4G,
so the maximum possible index for a single workitem is the
maximum size divided by the smallest granularity for a dispatch.
This increases the number of known zero high bits, which
enables more offset folding. The maximum private size per
workitem with this is 128M but may be smaller still.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262153
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Duncan P. N. Exon Smith [Sat, 27 Feb 2016 20:23:14 +0000 (20:23 +0000)]
CodeGen: Use MachineInstr& in InlineSpiller::rematerializeFor()
InlineSpiller::rematerializeFor() never uses its parameter as an
iterator, so take it by reference instead. This removes an implicit
conversion from MachineBasicBlock::iterator to MachineInstr*.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262152
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Duncan P. N. Exon Smith [Sat, 27 Feb 2016 20:14:29 +0000 (20:14 +0000)]
CodeGen: Update LiveIntervalAnalysis API to use MachineInstr&, NFC
These parameters aren't expected to be null, so take them by reference.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262151
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Duncan P. N. Exon Smith [Sat, 27 Feb 2016 20:01:33 +0000 (20:01 +0000)]
CodeGen: Change MachineInstr to use MachineInstr&, NFC
Change MachineInstr API to prefer MachineInstr& over MachineInstr*
whenever the parameter is expected to be non-null. Slowly inching
toward being able to fix PR26753.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262149
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Matt Arsenault [Sat, 27 Feb 2016 19:57:45 +0000 (19:57 +0000)]
DAGCombiner: Don't unnecessarily swap operands in ReassociateOps
In the case where op = add, y = base_ptr, and x = offset, this
transform:
(op y, (op x, c1)) -> (op (op x, y), c1)
breaks the canonical form of add by putting the base pointer in the
second operand and the offset in the first.
This fix is important for the R600 target, because for some address
spaces the base pointer and the offset are stored in separate register
classes. The old pattern caused the ISel code for matching addressing
modes to put the base pointer and offset in the wrong register classes,
which required no-trivial code transformations to fix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262148
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Duncan P. N. Exon Smith [Sat, 27 Feb 2016 19:48:01 +0000 (19:48 +0000)]
CodeGen: Use MachineInstr& in HashMachineInstr, NFC
Also update HashEndOfMBB to take MachineBasicBlock&.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262146
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Duncan P. N. Exon Smith [Sat, 27 Feb 2016 19:33:37 +0000 (19:33 +0000)]
CodeGen: Use MachineInstr& in AntiDepBreaker API, NFC
Take parameters as MachineInstr& instead of MachineInstr* in
AntiDepBreaker API, since these are required to be non-null. No
functionality change intended. Looking toward PR26753.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262145
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Duncan P. N. Exon Smith [Sat, 27 Feb 2016 19:23:34 +0000 (19:23 +0000)]
CodeGen: Assert valid MI in AntiDepBreaker::UpdateDbgValue
This already assumes a valid MI, since it dereferences the MI in an
assertion before checking for null. At an explicit assert.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262144
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Duncan P. N. Exon Smith [Sat, 27 Feb 2016 19:12:54 +0000 (19:12 +0000)]
AArch64: Use MachineInstr& in guaranteesZeroRegInBlock(), NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262143
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Duncan P. N. Exon Smith [Sat, 27 Feb 2016 19:09:00 +0000 (19:09 +0000)]
CodeGen: Update DFAPacketizer API to take MachineInstr&, NFC
In all but one case, change the DFAPacketizer API to take MachineInstr&
instead of MachineInstr*. In DFAPacketizer::endPacket(), take
MachineBasicBlock::iterator. Besides cleaning up the API, this is in
search of PR26753.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262142
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Duncan P. N. Exon Smith [Sat, 27 Feb 2016 17:05:33 +0000 (17:05 +0000)]
WIP: CodeGen: Use MachineInstr& in MachineInstrBundle.h, NFC
Update APIs in MachineInstrBundle.h to take and return MachineInstr&
instead of MachineInstr* when the instruction cannot be null. Besides
being a nice cleanup, this is tacking toward a fix for PR26753.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262141
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JF Bastien [Sat, 27 Feb 2016 16:38:23 +0000 (16:38 +0000)]
WebAssembly: fix build
It was broken by the work for PR26753.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262140
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Renato Golin [Sat, 27 Feb 2016 14:19:19 +0000 (14:19 +0000)]
Revert "[sancov] do not instrument nodes that are full pre-dominators"
This reverts commit r262103, as it broke all ARM and AArch64 bots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262139
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Simon Pilgrim [Sat, 27 Feb 2016 13:26:58 +0000 (13:26 +0000)]
Tidyup for loops - don't repeat upper limit evaluation if you don't have to. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262137
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Chris Dewhurst [Sat, 27 Feb 2016 12:52:26 +0000 (12:52 +0000)]
Addition of tests to previous check-in. Tests for coprocessor register usage in Sparc.
Previous check-in message was:
The patch adds missing registers and instructions to complete all the registers supported by the Sparc v8 manual.
These are all co-processor registers, with the exception of the floating-point deferred-trap queue register.
Although these will not be lowered automatically by any instructions, it allows the use of co-processor
instructions implemented by inline-assembly.
Code Reviewed at http://reviews.llvm.org/D17133, with the exception of a very small change in brace placement in SparcInstrInfo.td,
which was formerly causing a problem in the disassembly of the %fq register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262135
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Simon Pilgrim [Sat, 27 Feb 2016 12:51:46 +0000 (12:51 +0000)]
[X86][AVX] vpermilvar.pd mask element indices only use bit1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262134
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Chris Dewhurst [Sat, 27 Feb 2016 12:49:59 +0000 (12:49 +0000)]
The patch adds missing registers and instructions to complete all the registers supported by the Sparc v8 manual.
These are all co-processor registers, with the exception of the floating-point deferred-trap queue register.
Although these will not be lowered automatically by any instructions, it allows the use of co-processor
instructions implemented by inline-assembly.
Code Reviewed at http://reviews.llvm.org/D17133, with the exception of a very small change in brace placement in SparcInstrInfo.td,
which was formerly causing a problem in the disassembly of the %fq register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262133
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Simon Pilgrim [Sat, 27 Feb 2016 12:33:08 +0000 (12:33 +0000)]
[X86][AVX] Added AVX1 target shuffle combine tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262132
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Simon Pilgrim [Sat, 27 Feb 2016 11:49:16 +0000 (11:49 +0000)]
Strip trailing whitespace. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262131
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Chandler Carruth [Sat, 27 Feb 2016 11:07:16 +0000 (11:07 +0000)]
[PM] Loosen the regex for the proxy template name even further to cope
with 'class' keywords in the template arguments and other silliness.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262130
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Chandler Carruth [Sat, 27 Feb 2016 10:48:14 +0000 (10:48 +0000)]
[PM] Use a boring regex instead of explicitly naming the analysis
manager as some compilers print the typedef name and others print the
"canonical" name of the underlying class template.
This isn't really an important artifact of the test anyways so it seems
fine to just loosen the test assertions here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262129
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Chandler Carruth [Sat, 27 Feb 2016 10:45:35 +0000 (10:45 +0000)]
[PM] Provide explicit instantiation declarations and definitions for the
PassManager and AnalysisManager template specializations as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262128
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Chandler Carruth [Sat, 27 Feb 2016 10:38:10 +0000 (10:38 +0000)]
[PM] Provide two templates for the two directionalities of analysis
manager proxies and use those rather than repeating their definition
four times.
There are real differences between the two directions: outer AMs are
const and don't need to have invalidation tracked. But every proxy in
a particular direction is identical except for the analysis manager type
and the IR unit they proxy into. This makes them prime candidates for
nice templates.
I've started introducing explicit template instantiation declarations
and definitions as well because we really shouldn't be emitting all this
everywhere. I'm going to go back and add the same for the other
templates like this in a follow-up patch.
I've left the analysis manager as an opaque type rather than using two
IR units and requiring it to be an AnalysisManager template
specialization. I think its important that users retain the ability to
provide their own custom analysis management layer and provided it has
the appropriate API everything should Just Work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262127
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Matt Arsenault [Sat, 27 Feb 2016 09:38:05 +0000 (09:38 +0000)]
DAGCombiner: Relax sqrt NaN folding check
This is OK for +0 since compares to +/-0 give the same result.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262125
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Matt Arsenault [Sat, 27 Feb 2016 08:53:55 +0000 (08:53 +0000)]
AMDGPU: Split vi-insts subtarget feature
This will be more useful for marking builtins acceptable for which
subtargets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262121
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Matt Arsenault [Sat, 27 Feb 2016 08:53:52 +0000 (08:53 +0000)]
AMDGPU: Add s_sleep intrinsic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262120
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Matt Arsenault [Sat, 27 Feb 2016 08:53:46 +0000 (08:53 +0000)]
AMDGPU: Implement readcyclecounter
This matches the behavior of the HSAIL clock instruction.
s_realmemtime is used if the subtarget supports it, and falls
back to s_memtime if not.
Also introduces new intrinsics for each of s_memtime / s_memrealtime.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262119
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Duncan P. N. Exon Smith [Sat, 27 Feb 2016 07:00:35 +0000 (07:00 +0000)]
CodeGen: Avoid implicit conversion in MachineInstrBuilder, NFC
Avoid another implicit conversion from MachineInstrBundleIterator to
MachineInstr*, this time in MachineInstrBuilder.h (this is in pursuit of
PR26753).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262118
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Duncan P. N. Exon Smith [Sat, 27 Feb 2016 06:51:00 +0000 (06:51 +0000)]
CodeGen: Remove implicit iterator to pointer conversions, NFC
Remove a couple of implicit conversions from MachineInstrBundleIterator
to MachineInstr*.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262116
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Duncan P. N. Exon Smith [Sat, 27 Feb 2016 06:40:41 +0000 (06:40 +0000)]
CodeGen: Take MachineInstr& in SlotIndexes and LiveIntervals, NFC
Take MachineInstr by reference instead of by pointer in SlotIndexes and
the SlotIndex wrappers in LiveIntervals. The MachineInstrs here are
never null, so this cleans up the API a bit. It also incidentally
removes a few implicit conversions from MachineInstrBundleIterator to
MachineInstr* (see PR26753).
At a couple of call sites it was convenient to convert to a range-based
for loop over MachineBasicBlock::instr_begin/instr_end, so I added
MachineBasicBlock::instrs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262115
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Sean Silva [Sat, 27 Feb 2016 06:01:26 +0000 (06:01 +0000)]
[instrprof] Use __{start,stop}_SECNAME on PS4 too.
Summary:
The PS4 linker seems to handle this fine.
Hi David, it seems that indeed most ELF linkers support
__{start,stop}_SECNAME, as our proprietary linker does as well.
This follows the pattern of r250679 w.r.t. the testing.
Maggie, Phillip, Paul: I've tested this with the PS4 SDK 3.5 toolchain
prerelease and it seems to work fine.
Reviewers: davidxl
Subscribers: probinson, phillip.power, MaggieYi
Differential Revision: http://reviews.llvm.org/D17672
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262112
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Mike Aizatsky [Sat, 27 Feb 2016 05:50:40 +0000 (05:50 +0000)]
[sancov] properly initializing pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262111
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Kostya Serebryany [Sat, 27 Feb 2016 05:45:12 +0000 (05:45 +0000)]
[libFuzzer] don't emit callbacks to sanitizer run-time in -fsanitize-coverage=trace-pc mode; update libFuzzer doc for previous commit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262110
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Philip Reames [Sat, 27 Feb 2016 05:18:30 +0000 (05:18 +0000)]
Suppress an uncovered switch warning [NFC]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262109
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Chandler Carruth [Sat, 27 Feb 2016 04:34:07 +0000 (04:34 +0000)]
[LICM] Teach LICM how to handle cases where the alias set tracker was
merged into a loop that was subsequently unrolled (or otherwise nuked).
In this case it can't merge in the ASTs for any remaining nested loops,
it needs to re-add their instructions dircetly.
The fix is very isolated, but I've pulled the code for merging blocks
into the AST into a single place in the process. The only behavior
change is in the case which would have crashed before.
This fixes a crash reported by Mikael Holmen on the list after r261316
restored much of the loop pass pipelining and allowed us to actually do
this kind of nested transformation sequenc. I've taken that test case
and further reduced it into the somewhat twisty maze of loops in the
included test case. This does in fact trigger the bug even in this
reduced form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262108
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Kostya Serebryany [Sat, 27 Feb 2016 03:14:23 +0000 (03:14 +0000)]
[libFuzzer] fixing the bot
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262106
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Mike Aizatsky [Sat, 27 Feb 2016 02:21:44 +0000 (02:21 +0000)]
[sancov] print_coverage_points command.
Differential Revision: http://reviews.llvm.org/D17670
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262104
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