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Hans Wennborg [Wed, 20 Sep 2017 18:00:02 +0000 (18:00 +0000)]
Pacify gcc's -Wnum-compare after r313775
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313779
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Adrian Prantl [Wed, 20 Sep 2017 17:44:00 +0000 (17:44 +0000)]
llvm-dwarfdump: implement --recurse-depth=<N>
This patch implements the Darwin dwarfdump option --recurse-depth=<N>,
which limits the recursion depth when selectively printing DIEs at an
offset.
Differential Revision: https://reviews.llvm.org/D38064
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313778
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Reid Kleckner [Wed, 20 Sep 2017 17:32:54 +0000 (17:32 +0000)]
[DebugInfo] Use a MapVector to coalesce MachineOperand locations
Summary:
The new code should be linear in the number of DBG_VALUEs, while the old
code was quadratic. NFC intended.
This is also hopefully a more direct expression of the problem, which is
to:
1. Rewrite all virtual register operands to stack slots or physical
registers
2. Uniquely number those machine operands, assigning them location
numbers
3. Rewrite all uses of the old location numbers in the interval map to
use the new location numbers
In r313400, I attempted to track which locations were spilled in a
parallel bitvector indexed by location number. My code was broken
because these location numbers are not stable during rewriting.
Reviewers: aprantl, hans
Subscribers: hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D38068
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313775
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Quentin Colombet [Wed, 20 Sep 2017 17:32:16 +0000 (17:32 +0000)]
[InstCombine] Add select simplifications
In these cases, two selects have constant selectable operands for
both the true and false components and have the same conditional
expression.
We then create two arithmetic operations of the same type and feed a
final select operation using the result of the true arithmetic for the true
operand and the result of the false arithmetic for the false operand and reuse
the original conditionl expression.
The arithmetic operations are naturally folded as a consequence, leaving
only the newly formed select to replace the old arithmetic operation.
Patch by: Michael Berg <michael_c_berg@apple.com>
Differential Revision: https://reviews.llvm.org/D37019
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313774
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Jake Ehrlich [Wed, 20 Sep 2017 17:22:06 +0000 (17:22 +0000)]
Reland "[llvm-objcopy] Add support for .dynamic, .dynsym, and .dynstr"
I did not upload two binaries that I reference in tests.
This change adds support for sections involved in dynamic loading such
as SHT_DYNAMIC, SHT_DYNSYM, and allocated string tables.
The two added binaries used for tests can be downloaded here and here
Differential Revision: https://reviews.llvm.org/D36560
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313772
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Mohammad Shahid [Wed, 20 Sep 2017 17:19:57 +0000 (17:19 +0000)]
[SLP] Vectorize jumbled memory loads.
Summary:
This patch tries to vectorize loads of consecutive memory accesses, accessed
in non-consecutive or jumbled way. An earlier attempt was made with patch D26905
which was reverted back due to some basic issue with representing the 'use mask'
jumbled accesses.
This patch fixes the mask representation by recording the 'use mask' in the usertree entry.
Change-Id: I9fe7f5045f065d84c126fa307ef6ebe0787296df
Subscribers: mzolotukhin
Reviewed By: ayal
Differential Revision: https://reviews.llvm.org/D36130
Review comments updated accordingly
Change-Id: I22ab0a8a9bac9d49d74baa81a08e1e486f5e75f0
Added a TODO for sortLoadAccesses API
Change-Id: I3c679bf1865422d1b45e17ea28f1992bca660b58
Modified the TODO for sortLoadAccesses API
Change-Id: Ie64a66cb5f9e2a7610438abb0e750c6e090f9565
Review comment update for using OpdNum to insert the mask in respective location
Change-Id: I016d0c1b29874e979efc0205bbf078991f92edce
Fixes '-Wsign-compare warning' in LoopAccessAnalysis.cpp and code rebase
Change-Id: I64b2ea5e68c1d7b6a028f5ef8251c5a97333f89b
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313771
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Vedant Kumar [Wed, 20 Sep 2017 17:16:01 +0000 (17:16 +0000)]
[cmake] Add an option to build llvm with IR PGO
This adds an LLVM_ENABLE_IR_PGO option to enable building llvm and its
tools with IR PGO instrumentation.
Usage: -DLLVM_BUILD_INSTRUMENTED=On -DLLVM_ENABLE_IR_PGO=On (both
options must be enabled)
Differential Revision: https://reviews.llvm.org/D38066
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313770
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Vedant Kumar [Wed, 20 Sep 2017 17:16:00 +0000 (17:16 +0000)]
[cmake] Unmark LLVM_BUILD_INSTRUMENTED_COVERAGE as experimental
The coverage bot has been stable for a while:
http://lab.llvm.org:8080/coverage/coverage-reports/index.html
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313769
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Vedant Kumar [Wed, 20 Sep 2017 17:16:00 +0000 (17:16 +0000)]
[docs] Make a note of LLVM_BUILD_INSTRUMENTED_COVERAGE
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313768
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Jake Ehrlich [Wed, 20 Sep 2017 17:11:58 +0000 (17:11 +0000)]
Reland "[llvm-objcopy] Add support for .dynamic, .dynsym, and .dynstr"
I overzealously landed this before I was sure that another change
wouldn't break the build that this change depends on.
This change adds support for sections involved in dynamic loading such
as SHT_DYNAMIC, SHT_DYNSYM, and allocated string tables.
The two added binaries used for tests can be downloaded here and here
Differential Revision: https://reviews.llvm.org/D36560
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313767
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Teresa Johnson [Wed, 20 Sep 2017 17:09:47 +0000 (17:09 +0000)]
[ThinLTO] Fix dead stripping analysis for SamplePGO
Summary:
The fix for dead stripping analysis in the case of SamplePGO indirect
calls to local functions (r313151) introduced the possibility of an
infinite loop.
Make sure we check for the value being already live after we update it
for SamplePGO indirect call handling.
Reviewers: danielcdh
Subscribers: mehdi_amini, inglorion, llvm-commits, eraman
Differential Revision: https://reviews.llvm.org/D38086
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313766
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Zachary Turner [Wed, 20 Sep 2017 17:08:20 +0000 (17:08 +0000)]
[lit] Reverse path list when updating environment vars.
Bug pointed out by EricWF. This would construct a path where
items would be added in the wrong order, potentially leading
to using the wrong tools for testing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313765
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Zachary Turner [Wed, 20 Sep 2017 16:01:50 +0000 (16:01 +0000)]
Make libcxx tests work when llvm sources are not present.
Despite a strong CMake warning that this is an unsupported
libcxx build configuration, some bots still rely on being
able to check out lit and libcxx independently with no
LLVM sources, and then run lit against libcxx.
A previous patch broke that workflow, so this is making it work
again. Unfortunately, it breaks generation of the llvm-lit
script for libcxx, but we will just have to live with that until
a solution is found that allows libcxx to make more use of
llvm build pieces. libcxx can still run tests by using the
ninja check target, or by running lit.py directly against the
build tree or source tree.
Differential Revision: https://reviews.llvm.org/D38057
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313763
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David Blaikie [Wed, 20 Sep 2017 15:59:57 +0000 (15:59 +0000)]
DebugInfo: Remove unneeded attributes from test/DebugInfo/Generic/imported-name-inlined.ll
Remove unneeded attributes from test/DebugInfo/Generic/imported-name-inlined.ll because it was causing failures on pure MIPS builds.
Patch by Miloš Stojanović!
Differential Revision: https://reviews.llvm.org/D38079
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313762
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Simon Atanasyan [Wed, 20 Sep 2017 15:57:25 +0000 (15:57 +0000)]
[mips] Add a valid test case to check the reason of the recent build-bot failure. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313761
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Alexander Kornienko [Wed, 20 Sep 2017 14:53:07 +0000 (14:53 +0000)]
Revert r313736: "[SLP] Vectorize jumbled memory loads."
The revision breaks buildbots:
http://lab.llvm.org:8011/builders/clang-x86_64-debian-fast/builds/6694/steps/test/logs/stdio
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313758
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Alexander Kornienko [Wed, 20 Sep 2017 14:52:56 +0000 (14:52 +0000)]
Revert r313753: "Fix a -Wsign-compare warning in LoopAccessAnalysis.cpp"
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313757
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Simon Pilgrim [Wed, 20 Sep 2017 13:49:52 +0000 (13:49 +0000)]
[X86][SSE] Add PR22415 test case
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313755
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Alexander Kornienko [Wed, 20 Sep 2017 12:18:22 +0000 (12:18 +0000)]
Fix a -Wsign-compare warning in LoopAccessAnalysis.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313753
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Florian Hahn [Wed, 20 Sep 2017 11:54:37 +0000 (11:54 +0000)]
Recommit [MachineCombiner] Update instruction depths incrementally for large BBs.
This version of the patch fixes an off-by-one error causing PR34596. We
do not need to use std::next(BlockIter) when calling updateDepths, as
BlockIter already points to the next element.
Original commit message:
> For large basic blocks with lots of combinable instructions, the
> MachineTraceMetrics computations in MachineCombiner can dominate the compile
> time, as computing the trace information is quadratic in the number of
> instructions in a BB and it's relevant successors/predecessors.
> In most cases, knowing the instruction depth should be enough to make
> combination decisions. As we already iterate over all instructions in a basic
> block, the instruction depth can be computed incrementally. This reduces the
> cost of machine-combine drastically in cases where lots of instructions
> are combined. The major drawback is that AFAIK, computing the critical path
> length cannot be done incrementally. Therefore we only compute
> instruction depths incrementally, for basic blocks with more
> instructions than inc_threshold. The -machine-combiner-inc-threshold
> option can be used to set the threshold and allows for easier
> experimenting and checking if using incremental updates for all basic
> blocks has any impact on the performance.
>
> Reviewers: sanjoy, Gerolf, MatzeB, efriedma, fhahn
>
> Reviewed By: fhahn
>
> Subscribers: kiranchandramohan, javed.absar, efriedma, llvm-commits
>
> Differential Revision: https://reviews.llvm.org/D36619
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313751
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George Rimar [Wed, 20 Sep 2017 10:24:37 +0000 (10:24 +0000)]
Revert r313746 "[yaml2obj] - Don't crash on invalid document."
It broke BB:
http://lab.llvm.org:8011/builders/llvm-hexagon-elf/builds/9781
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313748
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George Rimar [Wed, 20 Sep 2017 09:57:11 +0000 (09:57 +0000)]
[yaml2obj] - Don't crash on invalid document.
Previously jaml2obj would segfault on empty document.
(without yaml description).
Patch fixes the issue.
Differential revision: https://reviews.llvm.org/D38036
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313746
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Simon Pilgrim [Wed, 20 Sep 2017 09:36:11 +0000 (09:36 +0000)]
[X86][SSE] Remove unnecessary NonceMasks from combineX86ShufflesRecursively calls (NFCI)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313743
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Mikael Holmen [Wed, 20 Sep 2017 08:23:29 +0000 (08:23 +0000)]
[IfConversion] Add testcases [NFC]
These tests should have been included in r310697 / D34099 but apparently
I missed them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313737
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Mohammad Shahid [Wed, 20 Sep 2017 08:18:28 +0000 (08:18 +0000)]
[SLP] Vectorize jumbled memory loads.
Summary:
This patch tries to vectorize loads of consecutive memory accesses, accessed
in non-consecutive or jumbled way. An earlier attempt was made with patch D26905
which was reverted back due to some basic issue with representing the 'use mask' of
jumbled accesses.
This patch fixes the mask representation by recording the 'use mask' in the usertree entry.
Change-Id: I9fe7f5045f065d84c126fa307ef6ebe0787296df
Reviewers: mkuper, loladiro, Ayal, zvi, danielcdh
Reviewed By: Ayal
Subscribers: mzolotukhin
Differential Revision: https://reviews.llvm.org/D36130
Commit after rebase for patch D36130
Change-Id: I8add1c265455669ef288d880f870a9522c8c08ab
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313736
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Andrew V. Tischenko [Wed, 20 Sep 2017 08:17:17 +0000 (08:17 +0000)]
'into' instruction should not be decoded as a valid instr in 64-bit mode
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313735
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Craig Topper [Wed, 20 Sep 2017 06:38:41 +0000 (06:38 +0000)]
[X86] Remove isel checks for immediate size on floating point compare and xop compare instructions. NFCI
If these checks fail we end up not selecting an instruction at all. So we are already relying on the immediate being checked upstream of isel. So doing the check in isel is just bloat to the isel table. Interestingly, we didn't check on the AVX512 version of the instructions anyway.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313724
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Stanislav Mekhanoshin [Wed, 20 Sep 2017 06:34:28 +0000 (06:34 +0000)]
[AMDGPU] Fixed memory leak with inliner replaced
Delete inliner before replacing it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313723
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Matt Arsenault [Wed, 20 Sep 2017 06:11:25 +0000 (06:11 +0000)]
AMDGPU: Move r600 only code into r600 only td file
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313719
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Stanislav Mekhanoshin [Wed, 20 Sep 2017 06:10:15 +0000 (06:10 +0000)]
[AMDGPU] Fix regression in test clang/test/CodeGen/backend-unsupported-error.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313718
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Matt Arsenault [Wed, 20 Sep 2017 05:01:53 +0000 (05:01 +0000)]
AMDGPU: Match load d16 hi instructions
Also starts selecting global loads for constant address
in some cases. Some end up selecting to mubuf still, which
requires investigation.
We still get sub-optimal regalloc and extra waitcnts inserted
due to not really tracking the liveness of the separate register
halves.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313716
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NAKAMURA Takumi [Wed, 20 Sep 2017 04:39:02 +0000 (04:39 +0000)]
DiagnosticInfoOptimizationBase: Appease g++-4.8.2 not confused to add an explicit type to resolve emit() as non-template function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313715
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Stanislav Mekhanoshin [Wed, 20 Sep 2017 04:25:58 +0000 (04:25 +0000)]
[AMDGPU] Port of HSAIL inliner
Differential Revision: https://reviews.llvm.org/D36849
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313714
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Matt Arsenault [Wed, 20 Sep 2017 03:43:35 +0000 (03:43 +0000)]
AMDGPU: Cleanup load/store PatFrags
Try to use a consistent naming scheme.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313713
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Matt Arsenault [Wed, 20 Sep 2017 03:20:09 +0000 (03:20 +0000)]
AMDGPU: Match store d16_hi instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313712
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Sanjoy Das [Wed, 20 Sep 2017 02:31:57 +0000 (02:31 +0000)]
Tighten the invariants around LoopBase::invalidate
Summary:
With this change:
- Methods in LoopBase trip an assert if the receiver has been invalidated
- LoopBase::clear frees up the memory held the LoopBase instance
This change also shuffles things around as necessary to work with this stricter invariant.
Reviewers: chandlerc
Subscribers: mehdi_amini, mcrosier, llvm-commits
Differential Revision: https://reviews.llvm.org/D38055
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313708
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Mike Edwards [Wed, 20 Sep 2017 01:21:02 +0000 (01:21 +0000)]
Reverting due to Green Dragon bot failure.
http://green.lab.llvm.org/green/job/clang-stage1-cmake-RA-incremental/42594/
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313706
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Sanjoy Das [Wed, 20 Sep 2017 01:12:09 +0000 (01:12 +0000)]
Clang-format few files to make later diffs leaner; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313705
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Daniel Berlin [Wed, 20 Sep 2017 00:07:27 +0000 (00:07 +0000)]
GVNSink: Make ModelledPHIs constructor linear (and avoid edge case it worries about) by avoiding getIncomingValueForBlock
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313702
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Daniel Berlin [Wed, 20 Sep 2017 00:07:25 +0000 (00:07 +0000)]
Revert "[GVNSink] Remove dependency on SmallPtrSet iteration order."
This reverts commit r312156, because now the op and block arrays are not in the same order :(.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313701
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Daniel Berlin [Wed, 20 Sep 2017 00:07:12 +0000 (00:07 +0000)]
NewGVN: Remove unused includes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313700
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Zachary Turner [Tue, 19 Sep 2017 23:50:28 +0000 (23:50 +0000)]
Make lit stop writing pyc files.
Many svn-based buildbots seem to be getting stuck continually
in tree conflicts due to the output of pyc files. I'm disabling
these as a temporary measure in an attempt to get everything
stable again.
I'll try to remove this code once I understand the problem
better.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313698
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Quentin Colombet [Tue, 19 Sep 2017 23:34:12 +0000 (23:34 +0000)]
[MIRPrinter] Print empty successor lists when they cannot be guessed
This re-applies commit r313685, this time with the proper updates to
the test cases.
Original commit message:
Unreachable blocks in the machine instr representation are these
weird empty blocks with no successors.
The MIR printer used to not print empty lists of successors. However,
the MIR parser now treats non-printed list of successors as "please
guess it for me". As a result, the parser tries to guess the list of
successors and given the block is empty, just assumes it falls through
the next block (if any).
For instance, the following test case used to fail the verifier.
The MIR printer would print
entry
/ \
true (def) false (no list of successors)
|
split.true (use)
The MIR parser would understand this:
entry
/ \
true (def) false
| / <-- invalid edge
split.true (use)
Because of the invalid edge, we get the "def does not
dominate all uses" error.
The fix consists in printing empty successor lists, so that the parser
knows what to do for unreachable blocks.
rdar://problem/
34022159
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313696
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Sanjoy Das [Tue, 19 Sep 2017 23:19:00 +0000 (23:19 +0000)]
[LoopInfo] Make LoopBase and Loop destructors non-public
Summary:
See comment for why I think this is a good idea.
This change also:
- Removes an SCEV test case. The SCEV test was not testing anything useful (most of it was `#if 0` ed out) and it would need to be updated to deal with a private ~Loop::Loop.
- Updates the loop pass manager test case to deal with a private ~Loop::Loop.
- Renames markAsRemoved to markAsErased to contrast with removeLoop, via the usual remove vs. erase idiom we already have for instructions and basic blocks.
Reviewers: chandlerc
Subscribers: mehdi_amini, mcrosier, llvm-commits
Differential Revision: https://reviews.llvm.org/D37996
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313695
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Sam Clegg [Tue, 19 Sep 2017 23:00:57 +0000 (23:00 +0000)]
[WebAssembly] Add support for naming wasm data segments
Add adds support for naming data segments. This is useful
useful linkers so that they can merge similar sections.
Differential Revision: https://reviews.llvm.org/D37886
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313692
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Adam Nemet [Tue, 19 Sep 2017 23:00:55 +0000 (23:00 +0000)]
Allow ORE.emit to take a closure to delay building the remark object
In the lambda we are now returning the remark by value so we need to preserve
its type in the insertion operator. This requires making the insertion
operator generic.
I've also converted a few cases to use the new API. It seems to work pretty
well. See the LoopUnroller for a slightly more interesting case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313691
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Vlad Tsyrklevich [Tue, 19 Sep 2017 22:36:32 +0000 (22:36 +0000)]
Revert "Introduce the llvm-cfi-verify tool."
This reverts commit r313688, it caused build failures for
llvm-i686-linux-RA
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313689
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Vlad Tsyrklevich [Tue, 19 Sep 2017 22:33:09 +0000 (22:33 +0000)]
Introduce the llvm-cfi-verify tool.
Summary: Introduces the llvm-cfi-verify tool to llvm. Includes the design document (docs/CFIVerify.rst). Current implementation of the tool is simply a disassembler that identifies and prints the indirect control flow instructions.
Reviewers: vlad.tsyrklevich
Reviewed By: vlad.tsyrklevich
Patch by Mitch Phillips
Subscribers: llvm-commits, kcc, pcc, mgorny
Differential Revision: https://reviews.llvm.org/D37937
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313688
91177308-0d34-0410-b5e6-
96231b3b80d8
Saleem Abdulrasool [Tue, 19 Sep 2017 22:10:20 +0000 (22:10 +0000)]
CodeGen: use range based for loops (NFC)
Simplify the RPOT traversal by using a range based for loop for the
iterator dereference.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313687
91177308-0d34-0410-b5e6-
96231b3b80d8
Quentin Colombet [Tue, 19 Sep 2017 22:03:50 +0000 (22:03 +0000)]
Revert "[MIRPrinter] Print empty successor lists when they cannot be guessed"
This reverts commit r313685.
I thought I had ran ninja check, but apparently I didn't...
Need to update a bunch of mir tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313686
91177308-0d34-0410-b5e6-
96231b3b80d8
Quentin Colombet [Tue, 19 Sep 2017 21:55:51 +0000 (21:55 +0000)]
[MIRPrinter] Print empty successor lists when they cannot be guessed
Unreachable blocks in the machine instr representation are these
weird empty blocks with no successors.
The MIR printer used to not print empty lists of successors. However,
the MIR parser now treats non-printed list of successors as "please
guess it for me". As a result, the parser tries to guess the list of
successors and given the block is empty, just assumes it falls through
the next block (if any).
For instance, the following test case used to fail the verifier.
The MIR printer would print
entry
/ \
true (def) false (no list of successors)
|
split.true (use)
The MIR parser would understand this:
entry
/ \
true (def) false
| / <-- invalid edge
split.true (use)
Because of the invalid edge, we get the "def does not
dominate all uses" error.
The fix consists in printing empty successor lists, so that the parser
knows what to do for unreachable blocks.
rdar://problem/
34022159
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313685
91177308-0d34-0410-b5e6-
96231b3b80d8
Jake Ehrlich [Tue, 19 Sep 2017 21:37:35 +0000 (21:37 +0000)]
Reland "[llvm-objcopy] Add support for nested and overlapping segments"
I didn't initialize a pointer to be nullptr that I needed to.
This change adds support for nested and even overlapping segments. This means
that PT_PHDR, PT_GNU_RELRO, PT_TLS, and PT_DYNAMIC can be supported properly.
Differential Revision: https://reviews.llvm.org/D36558
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313682
91177308-0d34-0410-b5e6-
96231b3b80d8
Jonathan Roelofs [Tue, 19 Sep 2017 21:23:19 +0000 (21:23 +0000)]
[ARM] Relax 'cpsie'/'cpsid' flag parsing.
The ARM docs suggest in examples that the flags can have either case, and there
are applications in the wild that (libopencm3, for example) that expect to be
able to use the uppercase spelling.
https://reviews.llvm.org/D37953
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313680
91177308-0d34-0410-b5e6-
96231b3b80d8
Reid Kleckner [Tue, 19 Sep 2017 21:18:32 +0000 (21:18 +0000)]
Revert "[DebugInfo] Insert DW_OP_deref when spilling indirect DBG_VALUEs"
This reverts r313640, originally r313400, one more time for essentially
the same issue. My BitVector of spilled location numbers isn't working
because we coalesce identical DBG_VALUE locations as we rewrite them,
invalidating the location numbers used to index the BitVector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313679
91177308-0d34-0410-b5e6-
96231b3b80d8
Dehao Chen [Tue, 19 Sep 2017 21:18:14 +0000 (21:18 +0000)]
Import all inlined indirect call targets for SamplePGO.
Summary: In the ThinLTO compilation, if a function is inlined in the profiling binary, we need to inline it before annotation. If the callee is not available in the primary module, a first step is needed to import that callee function. For the current implementation, if the call is an indirect call, which has been promoted to >1 targets and inlined, SamplePGO will only import one target with the largest sample count. This patch fixed the bug to import all targets instead.
Reviewers: tejohnson, davidxl
Reviewed By: tejohnson
Subscribers: sanjoy, llvm-commits, mehdi_amini
Differential Revision: https://reviews.llvm.org/D36637
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313678
91177308-0d34-0410-b5e6-
96231b3b80d8
Vadzim Dambrouski [Tue, 19 Sep 2017 21:05:20 +0000 (21:05 +0000)]
[MSP430] Align functions on 2-byte boundary instead of 4.
Summary:
There is no benefit in having the 4-byte alignment, and removing this
restriction can save a lot of space for some applications.
Reviewers: asl, awygle
Reviewed By: awygle
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D36165
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313676
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Tue, 19 Sep 2017 21:03:57 +0000 (21:03 +0000)]
[TableGen] Generate formatted DAGISelEmitter without relying on formatted_raw_ostream.
The generated DAG isel file currently makes use of formatted_raw_ostream primarily for generating a hierarchical representation while also skipping over the initial comment that contains the current index.
It was reported in D37957 that this formatting might be slow due to the need to keep track of column numbers by monitoring all the written data for new lines.
This patch attempts to rewrite the emitter to make use of simpler formatting mechanisms to generate a fairly similar output. The main difference is that the number in the index comment is now right justified and padded with spaces inside the comment. Previously we appended the spaces after the comment.
Differential Revision: https://reviews.llvm.org/D37966
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313674
91177308-0d34-0410-b5e6-
96231b3b80d8
Adrian Prantl [Tue, 19 Sep 2017 20:58:57 +0000 (20:58 +0000)]
llvm-dwarfdump: un-hide more command line options
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313673
91177308-0d34-0410-b5e6-
96231b3b80d8
Adrian Prantl [Tue, 19 Sep 2017 20:58:56 +0000 (20:58 +0000)]
Move test into non-target-specific directory.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313672
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Tue, 19 Sep 2017 20:58:14 +0000 (20:58 +0000)]
[SimplifyCFG] fix typos/formatting; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313671
91177308-0d34-0410-b5e6-
96231b3b80d8
Stanislav Mekhanoshin [Tue, 19 Sep 2017 20:54:38 +0000 (20:54 +0000)]
[AMDGPU] Prevent post-RA scheduler from breaking memory clauses
The pre-RA scheduler does load/store clustering, but post-RA
scheduler undoes it. Add mutation to prevent it.
Differential Revision: https://reviews.llvm.org/D38014
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313670
91177308-0d34-0410-b5e6-
96231b3b80d8
Ulrich Weigand [Tue, 19 Sep 2017 20:50:05 +0000 (20:50 +0000)]
[SystemZ] Fix truncstore + bswap codegen bug
SystemZTargetLowering::combineSTORE contains code to transform a
combination of STORE + BSWAP into a STRV type instruction.
This transformation is correct for regular stores, but not for
truncating stores. The routine neglected to check for that case.
Fixes a miscompilation of llvm-objcopy with clang, which caused
test suite failures in the SystemZ multistage build bot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313669
91177308-0d34-0410-b5e6-
96231b3b80d8
Saleem Abdulrasool [Tue, 19 Sep 2017 20:35:25 +0000 (20:35 +0000)]
Revert "ExecutionEngine: add R_AARCH64_ABS{16,32}"
This reverts commit SVN r313654. Seems that it is triggering an
assertion on Windows specifically. Revert until I can build on Windows
and look into what is happening there.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313668
91177308-0d34-0410-b5e6-
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Jake Ehrlich [Tue, 19 Sep 2017 20:00:04 +0000 (20:00 +0000)]
Revert "[llvm-objcopy] Add support for .dynamic, .dynsym, and .dynstr"
This reverts commit r313663. Broken because overlapping-sections was
reverted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313665
91177308-0d34-0410-b5e6-
96231b3b80d8
Jake Ehrlich [Tue, 19 Sep 2017 19:52:09 +0000 (19:52 +0000)]
Revert "[llvm-objcopy] Add support for nested and overlapping segments"
This reverts commit r313656. Appears to be broken on Windows.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313664
91177308-0d34-0410-b5e6-
96231b3b80d8
Jake Ehrlich [Tue, 19 Sep 2017 19:21:09 +0000 (19:21 +0000)]
[llvm-objcopy] Add support for .dynamic, .dynsym, and .dynstr
This change adds support for sections involved in dynamic loading such
as SHT_DYNAMIC, SHT_DYNSYM, and allocated string tables.
The two added binaries used for tests can be downloaded [[
https://drive.google.com/file/d/0B3gtIAmiMwZXOXE3T0RobFg4ZTg/view?usp=sharing
| here ]] and [[
https://drive.google.com/file/d/0B3gtIAmiMwZXTFJSQUJZMGxNSXc/view?usp=sharing
| here ]]
Differential Revision: https://reviews.llvm.org/D36560
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313663
91177308-0d34-0410-b5e6-
96231b3b80d8
David Blaikie [Tue, 19 Sep 2017 19:20:08 +0000 (19:20 +0000)]
Fix test to not depend on another subdirectories Input directory
Inputs should be placed local to the test (or possibly in a common
parent? I think we do that in some places - but the only common parent
between these two directories is 'test' which seems a bit overly broad).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313662
91177308-0d34-0410-b5e6-
96231b3b80d8
Jake Ehrlich [Tue, 19 Sep 2017 19:05:15 +0000 (19:05 +0000)]
[llvm-objcopy] Add test to check that architecture specific values are not used on wrong architecture.
This change adds a test that checks the an error is produced when a hexagon
specific reserved section index is used but e_machine is not EM_HEXAGON.
Differential Revision: https://reviews.llvm.org/D38017
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313661
91177308-0d34-0410-b5e6-
96231b3b80d8
Krzysztof Parzyszek [Tue, 19 Sep 2017 18:42:34 +0000 (18:42 +0000)]
Recommit r313647 now that GCC seems to accept the offering
Add some member types to MachineValueTypeSet::const_iterator so that
iterator_traits can work with it.
Improve TableGen performance of -gen-dag-isel (motivated by X86 backend)
The introduction of parameterized register classes in r313271 caused the
matcher generation code in TableGen to run much slower, particularly so
in the unoptimized (debug) build. This patch recovers some of the lost
performance.
Summary of changes:
- Cache the set of legal types in TypeInfer::getLegalTypes. The contents
of this set do not change.
- Add LLVM_ATTRIBUTE_ALWAYS_INLINE to several small functions. Normally
this would not be necessary, but in the debug build TableGen is not
optimized, so this helps a little bit.
- Add an early exit from TypeSetByHwMode::operator== for the case when
one or both arguments are "simple", i.e. only have one mode. This
saves some time in GenerateVariants.
- Finally, replace the underlying storage type in TypeSetByHwMode::SetType
with MachineValueTypeSet based on std::array instead of std::set.
This significantly reduces the number of memory allocation calls.
I've done a number of experiments with the underlying type of InfoByHwMode.
The type is a map, and for targets that do not use the parameterization,
this map has only one entry. The best (unoptimized) performance, somewhat
surprisingly came from std::map, followed closely by std::unordered_map.
DenseMap was the slowest by a large margin.
Various hand-crafted solutions (emulating enough of the map interface
not to make sweeping changes to the users) did not yield any observable
improvements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313660
91177308-0d34-0410-b5e6-
96231b3b80d8
David Blaikie [Tue, 19 Sep 2017 18:36:11 +0000 (18:36 +0000)]
dwarfdump/symbolizer: Avoid loading unneeded CUs from a DWP
When symbolizing large binaries, parsing every CU in a DWP file is a
significant performance penalty. Instead, use the index to only load the
CUs that are needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313659
91177308-0d34-0410-b5e6-
96231b3b80d8
Dehao Chen [Tue, 19 Sep 2017 18:26:54 +0000 (18:26 +0000)]
Handle profile mismatch correctly for SamplePGO.
Summary: Fix the bug when promoted call return type mismatches with the promoted function, we should not try to inline it. Otherwise it may lead to compiler crash.
Reviewers: davidxl, tejohnson, eraman
Reviewed By: tejohnson
Subscribers: llvm-commits, sanjoy
Differential Revision: https://reviews.llvm.org/D38018
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313658
91177308-0d34-0410-b5e6-
96231b3b80d8
Reid Kleckner [Tue, 19 Sep 2017 18:14:45 +0000 (18:14 +0000)]
Re-land "Fix Bug 30978 by emitting cv file checksums."
This reverts r313431 and brings back r313374 with a fix to write
checksums as binary data and not ASCII hex strings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313657
91177308-0d34-0410-b5e6-
96231b3b80d8
Jake Ehrlich [Tue, 19 Sep 2017 18:14:03 +0000 (18:14 +0000)]
[llvm-objcopy] Add support for nested and overlapping segments
This change adds support for nested and even overlapping segments. This means
that PT_PHDR, PT_GNU_RELRO, PT_TLS, and PT_DYNAMIC can be supported properly.
Differential Revision: https://reviews.llvm.org/D36558
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313656
91177308-0d34-0410-b5e6-
96231b3b80d8
Saleem Abdulrasool [Tue, 19 Sep 2017 18:00:50 +0000 (18:00 +0000)]
ExecutionEngine: add R_AARCH64_ABS{16,32}
Add support for the R_AARCH64_ABS{16,32} relocations in the execution
engine. This is primarily used for DWARF debug information relocations
and needed by the LLVM JIT to support JITing for lldb.
Patch by Alex Langford!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313654
91177308-0d34-0410-b5e6-
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Krzysztof Parzyszek [Tue, 19 Sep 2017 17:55:07 +0000 (17:55 +0000)]
Revert "Improve TableGen performance of -gen-dag-isel (motivated by X86 backend)"
It breaks a lot of bots due to missing "__iterator_category".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313651
91177308-0d34-0410-b5e6-
96231b3b80d8
Krzysztof Parzyszek [Tue, 19 Sep 2017 17:47:53 +0000 (17:47 +0000)]
Move "(void)variable" closer to the assertion that uses it, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313649
91177308-0d34-0410-b5e6-
96231b3b80d8
Shoaib Meenai [Tue, 19 Sep 2017 17:44:42 +0000 (17:44 +0000)]
[cmake] Add SOURCE_DIR argument to llvm_check_source_file_list
The motivation is to be able to check sources outside the current
directory. See D31363 for example usage.
Differential Revision: https://reviews.llvm.org/D37859
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313648
91177308-0d34-0410-b5e6-
96231b3b80d8
Krzysztof Parzyszek [Tue, 19 Sep 2017 17:32:35 +0000 (17:32 +0000)]
Improve TableGen performance of -gen-dag-isel (motivated by X86 backend)
The introduction of parameterized register classes in r313271 caused the
matcher generation code in TableGen to run much slower, particularly so
in the unoptimized (debug) build. This patch recovers some of the lost
performance.
Summary of changes:
- Cache the set of legal types in TypeInfer::getLegalTypes. The contents
of this set do not change.
- Add LLVM_ATTRIBUTE_ALWAYS_INLINE to several small functions. Normally
this would not be necessary, but in the debug build TableGen is not
optimized, so this helps a little bit.
- Add an early exit from TypeSetByHwMode::operator== for the case when
one or both arguments are "simple", i.e. only have one mode. This
saves some time in GenerateVariants.
- Finally, replace the underlying storage type in TypeSetByHwMode::SetType
with MachineValueTypeSet based on std::array instead of std::set.
This significantly reduces the number of memory allocation calls.
I've done a number of experiments with the underlying type of InfoByHwMode.
The type is a map, and for targets that do not use the parameterization,
this map has only one entry. The best (unoptimized) performance, somewhat
surprisingly came from std::map, followed closely by std::unordered_map.
DenseMap was the slowest by a large margin.
Various hand-crafted solutions (emulating enough of the map interface
not to make sweeping changes to the users) did not yield any observable
improvements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313647
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Tue, 19 Sep 2017 17:19:45 +0000 (17:19 +0000)]
[X86] Convert X86ISD::SELECT to ISD::VSELECT just before instruction selection to avoid duplicate patterns
Similar to what we do for X86ISD::SHRUNKBLEND just turn X86ISD::SELECT into ISD::VSELECT. This allows us to remove the duplicated TRUNC patterns.
Differential Revision: https://reviews.llvm.org/D38022
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313644
91177308-0d34-0410-b5e6-
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Zachary Turner [Tue, 19 Sep 2017 17:19:10 +0000 (17:19 +0000)]
Resubmit "Fix llvm-lit script generation in libcxx."
After speaking with the libcxx owners, they agreed that this is
a bug in the bot that needs to be fixed by the bot owners, and
the CMake changes are correct.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313643
91177308-0d34-0410-b5e6-
96231b3b80d8
Reid Kleckner [Tue, 19 Sep 2017 16:32:15 +0000 (16:32 +0000)]
Re-land r313400 "[DebugInfo] Insert DW_OP_deref when spilling indirect DBG_VALUEs"
I forgot to zero out the BitVector when reusing it between UserValues.
Later uses of the same location number for a different UserValue would
falsely indicate that they were spilled. Usually this would lead to
incorrect debug info, but in some cases they would indicate something
nonsensical like a memory location based on a vector register (Q8 on
ARM).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313640
91177308-0d34-0410-b5e6-
96231b3b80d8
Tony Jiang [Tue, 19 Sep 2017 16:14:37 +0000 (16:14 +0000)]
[PowerPC Peephole] Constants into a join add, use ADDI over LI/ADD.
Two blocks prior to the join each perform an li and the the join block has an
add using the initialized register. Optimize each predecessor block to instead
use addi and delete the li's and add.
Differential Revision: https://reviews.llvm.org/D36734
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313639
91177308-0d34-0410-b5e6-
96231b3b80d8
Evandro Menezes [Tue, 19 Sep 2017 15:46:35 +0000 (15:46 +0000)]
[AArch64] Extend tests of loads and stores of register pairs
Include instances of FP register pairs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313638
91177308-0d34-0410-b5e6-
96231b3b80d8
Tony Jiang [Tue, 19 Sep 2017 15:22:36 +0000 (15:22 +0000)]
[Power9] Add missing Power9 instructions.
The following 8 instructions are implemented in this patch.
addpcis(subpcis, lnia), darn, maddhd, maddhdu, maddld, setb
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313636
91177308-0d34-0410-b5e6-
96231b3b80d8
David Blaikie [Tue, 19 Sep 2017 15:13:55 +0000 (15:13 +0000)]
dwarfdump: Delay parsing abbreviations until they're needed
This speeds up dumping specific DIEs by not parsing abbreviations for
units that are not used.
(this is also handy to have in eventually to speed up llvm-symbolizer
for .dwp files, where parsing most of the DWP file can be avoided by
using the index)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313635
91177308-0d34-0410-b5e6-
96231b3b80d8
Daniel Sanders [Tue, 19 Sep 2017 14:25:15 +0000 (14:25 +0000)]
[globalisel] Add a G_BSWAP instruction and support bswap using it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313633
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Tue, 19 Sep 2017 14:02:16 +0000 (14:02 +0000)]
[X86][SSE] Add 'redundant pand' test case from PR34620
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313632
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Tue, 19 Sep 2017 13:43:09 +0000 (13:43 +0000)]
[x86] regenerate checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313631
91177308-0d34-0410-b5e6-
96231b3b80d8
Alexey Bataev [Tue, 19 Sep 2017 13:38:56 +0000 (13:38 +0000)]
[SLP] Reduce test, NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313630
91177308-0d34-0410-b5e6-
96231b3b80d8
Daniel Sanders [Tue, 19 Sep 2017 13:23:01 +0000 (13:23 +0000)]
[globalisel] Add support for intrinsic_void
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313629
91177308-0d34-0410-b5e6-
96231b3b80d8
Daniel Sanders [Tue, 19 Sep 2017 12:56:36 +0000 (12:56 +0000)]
[globalisel] Add support for intrinsic_w_chain.
This maps directly to G_INTRINSIC_W_SIDE_EFFECTS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313627
91177308-0d34-0410-b5e6-
96231b3b80d8
Nikolai Bozhenov [Tue, 19 Sep 2017 11:54:29 +0000 (11:54 +0000)]
[Nios2] Subtarget, basic infrastructure for frame, instructions and registers
This is the second minimal patch keeping Nios2 target buildable.
I'm adding subtarget here and other stuff for frame lowering, instruction,
register information methods. I do not add any test cases, as still there
are missing parts like DAG selector and assembly printing. I plan to include
them into the next patch.
Patch by Andrei Grischenko <andrei.l.grischenko@intel.com>
Differential Revision: https://reviews.llvm.org/D37256
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313626
91177308-0d34-0410-b5e6-
96231b3b80d8
Jina Nahias [Tue, 19 Sep 2017 11:03:06 +0000 (11:03 +0000)]
[x86] Lowering Mask Set1 intrinsics to LLVM IR
This patch, together with a matching clang patch (https://reviews.llvm.org/D37668), implements the lowering of X86 mask set1 intrinsics to IR.
Differential Revision: https://reviews.llvm.org/D37669
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313625
91177308-0d34-0410-b5e6-
96231b3b80d8
Roger Ferrer Ibanez [Tue, 19 Sep 2017 09:05:39 +0000 (09:05 +0000)]
[ARM] Use ADDCARRY / SUBCARRY
This is a preparatory step for D34515.
This change:
- makes nodes ISD::ADDCARRY and ISD::SUBCARRY legal for i32
- lowering is done by first converting the boolean value into the carry flag
using (_, C) ← (ARMISD::ADDC R, -1) and converted back to an integer value
using (R, _) ← (ARMISD::ADDE 0, 0, C). An ARMISD::ADDE between the two
operations does the actual addition.
- for subtraction, given that ISD::SUBCARRY second result is actually a
borrow, we need to invert the value of the second operand and result before
and after using ARMISD::SUBE. We need to invert the carry result of
ARMISD::SUBE to preserve the semantics.
- given that the generic combiner may lower ISD::ADDCARRY and
ISD::SUBCARRYinto ISD::UADDO and ISD::USUBO we need to update their lowering
as well otherwise i64 operations now would require branches. This implies
updating the corresponding test for unsigned.
- add new combiner to remove the redundant conversions from/to carry flags
to/from boolean values (ARMISD::ADDC (ARMISD::ADDE 0, 0, C), -1) → C
- fixes PR34045
- fixes PR34564
Differential Revision: https://reviews.llvm.org/D35192
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313618
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Andrei Elovikov [Tue, 19 Sep 2017 07:56:20 +0000 (07:56 +0000)]
Test commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313617
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Matt Arsenault [Tue, 19 Sep 2017 07:40:11 +0000 (07:40 +0000)]
AMDGPU: Run internalize symbols at -O0
The relocations used for externally visible functions
aren't supported, so the direct call emitted ends
up hitting a linker error.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313616
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Gadi Haber [Tue, 19 Sep 2017 06:19:27 +0000 (06:19 +0000)]
[X86][Skylake] Adding the scheduling information for the SkylakeClient target
This patch adds the instruction scheduling information for the SkylakeClient (SKL) architecture target by adding the file X86SchedSkylakeClient.td located under the X86 Target.
We used the scheduling information retrieved from the Skylake architects in order to create the file.
The scheduling information includes latency, number of micro-Ops and used ports by each SKL instruction.
The patch continues the scheduling replacement and insertion effort started with the SNB target in r307529 and r310792 and for HSW in r311879.
Please expect some performance fluctuations due to code alignment effects.
Reviewers: craig.topper, zvi, chandlerc, igorb, aymanmus, RKSimon, delena
Differential Revision: https://reviews.llvm.org/D37294
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313613
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Craig Topper [Tue, 19 Sep 2017 05:30:24 +0000 (05:30 +0000)]
[X86] Remove some unnecessary patterns for truncate with X86ISD::SELECT and undef preserved source.
We canonicalize undef preserved sources to zero during intrinsic lowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313612
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Hongbin Zheng [Tue, 19 Sep 2017 04:59:27 +0000 (04:59 +0000)]
[LLVM] [RegionInfo] Introduce getExitingBlocks to get all predecessors of Exit in the current region.
This function will return true if all predecessors of Exit are in the current region, false otherwise.
Differential Revision: https://reviews.llvm.org/D36210
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313611
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Craig Topper [Tue, 19 Sep 2017 04:39:55 +0000 (04:39 +0000)]
[X86] Add VPERMPD/VPERMQ and VPERMPS/VPERMD to the execution domain fixing table.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313610
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