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Teresa Johnson [Tue, 10 Nov 2015 21:09:06 +0000 (21:09 +0000)]
Ensure ModuleLinker materializes complete comdat groups
Summary:
The module linker lazy links some "discardable if unused" global
values (e.g. linkonce), materializing and linking them only
if they are referenced in the module. If a comdat group contains a
linkonce member that is not referenced, however, it would not be
materialized and linked, leading to an incomplete comdat group.
If there are other object files not part of the same LTO link that also
define and use that comdat group, the linker may select the incomplete
group leading to link time unsats.
To solve this, whenever a global value body is linked, make sure we
materialize any other members of the same comdat group that are not yet
materialized. This ensures they are in the lazy link list and get linked
as well.
Added new test and adjusted old test to remove parts that didn't
make sense with fix.
Reviewers: rafael
Subscribers: dexonsmith, davidxl, llvm-commits
Differential Revision: http://reviews.llvm.org/D14516
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252647
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Sanjoy Das [Tue, 10 Nov 2015 20:13:21 +0000 (20:13 +0000)]
[IR] Make {Call,Invoke}::cloneImpl aware of operand bundles
This was an omission in the patch that landed initial support for
operand bundles. So far we haven't hit this, but we will once the
inliner is able to inline calls to functions that contain calls with
operand bundles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252645
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Sanjoy Das [Tue, 10 Nov 2015 20:13:15 +0000 (20:13 +0000)]
[OperandBundles] Identify operand bundles with both their names and IDs
No code uses this functionality yet. This change just exposes
information / structure that was already present.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252644
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Sanjay Patel [Tue, 10 Nov 2015 20:09:02 +0000 (20:09 +0000)]
less indent; NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252643
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Sanjay Patel [Tue, 10 Nov 2015 19:24:31 +0000 (19:24 +0000)]
[ARM] add overrides for isCheapToSpeculateCttz() and isCheapToSpeculateCtlz()
ARM V6T2 has instructions for efficient count-leading/trailing-zeros, so this should be
considered a cheap operation (and therefore fair game for speculation) for any ARM V6T2
implementation.
The net result of allowing this speculation for the regression tests in this patch is
that we get this code:
ctlz:
clz r0, r0
bx lr
cttz:
rbit r0, r0
clz r0, r0
bx lr
Instead of:
ctlz:
cmp r0, #0
moveq r0, #32
clzne r0, r0
bx lr
cttz:
cmp r0, #0
moveq r0, #32
rbitne r0, r0
clzne r0, r0
bx lr
This will help solve a general speculation/despeculation problem noted in PR24818:
https://llvm.org/bugs/show_bug.cgi?id=24818
Differential Revision: http://reviews.llvm.org/D14469
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252639
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Yunzhong Gao [Tue, 10 Nov 2015 18:52:48 +0000 (18:52 +0000)]
llvm-lto: trivial spelling changes to distinguish custom diagnostic handler and
default diagnostic handler.
Differential Revision: http://reviews.llvm.org/D14520
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252633
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Matt Arsenault [Tue, 10 Nov 2015 18:48:11 +0000 (18:48 +0000)]
LegalizeDAG: Implement promote for scalar_to_vector
This allows avoiding the default Expand behavior which
introduces stack usage. Bitcast the scalar and replace
the missing elements with undef.
This is covered by existing tests and used by a future
commit which makes 64-bit vectors legal types on AMDGPU.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252632
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Matt Arsenault [Tue, 10 Nov 2015 18:48:08 +0000 (18:48 +0000)]
LegalizeDAG: Implement promote for insert_vector_elt
This is covered by existing tests and used by a future
commit which makes 64-bit vectors legal types on AMDGPU.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252631
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Matt Arsenault [Tue, 10 Nov 2015 18:48:04 +0000 (18:48 +0000)]
LegalizeDAG: Implement promote for extract_vector_elt
This is for AMDGPU to implement v2i64 extract as extract of
half of a v4i32.
This is covered by existing tests and used by a future
commit which makes 64-bit vectors legal types on AMDGPU.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252630
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Philip Reames [Tue, 10 Nov 2015 18:46:14 +0000 (18:46 +0000)]
[ValueTracking] Recognize that and(x, add (x, -1)) clears the low bit
This is a cleaned up version of a patch by John Regehr with permission. Originally found via the souper tool.
If we add an odd number to x, then bitwise-and the result with x, we know that the low bit of the result must be zero. Either it was zero in x originally, or the add cleared it in the temporary value. As a result, one of the two values anded together must have the bit cleared.
Differential Revision: http://reviews.llvm.org/D14315
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252629
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Ramkumar Ramachandra [Tue, 10 Nov 2015 18:26:34 +0000 (18:26 +0000)]
AddLLVM: squelch CMP0007 by not adding empty elements to list
When configuring various llvm projects that use AddLLVM.cmake, this warning is
emitted many times, flooding the screen:
Policy CMP0007 is not set: list command no longer ignores empty elements.
The fix is removing an extra semicolon.
Differential Revision: http://reviews.llvm.org/D14339
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252628
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Teresa Johnson [Tue, 10 Nov 2015 18:26:31 +0000 (18:26 +0000)]
[ThinLTO] Update comment per change in WeakAny handling (NFC)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252627
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Teresa Johnson [Tue, 10 Nov 2015 18:20:11 +0000 (18:20 +0000)]
[ThinLTO] WeakAny fixes/cleanup
Ensure WeakAny variables are imported as ExternalWeak declarations. To
handle WeakAny more consistently and fix this issue:
1) Update helper doImportAsDefinition to properly flag WeakAny variables
and aliases as not importing defintions.
Update callers of doImportAsDefinition to remove now redundant checks for
WeakAny aliases, or ignore aliases, as appropriate.
2) Add any !doImportAsDefinition GVs to DoNotLinkFromSource set during
linking of the GV prototype, where we usually add GVs to the
DoNotLinkFromSource set for other reasons.
Remove now unnecessary adding of WeakAny aliases to
DoNotLinkFromSource set from copyGlobalAliasProto.
Remove now unnecessary guard against linking non-imported function
bodies from ModuleLinker::run.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252626
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Sanjay Patel [Tue, 10 Nov 2015 18:11:37 +0000 (18:11 +0000)]
[AArch64] add overrides for isCheapToSpeculateCttz() and isCheapToSpeculateCtlz()
AArch64 has instructions for efficient count-leading/trailing-zeros, so this should be
considered a cheap operation (and therefore fair game for speculation) for any AArch64
implementation.
The net result of allowing this speculation for the regression tests in this
patch is that we get this code:
ctlz:
clz w0, w0
ret
cttz:
rbit w8, w0
clz w0, w8
ret
Instead of:
ctlz:
cbz w0, .LBB0_2
clz w0, w0
ret
.LBB0_2:
orr w0, wzr, #0x20
ret
cttz:
cbz w0, .LBB1_2
rbit w8, w0
clz w0, w8
ret
.LBB1_2:
orr w0, wzr, #0x20
ret
See D14469 for the larger motivation.
Differential Revision: http://reviews.llvm.org/D14505
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252625
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Renato Golin [Tue, 10 Nov 2015 18:01:16 +0000 (18:01 +0000)]
Revert "Strip metadata when speculatively hoisting instructions"
This reverts commit r252604, as it broke all ARM and AArch64 buildbots, as
well as some x86, et al.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252623
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Michael Kuperstein [Tue, 10 Nov 2015 17:37:49 +0000 (17:37 +0000)]
[X86] Do not try to custom-lower sitofp/fptosi in soft-float mode
Differential Revision: http://reviews.llvm.org/D14495
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252621
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Xinliang David Li [Tue, 10 Nov 2015 17:11:33 +0000 (17:11 +0000)]
Fix asan warning (NFC)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252617
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Sanjay Patel [Tue, 10 Nov 2015 16:48:53 +0000 (16:48 +0000)]
add 'MustReduceDepth' as an objective/cost-metric for the MachineCombiner
This is one of the problems noted in PR25016:
https://llvm.org/bugs/show_bug.cgi?id=25016
and:
http://lists.llvm.org/pipermail/llvm-dev/2015-October/090998.html
The spilling problem is independent and not addressed by this patch.
The MachineCombiner was doing reassociations that don't improve or even worsen the critical path.
This is caused by inclusion of the "slack" factor when calculating the critical path of the original
code sequence. If we don't add that, then we have a more conservative cost comparison of the old code
sequence vs. a new sequence. The more liberal calculation must be preserved, however, for the AArch64
MULADD patterns because benchmark regressions were observed without that.
The two failing test cases now have identical asm that does what we want:
a + b + c + d ---> (a + b) + (c + d)
Differential Revision: http://reviews.llvm.org/D13417
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252616
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James Molloy [Tue, 10 Nov 2015 14:22:05 +0000 (14:22 +0000)]
Reapply "[ARM] Combine CMOV into BFI where possible"
Added fixes for stage2 failures: CMOV is not commutable; commuting the operands results in the condition being flipped! d'oh!
Original commit message:
If we have a CMOV, OR and AND combination such as:
if (x & CN)
y |= CM;
And:
* CN is a single bit;
* All bits covered by CM are known zero in y;
Then we can convert this to a sequence of BFI instructions. This will always be a win if CM is a single bit, will always be no worse than the TST & OR sequence if CM is two bits, and for thumb will be no worse if CM is three bits (due to the extra IT instruction).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252606
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Igor Laevsky [Tue, 10 Nov 2015 14:10:31 +0000 (14:10 +0000)]
Strip metadata when speculatively hoisting instructions
This is fix for PR24059.
When we are hoisting instruction above some condition it may turn out
that metadata on this instruction was control dependant on the condition.
This metadata becomes invalid and we need to drop it.
This patch should cover most obvious places of speculative execution (which
I have found by greping isSafeToSpeculativelyExecute). I think there are more
cases but at least this change covers the severe ones.
Differential Revision: http://reviews.llvm.org/D14398
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252604
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Oliver Stannard [Tue, 10 Nov 2015 14:09:08 +0000 (14:09 +0000)]
Update test to use explicit triple
This is needed for targets which do not support big-endian with the default
triple.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252603
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Tilmann Scheller [Tue, 10 Nov 2015 12:29:37 +0000 (12:29 +0000)]
[PowerPC] Remove redundant code.
The local variable Hi is never being read.
Issue identified by the Clang static analyzer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252600
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Oliver Stannard [Tue, 10 Nov 2015 11:04:18 +0000 (11:04 +0000)]
[AArch64] Fix halfword load merging for big-endian targets
For big-endian targets, when we merge two halfword loads into a word load, the
order of the halfwords in the loaded value is reversed compared to
little-endian, so the load-store optimiser needs to swap the destination
registers.
This does not affect merging of two word loads, as we use ldp, which treats the
memory as two separate 32-bit words.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252597
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Hans Wennborg [Tue, 10 Nov 2015 09:47:48 +0000 (09:47 +0000)]
Inliner: Do zero-cost inlines even if above a negative threshold (PR24851)
Differential Revision: http://reviews.llvm.org/D14499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252595
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Igor Breger [Tue, 10 Nov 2015 07:09:07 +0000 (07:09 +0000)]
AVX512 : Implemented encoding and DAG lowering for VMOVHPS/PD and VMOVLPS/PD instructions.
Differential Revision: http://reviews.llvm.org/D14492
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252592
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David Blaikie [Tue, 10 Nov 2015 04:10:04 +0000 (04:10 +0000)]
Remove another variable unused in -Asserts build
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252582
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David Blaikie [Tue, 10 Nov 2015 03:16:28 +0000 (03:16 +0000)]
Remove some unused variables to clean up the -Werror build
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252580
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Colin LeMahieu [Tue, 10 Nov 2015 01:58:26 +0000 (01:58 +0000)]
[Hexagon] Adding instruction aliases and tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252579
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Andy Ayers [Tue, 10 Nov 2015 01:50:49 +0000 (01:50 +0000)]
Support for emitting inline stack probes
For CoreCLR on Windows, stack probes must be emitted as inline sequences that probe successive stack pages
between the current stack limit and the desired new stack pointer location. This implements support for
the inline expansion on x64.
For in-body alloca probes, expansion is done during instruction lowering. For prolog probes, a stub call
is initially emitted during prolog creation, and expanded after epilog generation, to avoid complications
that arise when introducing new machine basic blocks during prolog and epilog creation.
Added a new test case, modified an existing one to exclude non-x64 coreclr (for now).
Add test case
Fix tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252578
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Richard Diamond [Tue, 10 Nov 2015 01:03:51 +0000 (01:03 +0000)]
Fix mingw targets. Bandaid for r252532's buildbot brakage.
Reviewers: brad.king, beanz
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D14523
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252576
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Colin LeMahieu [Tue, 10 Nov 2015 00:51:56 +0000 (00:51 +0000)]
[Hexagon] Fixing compound register printing and reenabling more tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252574
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Tim Northover [Tue, 10 Nov 2015 00:44:23 +0000 (00:44 +0000)]
AArch64: add experimental support for address tagging.
AArch64 has the ability to use the top 8-bits of an "address" for extra
information, with the memory subsystem automatically masking them off for loads
and stores. When that's happening, we can sometimes skip masks on memory
operations in the compiler.
However, this requires the host OS and support stack to preserve those bits so
it can't be enabled everywhere. In principle iOS 8.0 and above do take the
required precautions and but we'll put it under a flag for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252573
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Kevin Enderby [Tue, 10 Nov 2015 00:31:08 +0000 (00:31 +0000)]
Fix llvm-nm(1) printing of llvm-bitcode files for -format darwin to match darwin’s nm(1).
Also a small fix to match printing of Mach-O objects with -format posix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252567
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Derek Schuff [Tue, 10 Nov 2015 00:30:57 +0000 (00:30 +0000)]
[WebAssembly] Support 'unreachable' expression
Lower LLVM's 'unreachable' terminator to ISD::TRAP, and lower ISD::TRAP to
wasm's 'unreachable' expression.
WebAssembly type-checks expressions, but a noreturn function with a
return type that doesn't match the context will cause a check
failure. So we lower LLVM 'unreachable' to ISD::TRAP and then lower that
to WebAssembly's 'unreachable' expression, which typechecks in any
context and causes a trap if executed.
Differential Revision: http://reviews.llvm.org/D14515
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252566
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Matt Arsenault [Tue, 10 Nov 2015 00:30:14 +0000 (00:30 +0000)]
Remove unnecessary call to getAllocatableRegClass
I'm not sure what the point of this was. I'm not sure why
you would ever define an instruction that produces an unallocatable
register class. No tests fail with this removed, and it seems like
it should be a verifier error to define such an instruction.
This was problematic for AMDGPU because it would make bad decisions
by arbitrarily changing the register class when unsetting isAllocatable
for VS_32/VS_64, which is currently set as a workaround to this problem.
AMDGPU uses the VS_32/VS_64 register classes to represent operands which
can use either VGPRs or SGPRs. When isAllocatable is unset for these,
this would need to pick either the SGPR or VGPR class and insert either
a copy we don't want, or an illegal copy we would need to deal with
later. A semi-arbitrary register class ordering decision is made in tablegen,
which resulted in always picking a VGPR class because it happens to have
more registers than the SGPR register class. We really just want to
use whatever register class the original register had.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252565
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Xinliang David Li [Tue, 10 Nov 2015 00:24:45 +0000 (00:24 +0000)]
[PGO] Make indexed value profile data more compact
- Make indexed value profile data more compact by peeling out
the per-site value count field into its own smaller sized array.
- Introduced formal data structure definitions to specify value
profile data layout in indexed format. Previously the layout
of the data is only assumed in the client code (scattered in
three different places : size computation, EmitData, and ReadData
- The new data structure serves as a central place for layout documentation.
- Add interfaces to force BE output for value profile data (testing purpose)
- Add byte swap unit tests
Differential Revision: http://reviews.llvm.org/D14401
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252563
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Colin LeMahieu [Tue, 10 Nov 2015 00:22:00 +0000 (00:22 +0000)]
[Hexagon] Fixing store instructions and reenabling a few more tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252561
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Akira Hatanaka [Tue, 10 Nov 2015 00:10:41 +0000 (00:10 +0000)]
[ARM] Handle t2ADDri in ARMAsmPrinter::EmitUnwindingInstruction.
This fixes a bug in ARMAsmPrinter::EmitUnwindingInstruction where
llvm_unreachable was reached because t2ADDri wasn't handled.
Test case provided by Tim Northover.
rdar://problem/
23270609
http://reviews.llvm.org/D14518
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252557
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Colin LeMahieu [Tue, 10 Nov 2015 00:02:27 +0000 (00:02 +0000)]
[Hexagon] Fixing load instruction parsing and reenabling tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252555
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Matthias Braun [Mon, 9 Nov 2015 23:59:33 +0000 (23:59 +0000)]
MachineVerifier: Streamline live interval related error reporting
Simply perform additional report_context() calls after a report()
instead of adding more and more overloaded variations of report(). Also
improve several instances where information was output in an ad-hoc way
probably because no matching report() overload was available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252552
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Matthias Braun [Mon, 9 Nov 2015 23:59:29 +0000 (23:59 +0000)]
MachineVerifier: Add missing linebreak
MachineInstr::print() with SkipOppers==true does not produce a
linebreak, so we have to do that in MachineVerifier::report().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252551
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Matthias Braun [Mon, 9 Nov 2015 23:59:25 +0000 (23:59 +0000)]
MachineVerifier: MI::print has no TargetMachine overload
The code was passing a target machine pointer which degraded to a true
operand to SkipOppers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252550
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Matthias Braun [Mon, 9 Nov 2015 23:59:23 +0000 (23:59 +0000)]
MachineVerifier: print list of live intervals if available
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252549
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David Blaikie [Mon, 9 Nov 2015 23:51:45 +0000 (23:51 +0000)]
Simplify some APIs I was cleaning up while fixing -Wpessimizing-move warning
(Reid fixed the original error, but this seems nice to do in any case)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252548
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Reid Kleckner [Mon, 9 Nov 2015 23:37:26 +0000 (23:37 +0000)]
Fix -Wpessimizing-move warning in llvm-config.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252542
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Reid Kleckner [Mon, 9 Nov 2015 23:34:42 +0000 (23:34 +0000)]
[WinEH] Remove isBarrier from instructions that do not return
Fixes machine verification failures with David's latest EH change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252541
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Sanjay Patel [Mon, 9 Nov 2015 23:31:38 +0000 (23:31 +0000)]
add a SelectionDAG method to check if no common bits are set in two nodes; NFCI
This was suggested in:
http://reviews.llvm.org/D13956
and is a follow-on to:
http://reviews.llvm.org/rL252515
http://reviews.llvm.org/rL252519
This lets us remove logically equivalent/duplicated code from DAGCombiner and X86ISelDAGToDAG.
A corresponding function for IR instructions already exists in ValueTracking.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252539
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Duncan P. N. Exon Smith [Mon, 9 Nov 2015 23:31:01 +0000 (23:31 +0000)]
CodeGen: Be clear about semantics in SlotIndex::getNextSlot(), NFC
Be honest about using iterator semantics in `SlotIndex::getNextSlot()`
and `SlotIndex::getPrevSlot()`. Instead of calling `getNextNode()` --
which is documented (but fails) to check for the sentinel -- call
`&*++getIterator()`.
This is (surprisingly!) a NFC commit. `ilist_traits<IndexListEntry>`
has an `ilist_half_node<IndexListEntry>` as a sentinel (and no other
fields), and so the layout of `ilist<IndexListEntry>` is:
--
struct ilist<IndexListEntry> {
ilist_half_node<IndexListEntry> Sentinel;
IndexListEntry *Head;
IndexListEntry *getHead() { return Head; }
IndexListEntry *getSentinel() { return cast<...>(&Sentinel); }
};
--
In memory, this happens to look just like:
--
struct ilist<IndexListEntry> {
ilist_node<IndexListEntry> Sentinel;
IndexListEntry *getHead() { return Sentinel.getNext(); }
IndexListEntry *getSentinel() { return cast<...>(&Sentinel); }
};
--
As a result, `ilist_node<IndexListEntry>::getNextNode()` that checks
`getNext()` of the possible sentinel will get a pointer to the head of
the list; it will never detect the sentinel, and will return the
sentinel itself instead of `nullptr` in the special cases.
Since `getNextNode()` and `getPrevNode()` don't work, just be honest
that we're not checking for the end/beginning of the list here. Since
this code works, I guess we must never go past the sentinel.
(It's possible we're just getting lucky, and the new code will get
"lucky" in the same situations. To properly fix that hypothetical bug,
we would need to check the iterator against `end()`/`begin()`.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252538
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David Blaikie [Mon, 9 Nov 2015 23:30:15 +0000 (23:30 +0000)]
Fix -Wdeprecated warnings due to the use of copy ops on SCEVPredicate derived class objects
SCEVUnionPredicate is copied constructed here: lib/Transforms/Scalar/LoopDistribute.cpp:793
and move assigned (which can use the base class's copy ctor just
fine/without extra cost (I'd add it if it weren't for MSVC's issues
meaning = default is insufficient)) here: lib/Transforms/Utils/LoopVersioning.cpp:46
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252537
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Davide Italiano [Mon, 9 Nov 2015 23:23:20 +0000 (23:23 +0000)]
[TargetLibraryInfo] Add support for fls, flsl, flsll.
This is a prerequisite for further optimisations of these functions,
which will be commited as a separate patch.
Differential Revision: http://reviews.llvm.org/D14219
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252535
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Kostya Serebryany [Mon, 9 Nov 2015 23:17:45 +0000 (23:17 +0000)]
[libFuzzer] make libFuzzer link if there is no sanitizer coverage instrumentation (it will fail at start-up time)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252533
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Richard Diamond [Mon, 9 Nov 2015 23:15:38 +0000 (23:15 +0000)]
Fix `llvm-config` to adapt to the install environment.
Summary:
This patch does a couple of things:
- Adds a new argument `--shared-mode` which accepts a list of components and prints whether or not the provided components need to be linked statically or shared.
- Fixes `--libnames` when CMake BUILD_SHARED_LIBS is used.
- Fixes `--libnames`, `--libs`, and `--libfiles` for dylib when static components aren't installed.
- Fixes `--libnames`, `--libs`, `--libfiles`, and `--components` to use LLVM_DYLIB_COMPONENTS as the component manifest for dylib linking.
- Uses the host platform's usual convention for filename extensions and such, instead of always defaulting to Unix-izms.
Because I don't own a Mac, I am not able to test the Mac platform dependent stuff locally. If someone would be willing to run a build for me on their machine (unless there's a better option), I'd appreciate it.
Reviewers: jfb, brad.king, whitequark, beanz
Subscribers: beanz, jauhien, llvm-commits
Differential Revision: http://reviews.llvm.org/D13198
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252532
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Reid Kleckner [Mon, 9 Nov 2015 23:10:29 +0000 (23:10 +0000)]
Combine ifdefs around dl_iterate_phdr in Unix/Signals.inc
This avoids the need to have two dummy implementations of
findModulesAndOffsets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252531
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David Majnemer [Mon, 9 Nov 2015 23:07:48 +0000 (23:07 +0000)]
[WinEH] Don't emit CATCHRET from visitCatchPad
Instead, emit a CATCHPAD node which will get selected to a target
specific sequence.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252528
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Chris Bieneman [Mon, 9 Nov 2015 21:54:55 +0000 (21:54 +0000)]
Deprecate Autoconf
As per the very positive feedback from llvm-dev (http://lists.llvm.org/pipermail/llvm-dev/2015-November/092150.html), this commit officially deprecates the LLVM autoconf-based build system.
Anyone still using it should switch to CMake.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252520
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Sanjay Patel [Mon, 9 Nov 2015 21:53:58 +0000 (21:53 +0000)]
specify triple so Windows bots won't be sad
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252519
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Rafael Espindola [Mon, 9 Nov 2015 21:34:45 +0000 (21:34 +0000)]
Add templated read/write to support::endian.
Expose read and write functions that take endianess as a template
parameter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252517
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Sanjay Patel [Mon, 9 Nov 2015 21:16:49 +0000 (21:16 +0000)]
[x86] try harder to match bitwise 'or' into an LEA
The motivation for this patch starts with the epic fail example in PR18007:
https://llvm.org/bugs/show_bug.cgi?id=18007
...unfortunately, this patch makes no difference for that case, but it solves some
simpler cases. We'll get there some day. :)
The current 'or' matching code was using computeKnownBits() via
isBaseWithConstantOffset() -> MaskedValueIsZero(), but that's an unnecessarily limited use.
We can do more by copying the logic in ValueTracking's haveNoCommonBitsSet(), so we can
treat the 'or' as if it was an 'add'.
There's a TODO comment here because we should lift the bit-checking logic into a helper
function, so it's not duplicated in DAGCombiner.
An example of the better LEA matching:
leal (%rdi,%rdi), %eax
andl $1, %esi
orl %esi, %eax
Becomes:
andl $1, %esi
leal (%rsi,%rdi,2), %eax
Differential Revision: http://reviews.llvm.org/D13956
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252515
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Colin LeMahieu [Mon, 9 Nov 2015 21:06:28 +0000 (21:06 +0000)]
[Hexagon] Separating statement to match what clang-format would do.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252513
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Reid Kleckner [Mon, 9 Nov 2015 21:04:00 +0000 (21:04 +0000)]
[WinEH] Tweak funclet prologue/epilogue insertion to pass verifier
For some reason we'd never run MachineVerifier on WinEH code, and you
explicitly have to ask for it with llc. I added it to a few test cases
to get some coverage.
Fixes PR25461.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252512
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Andrew Kaylor [Mon, 9 Nov 2015 19:59:02 +0000 (19:59 +0000)]
[WinEH] Re-committing r252249 (Clone funclets with multiple parents) with additional fixes for determinism problems
Differential Revision: http://reviews.llvm.org/D14454
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252508
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Reid Kleckner [Mon, 9 Nov 2015 19:44:38 +0000 (19:44 +0000)]
[Hexagon] Fix -Wmicrosoft-enum-value warning with explicit enum type
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252505
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Mike Aizatsky [Mon, 9 Nov 2015 19:36:53 +0000 (19:36 +0000)]
Windows-specific test for sys::path::remove_dots.
Differential Revision: http://reviews.llvm.org/D14503
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252504
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Sanjay Patel [Mon, 9 Nov 2015 19:18:26 +0000 (19:18 +0000)]
don't repeat function names in comments; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252502
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Sanjay Patel [Mon, 9 Nov 2015 18:59:30 +0000 (18:59 +0000)]
fix formatting; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252500
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Mike Aizatsky [Mon, 9 Nov 2015 18:56:31 +0000 (18:56 +0000)]
Moving FileManager::removeDotPaths to llvm::sys::path::remove_dots
Differential Revision: http://reviews.llvm.org/D14393
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252499
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Adhemerval Zanella [Mon, 9 Nov 2015 18:03:48 +0000 (18:03 +0000)]
[sanitizer] Use same shadow offset for ASAN on aarch64
This patch makes ASAN for aarch64 use the same shadow offset for all
currently supported VMAs (39 and 42 bits). The shadow offset is the
same for 39-bit (36). Similar to ppc64 port, aarch64 transformation
also requires to use an add instead of 'or' for 42-bit VMA.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252495
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Dehao Chen [Mon, 9 Nov 2015 17:30:38 +0000 (17:30 +0000)]
Add discriminators for call instructions that are from the same line and same basic block.
Summary: Call instructions that are from the same line and same basic block needs to have separate discriminators to distinguish between different callsites.
Reviewers: davidxl, dnovillo, dblaikie
Subscribers: dblaikie, probinson, llvm-commits
Differential Revision: http://reviews.llvm.org/D14464
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252492
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Chad Rosier [Mon, 9 Nov 2015 16:56:06 +0000 (16:56 +0000)]
Simplify. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252491
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Oliver Stannard [Mon, 9 Nov 2015 16:47:16 +0000 (16:47 +0000)]
GlobalOpt should maintain externally_initialized when splitting aggregates
When GlobalOpt splits an internal, global variable with an aggregate type, it
should propagate the externally_initialized flag to the newly created globals.
This makes the pass safe for our downstream use of this flag, while still
allowing some useful optimisations (such as removing dead parts of the split
aggregate) to be performed.
Differential Revision: http://reviews.llvm.org/D13382
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252490
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Jonathan Roelofs [Mon, 9 Nov 2015 16:10:00 +0000 (16:10 +0000)]
Create Makefile variables for 'share' and 'libexec'
in preparation for a Clang commit.
http://reviews.llvm.org/D14405
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252473
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James Molloy [Mon, 9 Nov 2015 14:32:05 +0000 (14:32 +0000)]
[LoopVectorize] Address post-commit feedback on r250032
Implemented as many of Michael's suggestions as were possible:
* clang-format the added code while it is still fresh.
* tried to change Value* to Instruction* in many places in computeMinimumValueSizes - unfortunately there are several places where Constants need to be handled so this wasn't possible.
* Reduce the pass list on loop-vectorization-factors.ll.
* Fix a bug where we were querying MinBWs for I->getOperand(0) but using MinBWs[I].
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252469
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Silviu Baranga [Mon, 9 Nov 2015 13:26:09 +0000 (13:26 +0000)]
Allow LLE/LD and the loop versioning infrastructure to use SCEV predicates
Summary:
LAA currently generates a set of SCEV predicates that must be checked by users.
In the case of Loop Distribute/Loop Load Elimination, no such predicates could have
been emitted, since we don't allow stride versioning. However, in the future there
could be SCEV predicates that will need to be checked.
This change adds support for SCEV predicate versioning in the Loop Distribute, Loop
Load Eliminate and the loop versioning infrastructure.
Reviewers: anemet
Subscribers: mssimpso, sanjoy, llvm-commits
Differential Revision: http://reviews.llvm.org/D14240
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252467
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Charlie Turner [Mon, 9 Nov 2015 13:10:52 +0000 (13:10 +0000)]
[AArch64] Add UABDL patterns for log2 shuffle.
Summary:
This matches the sum-of-absdiff patterns emitted by the vectoriser using log2 shuffles.
Relies on D14207 to be able to match the `extract_subvector(..., 0)`
Reviewers: t.p.northover, jmolloy
Subscribers: aemerson, llvm-commits, rengolin
Differential Revision: http://reviews.llvm.org/D14208
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252465
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Charlie Turner [Mon, 9 Nov 2015 12:45:11 +0000 (12:45 +0000)]
[AArch64] Handle extract_subvector(..., 0) in ISel.
Summary:
Lowering this pattern early to an `EXTRACT_SUBREG` was making it impossible to match larger patterns in tblgen that use `extract_subvector(..., 0)` as part of the their input pattern.
It seems like there will exist somewhere a better way of specifying this pattern over all relevant register value types, but I didn't manage to find it.
Reviewers: t.p.northover, jmolloy
Subscribers: aemerson, llvm-commits, rengolin
Differential Revision: http://reviews.llvm.org/D14207
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252464
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Renato Golin [Mon, 9 Nov 2015 12:40:30 +0000 (12:40 +0000)]
[EABI] Add LLVM support for -meabi flag
"GCC requires the freestanding environment provide memcpy, memmove, memset
and memcmp": https://gcc.gnu.org/onlinedocs/gcc-5.2.0/gcc/Standards.html
Hence in GNUEABI targets LLVM should not convert 'memops' to their equivalent
'__aeabi_memops'. This convertion violates GCC contract.
The -meabi flag controls whether or not LLVM will modify 'memops' in GNUEABI
targets.
Without -meabi: use the triple default EABI.
With -meabi=default: use the triple default EABI.
With -meabi=gnu: use 'memops'.
With -meabi=4 or -meabi=5: use '__aeabi_memops'.
With -meabi set to an unknown value: same as -meabi=default.
Patch by Vinicius Tinti.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252462
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Renato Golin [Mon, 9 Nov 2015 12:19:10 +0000 (12:19 +0000)]
Revert "[ARM] Combine CMOV into BFI where possible"
This reverts commit r252057, as it broke ARM self-hosting buildbots, probably
due to a code-gen fault.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252460
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Oliver Stannard [Mon, 9 Nov 2015 11:03:18 +0000 (11:03 +0000)]
[CodeGen] Always promote f16 if not legal
We don't currently have any runtime library functions for operations on
f16 values (other than conversions to and from f32 and f64), so we
should always promote it to f32, even if that is not a legal type. In
that case, the f32 values would be softened to f32 library calls.
SoftenFloatRes_FP_EXTEND now needs to check the promoted operand's type,
as it may ne a no-op or require a different library call.
getCopyFromParts and getCopyToParts now need to cope with a
floating-point value stored in a larger integer part, as is the case for
any target that needs to store an f16 value in a 32-bit integer
register.
Differential Revision: http://reviews.llvm.org/D12856
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252459
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Colin LeMahieu [Mon, 9 Nov 2015 07:10:24 +0000 (07:10 +0000)]
[Hexagon] Adding override to methods.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252453
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Colin LeMahieu [Mon, 9 Nov 2015 06:15:55 +0000 (06:15 +0000)]
[Hexagon] Removing XFAIL on Hexagon target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252450
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Colin LeMahieu [Mon, 9 Nov 2015 05:47:56 +0000 (05:47 +0000)]
[Hexagon] Fixing warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252448
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Colin LeMahieu [Mon, 9 Nov 2015 05:31:39 +0000 (05:31 +0000)]
[Hexagon] Removing extra gen line.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252447
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Colin LeMahieu [Mon, 9 Nov 2015 05:16:08 +0000 (05:16 +0000)]
[Hexagon] Maybe the makefile?
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252446
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Colin LeMahieu [Mon, 9 Nov 2015 04:31:02 +0000 (04:31 +0000)]
[Hexagon] Adding LLVMBuild.txt reference to HexagonAsmParser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252444
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Colin LeMahieu [Mon, 9 Nov 2015 04:07:48 +0000 (04:07 +0000)]
[Hexagon] Enabling ASM parsing on Hexagon backend and adding instruction parsing tests. General updating of the code emission.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252443
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Mehdi Amini [Mon, 9 Nov 2015 02:46:41 +0000 (02:46 +0000)]
Add a method to the BitcodeReader to parse only the identification block
Summary: Mimic parseTriple(); and exposes it to LTOModule.cpp
Reviewers: dexonsmith, rafael
Subscribers: llvm-commits
From: Mehdi Amini <mehdi.amini@apple.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252442
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Colin LeMahieu [Mon, 9 Nov 2015 00:46:46 +0000 (00:46 +0000)]
[AsmParser] Generalize matching for grammars without mnemonic-lead statements
Differential Revision: http://reviews.llvm.org/D14257
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252440
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Colin LeMahieu [Mon, 9 Nov 2015 00:31:07 +0000 (00:31 +0000)]
[AsmParser] Backends can parameterize ASM tokenization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252439
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Colin LeMahieu [Mon, 9 Nov 2015 00:15:45 +0000 (00:15 +0000)]
[AsmParser] Provide target direct access to mnemonic token. Allow assignment parsing to be hooked by target. Allow target to specify if identifier is a label.
Differential Revision: http://reviews.llvm.org/D14255
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252435
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Xinliang David Li [Mon, 9 Nov 2015 00:01:22 +0000 (00:01 +0000)]
[PGO] Instr func name var creation code refactoring
Move the code from cfe to LLMV and become shared interfaces.
There is no functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252433
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Colin LeMahieu [Sun, 8 Nov 2015 23:48:23 +0000 (23:48 +0000)]
[AsmParser] Allow tokens to be put back in to the token stream.
Differential Revision: http://reviews.llvm.org/D14252
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252432
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Maksim Panchenko [Sun, 8 Nov 2015 19:34:17 +0000 (19:34 +0000)]
[RuntimeDyld] Add support for R_X86_64_PC8 relocation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252423
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NAKAMURA Takumi [Sun, 8 Nov 2015 09:45:06 +0000 (09:45 +0000)]
Appease hosts without HAVE_BACKTRACE nor ENABLE_BACKTRACES.
llvm/lib/Support/Signals.cpp:66:13: warning: unused function 'printSymbolizedStackTrace' [-Wunused-function]
llvm/lib/Support/Signals.cpp:52:13: warning: function 'findModulesAndOffsets' has internal linkage but is not defined [-Wundefined-internal]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252418
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Hal Finkel [Sun, 8 Nov 2015 08:04:40 +0000 (08:04 +0000)]
[PowerPC] Fix LoopPreIncPrep not to depend on SCEV constant simplifications
Under most circumstances, if SCEV can simplify X-Y to a constant, then it can
also simplify Y-X to a constant. However, there is no guarantee that this is
always true, and concensus is not to consider that a correctness bug in SCEV
(although it is undesirable).
PPCLoopPreIncPrep gathers pointers used to access memory (via loads, stores and
prefetches) into buckets, where in each bucket the relative pointer offsets are
constant. We used to keep each bucket as a multimap, where SCEV's subtraction
operation was used to define the ordering predicate. Instead, use a fixed SCEV
base expression for each bucket, record the constant offsets from that base
expression, and adjust it later, if desirable, once all pointers have been
collected.
Doing it this way should be more compile-time efficient than the previous
scheme (in addition to making the implementation less sensitive to SCEV
simplification quirks).
Fixes PR25170.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252417
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David Majnemer [Sun, 8 Nov 2015 05:04:07 +0000 (05:04 +0000)]
[LoopStrengthReduce] Don't bother fixing up PHIs from EH Pad preds
We cannot really insert fixup code into a PHI's predecessor.
This fixes PR25445.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252416
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David Majnemer [Sun, 8 Nov 2015 04:16:12 +0000 (04:16 +0000)]
Make bugpoint ehpad/token friendly
Tokens shouldn't be blindly replaced with undef/null. Also, don't try
to remove EH pad instructions from the top of basic blocks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252414
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David Majnemer [Sun, 8 Nov 2015 02:36:00 +0000 (02:36 +0000)]
[WinEH] Update PHIs of CATCHRET successors
The TailDuplication machine pass ran across a malformed CFG: a PHI node
referred it's predecessor's predecessor instead of it's predecessor.
This occurred because we split the edge in X86ISelLowering when we
processed the CATCHRET but forgot to do something about the PHI nodes.
This fixes PR25444.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252413
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Yaron Keren [Sat, 7 Nov 2015 10:21:25 +0000 (10:21 +0000)]
Erase unused FunctionDIs variables after r252219.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252401
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Akira Hatanaka [Sat, 7 Nov 2015 02:48:49 +0000 (02:48 +0000)]
[Bitcode] Add enums for call instruction markers and flags. NFC.
This commit adds enums in LLVMBitCodes.h to improve readability and
maintainability. This is a follow-up to r252368 which was discussed
here:
http://reviews.llvm.org/D12923
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252395
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Nico Weber [Sat, 7 Nov 2015 02:47:31 +0000 (02:47 +0000)]
Try to fix build more -- like r252392 but for WebAssembly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252394
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