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Eric Yang [Sun, 5 Apr 2020 20:40:54 +0000 (16:40 -0400)]
drm/amd/display: change default pipe_split policy for DCN1
[Why]
Changing policy to dynamic will allow 4k multi display configs
to be supported at DPM0
Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nicholas Kazlauskas [Sun, 5 Apr 2020 20:40:53 +0000 (16:40 -0400)]
drm/amd/display: Translate cursor position by source rect
[Why]
Cursor is drawn as part of the framebuffer for a plane on AMD hardware.
The cursor position on the framebuffer does not change even if the
source rect viewport for the cursor does. This causes the cursor to be
clipped.
The following IGT tests fail as a result of this issue:
- kms_plane_cursor@pipe-*-viewport-size-*
[How]
Offset cursor position by plane source rect viewport. If the viewport
is unscaled then the cursor is now correctly positioned on any
plane - primary or overlay.
There is still a hardware limitation for dealing with the cursor size
being incorrectly scaled but that's not something we can address.
Add some documentation explaining some of this in the code while we're
at it.
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Zhan Liu <Zhan.Liu@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Wyatt Wood [Sun, 5 Apr 2020 20:40:52 +0000 (16:40 -0400)]
drm/amd/display: Fix ABM config copy for dmcub
Decouple dmcub config copy from dmcu iram copy.
Signed-off-by: Wyatt Wood <wyatt.wood@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaodong Yan [Sun, 5 Apr 2020 20:40:51 +0000 (16:40 -0400)]
drm/amd/display: only blank dp stream which will be powered off
[why]
blank all dp stream would impact edp
[how]
only blank the one which will be powered off
Signed-off-by: Xiaodong Yan <Xiaodong.Yan@amd.com>
Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Joseph Gravenor [Sun, 5 Apr 2020 20:40:50 +0000 (16:40 -0400)]
drm/amd/display: fix typo
[why]
MOD_HDCP_STATUS_HDCP1_ENABLE_ENCRYPTION and
MOD_HDCP_STATUS_HDCP2_ENABLE_ENCRYPTION were supposed to be
MOD_HDCP_STATUS_HDCP1_ENABLE_ENCRYPTION_FAILURE and
MOD_HDCP_STATUS_HDCP2_ENABLE_ENCRYPTION_FAILURE. Because of this
it always seems like mod_hdcp_hdcp1_enable_encryption
and mod_hdcp_hdcp2_enable_encryption are always passing
[how]
rename the elements to what they were supposed to be called
Signed-off-by: Joseph Gravenor <joseph.gravenor@amd.com>
Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Wyatt Wood [Sun, 5 Apr 2020 20:40:49 +0000 (16:40 -0400)]
drm/amd/display: Use config flag to disable dmcu obj creation
[Why]
When dmcub is the default we no longer wish to create the psr and dmcu
objects. Currently a dc debug flag is used to implement this, but these
flags aren't populated until after dcn21_resource_construct is called.
This means the dmcub objects will never be created. Therefore we must
use a dc config flag, which is populated before dc resource construct.
[How]
Add a dc config flag.
Signed-off-by: Wyatt Wood <wyatt.wood@amd.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Sung Lee [Sun, 5 Apr 2020 20:40:48 +0000 (16:40 -0400)]
drm/amd/display: Check power_down functions exist before calling
[WHY]
The power_down() function was only defined for specific asics and will
crash the system if it is called by an asic with eDP connected that does
not have it defined.
[HOW]
Add a check for the function's existence before calling it.
Signed-off-by: Sung Lee <sung.lee@amd.com>
Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nicholas Kazlauskas [Sun, 5 Apr 2020 20:40:47 +0000 (16:40 -0400)]
drm/amd/display: Don't change mpcc tree for medium updates on DCN20 hwseq
[Why]
Overlay planes disappear when the plane's alpha blending mode or global
opacity is modified.
These are considered UPDATE_TYPE_MEDIUM and trigger the update_mpcc path
in the DCN hardware sequencer.
On DCN10 we have an "optimization" to avoid touching the blending tree
on these updates, but this is actually required behavior based on how
update_mpcc is structured.
For full updates we acquire a MPCC for the plane, remove it if it
already exists then reinsert it after with insert_plane.
The call to insert_plane can take an optional mpcc to insert the new one
above to preserve the current blending order. The update_mpcc hwseq
function doesn't do this so the overlay gets sent to the very bottom
of the tree.
[How]
Copy the check over from DCN10 to DCN20. The only time we need to
actually touch the tree really is the full update, so this is also
an optimization on top of the fix.
Fixing the logic for insert_plane is rather simple (cache the bot_mpcc
and pass it to insert_plane) but is a change that impacts most display
usecases.
For now stick with the optimization.
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Chris Park <Chris.Park@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaodong Yan [Sun, 5 Apr 2020 20:40:46 +0000 (16:40 -0400)]
drm/amd/display: blank dp stream before power off receiver
[why]
power off dp receiver directly cause garbage during hw init
[how]
blank dp stream and then power off receiver
Signed-off-by: Xiaodong Yan <Xiaodong.Yan@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Sung Lee [Sun, 5 Apr 2020 20:40:45 +0000 (16:40 -0400)]
drm/amd/display: Power down hw blocks on boot
[WHY]
On headless boot a DIG may be turned on by VBIOS on RN. This leads to
display_count being non-zero in hybrid graphics cases leading to SMU
DISPLAY_OFF message not being sent.
[HOW]
Power down hardware on boot
if seamless boot is not occurring
(power_down_display_on_boot == 1)
Signed-off-by: Sung Lee <sung.lee@amd.com>
Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Isabel Zhang [Sun, 5 Apr 2020 20:40:44 +0000 (16:40 -0400)]
drm/amd/display: Remove hdcp display state with mst fix
[Why]
Due to previous code changes, displays transition from active to active
and added state immediately, making it redundant to have both display
states. Previous change to fix this caused HDCP to get into a bad state
when monitor is connected to MST hub, this change fixes that issue.
[How]
Change code behavior so when a device is added successfully the state
remains as active and when addition is unsuccessful change state to
inactive. This removes need for added and active state.
Signed-off-by: Isabel Zhang <isabel.zhang@amd.com>
Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Wyatt Wood [Sun, 5 Apr 2020 20:40:43 +0000 (16:40 -0400)]
drm/amd/display: Implement abm config table copy to dmcub
[Why]
Driver must pass abm config table to dmub fw. This provides various
parameters for abm functionality.
[How]
There is too much data to be passed in an inbox message, so we must pass
this data using an indirect buffer. Copy the table to cw7 via x86,
driver copies to fw_state structure.
Signed-off-by: Wyatt Wood <wyatt.wood@amd.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: Tony Cheng <Tony.Cheng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nikola Cornij [Sun, 5 Apr 2020 20:40:42 +0000 (16:40 -0400)]
drm/amd/display: Program DSC before enabling link
[why]
Link or DIG BE can't be exposed to a higher stream bandwidth than they
can handle. When DSC is required to fit the stream into the link
bandwidth, DSC has to be programmed before the link is enabled to ensure
this. Without it, intermittent issues such as black screen after S3 or a
hot-plug can be seen with DSC timings like 4k144Hz or 8k60Hz.
[how]
Move DSC programming from before enabling stream to before enabling link
Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Josip Pavic [Sun, 5 Apr 2020 20:40:41 +0000 (16:40 -0400)]
drm/amd/display: prevent loop from occuring in pipe list
[Why]
If no free pipes are available, acquire_first_split_pipe is called to
get a pipe to use. This call may alter the ordering of the pipes in the
list so that, for example, the tail pipe changes.
If acquire_first_split_pipe returns the tail pipe, we'll have free_pipe
== tail_pipe. What tail_pipe refers to is not the current tail_pipe, but
what was previously the tail pipe - i.e. prior to the call to
acquire_first_split_pipe
The logic that follows will link free_pipe to the tail pipe, referring to
the current tail pipe. However, since tail_pipe is cached from before the
call to acquire_first_split_pipe, the wrong tail pipe will be used, and
it will end up being linked to itself, creating a loop that, if traversed,
will result in a soft hang.
[How]
Do not cache the tail pipe. Instead, check the tail pipe after the call to
acquire_first_split_pipe is made.
Signed-off-by: Josip Pavic <Josip.Pavic@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aric Cyr [Sun, 5 Apr 2020 20:40:40 +0000 (16:40 -0400)]
drm/amd/display: 3.2.78
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Zhang [Tue, 7 Apr 2020 05:50:05 +0000 (13:50 +0800)]
drm/amdgpu/sriov add amdgpu_amdkfd_pre_reset in gpu reset
[PATCH 2/2]
kfd_pre_reset will free mem_objs allocated by kfd_gtt_sa_allocate
Without this change, sriov tdr code path will never free those
allocated memories and get memory leak.
Signed-off-by: Jack Zhang <Jack.Zhang1@amd.com>
Reviewed-by: Monk Liu <monk.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Zhang [Tue, 7 Apr 2020 05:44:51 +0000 (13:44 +0800)]
drm/amdkfd Avoid destroy hqd when GPU is on reset
This reverts commit
5161bba4311f in order to split it into two
different patches, and this will make it easier to understand.
[PATCH 1/2]
porting to gfx10 from
commit
1b0bfcff463f390c40 ("drm/amdgpu: Avoid destroy hqd when GPU is on reset")
Originally, MEC is touched
without GPU initialized first.
Signed-off-by: Jack Zhang <Jack.Zhang1@amd.com>
Reviewed-by: Monk Liu <monk.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
John Clements [Tue, 7 Apr 2020 08:54:33 +0000 (16:54 +0800)]
drm/amdgpu: update RAS related dmesg print
prefix RAS error related dmesg print with pci device info
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: John Clements <john.clements@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
John Clements [Tue, 7 Apr 2020 07:08:15 +0000 (15:08 +0800)]
drm/amdgpu: resolve mGPU RAS query instability
upon receiving uncorrectable error, query every GPU node for ras errors
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: John Clements <john.clements@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chengming Gui [Fri, 3 Apr 2020 03:32:15 +0000 (11:32 +0800)]
drm/amd/amdgpu: Correct gfx10's CG sequence
Incorrect CG sequence will cause gfx timedout,
if we keep switching power profile mode
(enter profile mod such as PEAK will disable CG,
exit profile mode EXIT will enable CG)
when run Vulkan test case(case used for test: vkexample).
Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Acked-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tianci.Yin [Tue, 7 Apr 2020 14:24:21 +0000 (22:24 +0800)]
drm/amdgpu: add SPM golden settings for Navi12
Add RLC_SPM golden settings
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Tianci.Yin <tianci.yin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tianci.Yin [Tue, 7 Apr 2020 04:51:04 +0000 (12:51 +0800)]
drm/amdgpu: add SPM golden settings for Navi14
Add RLC_SPM golden settings
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Tianci.Yin <tianci.yin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tianci.Yin [Thu, 2 Apr 2020 10:48:22 +0000 (18:48 +0800)]
drm/amdgpu: add SPM golden settings for Navi10(v2)
Add RLC_SPM golden settings
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Tianci.Yin <tianci.yin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Oak Zeng [Mon, 6 Apr 2020 17:11:31 +0000 (12:11 -0500)]
drm/amdgpu: Print UTCL2 client ID on a gpuvm fault
UTCL2 client ID is useful information to get which
UTCL2 client caused the gpuvm fault. Print it out
for debug purpose
Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian Konig <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nirmoy Das [Mon, 6 Apr 2020 08:08:47 +0000 (10:08 +0200)]
drm/amd/powerplay: fix a typo
Util -> Until
Fixes:
567c8fc4a0d28b63f ("drm/amd/powerplay: implement the is_dpm_running()")
Signed-off-by: Nirmoy Das <nirmoy.das@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
James Zhu [Fri, 3 Apr 2020 03:25:45 +0000 (23:25 -0400)]
drm/amdgpu/vcn: add shared memory restore after wake up from sleep.
VCN shared memory needs restore after wake up during S3 test.
v2: Allocate shared memory saved_bo at sw_init and free it in sw_fini.
Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aaron Ma [Fri, 3 Apr 2020 14:34:19 +0000 (22:34 +0800)]
drm/amdgpu: Fix oops when pp_funcs is unset in ACPI event
On ARCTURUS and RENOIR, powerplay is not supported yet.
When plug in or unplug power jack, ACPI event will issue.
Then kernel NULL pointer BUG will be triggered.
Check for NULL pointers before calling.
Signed-off-by: Aaron Ma <aaron.ma@canonical.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Fri, 3 Apr 2020 16:25:48 +0000 (12:25 -0400)]
drm/amdgpu/psp: dont warn on missing optional TA's
Replace dev_warn() with dev_info() and note that they are
optional to avoid confusing users.
The RAS TAs only exist on server boards and the HDCP and DTM
TAs only exist on client boards. They are optional either way.
Acked-by: Nirmoy Das <nirmoy.das@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nirmoy Das [Wed, 1 Apr 2020 09:46:57 +0000 (11:46 +0200)]
drm/amdgpu: rework sched_list generation
Generate HW IP's sched_list in amdgpu_ring_init() instead of
amdgpu_ctx.c. This makes amdgpu_ctx_init_compute_sched(),
ring.has_high_prio and amdgpu_ctx_init_sched() unnecessary.
This patch also stores sched_list for all HW IPs in one big
array in struct amdgpu_device which makes amdgpu_ctx_init_entity()
much more leaner.
v2:
fix a coding style issue
do not use drm hw_ip const to populate amdgpu_ring_type enum
v3:
remove ctx reference and move sched array and num_sched to a struct
use num_scheds to detect uninitialized scheduler list
v4:
use array_index_nospec for user space controlled variables
fix possible checkpatch.pl warnings
Signed-off-by: Nirmoy Das <nirmoy.das@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nirmoy Das [Tue, 31 Mar 2020 11:29:08 +0000 (13:29 +0200)]
drm/amdgpu: sync ring type and drm hw_ip type
Use AMDGPU_HW_IP_* to set amdgpu_ring_type enum values
Signed-off-by: Nirmoy Das <nirmoy.das@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Zhang [Thu, 2 Apr 2020 07:10:24 +0000 (15:10 +0800)]
drm/amdgpu/sriov add amdgpu_amdkfd_pre_reset in gpu reset
kfd_pre_reset will free mem_objs allocated by kfd_gtt_sa_allocate
Without this change, sriov tdr code path will never free those allocated
memories and get memory leak.
v2:add a bugfix for kiq ring test fail
Signed-off-by: Jack Zhang <Jack.Zhang1@amd.com>
Reviewed-by: Monk Liu <monk.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yifan Zhang [Fri, 3 Apr 2020 09:11:14 +0000 (17:11 +0800)]
drm/amd/display: fix the broken logic in dc_link.c
Add missing braces.
Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tiecheng Zhou [Thu, 2 Apr 2020 08:49:36 +0000 (16:49 +0800)]
drm/amd/powerplay: avoid using pm_en before it is initialized
hwmgr->pm_en is initialized at hwmgr_hw_init.
during amdgpu_device_init, there is amdgpu_asic_reset that calls to
pp_get_asic_baco_capability, while hwmgr->pm_en has not yet been initialized.
so avoid using pm_en in pp_get_asic_baco_capability.
Reviewed-by: Emily Deng <Emily.Deng@amd.com>
Signed-off-by: Tiecheng Zhou <Tiecheng.Zhou@amd.com>
Signed-off-by: Yintian Tao <yttao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Prike Liang [Fri, 3 Apr 2020 04:26:15 +0000 (12:26 +0800)]
drm/amd/powerplay: implement the is_dpm_running()
As the pmfw hasn't exported the interface of SMU feature
mask to APU SKU so just force on all the features to driver
inquired interface at early initial stage.
Signed-off-by: Prike Liang <Prike.Liang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Shirish S [Thu, 2 Apr 2020 09:10:11 +0000 (14:40 +0530)]
drm/amd/display: re-order asic declarations
Fixes build error of:
"use of undeclared identifier 'RENOIR_A0'"
To fix the same, this patch re-orders the
ASIC declarations accordingly.
Fixes:
41ef3dcd86443fa ("drm/amd/display: Fix RV2 Variant Detection")
Signed-off-by: Shirish S <shirish.s@amd.com>
Reviewed-by: Zhan Liu <zhan.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yuxian Dai [Wed, 1 Apr 2020 11:26:26 +0000 (19:26 +0800)]
drm/amdgpu/powerplay: using the FCLK DPM table to set the MCLK
1.Using the FCLK DPM table to set the MCLK for DPM states consist of
three entities:
FCLK
UCLK
MEMCLK
All these three clk change together, MEMCLK from FCLK, so use the fclk
frequency.
2.we should show the current working clock freqency from clock table metric
Signed-off-by: Yuxian Dai <Yuxian.Dai@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <Kevin1.Wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Sierra [Wed, 1 Apr 2020 21:57:17 +0000 (16:57 -0500)]
amdgpu/drm: remove psp access on navi10 for sriov
Navi ASICs don't require to access through PSP to osssys registers.
This on SR-IOV configuration.
Signed-off-by: Alex Sierra <alex.sierra@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Bhawanpreet Lakha [Mon, 30 Mar 2020 21:44:00 +0000 (17:44 -0400)]
drm/amd/display: Guard calls to hdcp_ta and dtm_ta
[Why]
The buffer used when calling psp is a shared buffer. If we have multiple calls
at the same time we can overwrite the buffer.
[How]
Add mutex to guard the shared buffer.
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Bhawanpreet Lakha [Wed, 1 Apr 2020 19:55:24 +0000 (15:55 -0400)]
drm/amd/display: remove mod_hdcp_hdcp2_get_link_encryption_status()
It is not being used, so remove it
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Lyude Paul [Tue, 31 Mar 2020 21:22:24 +0000 (17:22 -0400)]
drm/amd/dc: Kill dc_conn_log_hex_linux()
DRM already supports tracing DPCD transactions, there's no reason for
the existence of this function. Also, it prints one byte per-line which
is way too loud. So, just remove it.
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Lyude Paul <lyude@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Lyude Paul [Tue, 31 Mar 2020 21:22:23 +0000 (17:22 -0400)]
drm/amd/amdgpu_dm/mst: Remove useless sideband tracing
We already trace DPCD reads/writes on both MST and SST, there's no
reason to have this code here (plus, toggling these things with a
define at the top of the file isn't how we do things in the kernel).
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Lyude Paul <lyude@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Colin Ian King [Wed, 1 Apr 2020 16:35:45 +0000 (17:35 +0100)]
drm/amdgpu/vcn: fix spelling mistake "fimware" -> "firmware"
There is a spelling mistake in a dev_err error message. Fix it.
Signed-off-by: Colin Ian King <colin.king@canonical.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Thu, 12 Mar 2020 11:03:34 +0000 (12:03 +0100)]
drm/amdgpu: fix and cleanup amdgpu_gem_object_close v4
The problem is that we can't add the clear fence to the BO
when there is an exclusive fence on it since we can't
guarantee the the clear fence will complete after the
exclusive one.
To fix this refactor the function and also add the exclusive
fence as shared to the resv object.
v2: fix warning
v3: add excl fence as shared instead
v4: squash in fix for fence handling in amdgpu_gem_object_close
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: xinhui pan <xinhui.pan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Melissa Wen [Tue, 31 Mar 2020 11:00:32 +0000 (08:00 -0300)]
drm/amd/display: code cleanup of dc_link file on func dc_link_construct
Removes codestyle issues in dc_link file, on dc_link_construct and
translate_encoder_to_transmitter as suggested by checkpatch.pl.
Types covered:
CHECK: Lines should not end with a '('
WARNING: Missing a blank line after declarations
CHECK: Alignment should match open parenthesis
CHECK: Comparison to NULL could be written
CHECK: Logical continuations should be on the previous line
CHECK: Blank lines aren't necessary after an open brace '{'
Signed-off-by: Melissa Wen <melissa.srw@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Melissa Wen [Tue, 31 Mar 2020 10:59:59 +0000 (07:59 -0300)]
drm/amd/display: code cleanup on dc_link from is_same_edid to get_ddc_line
Removes codestyle issues on the file dc_link between is_same_edid and
get_ddc_line as suggested by checkpatch.pl.
Types covered:
CHECK: Blank lines aren't necessary after an open brace '{'
CHECK: Blank lines aren't necessary before a close brace '}'
WARNING: braces {} are not necessary for single statement blocks
CHECK: Comparison to NULL could be written
CHECK: Lines should not end with a '('
CHECK: Alignment should match open parenthesis
CHECK: Using comparison to false is error prone
CHECK: Using comparison to true is error prone
WARNING: Avoid multiple line dereference - prefer 'link->dpcd_caps.sink_count.bits.SINK_COUNT'
CHECK: Unnecessary parentheses around
WARNING: Missing a blank line after declarations
Signed-off-by: Melissa Wen <melissa.srw@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Melissa Wen [Tue, 31 Mar 2020 10:59:20 +0000 (07:59 -0300)]
drm/amd/display: codestyle cleanup on dc_link file until detect_dp func
Removes codestyle issues on the file dc_link until detect_dp func as
suggested by checkpatch.pl.
Types covered:
CHECK: Please don't use multiple blank lines
CHECK: Comparison to NULL could be written
ERROR: space required before the open parenthesis '('
CHECK: Alignment should match open parenthesis
CHECK: Lines should not end with a '('
WARNING: please, no space before tabs
WARNING: Comparisons should place the constant on the right side of the test
WARNING: braces {} are not necessary for single statement blocks
CHECK: Please don't use multiple blank lines
Signed-off-by: Melissa Wen <melissa.srw@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Melissa Wen [Tue, 31 Mar 2020 10:57:34 +0000 (07:57 -0300)]
drm/amd/display: cleanup codestyle type BLOCK_COMMENT_STYLE on dc_link
Solve comments alignment problems on dc_link file
Signed-off-by: Melissa Wen <melissa.srw@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
James Zhu [Mon, 10 Feb 2020 15:28:00 +0000 (10:28 -0500)]
drm/amdgpu: enable VCN2.5 DPG mode for Arcturus
Enable VCN2.5 DPG mode for arcturus after below items are applied.
ASD: 0x21000023
SOS: 0x17003B
VCN firmware Version ENC: 1.1 DEC: 1 VEP: 0 Revision: 16
VBIOS: 23
Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
James Zhu [Mon, 30 Mar 2020 00:15:44 +0000 (20:15 -0400)]
drm/amdgpu/vcn2.5: Add firmware w/r ptr reset sync
Add firmware write/read point reset sync through shared memory
Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
James Zhu [Mon, 30 Mar 2020 00:11:34 +0000 (20:11 -0400)]
drm/amdgpu/vcn2.0: Add firmware w/r ptr reset sync
Add firmware write/read point reset sync through shared memory
Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
James Zhu [Mon, 30 Mar 2020 00:00:22 +0000 (20:00 -0400)]
drm/amdgpu/vcn: Add firmware share memory support
Added firmware share memory support for VCN. Current multiple
queue mode is enabled only.
Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
James Zhu [Tue, 18 Feb 2020 22:46:29 +0000 (17:46 -0500)]
drm/amdgpu/vcn2.5: stall DPG when WPTR/RPTR reset
Add vcn dpg harware synchronization to fix race condition
issue between vcn driver and hardware.
Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
James Zhu [Tue, 18 Feb 2020 22:44:39 +0000 (17:44 -0500)]
drm/amdgpu/vcn2.0: stall DPG when WPTR/RPTR reset
Add vcn dpg harware synchronization to fix race condition
issue between vcn driver and hardware.
Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
James Zhu [Mon, 10 Feb 2020 17:52:16 +0000 (12:52 -0500)]
drm/amdgpu/vcn: fix race condition issue for dpg unpause mode switch
Couldn't only rely on enc fence to decide switching to dpg unpaude mode.
Since a enc thread may not schedule a fence in time during multiple
threads running situation.
v3: 1. Rename enc_submission_cnt to dpg_enc_submission_cnt
2. Add dpg_enc_submission_cnt check in idle_work_handler
v4: Remove extra counter check, and reduce counter before idle
work schedule
Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
James Zhu [Mon, 10 Feb 2020 17:41:41 +0000 (12:41 -0500)]
drm/amdgpu/vcn: fix race condition issue for vcn start
Fix race condition issue when multiple vcn starts are called.
v2: Removed checking the return value of cancel_delayed_work_sync()
to prevent possible races here.
v3: Add total_submission_cnt to avoid gate power unexpectedly.
v4: Remove extra counter check, and reduce counter before idle
work schedule
Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yintian Tao [Tue, 10 Mar 2020 15:24:53 +0000 (23:24 +0800)]
drm/amdgpu: skip access sdma_v5_0 registers under SRIOV (v2)
Due to the new L1.
0b0c011b policy, many SDMA registers are blocked which raise
the violation warning. There are total 6 pair register needed to be skipped
when driver init and de-init.
mmSDMA0/1_CNTL
mmSDMA0/1_F32_CNTL
mmSDMA0/1_UTCL1_PAGE
mmSDMA0/1_UTCL1_CNTL
mmSDMA0/1_CHICKEN_BITS,
mmSDMA0/1_SEM_WAIT_FAIL_TIMER_CNTL
v2: squash in warning fix
Signed-off-by: Yintian Tao <yttao@amd.com>
Reviewed-by: Emily Deng <Emily.Deng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Fri, 21 Feb 2020 14:10:31 +0000 (15:10 +0100)]
drm/amdgpu: stop disable the scheduler during HW fini
When we stop the HW for example for GPU reset we should not stop the
front-end scheduler. Otherwise we run into intermediate failures during
command submission.
The scheduler should only be stopped in very few cases:
1. We can't get the hardware working in ring or IB test after a GPU reset.
2. The KIQ scheduler is not used in the front-end and should be disabled during GPU reset.
3. In amdgpu_ring_fini() when the driver unloads.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Nirmoy Das <nirmoy.das@amd.com>
Test-by: Dennis Li <dennis.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Fri, 27 Mar 2020 03:20:29 +0000 (11:20 +0800)]
drm/amd/powerplay: added mutex protection on msg issuing
This could avoid the possible race condition.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Fri, 27 Mar 2020 02:48:20 +0000 (10:48 +0800)]
drm/amd/powerplay: unified interfaces for message issuing and response checking
This can avoid potential race condition between them.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Thu, 26 Mar 2020 10:01:25 +0000 (18:01 +0800)]
drm/amd/powerplay: avoid calling Vega20 specific SMU message implemention
Prepare for coming lock protection for SMU message issuing.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Thu, 26 Mar 2020 09:52:50 +0000 (17:52 +0800)]
drm/amd/powerplay: avoid calling SMU10 specific SMU message implemention
Prepare for coming lock protection for SMU message issuing.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Thu, 26 Mar 2020 09:44:45 +0000 (17:44 +0800)]
drm/amd/powerplay: avoid calling SMU9 specific SMU message implemention
Prepare for coming lock protection for SMU message issuing.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Thu, 26 Mar 2020 08:47:45 +0000 (16:47 +0800)]
drm/amd/powerplay: avoid calling SMU8 specific SMU message implemention
Prepare for coming lock protection for SMU message issuing.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Thu, 26 Mar 2020 08:35:25 +0000 (16:35 +0800)]
drm/amd/powerpaly: drop unused APIs
Drop unused smu7 message APIs.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Thu, 26 Mar 2020 08:30:52 +0000 (16:30 +0800)]
drm/amd/powerplay: avoid calling SMU7 specific SMU message implemention
Prepare for coming lock protection for SMU message issuing.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Thu, 26 Mar 2020 08:09:05 +0000 (16:09 +0800)]
drm/amd/powerplay: avoid calling CI specific SMU message implemention
Prepare for coming lock protection for SMU message issuing.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Sierra [Mon, 23 Mar 2020 19:00:43 +0000 (14:00 -0500)]
drm/amdgpu: reroute VMC and UMD to IH ring 1 for oss v5
[Why]
Due Page faults can easily overwhelm the interrupt handler.
So to make sure that we never lose valuable interrupts on the primary ring
we re-route page faults to IH ring 1.
It also facilitates the recovery page process, since it's already
running from a process context.
This is valid for Arcturus and future Navi generation GPUs.
[How]
Setting IH_CLIENT_CFG_DATA for VMC and UMD IH clients.
Signed-off-by: Alex Sierra <alex.sierra@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Sierra [Mon, 23 Mar 2020 18:53:39 +0000 (13:53 -0500)]
drm/amdgpu: call psp to program ih cntl in SR-IOV for Navi
call psp to program ih cntl in SR-IOV if supported on Navi and Arcturus.
Signed-off-by: Alex Sierra <alex.sierra@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Sierra [Mon, 23 Mar 2020 18:28:15 +0000 (13:28 -0500)]
drm/amdgpu: enable IH ring 1 and ring 2 for navi
Support added into IH to enable ring1 and ring2 for navi10_ih.
Signed-off-by: Alex Sierra <alex.sierra@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Sierra [Wed, 18 Mar 2020 23:26:19 +0000 (18:26 -0500)]
drm/amdgpu: ih doorbell size of range changed for nbio v7.4
[Why]
nbio v7.4 size of ih doorbell range is 64 bit. This requires 2 DWords per register.
[How]
Change ih doorbell size from 2 to 4. This means two Dwords per ring.
Current configuration uses two ih rings.
Signed-off-by: Alex Sierra <alex.sierra@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Sierra [Wed, 18 Mar 2020 22:57:10 +0000 (17:57 -0500)]
drm/amdgpu: infinite retries fix from UTLC1 RB SDMA
[Why]
Previously these registers were set to 0. This was causing an
infinite retry on the UTCL1 RB, preventing higher priority RB such as paging RB.
[How]
Set to one the SDMAx_UTLC1_TIMEOUT registers for all SDMAs on Vega10, Vega12,
Vega20 and Arcturus.
Signed-off-by: Alex Sierra <alex.sierra@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Fri, 27 Mar 2020 07:39:06 +0000 (15:39 +0800)]
drm/amdgpu: fix non-pointer dereference for non-RAS supported
Backtrace on gpu recover test on Navi10.
[ 1324.516681] RIP: 0010:amdgpu_ras_set_error_query_ready+0x15/0x20 [amdgpu]
[ 1324.523778] Code: 4c 89 f7 e8 cd a2 a0 d8 e9 99 fe ff ff 45 31 ff e9 91 fe ff ff 0f 1f 44 00 00 55 48 85 ff 48 89 e5 74 0e 48 8b 87 d8 2b 01 00 <40> 88 b0 38 01 00 00 5d c3 66 90 0f 1f 44 00 00 55 31 c0 48 85 ff
[ 1324.543452] RSP: 0018:
ffffaa1040e4bd28 EFLAGS:
00010286
[ 1324.549025] RAX:
0000000000000000 RBX:
ffff911198b20000 RCX:
0000000000000000
[ 1324.556217] RDX:
00000000000c0a01 RSI:
0000000000000000 RDI:
ffff911198b20000
[ 1324.563514] RBP:
ffffaa1040e4bd28 R08:
0000000000001000 R09:
ffff91119d0028c0
[ 1324.570804] R10:
ffffffff9a606b40 R11:
0000000000000000 R12:
0000000000000000
[ 1324.578413] R13:
ffffaa1040e4bd70 R14:
ffff911198b20000 R15:
0000000000000000
[ 1324.586464] FS:
00007f4441cbf540(0000) GS:
ffff91119ed80000(0000) knlGS:
0000000000000000
[ 1324.595434] CS: 0010 DS: 0000 ES: 0000 CR0:
0000000080050033
[ 1324.601345] CR2:
0000000000000138 CR3:
00000003fcdf8004 CR4:
00000000003606e0
[ 1324.608694] DR0:
0000000000000000 DR1:
0000000000000000 DR2:
0000000000000000
[ 1324.616303] DR3:
0000000000000000 DR6:
00000000fffe0ff0 DR7:
0000000000000400
[ 1324.623678] Call Trace:
[ 1324.626270] amdgpu_device_gpu_recover+0x6e7/0xc50 [amdgpu]
[ 1324.632018] ? seq_printf+0x4e/0x70
[ 1324.636652] amdgpu_debugfs_gpu_recover+0x50/0x80 [amdgpu]
[ 1324.643371] seq_read+0xda/0x420
[ 1324.647601] full_proxy_read+0x5c/0x90
[ 1324.652426] __vfs_read+0x1b/0x40
[ 1324.656734] vfs_read+0x8e/0x130
[ 1324.660981] ksys_read+0xa7/0xe0
[ 1324.665201] __x64_sys_read+0x1a/0x20
[ 1324.669907] do_syscall_64+0x57/0x1c0
[ 1324.674517] entry_SYSCALL_64_after_hwframe+0x44/0xa9
[ 1324.680654] RIP: 0033:0x7f44417cf081
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: John Clements <John.Clements@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tom St Denis [Fri, 27 Mar 2020 13:30:52 +0000 (09:30 -0400)]
drm/amd/amdgpu: Include headers for PWR and SMUIO registers
Clean up the smu10, smu12, and gfx9 drivers to use headers for
registers instead of hardcoding in the C source files.
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
xinhui pan [Thu, 26 Mar 2020 00:38:29 +0000 (08:38 +0800)]
drm/amdgpu: implement more ib pools (v2)
We have three ib pools, they are normal, VM, direct pools.
Any jobs which schedule IBs without dependence on gpu scheduler should
use DIRECT pool.
Any jobs schedule direct VM update IBs should use VM pool.
Any other jobs use NORMAL pool.
v2: squash in coding style fix
Signed-off-by: xinhui pan <xinhui.pan@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Wyatt Wood [Wed, 11 Mar 2020 19:46:26 +0000 (15:46 -0400)]
drm/amd/display: Move backlight pwm enable function call
[Why]
Can't call dmub_abm_enable_fractional_pwm from dmub_abm_create as
dmub_srv is still null at this init stage, and therefore can't call to
fw.
[How]
Move call to dmub_abm_init_backlight. This should be the first call from
the driver for ABM.
Signed-off-by: Wyatt Wood <wyatt.wood@amd.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Wyatt Wood [Thu, 20 Feb 2020 16:50:44 +0000 (11:50 -0500)]
drm/amd/display: Add ABM driver implementation
[Why]
Moving ABM from DMCU to DMCUB.
[How]
Add ABM driver files and implementation.
Signed-off-by: Wyatt Wood <wyatt.wood@amd.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aric Cyr [Mon, 9 Mar 2020 15:08:49 +0000 (11:08 -0400)]
drm/amd/display: 3.2.77
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jiawei [Thu, 26 Mar 2020 07:10:51 +0000 (15:10 +0800)]
drm/amdgpu: extend compute job timeout
extend compute lockup timeout to 60000 for SR-IOV.
Reviewed-by: Emily Deng <Emily.Deng@amd.com>
Signed-off-by: Jiawei <Jiawei.Gu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Emily Deng [Thu, 26 Mar 2020 05:41:57 +0000 (13:41 +0800)]
drm/amdgpu: No need support vcn decode
As no need to support vcn decode feature, so disable the
ring for SR-IOV.
Signed-off-by: Emily Deng <Emily.Deng@amd.com>
Reviewed-by: Monk Liu <monk.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Monk Liu [Tue, 10 Mar 2020 10:12:13 +0000 (18:12 +0800)]
drm/amdgpu: postpone entering fullaccess mode
if host support new handshake we only need to enter
fullaccess_mode in ip_init() part, otherwise we need
to do it before reading vbios (becuase host prepares vbios
for VF only after received REQ_GPU_INIT event under
legacy handshake)
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Emily Deng <Emily.Deng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Monk Liu [Wed, 4 Mar 2020 13:33:27 +0000 (21:33 +0800)]
drm/amdgpu: adjust sequence of ip_discovery init and timeout_setting
what:
1)move timtout setting before ip_early_init to reduce exclusive mode
cost for SRIOV
2)move ip_discovery_init() to inside of amdgpu_discovery_reg_base_init()
it is a prepare for the later upcoming patches.
why:
in later upcoming patches we would use a new mailbox event --
"req_gpu_init_data", which is a callback hooked in adev->virt.ops and
this callback send a new event "REQ_GPU_INIT_DAT" to host to notify
host to do some preparation like "IP discovery/vbios on the VF FB"
and this callback must be:
A) invoked after set_ip_block() because virt.ops is configured during
set_ip_block()
B) invoked before ip_discovery_init() becausen ip_discovery_init()
need host side prepares everything in VF FB first.
current place of ip_discovery_init() is before we can invoke callback
of adev->virt.ops, thus we must move ip_discovery_init() to a place
after the adev->virt.ops all settle done, and the perfect place is in
amdgpu_discovery_reg_base_init()
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Emily Deng <Emily.Deng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Monk Liu [Wed, 4 Mar 2020 15:51:51 +0000 (23:51 +0800)]
drm/amdgpu: equip new req_init_data handshake
by this new handshake host side can prepare vbios/ip-discovery
and pf&vf exchange data upon recieving this request without
stopping world switch.
this way the world switch is less impacted by VF's exclusive mode
request
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Emily Deng <Emily.Deng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Monk Liu [Wed, 4 Mar 2020 15:46:45 +0000 (23:46 +0800)]
drm/amdgpu: use static mmio offset for NV mailbox
what:
with the new "req_init_data" handshake we need to use mailbox
before do IP discovery, so in mxgpu_nv.c file the original
SOC15_REG method won'twork because that depends on IP discovery
complete first.
how:
so the solution is to always use static MMIO offset for NV+ mailbox
registers.
HW team confirm us all MAILBOX registers will be at the same
offset for all ASICs, no IP discovery needed for those registers
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Emily Deng <Emily.Deng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Monk Liu [Wed, 4 Mar 2020 03:38:36 +0000 (11:38 +0800)]
drm/amdgpu: introduce new request and its function
1) modify xgpu_nv_send_access_requests to support
new idh request
2) introduce new function: req_gpu_init_data() which
is used to notify host to prepare vbios/ip-discovery/pfvf exchange
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Emily Deng <Emily.Deng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Monk Liu [Tue, 3 Mar 2020 10:13:51 +0000 (18:13 +0800)]
drm/amdgpu: introduce new idh_request/event enum
new idh_request and ihd_event to prepare for the
new handshake protocol implementation later
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Emily Deng <Emily.Deng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Monk Liu [Tue, 3 Mar 2020 08:40:00 +0000 (16:40 +0800)]
drm/amdgpu: cleanup idh event/req for NV headers
1) drop the headers from AI in mxgpu_nv.c, should refer to mxgpu_nv.h
2) the IDH_EVENT_MAX is not used and not aligned with host side
so drop it
3) the IDH_TEXT_MESSAG was provided in host but not defined in guest
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Emily Deng <Emily.Deng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tom St Denis [Wed, 25 Mar 2020 19:07:01 +0000 (15:07 -0400)]
drm/amd/amdgpu: Fix SMUIO/PWR Confusion (v2)
The PWR block was merged into the SMUIO block by revision 12 so we add
that to the smuio_12_0_0 headers.
(v2): Drop nonsensical smuio_10_0_0 header
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tom St Denis [Wed, 25 Mar 2020 17:44:54 +0000 (13:44 -0400)]
drm/amd/amdgpu: Move PWR_MISC_CNTL_STATUS to its own header
The register is part of the PWR block not the GC block. Move to
its own header.
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tom St Denis [Wed, 25 Mar 2020 13:33:29 +0000 (09:33 -0400)]
drm/amd/amdgpu: Add missing SMUIO v12 register to headers
This register is needed by umr.
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chen Zhou [Wed, 25 Mar 2020 02:32:50 +0000 (10:32 +0800)]
drm/amdgpu/uvd7: remove unnecessary conversion to bool
The conversion to bool is not needed, remove it.
Signed-off-by: Chen Zhou <chenzhou10@huawei.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Masahiro Yamada [Thu, 13 Feb 2020 15:39:27 +0000 (00:39 +0900)]
drm/radeon: align short build log
This beautifies the build log.
[Before]
HOSTCC drivers/gpu/drm/radeon/mkregtable
MKREGTABLE drivers/gpu/drm/radeon/r100_reg_safe.h
MKREGTABLE drivers/gpu/drm/radeon/rn50_reg_safe.h
CC [M] drivers/gpu/drm/radeon/r100.o
MKREGTABLE drivers/gpu/drm/radeon/r300_reg_safe.h
CC [M] drivers/gpu/drm/radeon/r300.o
[After]
HOSTCC drivers/gpu/drm/radeon/mkregtable
MKREG drivers/gpu/drm/radeon/r100_reg_safe.h
MKREG drivers/gpu/drm/radeon/rn50_reg_safe.h
CC [M] drivers/gpu/drm/radeon/r100.o
MKREG drivers/gpu/drm/radeon/r300_reg_safe.h
CC [M] drivers/gpu/drm/radeon/r300.o
Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Masahiro Yamada [Thu, 13 Feb 2020 15:39:26 +0000 (00:39 +0900)]
drm/radeon: use pattern rule to avoid code duplication in Makefile
This Makefile repeats similar build rules. Use a pattern rule.
Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Masahiro Yamada [Wed, 25 Mar 2020 20:48:35 +0000 (16:48 -0400)]
drm/radeon: fix build rules of *_reg_safe.h
if_changed must have FORCE as a prerequisite, and the targets must be
added to 'targets'.
Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Masahiro Yamada [Wed, 25 Mar 2020 20:47:16 +0000 (16:47 -0400)]
drm/radeon: remove unneeded header include path
A header include path without $(srctree)/ is suspicious because it does
not work with O= builds.
You can build drivers/gpu/drm/radeon/ without this include path.
Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Emily Deng [Wed, 25 Mar 2020 10:58:02 +0000 (18:58 +0800)]
drm/amdgpu: Ignore the not supported error from psp
As the VCN firmware will not use
vf vmr now. And new psp policy won't support set tmr
now.
For driver compatible issue, ignore the not support error.
Signed-off-by: Emily Deng <Emily.Deng@amd.com>
Reviewed-by: Monk Liu <monk.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Emily Deng [Wed, 25 Mar 2020 10:59:16 +0000 (18:59 +0800)]
drm/amdgpu: Add 4k resolution for virtual display
Add 4k resolution for virtual connector.
Signed-off-by: Emily Deng <Emily.Deng@amd.com>
Reviewed-by: Monk Liu <monk.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Emily Deng [Wed, 25 Mar 2020 11:01:58 +0000 (19:01 +0800)]
drm/amdgpu: Virtual display need to support multiple ctrcs
The crtc num is determined by virtual_display parameter.
Signed-off-by: Emily Deng <Emily.Deng@amd.com>
Reviewed-by: Monk Liu <monk.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
John Clements [Wed, 25 Mar 2020 08:01:14 +0000 (16:01 +0800)]
drm/amdgpu: disable ras query and iject during gpu reset
added flag to ras context to indicate if ras query functionality is ready
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: John Clements <john.clements@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
John Clements [Wed, 25 Mar 2020 07:56:31 +0000 (15:56 +0800)]
drm/amdgpu: added xgmi ras error reset sequence
added mechanism to clear xgmi ras status inbetween error queries
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: John Clements <john.clements@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Monk Liu [Wed, 4 Mar 2020 06:02:55 +0000 (14:02 +0800)]
drm/amdgpu: cleanup all virtualization detection routine
we need to move virt detection much earlier because:
1) HW team confirms us that RCC_IOV_FUNC_IDENTIFIER will always
be at DE5 (dw) mmio offset from vega10, this way there is no
need to implement detect_hw_virt() routine in each nbio/chip file.
for VI SRIOV chip (tonga & fiji), the BIF_IOV_FUNC_IDENTIFIER is at
0x1503
2) we need to acknowledged we are SRIOV VF before we do IP discovery because
the IP discovery content will be updated by host everytime after it recieved
a new coming "REQ_GPU_INIT_DATA" request from guest (there will be patches
for this new handshake soon).
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Emily Deng <Emily.Deng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>